Interface signal control method and system based on register

Abstract

The invention relates to the technical field of computers and provides an interface signal control method and system based on a register. The method comprises the following steps: determining an interface signal requirement of at least one module in at least one working mode; generating a register code based on the interface signal requirement; generating an interface top-layer code based on the interface signal requirement; and controlling the at least one interface signal according to the interface logic mode by utilizing the at least one register. Therefore, the automation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a register-based interface signal control method and system. Background Art

[0002] As the scale and complexity of digital integrated circuits increase, they are generally divided into multiple modules according to their functions. Each module has input signals and output signals for information exchange between different modules and interaction between modules and top-level architectures. Among them, key interface signal control needs to meet specific control logic requirements and specific connection requirements. When a module is integrated, if some signals are connected incorrectly or effective interface signal control is not applied, functional errors and performance degradation may occur. In the prior art, the chip design code needs to be frequently iterated during the chip design and development process, and the module division and structure inside the integrated circuit may need to be changed. It is necessary to rely on R&D personnel to manually add control logic and rely on verification personnel to verify and maintain it, which increases the difficulty and cost of development and prolongs the development cycle.

[0003] To this end, the present application proposes a register-based interface signal control method and system to address the technical difficulties in the prior art. Summary of the invention

[0004] In a first aspect, the present application provides a register-based interface signal control method. The interface signal control method comprises: determining the interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal; generating register code based on the interface signal requirements, wherein the register code includes control logic, and the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template, wherein the control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes; generating interface top-level code based on the interface signal requirements, and generating a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between the at least one register and the control logic, wherein the at least one register is instantiated based on the register code; and controlling the at least one interface signal according to the interface logic mode using the at least one register.

[0005] Through the first aspect of the present application, register codes and interface top-level codes are generated based on the interface signal requirements. On the one hand, after extracting the at least one logic mode from the interface signal requirements and then using the control logic template to generate the control logic, not only can a plurality of logic modes be defined in advance based on the limited change law of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also, on the basis of keeping the control logic unchanged, the first connection relationship can be changed in combination with the variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal (for example, By flexibly filling in the interface signal table), the register-related details and the enable signal-related details can be flexibly adjusted to a large extent. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the various modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the needs of frequent iterative modifications during chip design and development.

[0006] In a possible implementation manner of the first aspect of the present application, the at least one operating mode is variable, and the at least one logic mode does not change with the change of the at least one operating mode.

[0007] In a possible implementation manner of the first aspect of the present application, when the at least one interface signal changes with the change of the at least one operating mode, the first connection relationship changes with the change of the at least one operating mode.

[0008] In a possible implementation manner of the first aspect of the present application, the control logic does not change with the change of the at least one working mode, and the control logic is register-readable and controllable.

[0009] In a possible implementation manner of the first aspect of the present application, the change of the at least one working mode is achieved by changing the register value of the at least one register and thereby changing the configuration of the at least one interface signal.

[0010] In a possible implementation manner of the first aspect of the present application, the interface top-level code includes register connection attributes, register types, register names, and register default values ​​of each of the at least one module.

[0011] In a possible implementation of the first aspect of the present application, the interface top-level code is generated based on the interface signal requirements, including: based on the register connection properties, register type, register name and register default value of each of the at least one module, generating a register output signal for connecting the at least one module.

[0012] In a possible implementation of the first aspect of the present application, the multiple logic modes include: a readable logic mode, a rewrite logic mode, a readable and rewrite combination logic mode, and a non-processing logic mode.

[0013] In a possible implementation of the first aspect of the present application, an interface signal table records the interface signal requirements in a preset standard format, and the interface signal requirements are determined by parsing the interface signal table, wherein the preset standard format includes a table file format and a table item definition.

[0014] In a possible implementation manner of the first aspect of the present application, the register code is generated by parsing a register table, and the register table is obtained by converting the interface signal table using an automated script.

[0015] In a possible implementation manner of the first aspect of the present application, the preset standard format can be adjusted through an automated script, and the table entry definition includes a register name entry or a fixed signal prefix and suffix entry.

[0016] In a possible implementation manner of the first aspect of the present application, the interface signal requirement includes an input signal requirement and an output signal requirement.

[0017] In a possible implementation of the first aspect of the present application, the interface signal requirements also include signal name, input and output, control mode, control enable, data bit width, register name, register initial value, and register address.

[0018] In a possible implementation of the first aspect of the present application, generating the first connection relationship between the at least one interface signal and the control logic includes: implementing the connection between the at least one interface signal and the control logic through an assignment statement, wherein generating the second connection relationship between the at least one register and the control logic includes: implementing the connection between the at least one register and the control logic through an assignment statement.

[0019] In a second aspect, an embodiment of the present application further provides a computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements a method according to any one of the implementation modes of any of the above aspects when executing the computer program.

[0020] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0021] In a fourth aspect, an embodiment of the present application further provides a computer program product, which includes instructions stored on a computer-readable storage medium, and when the instructions are executed on a computer device, the computer device executes a method according to any one of the implementation methods of any of the above aspects.

[0022] In a fifth aspect, the embodiment of the present application also provides a register-based interface signal control system. The interface signal control system includes: an input module for inputting an interface signal table; an extraction module for parsing the interface signal table to determine the interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal; a processing module for generating a register code based on the interface signal requirements, wherein the register code includes a control logic, and the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template, wherein the control logic template is pre-set based on a plurality of logic modes, and the at least one logic mode is selected from the plurality of logic modes, and the processing module is also used to: generate an interface top-level code based on the interface signal requirements, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between the at least one register and the control logic, wherein the at least one register is instantiated based on the register code; an output module for outputting the register code, the interface top-level code, the first connection relationship and the second connection relationship, wherein the at least one register is used to control the at least one interface signal according to the interface logic mode.

[0023] According to the fifth aspect of the present application, register codes and interface top-level codes are generated based on the interface signal requirements. On the one hand, after extracting the at least one logic mode from the interface signal requirements and then using the control logic template to generate the control logic, not only can a plurality of logic modes be defined in advance based on the limited change law of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also, on the basis of keeping the control logic unchanged, the first connection relationship can be changed in combination with the variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal (for example, By flexibly filling in the interface signal table), the register-related details and the enable signal-related details can be flexibly adjusted to a large extent. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the various modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the needs of frequent iterative modifications during chip design and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A flowchart of a register-based interface signal control method provided in an embodiment of the present application;

[0026] Figure 2 A schematic diagram of a register-based interface signal control system provided in an embodiment of the present application;

[0027] Figure 3 A schematic diagram of the structure of a computing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0029] It should be understood that, in the description of this application, "at least one" means one or more, and "a plurality of" means two or more. In addition, unless otherwise specified, the words "first", "second", etc. are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order.

[0030] Figure 1 The following is a flow chart of a register-based interface signal control method provided in an embodiment of the present application. Figure 1 As shown, the interface signal control method includes the following steps.

[0031] Step S110: Determine an interface signal requirement of at least one module in at least one working mode, wherein the interface signal requirement includes at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal.

[0032] Step S120: Generate a register code based on the interface signal requirement, wherein the register code includes a control logic, and the control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, and the control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes.

[0033] Step S130: Based on the interface signal requirements, generate an interface top-level code, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code.

[0034] Step S140: Utilize the at least one register to control the at least one interface signal according to the interface logic mode.

[0035] Figure 1The register-based interface signal control method shown is aimed at the pain points in the chip design and development process, that is, the chip design code needs to be frequently iterated during the chip design and development process, and the module division and structure inside the integrated circuit may need to be changed. For this reason, it is necessary to ensure that the information interaction between the modules inside the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, and it is necessary to ensure that the specific interface signal connection requirements are met and the correct control logic is applied to the interface signal. In addition, the trend of integrated circuits is to provide higher flexibility, so multiple working modes are often provided, that is, the same module can embody different characteristics in multiple working modes, and thus can adapt to complex and changeable application environments. Therefore, it is also required to be able to adapt to the needs of multi-module chips under multiple working modes in terms of interface signal connection and interface signal control logic. Here, in step S110, the interface signal requirements of at least one module in at least one working mode are determined. Among them, the interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal. In this way, the interface signal requirements reflect the needs of multi-module chips in multiple working modes. The same module can have multiple working modes, and information interaction with firmware, etc. can be achieved through interface signals in different working modes. The interface signal requirement includes at least one interface signal. Generally speaking, at least one interface signal includes at least an input signal and an output signal. The interface logic mode associated with the at least one interface signal represents how to apply control logic to the interface signal. For example, the interface logic mode may include a rewrite logic mode, that is, reassigning values ​​through registers. For another example, the interface logic mode may include a readable logic mode, that is, reading interface signals through registers. The interface logic mode may include other logic modes and may also include various possible combinations of these logic modes. It should be understood that, here, at least one logic mode included in the interface logic mode associated with the at least one interface signal embodies the control logic aspects of the interface signal corresponding to the interface signal requirement.

[0036] Continue reading Figure 1, in step S120, based on the interface signal requirement, a register code is generated. The register code includes control logic, and the control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, the control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes. Here, the control logic template is a template for generating the code related to the control logic in the register code. In this way, by distinguishing the control logic of the interface signal, the control logic of the interface signal changes in a limited number of possibilities. In other words, the possible change rules of the control logic of the interface signal can be covered in advance by a limited number of logic modes, and then the at least one logic mode can be selected from the multiple logic modes, that is, the currently applicable at least one logic mode is selected within the range of the possible change rules of the control logic of the interface signal determined in advance, so that the control logic in the register code can be conveniently generated by using the control logic template. For example, the multiple logic modes can be readable logic modes, rewrite logic modes, and combinations thereof, so that the requirements for the control logic applied to the interface signal under a specific chip project can be covered. Moreover, any combination of rewrite logic mode and readable logic mode can be implemented based on the register, including control logic with a certain level of complexity. For example, the interface signal value is first read through the register, and then the interface signal value is rewritten through the register, and then the rewritten interface signal value is read through the register, and then the rewritten interface signal value is rewritten for a second time through the register.

[0037] Continue reading Figure 1In step S130, based on the interface signal requirements, an interface top-level code is generated, and a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between the at least one register and the control logic are generated. The at least one register is instantiated based on the register code. Here, the interface top-level code may exist in the form of an interface signal top-level file. The interface top-level code corresponds to the top-level architecture, which generally includes a top-level module and sub-layer modules contained in the top-level module, as well as module interconnection relationships between these sub-layer modules, and direct connection relationships between sub-layer modules and top-level modules. As mentioned above, in the process of chip design and development, it is necessary to frequently iterate the chip design code and may need to change the module division and structure inside the integrated circuit. For this reason, it is necessary to ensure that the information interaction between the modules inside the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, and it is also necessary to ensure that specific interface signal connection requirements are met and that the correct control logic is applied to the interface signal. Here, on the basis of generating register code based on the interface signal requirements in step S120 (including generating control logic in the register code using a control logic template), in step S130, an interface top-level code is generated based on the interface signal requirements, and a first connection relationship and a second connection relationship are generated. In this way, the connection between each interface signal and the control logic is realized, and the connection between the register and the control logic is also realized. Therefore, with the control logic as an intermediary, a mapping relationship from the register to the interface signal is established, which provides convenience for the subsequent use of the register to realize the readability and controllability of the interface signal. In addition, the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then using the control logic template, so that the isolation between the control logic and the multiple working modes of the multi-module is realized. In other words, when the multi-module is in different working modes, it is possible to keep the interface logic mode unchanged, that is, to keep at least one logic mode unchanged, which means that the control logic is also unchanged, and with the unchanged control logic as an intermediary, different configurations of the interface signal can be realized by changing the register value to be filled in, and the connection between the interface signal and the control logic can be changed, that is, the first connection relationship is changed to realize the adjustment of the interface signal connection, which is conducive to meeting the needs of the multi-module chip in multiple working modes. In addition, the second connection relationship between the register and the control logic can be flexibly adapted according to the register resources that can actually be called.For example, the interface signals included in the interface signal requirements, and the interface top-level code generated based on the interface signal requirements, can be obtained on the basis of the interface signal table, in which the relevant information of the specific interface signal can be defined, such as the signal name, the identifier indicating whether the interface signal is an input signal or an output signal, the signal bit width, the digital identifier for indicating the logic mode, the reset value for the corresponding control register, the register name for the corresponding control logic, etc. The interface signal table can also define other information of the specific interface signal, such as the register name and domain name corresponding to the rewrite enable signal corresponding to the rewrite logic mode, the reset value of the control register corresponding to the rewrite enable signal, etc. It can be seen that there is a large degree of flexibility in the relevant information of the register, and the enable signal such as the rewrite enable signal corresponding to the rewrite logic mode, that is, the interface signal table can be filled in according to the project needs and customer customization requirements. In this way, when the register code and the interface top-level code are generated based on the interface signal requirements, on the one hand, after extracting the at least one logic mode from the interface signal requirements and then using the control logic template to generate the control logic, not only can a plurality of logic modes be defined in advance based on the limited change law of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also, on the basis of keeping the control logic unchanged, the first connection relationship can be changed in combination with the variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal can be defined in combination with the project requirements and the customer customization requirements (for example, through the flexible Flexible filling in the interface signal table), thereby making substantial and flexible adjustments to the register-related details and the enable signal-related details. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changing application scenarios and the needs of frequent iterative modifications during chip design and development.

[0038] Continue reading Figure 1, in step S140, using the at least one register, control the at least one interface signal according to the interface logic mode. As mentioned above, based on the limited change rules of the interface logic mode of the interface signal, multiple logic modes are delineated in advance and the control logic template is pre-set, which improves the efficiency of automated script processing, and can achieve flexible adjustment in terms of interface signal connection and control logic applied to the interface signal on the basis of the unchanged control logic, while ensuring that the information interaction between the various modules inside the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the need for frequent iterative modifications during chip design and development. In this way, the overhead of R&D personnel manually adding control logic and verification personnel performing verification and maintenance is reduced, the development difficulty and development cost are reduced, and the development cycle is shortened.

[0039] In conclusion, Figure 1 The register-based interface signal control method shown generates register code and interface top-level code based on the interface signal requirements. On the one hand, after extracting the at least one logic mode from the interface signal requirements, the control logic is generated using a control logic template. Not only can a variety of logic modes be defined in advance based on the limited change rules of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also the first connection relationship can be changed on the basis of the unchanged control logic in combination with a variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal can be defined in combination with project requirements and customer customization requirements. (For example, by flexibly filling in the interface signal table), the register-related details and the enable signal-related details can be flexibly adjusted to a large extent. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the need for frequent iterative modifications during chip design and development.

[0040] In a possible implementation, the at least one working mode is variable, and the at least one logical mode does not change with the change of the at least one working mode. In some embodiments, when the at least one interface signal changes with the change of the at least one working mode, the first connection relationship changes with the change of the at least one working mode. In this way, the interface signal requirement reflects the requirements of the multi-module chip in multiple working modes. The same module can have multiple working modes, and in different working modes, information interaction with firmware and the like can be achieved through interface signals. The control logic is generated by extracting the at least one logical mode from the interface signal requirement and then using the control logic template, thereby achieving isolation between the control logic and the multiple working modes of the multi-module. In other words, when the multi-module is in different working modes, it is possible to keep the interface logic mode unchanged, that is, to keep at least one logical mode unchanged, which means that the control logic also remains unchanged, and with the unchanged control logic as an intermediary, different configurations of the interface signal can be achieved by changing the register value to be filled in, and the interface signal connection can be adjusted by changing the connection between the interface signal and the control logic, that is, changing the first connection relationship, which is conducive to meeting the requirements of the multi-module chip in multiple working modes.

[0041] In one possible implementation, the control logic does not change with the change of the at least one operating mode, and the control logic is register readable and controllable. In some embodiments, the change of the at least one operating mode is achieved by changing the register value of the at least one register and thereby changing the configuration of the at least one interface signal. In this way, when the register code and the interface top-level code are generated based on the interface signal requirements, on the one hand, after extracting the at least one logic mode from the interface signal requirements and then using the control logic template to generate the control logic, not only can a plurality of logic modes be identified in advance based on the limited change law of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also, on the basis of the unchanged control logic, the relevant information of the interface signal can be defined in combination with project requirements and customer customization requirements (for example, by flexibly filling in the interface signal table), thereby making large-scale flexible adjustments to the register-related details and enable signal-related details. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in, thereby achieving flexible adjustments in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the needs of frequent iterative modifications during chip design and development.

[0042] In a possible implementation, the interface top-level code includes register connection attributes, register types, register names, and register default values ​​of the at least one module. In some embodiments, based on the interface signal requirements, the interface top-level code is generated, including: based on the register connection attributes, register types, register names, and register default values ​​of the at least one module, a register output signal for connecting the at least one module is generated. This helps to achieve a large degree of flexible adjustment of register-related details and enable signal-related details.

[0043] In a possible implementation, the multiple logic modes include: a readable logic mode, a rewrite logic mode, a readable and rewrite combination logic mode, and a non-processing logic mode. The readable logic mode is to read the interface signal through a register. The rewrite logic mode is to reassign the value through the register. The non-processing logic mode means not to read or reassign the value. The readable and rewrite combination logic mode means a combination of a readable logic mode and a rewrite logic mode. In this way, the control logic for the interface signal changes in a limited number of possibilities, that is, the possible change rules of the control logic of the interface signal can be covered in advance by a limited number of logic modes, and then at least one logic mode can be selected from the multiple logic modes, that is, the currently applicable at least one logic mode can be selected within the range of the possible change rules of the control logic of the interface signal determined in advance, so that the control logic template can be conveniently used to generate the control logic in the register code. The multiple logic modes can be readable logic modes, rewrite logic modes, and combinations thereof, so that the requirements for the control logic applied to the interface signal under a specific chip project can be covered. Moreover, any combination of rewrite logic mode and readable logic mode can be implemented based on the register, including control logic with a certain level of complexity. For example, the interface signal value is first read through the register, and then the interface signal value is rewritten through the register, and then the rewritten interface signal value is read through the register, and then the rewritten interface signal value is rewritten for a second time through the register.

[0044] In a possible implementation, the interface signal table records the interface signal requirements in a preset standard format, and the interface signal requirements are determined by parsing the interface signal table, wherein the preset standard format includes a table file format and a table item definition. In some embodiments, the register code is generated by parsing a register table, and the register table is obtained by converting the interface signal table using an automated script. In some embodiments, the preset standard format can be adjusted by an automated script, and the table item definition includes a register name item or a fixed signal prefix and suffix item. The interface signal table may define relevant information of a specific interface signal, such as a signal name, an identifier indicating whether the interface signal is an input signal or an output signal, a signal bit width, a digital identifier for indicating a logic mode, a reset value for a corresponding control register, a register name for a corresponding control logic, etc. The interface signal table may also define other information of a specific interface signal, such as a register name and a domain name corresponding to a rewrite enable signal corresponding to a rewrite logic mode, a reset value of a control register corresponding to a rewrite enable signal, etc. It can be seen that there is a large degree of flexibility in the relevant information of the registers and the enable signals such as the rewrite enable signal corresponding to the rewrite logic mode, that is, the interface signal table can be filled in according to the project needs and customer customization requirements.

[0045] See also Figure 1 , the interface signal table records the interface signal requirements in a preset standard format, and a hardware language such as Verilog can be used to specify a standard code template for automated script compilation. In this way, the automated script can rewrite the signals that need to be rewritten in the instantiation module based on the information in the interface signal table read, and directly connect the readable and unnecessary signals. In addition, the register table is obtained by converting the interface signal table using the automated script, so it can help fill in the table according to the same specification, which helps to ensure the consistency between the register table and the interface signal table. The register table can record register information for generating register codes. The interface signal table is used to extract the control logic signal and the register signal, that is, by parsing the interface signal table to determine the interface signal requirements, and then generate the interface top-level code and register code, and automatically generate the connection between the control logic and the interface signal, and the connection between the control logic and the register. The following takes four interface signals as an example to explain how users can fill in the interface signal table in a standardized manner based on the automatic script usage instructions, according to the specific conditions of the project and the control mode type.

[0046] The first interface signal is named "test_signal0", which is an input signal (input), with a bit width of 2 and a control mode of 0, which means that it is not controlled in any way. The file name to which the first interface signal belongs can be specified as "DEMO_OVRT". The second interface signal is named "test_signal1", which is an output signal, with a bit width of 1 and a control mode of 1, which means that the control logic has been rewritten, and the default rewrite value is 0x0, the corresponding register is "TEST_REG_1", and the corresponding rewrite enabled register name is "TEST_REG_1" and the domain name is "TEST_SIGNAL1_OVRD_EN". Among them. The default rewrite enable is 0x0, that is, the rewrite function is enabled by default, the register description is "for test", the register address is 0x0, and the file name to which it belongs is "DEMO_OVRT". The third interface signal name is "test_signal2", which is an input signal with a bit width of 1 and a control mode of 2, which means that it passes through the readable control logic, and the default rewrite value is 0x0. The corresponding register is "TEST_REG_2_RO", and there is no corresponding rewrite enable, so there is no default rewrite enable. The register description is "for test", the register address is 0x1, and the file name is "DEMO_OVRT." The fourth interface signal name is "test_signal3", which is an input signal with a bit width of 1 and a control mode of "2-1", which means that it passes through the readable logic first and then the rewrite control logic, and the default rewrite value is 0x0. The corresponding registers are "TEST_REG_3_RO and TEST_REG_3", the corresponding rewrite enable register name is "TEST_REG_3" and the domain name is "TEST_SIGNAL3_OVRD_EN," the default rewrite enable is 0x0, that is, the rewrite function is not enabled by default, and the register description is "for test," the register addresses are "0x2 and 0x3," and the file name is "DEMO_OVRT." Thus, it can be seen that there is a large degree of flexibility in the relevant information of the registers and the enable signals such as the rewrite enable signal corresponding to the rewrite logic mode, that is, the interface signal table can be filled in according to the project needs and customer customization requirements.In this way, when the register code and the interface top-level code are generated based on the interface signal requirements, on the one hand, after extracting the at least one logic mode from the interface signal requirements and then using the control logic template to generate the control logic, not only can a plurality of logic modes be defined in advance based on the limited change law of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also, on the basis of keeping the control logic unchanged, the first connection relationship can be changed in combination with the variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal can be defined in combination with the project requirements and the customer customization requirements (for example, through the flexible Flexible filling in the interface signal table), thereby making substantial and flexible adjustments to the register-related details and the enable signal-related details. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changing application scenarios and the needs of frequent iterative modifications during chip design and development.

[0047] In a possible implementation, the interface signal requirements include input signal requirements and output signal requirements. In this way, the interface signal table can be filled in according to project needs and customer customization requirements, and there is a large degree of flexibility in the relevant information of the register and the enable signal such as the rewrite enable signal corresponding to the rewrite logic mode.

[0048] In a possible implementation, the interface signal requirements also include signal name, input and output, control mode, control enable, data bit width, register name, register initial value, and register address. In this way, the interface signal table can be filled in according to project needs and customer customization requirements, and there is a large degree of flexibility in the relevant information of the register and the enable signal, such as the rewrite enable signal corresponding to the rewrite logic mode.

[0049] In a possible implementation, generating the first connection relationship between the at least one interface signal and the control logic includes: realizing the connection between the at least one interface signal and the control logic through an assignment statement, wherein generating the second connection relationship between the at least one register and the control logic includes: realizing the connection between the at least one register and the control logic through an assignment statement. Flexible adjustment is achieved in terms of interface signal connection and control logic applied to the interface signal, while ensuring that the information interaction between the modules inside the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changing application scenarios and the need for frequent iterative modifications during chip design and development. In this way, the overhead of R&D personnel manually adding control logic and verification personnel performing verification and maintenance is reduced, the development difficulty and cost are reduced, and the development cycle is shortened.

[0050] Figure 2 Schematic diagram of a register-based interface signal control system provided in an embodiment of the present application. Figure 2 As shown, the interface signal control system includes an input module 210, an extraction module 220, a processing module 230 and an output module 240. The input module 210 is used to input an interface signal table. The extraction module 220 is used to parse the interface signal table to determine the interface signal requirements of at least one module in at least one working mode. The interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal. The processing module 230 is used to generate a register code based on the interface signal requirements. The register code includes a control logic, which is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template. The control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes. The processing module 230 is also used to: generate an interface top-level code based on the interface signal requirements, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between the at least one register and the control logic. The at least one register is instantiated based on the register code. The output module 240 is used to output the register code, the interface top-level code, the first connection relationship and the second connection relationship. Wherein, the at least one register is used to control the at least one interface signal according to the interface logic mode.

[0051] Figure 2The register-based interface signal control system shown generates register code and interface top-level code based on the interface signal requirements. On the one hand, after extracting the at least one logic mode from the interface signal requirements, the control logic is generated using a control logic template. Not only can a variety of logic modes be defined in advance based on the limited change rules of the interface logic mode of the interface signal and the control logic template be pre-set, thereby improving the efficiency of automated script processing, but also the first connection relationship can be changed on the basis of the unchanged control logic in combination with a variable working mode, that is, the connection between each interface signal and the control logic can be adjusted; on the other hand, the relevant information of the interface signal can be defined in combination with project requirements and customer customization requirements. (For example, by flexibly filling in the interface signal table), the register-related details and the enable signal-related details can be flexibly adjusted to a large extent. For example, different configurations of the interface signal can be achieved by changing the register value to be filled in. This can be combined with changing the connection between the interface signal and the control logic, that is, changing the first connection relationship to achieve the adjustment of the interface signal connection, thereby achieving flexible adjustment in both the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules within the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, which helps to adapt to complex and changeable application scenarios and the need for frequent iterative modifications during chip design and development.

[0052] Figure 3 3 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application, and the computing device 300 includes: one or more processors 310, a communication interface 320 and a memory 330. The processor 310, the communication interface 320 and the memory 330 are interconnected via a bus 340. Optionally, the computing device 300 may also include an input / output interface 350, and the input / output interface 350 is connected to an input / output device for receiving parameters set by a user, etc. The computing device 300 can be used to implement some or all of the functions of the device embodiment or system embodiment in the above-mentioned embodiment of the present application; the processor 310 can also be used to implement some or all of the operating steps of the method embodiment in the above-mentioned embodiment of the present application. For example, the specific implementation of the various operations performed by the computing device 300 can refer to the specific details in the above-mentioned embodiments, such as the processor 310 is used to perform some or all of the steps in the above-mentioned method embodiment or some or all of the operations in the above-mentioned method embodiment. For another example, in an embodiment of the present application, the computing device 300 may be used to implement part or all of the functions of one or more components in the above-mentioned apparatus embodiment. In addition, the communication interface 320 may be specifically used to perform the communication functions necessary to implement the functions of these apparatuses and components, and the processor 310 may be specifically used to perform the processing functions necessary to implement the functions of these apparatuses and components.

[0053] It should be understood that Figure 3 The computing device 300 may include one or more processors 310, and the multiple processors 310 may provide processing capabilities in a parallel connection mode, a serial connection mode, a serial-parallel connection mode, or any connection mode, or the multiple processors 310 may form a processor sequence or a processor array, or the multiple processors 310 may be divided into a main processor and an auxiliary processor, or the multiple processors 310 may have different architectures such as a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown in the figure, and the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 may include Figure 3 More or fewer components may be shown, or some components may be combined or separated, or may have a different arrangement of components.

[0054] The processor 310 may have a variety of specific implementation forms. For example, the processor 310 may include a central processing unit (CPU), a graphic processing unit (GPU), a neural-network processing unit (NPU), a tensor processing unit (TPU) or a data processing unit (DPU), etc., and the embodiment of the present application does not specifically limit it. The processor 310 may also be a single-core processor or a multi-core processor. The processor 310 may be a combination of a CPU and a hardware chip. The above-mentioned hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof. The processor 310 may also be implemented using a logic device with built-in processing logic alone, such as an FPGA or a digital signal processor (DSP). The communication interface 320 may be a wired interface or a wireless interface for communicating with other modules or devices. The wired interface may be an Ethernet interface, a local interconnect network (LIN), etc., and the wireless interface may be a cellular network interface or a wireless local area network interface, etc.

[0055] The memory 330 may be a non-volatile memory, such as a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The memory 330 may also be a volatile memory, which may be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM). The memory 330 may also be used to store program codes and data, so that the processor 310 calls the program codes stored in the memory 330 to execute some or all of the operation steps in the above method embodiment, or to execute the corresponding functions in the above device embodiment. Figure 3 Show more or fewer components, or have different component configurations.

[0056] The bus 340 may be a peripheral component interconnect express (PCIe) bus, an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 may be divided into an address bus, a data bus, a control bus, etc. In addition to the data bus, the bus 340 may also include a power bus, a control bus, and a status signal bus, etc. However, for the sake of clarity, Figure 3 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0057] The method and device provided in the embodiments of the present application are based on the same inventive concept. Since the principles of solving the problems in the methods and devices are similar, the embodiments, implementation methods, examples or implementation methods of the methods and devices can refer to each other, and the repeated parts will not be repeated. The embodiments of the present application also provide a system, which includes multiple computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, which will not be repeated here.

[0058] The present application also provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a computer device (such as one or more processors), the method steps in the above method embodiment can be implemented. The specific implementation of the processor of the computer-readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiment and / or the specific functions described in the above device embodiment, which will not be repeated here.

[0059] It should be understood by those skilled in the art that the embodiments of the present application may be provided as methods, systems, or computer program products. The present application may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. The embodiments of the present application may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented using software, the above embodiments may be implemented in whole or in part in the form of a computer program product. The present application may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program codes. The computer program product includes one or more computer instructions. When the computer program instructions are loaded or executed on a computer, the process or function described in the embodiments of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. Computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. Computer-readable storage media can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media. Available media can be magnetic media (such as floppy disks, hard disks, tapes), optical media, or semiconductor media. Semiconductor media can be solid-state hard disks, random access memory, flash memory, read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only memory, registers, or any other form of suitable storage media.

[0060] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. Each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing device to work in a specific way, so that the instructions stored in the computer-readable memory produce a product including an instruction device, which implements the functions specified in the process. Figure 1A process or multiple processes and / or boxes Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide for implementing the process in the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0061] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiment of the present application can be adjusted in order, merged or deleted according to actual needs; the modules in the system of the embodiment of the present application can be divided, merged or deleted according to actual needs. If these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A register-based interface signal control method, characterized in that: The interface signal control method comprises: Determining an interface signal requirement of at least one module in at least one operating mode, wherein the interface signal requirement includes at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal, the at least one operating mode is variable, and the at least one logic mode does not change with a change in the at least one operating mode; Generate a register code based on the interface signal requirement, wherein the register code includes a control logic, the control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, the control logic template is pre-set based on a plurality of logic modes, the at least one logic mode is selected from the plurality of logic modes, and the control logic does not change with a change in the at least one working mode; Based on the interface signal requirement, generate an interface top-level code, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code, and when the at least one interface signal changes with the change of the at least one working mode, the first connection relationship changes with the change of the at least one working mode; The at least one interface signal is controlled according to the interface logic mode using the at least one register.

2. The interface signal control method according to claim 1, characterized in that: The control logic is register readable and controllable.

3. The interface signal control method according to claim 1, characterized in that: The change of the at least one working mode is achieved by changing the register value of the at least one register and thereby changing the configuration of the at least one interface signal.

4. The interface signal control method according to claim 1, characterized in that: The interface top-level code includes register connection attributes, register types, register names and register default values ​​of each of the at least one module.

5. The interface signal control method according to claim 4, characterized in that: Based on the interface signal requirements, the interface top-level code is generated, including: based on the register connection attributes, register types, register names and register default values ​​of each of the at least one module, a register output signal for connecting the at least one module is generated.

6. The interface signal control method according to claim 1, characterized in that: The multiple logic modes include: a readable logic mode, a rewrite logic mode, a readable and rewrite combined logic mode, and a non-processing logic mode.

7. The interface signal control method according to claim 1, characterized in that: The interface signal table records the interface signal requirements according to a preset standard format, and the interface signal requirements are determined by parsing the interface signal table. The preset standard format includes a table file format and a table item definition.

8. The interface signal control method according to claim 7, characterized in that: The register code is generated by parsing a register table, and the register table is obtained by converting the interface signal table using an automated script.

9. The interface signal control method according to claim 7, characterized in that: The preset standard format can be adjusted through an automated script, and the table entry definition includes a register name entry or a fixed signal prefix and suffix entry.

10. The interface signal control method according to claim 1, characterized in that: The interface signal requirements include input signal requirements and output signal requirements.

11. The interface signal control method according to claim 1, characterized in that: The interface signal requirements also include signal name, input and output, control mode, control enable, data bit width, register name, register initial value, and register address.

12. The interface signal control method according to claim 1, characterized in that: Generating the first connection relationship between the at least one interface signal and the control logic includes: realizing the connection between the at least one interface signal and the control logic through an assignment statement, wherein generating the second connection relationship between the at least one register and the control logic includes: realizing the connection between the at least one register and the control logic through an assignment statement.

13. A computer device, characterized in that: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to perform the method according to any one of claims 1 to 12.

15. A register-based interface signal control system, characterized in that: The interface signal control system comprises: An input module, used for inputting an interface signal table; an extraction module, configured to parse the interface signal table to determine an interface signal requirement of at least one module in at least one working mode, wherein the interface signal requirement includes at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal, the at least one working mode is variable, and the at least one logic mode does not change with a change in the at least one working mode; a processing module, configured to generate a register code based on the interface signal requirement, wherein the register code includes a control logic, the control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, the control logic template is pre-set based on a plurality of logic modes, the at least one logic mode is selected from the plurality of logic modes, and the control logic does not change with a change in the at least one working mode; The processing module is further used to: generate an interface top-level code based on the interface signal requirement, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code, and when the at least one interface signal changes with the change of the at least one working mode, the first connection relationship changes with the change of the at least one working mode; An output module is used to output the register code, the interface top-level code, the first connection relationship and the second connection relationship, wherein the at least one register is used to control the at least one interface signal according to the interface logic mode.

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