Semiconductor memory device

Abstract

The embodiment of the invention relates to a semiconductor memory device. To reduce the time required for writing data. There is provided a semiconductor memory device including a memory cell having a gate electrode including a select gate and a memory gate, a source line connected to a source, and a bit line connected to a drain; an extraction section that extracts a current flowing from the source side to the drain side during writing of the memory cell from the bit line; a discharge member that has a higher capability of passing a current than the extraction member, and that reduces a voltage of the bit line; a charging member that has a higher capability of passing a current than the discharging member and applies a voltage to the bit line; and a control section that reduces a voltage of the bit line by the discharging section and applies a voltage to the bit line by the charging section at the start of writing to the memory cell.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2023-145828 filed on September 8, 2023, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Background Art

[0003] The present disclosure relates to a semiconductor memory device.

[0004] The disclosed technologies are listed below.

[0005] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2008-288503

[0006] Conventionally, a split gate type memory cell having a selection gate transistor and a memory gate transistor is known (for example, Patent Document 1). This type of memory cell is also called SG-MONOS (Split Gate-Metal Oxide Nitride Oxide Silicon) because the gate electrode is divided into a selection gate and a memory gate. MONOS is a structure in which a three-layer oxide film / nitride film (trap film) / oxide film is formed on a silicon substrate, and a gate electrode (metal) is placed thereon. SG-MONOS is used, for example, as a flash memory structure mounted on a microcontroller or the like. Summary of the invention

[0007] However, in the conventional technology, there is room for improvement in the time required for data writing.Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0008] In one embodiment, a semiconductor memory device is provided, which includes a memory cell having a gate electrode including a selection gate and a memory gate, a source line connected to a source, and a bit line connected to a drain; a pull-out component that pulls out a current flowing from a source side to a drain side during writing of the memory cell from the bit line; a discharge component that has a higher ability to pass current than the pull-out component and reduces a voltage of the bit line; a charging component that has a higher ability to pass current than the discharge component and applies a voltage to the bit line; and a control component that reduces the voltage of the bit line through the discharge component and applies a voltage to the bit line through the charging component when writing to the memory cell starts.

[0009] According to one embodiment, the time required for data writing can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment.

[0011] Figure 2 is a diagram showing a configuration example of a memory cell according to an embodiment.

[0012] Figure 3 is a diagram showing an example of operation during writing of a memory cell according to an embodiment.

[0013] Figure 4 is a flowchart showing an example of an operation of writing to a memory cell of a semiconductor memory device according to an embodiment.

[0014] Figure 5 is a timing diagram showing an example of voltage on a bit line during writing according to an embodiment.

[0015] Figure 6 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment. DETAILED DESCRIPTION

[0016] The present disclosure is illustrated with reference to several exemplary embodiments. These embodiments are described for illustrative purposes only, and it should be understood that they are intended to help those skilled in the art understand and implement the present disclosure, rather than to impose any limitation on the scope of the present disclosure. The disclosure described in this specification may be implemented in a variety of ways different from those described below.

[0017] In the following description and claims, unless defined otherwise, all technical and scientific terms used in the specification have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs.

[0018] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0019] <Configuration>

[0020] refer to Figure 1 , the configuration of the semiconductor memory device 10 according to this embodiment will be described. Figure 1 1 is a diagram showing a configuration example of a semiconductor memory device 10 according to this embodiment. The semiconductor memory device 10 includes a memory cell 11, a control section 12, a switch 13, a bias section 14, a pull-out section 15, a discharge section 16, and a charge section 17. Note that Figure 1 Elements necessary for explaining the present disclosure are shown, and explanation of elements having low relevance to the explanation of the present disclosure is appropriately omitted. Figure 1 For components not shown in the figure, those used in known semiconductor memory devices (semiconductor memories) can be used as needed.

[0021] The memory cell 11 is a circuit that performs a function such as data storage. The memory cell 11 may be a multi-level cell (MLC) that can record more than one bit of information by having multiple levels of storage charges and taking three or more different states.

[0022] The memory cell 11 is connected to the bias section 14, the pull-out section 15, the discharge section 16, and the charge section 17 through the bit line BL. Figure 1 Although not shown in the figure, as shown in the repeated diagram 21, the semiconductor memory device 10 includes a plurality of bit lines and memory cells, one memory cell is connected to one bit line, and the memory cell to be controlled can be selected by the switch 13.

[0023] The control section 12 controls each component of the semiconductor memory device 10. For example, the control section 12 instructs each component of the semiconductor memory device 10 to perform an operation required to write data to the memory cell 11. The control section 12 can control the operation of each component by controlling a voltage or signal applied to each input component of each component.

[0024] The bias section 14 is turned on at a specific point in the stage (stage 1) before the control section 12 instructs the start of writing data to the memory cell 11, and applies the power supply voltage Vinh (for example, 1.5 V) to the bit line BL. In addition, in the stage (stage 2) after the control section 12 instructs the start of writing data to the memory cell 11, the bias section 14 is turned off, and the application of voltage to the bit line BL is stopped.

[0025] The pull-out section 15 is turned off in phase 1. In addition, the pull-out section 15 is turned on in phase 2, and pulls out a current Ids flowing from the source S side to the drain D side during writing of the memory cell 11 from the bit line BL at a constant current (e.g., 1.3 μA). Therefore, the pull-out section 15 lowers the voltage Vbl on the bit line BL by the constant current.

[0026] The discharge section 16 has, for example, an NMOS (n-type MOS (metal oxide semiconductor)) transistor. When the voltage Vbl on the bit line BL is pulled out, the discharge section 16 has the ability to pass a current much higher than the constant current (for example, 1.3 μA) passed by the pull-out section 15, and when a specific signal is input, the gate is at a high (H) level. Therefore, while the specific signal is input, the discharge section 16 quickly reduces the voltage Vbl on the bit line BL.

[0027] The charging section 17 operates as a source follower circuit (drain grounding circuit). The charging section 17 has the same structure (film thickness and injection conditions) as the selection gate CG of the memory cell 11 to be described later, and has an NMOS transistor (working gate (WG) polycrystalline transistor) larger in size than the selection gate CG.

[0028] The WG poly transistor can be formed by a method similar to the select gate CG so as to have the same film thickness and implantation conditions as the select gate CG. The voltage (gate threshold voltage) at which the WG poly transistor starts to pass current is the same as the gate threshold voltage Vtm of the select gate CG.

[0029] Compared to the selection gate CG, the WG polycrystalline transistor may have a different size and current passing capability (current capacity). The WG polycrystalline transistor has the capability to pass a higher current than the discharge section 16. Therefore, if the current capacity of the charging section 17 is CAc, the current capacity of the discharge section 16 is CAd, and the current capacity of the pull-out section 15 is CAh, the following inequality (1) holds. CAc>CAd>>CAh...(1)

[0030] The charging section 17 is connected to the bit line BL through the WG polycrystalline transistors arranged in series and the PMOS transistors operating as switches. During writing of the memory cell 11, the same voltage as the voltage Vcg of the selection gate CG is applied from the power supply to the charging section 17. In addition, since the gate threshold voltage of the WG polycrystalline transistor is Vtm, when the charging section 17 is turned on, a voltage of about Vcg-Vtm is applied to the bit line BL.

[0031] <About Memory Unit 11>

[0032] <<Configuration of Memory Unit 11>>

[0033] Next, refer to Figure 2 , the configuration of the memory unit 11 will be described. Figure 2 is a diagram showing a configuration example of the memory unit 11 according to the embodiment. Figure 2 In the example of , the memory cell 11 has a three-layer oxide film 202 / nitride film (trap film) 203 / oxide film 204 formed on a silicon substrate 201, and a gate electrode (metal) as a memory gate MG is arranged thereon. Then, a high-density electron trap level is formed in the nitride film 203.

[0034] This type of structure is also called MONOS (metal oxide nitride oxysilicon). Figure 2 In the example of FIG. 1 , the gate electrode is divided into a selection gate CG and a memory gate MG. This type of gate electrode is also called SG (split gate). Figure 2 The memory cell 11 shown is also referred to as SG-MONOS and is used, for example, in embedded flash memories for microcontrollers.

[0035] <<Operation of Memory Cell 11 During Writing>>

[0036] Next, refer to Figure 3 , the operation of the memory cell 11 during writing will be described. Figure 3 is a diagram showing an example of the operation of the memory cell 11 during writing according to the embodiment. Figure 3 In the example of FIG. 2 , a positive high voltage (e.g., 10 V) is applied as the voltage Vmg of the memory gate MG, and a positive high voltage (e.g., 5 V) is applied as the voltage Vsl of the source line SL connected to the source S on the silicon substrate 201. In addition, a positive voltage (e.g., 1 V) is applied as the voltage Vcg of the selection gate CG. In addition, a positive voltage (e.g., 0.7 V) is applied as the voltage Vbl of the bit line BL connected to the drain D on the silicon substrate 201.

[0037] By applying high voltage to the voltage Vmg and the voltage Vsl, hot electrons are injected from the silicon substrate 201 into the nitride film 203. This hot electron injection technique is also called SSI (Source Side Injection).

[0038] Here, the control section 12 maintains the voltage of the bit line BL at about Vcg-Vtm by limiting the current of the bit line BL to a constant current (e.g., 1.3 μA). Vtm is the voltage (gate threshold voltage) at which the select gate CG starts to pass current. In addition, Vcg-Vtm is the voltage at which the select gate CG is applied to the bit line BL. As a result, a current Ids (e.g., about 1 μA to 4 μA) flows from the source S side to the drain D side, and writing is performed by hot electron injection. The current Ids flowing from the source S side to the drain D side is pulled out from the bit line BL by the pull-out section 15 at a constant current (e.g., 1.3 μA).

[0039] <<Operation of Memory Cell 11 During Reading>>

[0040] During reading of the memory cell 11, the voltage Vmg and the voltage Vsl are set to, for example, 0 V, and positive voltages (for example, 1.5 V and 1.25 V, respectively) are applied to the voltage Vcg and the voltage Vbl.

[0041] <<Operation of Memory Cell 11 During Erasure>>

[0042] When erasing data of the memory cell 11, the voltage Vcg and the voltage Vbl are set to 0 V, a negative high voltage is applied to the voltage Vmg, and a positive high voltage is applied to the voltage Vsl. This effectively lowers the energy barrier of the insulating film, and holes tunnel from the silicon substrate 201 to the nitride film 203. Then, the electrons at the trapped level recombine with the holes and disappear, so the stored charge disappears.

[0043] <Operation of Semiconductor Memory Device 10 During Writing>

[0044] Next, refer to Figure 4 and Figure 5 , the operation during writing to the memory cell 11 of the semiconductor memory device 10 will be described. Figure 4 : is a flowchart showing an example of operation during writing to the memory cell 11 of the semiconductor memory device 10 according to this embodiment. Figure 5 : is a timing chart showing an example of the voltage Vbl on the bit line BL during writing according to the embodiment. Figure 4 The processing steps in may be appropriately changed as long as they do not contradict each other.

[0045] In step S1, the control unit 12 detects a write operation to the memory cell 11. Here, for example, when the control unit 12 receives a write instruction from an external microcontroller or the like, the control unit 12 may determine the memory cell 11 to be written.

[0046] Next, the control unit 12 transitions each component of the semiconductor memory device 10 to phase 1, which is also a preparation phase before starting writing (step S2). Here, the control unit 12 turns on the bias unit 14 and applies the power supply voltage Vinh (e.g., 1.5V) to the bit line BL. In addition, the control unit 12 turns off the pull-out unit 15 to prevent the voltage Vbl on the bit line BL from dropping. As a result, as shown in FIG. Figure 5 As shown in the transition 501 of the voltage Vbl on the bit line BL in FIG. 5 , the voltage Vbl is set to the voltage Vinh before the time point ts. If each component of the semiconductor memory device 10 is already in the state of phase 1, the process of step S2 (the process of transitioning to phase 1) is unnecessary.

[0047] Next, the control unit 12 applies a voltage to each line except the bit line BL of the memory cell 11 (step S3). Here, the control unit 12 applies a positive high voltage (e.g., 10V) as the voltage Vmg of the memory gate MG, and applies a positive high voltage (e.g., 5V) as the voltage Vsl of the source line SL. In addition, the control unit 12 applies a positive voltage (e.g., 1V) as the voltage Vcg of the selection gate CG.

[0048] Next, the control unit 12 transitions to phase 2, which is a phase after the start of writing, by instructing the start of writing data to the memory cell 11 (step S4). Here, the control unit 12 turns off the bias unit 14 and stops applying voltage to the bit line BL. In addition, the control unit 12 turns on the pull-out unit 15 and causes the voltage Vbl on the bit line BL to be pulled out (lowered) at a constant current (e.g., 1.3 μA).

[0049] In addition, the control unit 12 inputs a pulse signal (one-shot signal) of a specific time length (width) to the discharge unit 16, and (almost simultaneously) turns on the charge unit 17 for a specific time length. As a result of the one-shot signal being input to the discharge unit 16, the voltage Vbl on the bit line BL drops sharply (at once) from the power supply voltage Vinh. This is because the current capacity CAd of the discharge unit 16 is much higher than the current capacity CAh of the pull-out unit 15 (CAd>>CAh).

[0050] In addition, by turning on the charging unit 17, a path is created to apply a voltage of about Vcg-Vtm to the bit line BL. As a result, when the charging unit 17 is turned on, when the voltage Vbl on the bit line BL drops to about Vcg-Vtm, current is supplied from the WG poly transistor to the bit line BL. Here, because the current capacity CAc of the charging unit 17 is higher than the current capacity CAd of the discharging unit 16 (CAc>CAd), the voltage Vbl on the bit line BL is quickly stabilized to about Vcg-Vtm. This can reduce undershoot.

[0051] like Figure 5 As shown in the transition 501 of the voltage Vbl on the bit line BL in FIG. 1 , between the time point ts indicating the start of writing data to the memory cell 11 and the time point t1, the voltage Vbl drops rapidly from the voltage Vinh to about Vcg-Vtm and then stabilizes.

[0052] When the voltage Vbl on the bit line BL becomes approximately Vcg-Vtm, in the memory cell 11, current flows from the source S side to the drain side, and writing actually starts by hot electron injection. Figure 5 In the example of , writing is performed by hot electron injection between time points t1 and t2.

[0053] Next, the control unit 12 returns to the stage 1 (step S5) by indicating the end of data writing to the memory cell 11. In addition, the control unit 12 can sequentially perform the processing from step S2 for each address of one or more memory cells as write targets among the plurality of memory cells of the semiconductor memory device 10.

[0054] <Others>

[0055] Will target Figure 1 The configuration of the present disclosure shown is explained in comparison with the case of a form without the discharge unit 16 and the charge unit 17. In this form, about 1 microsecond is required from the time ts when the start of writing data to the memory cell 11 is indicated to the time t2 when the writing is completed by hot electron injection. Among them, for example, about 500 nanoseconds are required to reduce the voltage Vbl on the bit line BL from the power supply voltage Vinh to about Vcg-Vtm by the extraction unit 15, which is mainly used to extract a constant current from the bit line BL during writing.

[0056] Next, we will focus on Figure 1 The configuration of the present disclosure shown is explained in comparison with the case of a form without the charging unit 17. In this form, since the target voltage Vcg-Vtm and the one-shot signal have PVT (Process-Voltage-Temperature) dependency, it is relatively difficult to set to the target voltage by the discharging unit 16.

[0057] On the other hand, according to the present disclosure, the voltage Vbl on the bit line BL can be quickly and appropriately set to the target voltage Vcg-Vtm by the discharge unit 16 and the charge unit 17. Therefore, it is possible to accelerate the writing of data to the memory cell 11. In particular, stable writing and acceleration in MLC, in which the writing time tends to be shortened by continuous writing operations, can be achieved.

[0058] <Modification example>

[0059] exist Figure 1 In the example of FIG. 1 , an explanation is given of a configuration in which one charging unit 17 is provided for a plurality of bit lines. Figure 6 , an explanation will be given of a configuration in which one charging unit 17A is provided for each bit line. Figure 6 is a block diagram showing a configuration example of a semiconductor memory device according to an embodiment.

[0060] exist Figure 1 In the example of , the WG polycrystalline transistor of the charging unit 17 needs to be larger than the selection gate CG of the memory cell 11 because it is shared by a plurality of memory cells. Therefore, even if the WG polycrystalline transistor of the charging unit 17 is manufactured by the same method as the selection gate CG, there is a possibility that the characteristics may be slightly different due to the size being larger than the selection gate CG.

[0061] exist Figure 6 In the example of , since the same object as the memory unit 11 can also be used as a component of the charging unit 17A, the characteristic difference due to the different sizes can be reduced. Figure 6 In the example, Figure 1Compared to the example of FIG. 1 , n dummy cells are provided for each of one or more bit lines, and thus the size of the entire semiconductor memory device 10 can be increased.

[0062] <<Modify the example configuration>>

[0063] exist Figure 6 The same reference numerals are used for Figure 1 In the following, the same configuration as in the example above is explained to avoid duplication of description. Figure 6 The configuration and operation in Figure 1 The different parts in.

[0064] exist Figure 6 In the example, Figure 1 , it has a charging unit 17A that is not connected to the bit line BL through the switch 13, instead of the charging unit 17 connected to the bit line BL through the switch 13.

[0065] The charging unit 17A has the same mechanism as the memory unit 11, and has n (multiple) dummy cells that are not used for data recording. Here, by having n dummy cells, the current capacity CAc' of the charging unit 17A is higher than the current capacity CAd of the discharge unit 16 (CAc'>CAd). Figure 1 The same example as the following inequality (2) holds. CAc'>CAd>>CAh...(2)

[0066] The current capacity CAh of the extraction unit 15 is equal to the current Ids (eg, 1.3 μA) flowing from the source S side to the drain D side during writing of the memory cell 11 , so CAc′=CAh×n.

[0067] <<Modify the example operation>>

[0068] and Figure 1 Compared to the operation of the example in , when transitioning to stage 2, the operation of the modified example is different from Figure 4 In the modified example, Figure 4 In step S4 in FIG. 1 , the control unit 12 inputs a pulse signal (one-shot signal) of a specific time length (width) to the discharge unit 16 and (almost simultaneously) turns on the charge unit 17A for a specific time length.

[0069] By turning on the charging unit 17A, a path is created that allows a voltage of about Vcg-Vtm to be applied to the bit line BL. As a result, when the charging unit 17A is turned on, if the voltage Vbl on the bit line BL drops to about Vcg-Vtm, current is supplied from the n dummy cells to the bit line BL.

[0070] As in Figure 1 In the example of FIG. 1 , the current capacity CAc′ of the charging unit 17A is higher than the current capacity CAd of the discharging unit 16 (CAc′>CAd), which quickly stabilizes the voltage Vbl on the bit line BL to about Vcg-Vtm. This can reduce undershoot.

[0071] Although the invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the embodiments that have been described, and it goes without saying that various modifications can be made without departing from the gist thereof.

Claims

1. A semiconductor memory device, comprising: a memory cell having a gate electrode including a select gate and a memory gate, a source line connected to a source, and a bit line connected to a drain; a pull-out circuit configured to pull out a current flowing from the source side to the drain side during writing from the bit line to the memory cell; a discharge circuit configured to pass a current higher than that of the pull-out circuit and reduce a voltage of the bit line; a charging circuit configured to pass a current with a higher capability than the discharge component and to apply a voltage to the bit line; as well as The control circuit is configured to, when starting to write to the memory cell, reduce the voltage of the bit line through the discharge circuit and apply a voltage to the bit line through the charge circuit.

2. The semiconductor memory device according to claim 1, The control circuit is configured to apply a power supply voltage to the bit line before starting to write to the memory cell, and is configured to stop applying the power supply voltage to the bit line when starting to write to the memory cell, and is configured to set the voltage of the bit line to a value corresponding to a value obtained by subtracting the gate threshold voltage of the selection gate from the voltage applied to the selection gate through the discharge circuit and the charging circuit.

3. The semiconductor memory device according to claim 1, wherein the charging circuit includes the same gate threshold voltage as the select gate, and applies to the bit line the same voltage as the voltage applied to the bit line by the select gate.

4. The semiconductor memory device according to claim 3, The charging circuit includes the same structure as the selection gate and includes an NMOS transistor that is larger than the selection gate.

5. The semiconductor memory device according to claim 3, The charging circuit includes the same mechanism as the memory cell and includes a plurality of dummy cells not used for data recording.

6. The semiconductor memory device according to claim 1, The memory cell includes a plurality of levels for the charge to be stored, and includes a multi-level cell configured to record more than one bit of information by taking three or more different states.

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