Test equipment and memory test method
By designing a test device that simulates the electrical characteristics of memory particles, the problems of signal delay, impedance discontinuity and trace residual pile reflection in DDR memory signal test are solved, and more accurate and stable memory signal testing is achieved.
Patent Information
- Application Number
- CN202411649503.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-03-11
AI Technical Summary
The prior art has problems such as signal delay, impedance discontinuity and trace residual pile reflection in DDR memory signal testing, resulting in inaccurate test results and poor signal quality.
A test device is designed, which includes an analog circuit, a connection path and a signal measurement interface, which is used to simulate the electrical characteristics of memory particles, a connection path is used to receive and transmit memory test signals, and a signal measurement interface is used to send signals to a signal measurement tool. Through a circuit structure design similar to the memory running device, ensure that the test signal is similar to the memory signal and improve the test accuracy.
By designing the test equipment with a circuit structure similar to the memory running device, we ensure the stability and accuracy of the memory test signal, avoid signal reflection and impedance mutation, and improve the accuracy and efficiency of DDR memory signal testing.
Smart Images
Figure CN119601071A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of computer technology, and in particular to a testing device and a memory testing method. Background Art
[0002] With the improvement of computing power of computer equipment, DDR (Double Data Rate) memory technology is widely used in the design of server, workstation and consumer electronics products. In order to ensure the normal use of DDR memory during the operation of computer equipment, how to improve the accuracy of memory signal testing has become a problem that technicians in this field need to solve urgently. Summary of the invention
[0003] In view of this, embodiments of the present application provide a testing device and a memory testing method to improve the accuracy of memory signal testing.
[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:
[0005] The embodiment of the present application provides a testing device for testing a memory path; the testing device comprises:
[0006] An analog circuit, wherein the analog circuit is used to simulate the electrical characteristics of the memory particles;
[0007] A connecting path connected to the first memory path, used for receiving a memory test signal through the first memory path, and transmitting the memory test signal to the analog circuit and the signal measurement interface;
[0008] A signal measurement interface is used to send the memory test signal to a signal measurement tool so that the signal measurement tool can determine the signal state of the memory test signal, and the signal state is used to indicate whether the first memory path is normal; wherein the memory test signal fans out to the signal measurement interface.
[0009] Optionally, the analog circuit includes:
[0010] At least one terminal resistor, used to simulate the electrical characteristics of memory particles;
[0011] At least one terminal resistance switch corresponds to the terminal resistance one by one and is used for controlling the connection of the terminal resistance.
[0012] Optionally, the signal state is reflected by an eye diagram;
[0013] The number of the terminal resistors that are turned on affects the signal state of the memory test signal.
[0014] Optionally, the signal measurement tool interface includes: an SMA radio frequency connector.
[0015] Optionally, also include:
[0016] A current limiting resistor is arranged between the connection path and the signal measurement interface;
[0017] The memory test signal includes: a pseudo-random binary sequence signal, a zeroth value signal, a first value signal, or a zeroth value and first value alternating signal.
[0018] The present application also provides a testing system, including:
[0019] A processor, wherein the processor is used to control the memory;
[0020] A memory path, the memory path comprising a first memory path for connecting the processor and a test device, and a second memory path for connecting the processor and a memory;
[0021] The test device as described above is connected to the processor, receives the memory test signal of the processor through the first memory path, and is used to test the first memory path;
[0022] The memory is connected to the processor and receives and processes the memory working signal of the processor through a second memory path.
[0023] Optionally, also include:
[0024] Baseboard; the baseboard includes: a processor socket for arranging a processor;
[0025] A plurality of memory slots, used for setting memory and test equipment; the plurality of memory slots include: a memory slot for setting the test equipment, and a memory slot for setting the memory;
[0026] The memory slot is connected to the processor slot via a memory path, and the memory path is arranged on the substrate.
[0027] The present application also provides a memory testing method running on a processor, including:
[0028] In response to a memory test instruction, a memory test signal is sent to a test device through a first memory path so as to determine a signal state of the memory test signal, wherein the signal state is used to indicate whether the first memory path is normal; wherein the test device is the test device described in the above item;
[0029] In response to the memory operation instruction, a memory operation signal is sent to the memory through the second memory path, so that the memory performs the memory operation based on the memory operation signal.
[0030] Optionally, the step of sending a memory test signal to a test device through a first memory path in response to a memory test instruction includes:
[0031] In response to a memory test instruction, a first memory path is selected from the memory paths, and a memory test signal is sent to a test device through the first memory path; wherein the first memory path is arranged on a substrate.
[0032] Optionally, the step of sending a memory working signal to the memory through the second memory path in response to the memory working instruction so that the memory performs the memory working based on the memory working signal includes:
[0033] In response to the memory work instruction, a second memory path is selected from the memory paths, and a memory test signal is sent to the test device through the second memory path; wherein the second memory path is arranged on the substrate.
[0034] Optionally, the signal state is reflected by an eye diagram;
[0035] The parameters of the eye diagram include the eye height and the eye width for obtaining the eye diagram.
[0036] Optionally, the test device further includes at least one terminal resistor and at least one terminal resistor switch;
[0037] The number of the terminal resistors that are turned on affects the signal state of the memory test signal. Optionally, the method further includes:
[0038] Control whether the terminal resistance switch is turned on, adjust the number of the terminal resistances turned on to adjust the size of the terminal resistance value, until the eye diagram quality reaches the preset requirements. An embodiment of the present application also provides a storage medium, which stores a design program of a chip, and when the design program is executed, the memory test method as described above is implemented.
[0039] The test device provided in the embodiment of the present application is used to test a memory path; the test device includes: an analog circuit, which is used to simulate the electrical characteristics of memory particles; a connecting path, which is connected to a first memory path, and is used to receive a memory test signal sent from a processor through the first memory path, and transmit it to the analog circuit and a signal measurement interface; a signal measurement interface, which is used to send the memory test signal from the first memory path to a signal measurement tool, so that the signal measurement tool determines the signal state of the memory test signal, and the signal state is used to indicate whether the first memory path is normal; wherein the memory test signal fans out to the signal measurement interface.
[0040] It can be seen that by designing the test equipment using a circuit structure similar to the circuit of the memory operation device, the memory test signal received by the test equipment during the memory test process can be the memory signal when the memory operation device is running, which can ensure that the memory test signal is similar to the memory signal, thereby improving the test accuracy. Then, by sending the memory test signal to the oscilloscope used for the test through the oscilloscope interface of the fanned-out memory circuit, the signal reflection caused by outputting the memory test signal to the oscilloscope can be avoided, thereby avoiding the deterioration of the signal quality in the circuit caused by the test equipment, thereby enhancing the stability of the memory test signal output to the signal measurement tool and improving the accuracy of the memory signal test. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.
[0042] Figure 1 It is a structural schematic diagram of a DDR test device;
[0043] Figure 2 It is a structural schematic diagram of another DDR test equipment;
[0044] Figure 3 It is a structural schematic diagram of another DDR test equipment;
[0045] Figure 4 A schematic diagram of the circuit structure of a test system using the test equipment provided in an embodiment of the present application for testing;
[0046] Figure 5 A schematic diagram of the circuit structure of the test equipment provided in the embodiment of the present application;
[0047] Figure 6 A schematic diagram of the structure of a memory test system provided in an embodiment of the present application;
[0048] Figure 7 A flowchart of a memory testing method provided in an embodiment of the present application;
[0049] Figure 8 Another flowchart of the memory testing method provided in an embodiment of the present application. DETAILED DESCRIPTION
[0050] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0051] DDR memory technology is widely used in various computer devices, and the debugging and testing of DDR signals is very important for the use of DDR memory. A DDR memory signal test device, such as Figure 1 As shown, the CPU Memory controller (memory controller) 403 sends a memory test signal to the memory 10 through the mainboard 404, and the signal test point 104 is brought out by welding the interposer (intermediary layer or plug-in board) 103 between the PCB (Printed Circuit Board) in the memory and the storage particles 102, and then the test probe 106 is connected to the signal test point 104 and introduced into the test equipment oscilloscope 105 to measure the electrical characteristics of the signal.
[0052] The above-mentioned memory signal test equipment introduces an interposer to transmit memory test signals to the test equipment oscilloscope, which causes the circuit of the original memory signal line to change. That is, in order to set the interposer on the substrate, it is necessary to fix the interposer by welding, thereby adding a solder ball 107 for BGA (Ball Grid Array) packaging to the circuit of the memory signal line, resulting in a sudden change in signal impedance. At the same time, the setting of the interposer also introduces a signal via 108 in the interposer into the circuit of the memory signal line. The signal via 108 also causes a sudden change in signal impedance, increases signal reflection, and then increases signal loss. The signal line 109 makes the signal routing from the memory controller to the memory particle have an additional fork, which is also called a routing stub. The introduction of the routing stub will also increase reflection, resulting in further deterioration of the signal quality that finally reaches the test equipment oscilloscope 105.
[0053] In addition, the test probe 106 is connected to the test point 104 by welding, which takes a long time to connect. The signal line 109 stub between 106 and the test point 104 is further lengthened, resulting in further increase in signal reflection, and the signal quality reaching the test equipment oscilloscope 105 becomes worse. Therefore, the above test equipment test has reflection not only at the terminal of the signal, but also in the middle of the link, resulting in inaccurate test results. It will also deteriorate the signal, causing the system to work unstably or even crash.
[0054] Furthermore, as the DDR signal rate increases, for example, when the rate reaches 4000MT / s, the impact of the above-mentioned test equipment on signal integrity will also increase, resulting in an increasing probability of system instability or even system crash.
[0055] Another DDR test structure, such as Figure 2 As shown, the signal vias of the memory module itself are used for signal testing, as follows Figure 2 As shown. The memory stick is a single-sided soldered particle, and the signal via 302 on the memory stick itself reaches the bottom surface 304 of the memory stick 303 and the soldered probe is connected to the oscilloscope for signal measurement. However, if the memory stick is a double-sided soldered particle, that is, memory particles are arranged on both sides of the PCB board, the DDR test structure cannot be soldered to the probe of the oscilloscope. In addition, if the DDR rate is too high, the memory stick 303 cannot be back-drilled to obtain a via. At the same time, traditional probe welding leads to complex test point procedures and low test efficiency.
[0056] A DDR test device, such as Figure 3 As shown, a first-level module interposer fixture is added to the memory slot for measurement. By adding a first-level PCB board 3 to fan out the measuring point 6, and welding a probe at the measuring point 6 to connect to the oscilloscope for signal measurement, the memory stick is inserted in the memory slot 1, and the gold finger 4 is set on the memory slot on the substrate. In this way, after the introduction of the first-level connector and PCB, the original signal link is completely changed, resulting in inaccurate and unreliable signal test results, which can only be used as a reference for protocol testing.
[0057] Based on the above description, it is urgently necessary to invent a DDR test solution that can solve signal problems such as signal delay, impedance discontinuity, and large reflection of wiring stubs caused by setting an interposer in signal testing.
[0058] To solve the above problems, the embodiment of the present application provides a test device, which can test the DDR without affecting the normal operation of the processor and DDR by designing the test device with a circuit structure similar to that of the memory operation device. As an optional implementation, Figure 4 The schematic diagram of the structure of the test equipment provided in the embodiment of the present application is shown. Figure 4 As shown, the test device 500 provided in the embodiment of the present application is used to test the memory path 521, and the test device 500 includes the following structure.
[0059] The simulation circuit 510 is used to simulate the electrical characteristics of the memory particles.
[0060] It should be noted that, in order to simulate the electrical characteristics of memory particles, the analog circuit 510 needs to be designed based on existing memory particles. Figure 5 .like Figure 5 As shown, the DRAM particles include multiple terminal resistors 511 (ODT, On-Die Termination), multiple terminal resistor switches 512, and a signal processing module 513. The multiple terminal resistors 511 and the multiple terminal resistor switches 512 cooperate with each other to provide the required terminal resistance value for the signal processing module 513. The terminal resistance value is used to match the characteristic impedance of the transmission circuit line, so that the signal can be effectively terminated at the end of the circuit line, and prevent signal reflection at the end of the circuit line from interfering with signal transmission.
[0061] Accordingly, the analog circuit 510 is to simulate the electrical characteristics of the memory particles and needs to have a circuit structure similar to the above-mentioned DRAM particles. Figure 5 As shown, since the analog circuit 510 is only used to simulate electrical characteristics and does not need to actually process the received signal, the DRAM particles can be omitted, and only the bit lines connected to the DRAM particles are retained to ensure that the electrical characteristics of the analog circuit 510 are not changed. The terminal resistor is a resistor used to reduce reflection and crosstalk in high-speed signal transmission, which can improve signal integrity and data transmission reliability. Therefore, the terminal resistor and the terminal resistor switch have a greater impact on the DDR signal during use and are therefore retained.
[0062] Further, such as Figure 5 As shown, in an optional implementation, the simulation circuit 510 includes: at least one terminal resistor 511, used to simulate the electrical characteristics of the memory chip; at least one terminal resistor switch 512, corresponding to the terminal resistor 511, used to control the connection of the terminal resistor 511.
[0063] It should be noted that one terminal resistor 511 and one terminal resistor switch 512 are connected to form a group, and multiple groups of terminal resistors 511 and terminal resistor switches 512 are connected in parallel between the connection path 520 and the bit line of the analog circuit 510. When the terminal electrical value required by the analog circuit 510 changes, the number of the terminal resistors 511 connected to the analog circuit 510 is adjusted by closing or opening the terminal resistor switch 512 to change the terminal resistance value.
[0064] Please continue to refer to Figure 4The test device provided in the embodiment of the present application also includes a connecting path 520 connected to the first memory path 5211, for receiving a memory test signal through the first memory path 5211, and transmitting the memory test signal to the analog circuit 510 and the signal measurement interface 530.
[0065] It should be noted that the first memory path 5211 is a signal path outside the test device provided in the embodiment of the present application, which is used to connect the test device to the upstream device of the test device, and is used to transmit memory test signals between the test device and the upstream device of the test device. The connection path 520 is used to transmit the memory test signal transmitted in the first memory path 5211 to other modules in the test device.
[0066] The signal measurement interface 530 is used to send the memory test signal from the first memory path 5211 to the signal measurement tool 540 so that the signal measurement tool 540 determines the signal state of the memory test signal, and the signal state is used to indicate whether the first memory path 5211 is normal. The memory test signal fans out to the signal measurement interface 530.
[0067] It should be noted that the "fan-out" refers to the process in which an input signal is distributed to multiple output channels or devices, and is usually used to describe data distribution and transmission in a computer system. For example, it can represent a single router, switch or server sending data to multiple clients through multiple physical connections. This method enables multiple terminal devices to obtain data from a single data source at the same time, and supports synchronous data transmission and efficient capture of various types of information. Through the fan-out setting method, the connection path 520 can simultaneously send the same memory signal to the analog circuit 510 and the signal measurement interface 530, thereby ensuring that the memory test signal transmitted to the signal measurement tool 540 via the signal measurement interface 530 is exactly the same as the memory test signal transmitted to the analog circuit 510, thereby ensuring the accuracy of the signal test.
[0068] Furthermore, the circuit structures of the analog circuit 510, the connection path 520, and the signal measurement interface 530 are as follows: Figure 6 As shown, the memory test signal of the connection path 520 fans out to the connection path 520 and the signal measurement interface 530. Figure 5 The memory 400 shown in the figure also includes a diode 514 of a fan-out connection path 520. The diode 514 is used to control the switch of the memory 400 and the terminal resistance switch.
[0069] As for the test equipment, since the test equipment does not need to process the memory test signal and the test equipment needs to remain turned on throughout the test process, the test equipment provided in the embodiment of the present application does not need to be controlled by the diode 514. At the same time, in the memory 400, since the memory test signal of the connection path 520 is fanned out to the diode 514, the direct use of the signal measurement interface 530 to replace the diode 514 can transmit the memory signal to the signal measurement tool 540 without changing the internal circuit structure of the memory 400.
[0070] In this way, by designing the test equipment using a circuit structure similar to the circuit of the memory operation device, the memory test signal received by the test equipment during the memory test process can be the memory signal when the memory operation device is running, which can ensure that the memory test signal is similar to the memory signal, thereby improving the test accuracy. Then, by sending the memory test signal to the oscilloscope used for the test through the oscilloscope interface of the fanned-out memory circuit, the signal reflection caused by outputting the memory test signal to the oscilloscope can be avoided, thereby avoiding the deterioration of the signal quality in the circuit caused by the test equipment, thereby enhancing the stability of the memory test signal output to the signal measurement tool and improving the accuracy of the memory signal test.
[0071] Furthermore, in an optional implementation, the signal measurement interface 530 includes: an SMA RF connector. The SMA RF connector is a standard small threaded coaxial connector, with a female interface at one end and a male interface at the other end to achieve matching plugging and unplugging. By using an SMA RF connector instead of a welding probe, when connecting the signal measurement tool 540, it can be completed only by plugging and unplugging the SMA RF connector, which greatly reduces the time used compared to welding.
[0072] For example, for a memory 400 with 8 test points, it takes about 20 minutes to solder one test point when using a soldering probe, and then about 240 minutes to solder and test. If the SMA RF connector only takes 90 minutes to plug and unplug, it can be seen that the SMA RF connector can significantly improve the test efficiency.
[0073] Furthermore, in an optional implementation, the embodiment of the present application also provides: a current limiting resistor 531, which is arranged between the connection path and the signal measurement interface. By setting the current limiting resistor 531, the resistance of the original diode 514 can be simulated to eliminate the influence of the replacement of the diode 514 on the electrical characteristics in the test equipment, and at the same time, the circuit safety of the signal measurement interface 530 and the signal measurement tool 540 can be protected.
[0074] Furthermore, in an optional implementation, the signal measurement tool 540 includes an oscilloscope. It should be noted that during the test process, the test device usually needs to detect the transmission quality of the signal, and whether the signal content of the memory test signal is correct cannot obtain the test result more intuitively and efficiently. If the memory test signal is converted into an image, the signal state of the memory test signal can be made more intuitive.
[0075] Furthermore, in an optional implementation, the signal state is reflected by an eye diagram. The eye diagram is a graph displayed by accumulating the memory test signal on an oscilloscope, which contains rich information. The influence of the memory test signal inter-symbol crosstalk and noise can be observed from the eye diagram, which reflects the overall characteristics of the memory test signal and facilitates the estimation of the transmission quality of the memory path.
[0076] Furthermore, in an optional implementation, the terminal resistor 511 affects the signal state of the memory test signal. In the memory 400, the terminal resistor 511 is a controllable resistor built into the memory chip, which is used to reduce reflections and crosstalk in high-speed signal transmission, improve signal integrity and reliability of data transmission. Therefore, during the memory test, in addition to testing whether the memory path 521 is good, it is also necessary to adjust the terminal resistor 511 at the same time to find the terminal resistor value that best optimizes the memory test signal. In addition, based on the use of eye diagrams and debugging of memory test signals, debugging can be more intuitive and efficient on the basis of smaller inter-code crosstalk.
[0077] Furthermore, in an optional implementation, the memory test signal includes: a pseudo-random binary sequence signal, a zeroth value signal, a first value signal, or a zeroth value and first value alternating signal. The above signals are all common signals in memory testing, and using the eye diagram of the above signals can provide a clearer eye diagram.
[0078] The embodiment of the present application also provides a test system, which uses the test device as described above to test the DDR without affecting the normal operation of the processor and the DDR. As an optional implementation, Figure 6 FIG. 1 shows a schematic diagram of the structure of the test system provided in the embodiment of the present application. Figure 6 As shown, the test system provided in the embodiment of the present application includes the following structure.
[0079] The processor 600 is used to control the memory 810 .
[0080] The memory path 521 includes a first memory path 5211 for connecting the processor 600 and the test device 500 , and a second memory path 5212 for connecting the processor 600 and the memory 810 .
[0081] The test device 500 as described above is connected to the processor 600 , and receives the memory test signal of the processor 600 through the first memory path 5211 , so as to test the memory path 5211 .
[0082] The memory 810 is connected to the processor 600 , and receives and processes the memory working signal of the processor 600 through the second memory path 5212 .
[0083] It should be noted that the memory test system using the test device is as follows Figure 6 As shown, in an optional implementation, the processor 600 generally includes a CPU for controlling the use of a memory 810. The processor 600 and the memory 810 are arranged on a substrate 800. A memory path 521 is arranged on the substrate 800 for connecting the memory 810 and the processor 600. The memory path 521 includes a first memory path 5211 for connecting the processor 600 and the test device 500, and a second memory path 5212 for connecting the processor 600 and the memory 810.
[0084] When using the test device 500 as described above to perform a memory test on the substrate 800 provided with the processor 600, the test device needs to be set on the first memory path 5211 to be tested. At the same time, the memory 810 is set on the second memory path 5212 that is not tested, so that the processor 600 can work normally. After the test device 500, the memory 810, and the processor 600 are set as described above, the following can be obtained: Figure 7 A memory testing system using the testing device is shown.
[0085] Furthermore, in an optional implementation, the test system provided in the embodiment of the present application further includes:
[0086] Base plate 800 ; the base plate 800 comprises: a processor socket 820 for arranging the processor 600 .
[0087] A plurality of memory slots 830 are used to set the memory 810 and the test equipment 500; the plurality of memory slots include: a memory slot 831 for setting the test equipment, and a memory slot 832 for setting the memory. The memory slot 830 is connected to the processor slot 820 via a memory path 521, and the memory path 521 is set on the substrate 800.
[0088] The embodiment of the present application also provides a memory testing method, which runs on a processor and uses the above-mentioned testing device to test the DDR without affecting the normal operation of the processor and the DDR. As an optional implementation, Figure 7FIG. 1 is a flow chart of a memory testing method provided by an embodiment of the present application. Figure 7 As shown, the memory testing method provided in the embodiment of the present application includes the following steps.
[0089] Step S10: In response to the memory test instruction, a memory test signal is sent to a test device through a first memory path to determine a signal state of the memory test signal. The signal state is used to indicate whether the first memory path is normal; wherein the test device is the test device described above.
[0090] Step S20: In response to the memory working instruction, a memory working signal is sent to the memory through the second memory path, so that the memory performs the memory working based on the memory working signal.
[0091] Furthermore, in an optional implementation, when the memory test system is used to perform in-memory testing, the processor is first started, and at this time, the memory ensures the normal operation of the processor through the second memory path. The processor will identify and determine the first memory path provided with the test device, and the second memory path provided with the memory. Then, when the processor obtains a memory working instruction, in response to the memory working instruction, the processor sends a memory working signal to the second memory path, which is then transmitted to the memory, and then the memory performs memory work normally based on the memory working signal.
[0092] Afterwards, when the processor formally performs a memory test, in response to a memory test instruction, the processor sends a memory test signal to the test device. The memory test signal is transmitted to the test device via the second memory path, and then transmitted to the signal measurement tool via the connection path and signal measurement interface in the test device. Finally, based on the eye diagram displayed by the signal measurement tool, it is determined whether the signal state of the memory test signal is good, and then whether the first memory path is normal.
[0093] It can be seen that by designing the test equipment using a circuit structure similar to the circuit of the memory operation device, the memory test signal received by the test equipment during the memory test process can be the memory signal when the memory operation device is running, which can ensure that the memory test signal is similar to the memory signal, thereby improving the test accuracy. Then, by sending the memory test signal to the oscilloscope used for the test through the oscilloscope interface of the fanned-out memory circuit, the signal reflection caused by outputting the memory test signal to the oscilloscope can be avoided, thereby avoiding the deterioration of the signal quality in the circuit caused by the test equipment, thereby enhancing the stability of the memory test signal output to the signal measurement tool and improving the accuracy of the memory signal test.
[0094] Furthermore, in the memory test system as described above, a test device and a memory are provided at the same time, so the memory upstream device needs to select a correct device before sending the memory working signal and the memory test signal.
[0095] Specifically, Figure 8 As shown, in an optional implementation, the step S10 includes a step S11: in response to a memory test instruction, selecting a first memory path from the memory paths, and sending a memory test signal to a test device through the first memory path. The first memory path is disposed on a substrate.
[0096] The step S20 includes a step S21: in response to the memory work instruction, selecting a second memory path from the memory paths, and sending a memory test signal to the test device through the second memory path, wherein the second memory path is arranged on the substrate.
[0097] Further, as mentioned above, the content displayed by the signal testing tool is an eye diagram. Therefore, in an optional implementation, the signal state is reflected by an eye diagram; the parameters of the eye diagram include the eye height and eye width of the eye diagram. It should be noted that in the eye diagram, the eye height (Eye Height) and eye width (Eye Width) of the eye diagram are data used to evaluate the quality of the signal and the integrity of the transmission. The eye height is the vertical height of the opening in the eye diagram, which indicates the noise margin of the signal. The larger the eye height, the more resistant the signal is to noise and the more reliable the data transmission is. The eye width is the horizontal width of the opening in the eye diagram, which indicates the jitter margin of the signal. The larger the eye width, the better the stability of the signal in timing, and the more accurately the data can be read at the right time.
[0098] Furthermore, in an optional implementation, the test device also includes at least one terminal resistor and at least one terminal resistor switch. The number of the terminal resistors that are turned on affects the signal state of the memory test signal. Among them, the at least one terminal resistor is in a parallel relationship, and the magnitude of the terminal resistance value is the resistance value of the at least one terminal resistor in parallel after the at least one terminal resistor is connected in parallel. The magnitude of the terminal resistance value is used to adjust the eye diagram quality of the memory path data signal and improve the signal transmission stability of the link.
[0099] For further information, please continue to refer to Figure 6 In an optional implementation, the memory testing method provided by the present application also includes step S30: controlling whether the terminal resistance switch is turned on, adjusting the number of the terminal resistances turned on to adjust the size of the terminal resistance value until the eye diagram quality meets the preset requirements.
[0100] It should be noted that, since there are terminal resistors in the test device, it can be seen from the above content that the number of the terminal resistors that are turned on affects the signal state of the memory test signal. Therefore, the terminal resistors need to be adjusted during the memory test to obtain the optimal eye diagram. Furthermore, adjusting the resistance value of the terminal resistor requires turning on or off the terminal resistor switch, and the terminal resistor switch is controlled by the internal chip of the memory, or by adjusting the internal chip by the upstream device of the memory. However, inside the test device, in order to simplify the circuit structure, there is no internal chip, so the upstream device of the memory and the test device cannot control the terminal resistor switch. Therefore, the control of the terminal resistor switch can only be manually controlled from the outside of the test chip.
[0101] Adjusting the resistance value of the terminal resistor can adjust the eye diagram quality of the memory path data signal and improve the signal transmission stability of the link. Since the eye height and eye width are values representing the eye diagram attributes, the optimal eye diagram is obtained, that is, the optimal eye height and eye width of the eye diagram are obtained. The optimal eye height and eye width need to maximize the opening of the eye diagram so that the signal has sufficient margin in noise and timing. Therefore, the preset requirement is that when the total value of the eye height and eye width is the maximum value, the signal state corresponding to the eye diagram is most accurate and stable.
[0102] An embodiment of the present application further provides a storage medium, wherein the storage medium stores a design program of a chip, and when the design program is executed, the memory testing method as described above is implemented.
[0103] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.
Claims
1. A testing device, characterized in that: Used to test memory paths; the testing equipment comprises: An analog circuit, wherein the analog circuit is used to simulate the electrical characteristics of the memory particles; a connecting path connected to the first memory path, used to receive a memory test signal through the first memory path, and transmit the memory test signal to the analog circuit and the signal measurement interface; A signal measurement interface is used to send the memory test signal to a signal measurement tool so that the signal measurement tool can determine a signal state of the memory test signal, wherein the signal state is used to indicate whether the first memory path is normal; wherein the memory test signal fans out to the signal measurement interface.
2. The test device according to claim 1, characterized in that The analog circuit comprises: At least one terminal resistor, used to simulate the electrical characteristics of memory particles; At least one terminal resistance switch corresponds to the terminal resistance one by one and is used for controlling the connection of the terminal resistance.
3. The test device according to claim 2, characterized in that The signal state is reflected by an eye diagram; The number of the terminal resistors that are turned on affects the signal state of the memory test signal.
4. The testing device according to claim 1, characterized in that The signal measurement tool interface includes: an SMA radio frequency connector.
5. The testing device according to claim 1, characterized in that Also includes: A current limiting resistor is arranged between the connection path and the signal measurement interface; The memory test signal includes: a pseudo-random binary sequence signal, a zeroth value signal, a first value signal, or a zeroth value and first value alternating signal.
6. A testing system, characterized in that: include: A processor, wherein the processor is used to control the memory; A memory path, the memory path comprising a first memory path for connecting the processor and a test device, and a second memory path for connecting the processor and a memory; The test device according to any one of claims 1 to 5, connected to the processor, receiving a memory test signal of the processor through a first memory path, and used for testing the first memory path; The memory is connected to the processor and receives and processes the memory working signal of the processor through a second memory path.
7. The test system according to claim 6, characterized in that: Also includes: substrate; The substrate comprises: a processor socket for arranging a processor; A plurality of memory slots, used for setting memory and test equipment; the plurality of memory slots include: a memory slot for setting the test equipment, and a memory slot for setting the memory; The memory slot is connected to the processor slot via a memory path, and the memory path is arranged on the substrate.
8. A memory testing method, characterized in that: Runs on a processor, including: In response to a memory test instruction, a memory test signal is sent to a test device through a first memory path so as to determine a signal state of the memory test signal, wherein the signal state is used to indicate whether the first memory path is normal; wherein the test device is a test device according to any one of claims 1 to 5; In response to the memory operation instruction, a memory operation signal is sent to the memory through the second memory path, so that the memory performs the memory operation based on the memory operation signal.
9. The memory testing method according to claim 8, characterized in that: The step of sending a memory test signal to a test device through a first memory path in response to a memory test instruction comprises: In response to a memory test instruction, a first memory path is selected from the memory paths, and a memory test signal is sent to a test device through the first memory path; wherein the first memory path is arranged on a substrate.
10. The memory testing method according to claim 8, characterized in that: The step of sending a memory working signal to the memory through the second memory path in response to the memory working instruction so that the memory performs the memory working based on the memory working signal comprises: In response to the memory work instruction, a second memory path is selected from the memory paths, and a memory test signal is sent to the test device through the second memory path; wherein the second memory path is arranged on the substrate.
11. The memory testing method according to claim 8, characterized in that: The signal state is reflected by an eye diagram; The parameters of the eye diagram include the eye height and the eye width for obtaining the eye diagram.
12. The memory testing method according to claim 11, characterized in that: The test device also includes at least one terminal resistor, and at least one terminal resistor switch; The number of the terminal resistors that are turned on affects the signal state of the memory test signal.
13. The memory testing method according to claim 12, characterized in that: Also includes: Controlling whether the terminal resistance switch is turned on, adjusting the number of the terminal resistances turned on to adjust the size of the terminal resistance value, until the eye diagram quality reaches a preset requirement.
14. A storage medium, characterized in that: The storage medium stores a design program of the chip, and when the design program is executed, the memory testing method as described in any one of claims 8 to 13 is implemented.