Chip thinning method

Abstract

The invention relates to a chip thinning method. The method comprises the following steps: providing a first polishing and grinding lining plate; a chip to be thinned is arranged on the first polishing and grinding lining plate; an accompanying chip structure is arranged on the first polishing and grinding lining plate, and the accompanying chip structure wraps the periphery of the to-be-thinned chip; the first polishing and grinding lining plate, the to-be-thinned chip and the accompanying chip structure serve as temporary assemblies in the thinning process, and thinning operation is conducted on the to-be-thinned chip; and after the thinning operation is completed, the to-be-thinned chip is separated from the first polishing and grinding lining plate. Damage to the to-be-thinned chip in the thinning process can be reduced, and the yield is improved.

Description

Technical Field

[0001] The invention relates to the field of chip manufacturing, and in particular to a chip thinning method. Background Art

[0002] In recent years, infrared detection technology has developed rapidly and is widely used in medical, meteorological and civil fields. The materials currently used in infrared detectors include but are not limited to InSb (indium antimonide), HgCdTe (mercury cadmium telluride), QWs (quantum dots) and InAs / GaSb type II superlattice.

[0003] The infrared detector chip adopts a hybrid structure, that is, the photosensitive chip and the readout circuit chip are prepared separately, and are interconnected by indium pillar flip-chip to form a detector hybrid chip. Infrared radiation irradiates the detector photosensitive chip in a back-incident manner. After the infrared light passes through the semiconductor material, it is absorbed by the photosensitive element of the photosensitive chip and converted into an electrical signal. After the conversion, amplification and noise removal of the readout circuit, the electrical signal output is realized. In order to achieve the maximum conversion output of the optical signal, the photosensitive chip needs to be thinned to a certain thickness. However, hard and brittle hybrid chips are prone to chip damage during the thinning process, resulting in a decrease in the yield rate. Summary of the invention

[0004] The purpose of the present invention is to provide a chip thinning method to solve the problem that the chip is easily damaged during the thinning process, resulting in a decrease in the yield rate.

[0005] The chip thinning method of the present invention comprises:

[0006] Providing a first polishing liner;

[0007] Placing the chip to be thinned on the first polishing liner;

[0008] A companion sheet structure is arranged on the first polishing liner, wherein the companion sheet structure covers the four sides of the chip to be thinned;

[0009] Using the first polishing liner, the chip to be thinned and the companion structure as temporary components in the thinning process, and performing a thinning operation on the chip to be thinned;

[0010] After the thinning operation is completed, the chip to be thinned is separated from the first polishing liner.

[0011] Optionally, the companion chip structure includes a liquid conducting channel, and the liquid conducting channel is used for allowing liquid to pass through during the grinding and polishing process to guide the liquid at the chip to be thinned outward.

[0012] Optionally, the accompanying sheet structure includes four accompanying strips, and the four accompanying strips are respectively arranged on four sides of the chip to be thinned; and there is a gap between each of the accompanying strips to serve as the liquid guiding channel.

[0013] Optionally, the cross-sectional width of the liquid-conducting channel is not greater than 3 mm.

[0014] Optionally, the chip to be thinned includes a circuit board and a chip wafer arranged on the circuit board;

[0015] The shape of the companion structure satisfies at least one of the following conditions:

[0016] The width of the companion structure is not less than one quarter of the length of the side of the chip wafer perpendicular to it;

[0017] The difference between the thickness of the companion chip structure and the chip to be thinned is in the range of 30 μm to 50 μm.

[0018] Optionally, before performing the thinning operation on the chip to be thinned, the method further includes:

[0019] Disposing a first protective layer on the circuit board, wherein the first protective layer covers the exposed area of ​​the circuit board and does not contact the chip wafer;

[0020] A second protective layer is arranged on the circuit board. The second protective layer is made of a material that is repellent to semiconductor materials. The second protective layer covers all exposed areas of the circuit board and the first protective layer.

[0021] Optionally, the step of providing a companion plate structure on the first polishing liner further comprises:

[0022] The bonding material is accumulated on the periphery of the companion sheet structure to form a reinforcement structure.

[0023] Optionally, the thinning operation on the chip to be thinned includes:

[0024] placing the temporary assembly on the second polishing lining;

[0025] The second polishing liner is arranged on the polishing equipment to pre-polish the chip to be thinned.

[0026] Optionally, after the pre-polishing of the chip to be thinned, the method further comprises:

[0027] Removing the temporary assembly from the second polishing liner as a whole;

[0028] The temporary assembly is placed in an etching solution to perform full surface etching on the chip to be thinned.

[0029] Optionally, after the temporary component is fully corroded, the method further comprises:

[0030] The temporary assembly is arranged on the third polishing lining plate;

[0031] The third polishing liner is arranged on the polishing equipment to carry out the subsequent polishing process.

[0032] The chip thinning method of the present invention forms a temporary assembly by placing the chip to be thinned on the first polishing liner. The temporary assembly is processed as a whole during the thinning process, so that the chip to be thinned is prevented from being repeatedly placed, bonded, and removed, etc., making it easier to operate during the thinning process, and reducing the risk of uneven bonding of the chip to be thinned during the thinning process, resulting in uneven grinding during thinning. The arrangement of the accompanying chip structure suppresses the warping of the chip to be thinned during the thinning process, avoids severe warping of the chip to be thinned, supports and disperses the polishing pressure, and reduces damage to the chip to be thinned. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a basic flow chart of the chip thinning method of this embodiment;

[0034] Figure 2 is a structural schematic diagram of the infrared detector chip of this embodiment;

[0035] Figure 3 A schematic diagram of providing a companion chip structure around the chip to be thinned in this embodiment;

[0036] Figure 4 Schematic diagram of the dimensions of the accompanying plate structure of this embodiment;

[0037] Figure 5 The detailed process diagram of the chip thinning method of this embodiment is shown in FIG. Figure 1 ;

[0038] Figure 6 The detailed process diagram of the chip thinning method of this embodiment is shown in FIG. Figure 2 ;

[0039] Figure 7 A schematic diagram of a complete process of an exemplary chip thinning method of this embodiment;

[0040] Figure 8 is a schematic diagram of an exemplary chip thinning process of this embodiment;

[0041] Description of reference numerals:

[0042] 10-chip to be thinned; 11-circuit board; 111-readout circuit; 112-indium column; 12-chip wafer; 121-photosensitive chip; 21-accompanying film structure; 211-first accompanying strip; 212-second accompanying strip; 22-liquid guide channel; 23-reinforcement structure; 24-first protective layer; 25-second protective layer; 30-first polishing lining; 40-second polishing lining. DETAILED DESCRIPTION

[0043] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0045] Embodiment 1:

[0046] This embodiment provides a chip thinning method, such as Figure 1 As shown, the chip thinning method of this embodiment includes but is not limited to the following steps:

[0047] S101, providing a first polishing lining plate;

[0048] The first polishing plate 30 in this embodiment is used as a temporary chip support carrier to provide support for the chip during the subsequent chip thinning process. The first polishing plate 30 can be made of the same material and structure as the polishing plate in the existing chip thinning process, such as glass, ceramic plate, etc.

[0049] S102, placing the chip to be thinned on the first polishing liner;

[0050] The chip to be thinned 10 and the first polishing liner 30 can be fixed by adhesive materials or the like. The chip to be thinned 10 can be a chip crystal, or a hybrid chip formed by a chip crystal and related circuits. The chip thinning method of this embodiment can be applied to various chip forms. Figure 2 As shown, taking a structure of an infrared detector chip as an example, the photosensitive chip 121 and the readout circuit 111 are prepared separately, and are flip-chip interconnected through the indium pillar 112 to form a detector hybrid chip. When thinning, the epitaxial part of the photosensitive chip 121 is thinned to a certain thickness to ensure the maximum conversion output of the optical signal. In this embodiment, the first polishing liner 30 and the chip to be thinned 10 remain connected during at least part of the chip thinning process.

[0051] S103, setting a companion sheet structure on the first polishing liner, wherein the companion sheet structure covers the four sides of the chip to be thinned;

[0052] The accompanying chip structure 21 can be understood as a structure that is arranged around the chip to be thinned 10 to support the chip to be thinned 10 and disperse the polishing pressure. The hybrid chip includes a multi-layer structure and a bonding material that connects these structures. The different thermal expansion coefficients between these structures make the hybrid chip prone to a certain degree of warping. This causes its surface to be in a non-ideal planar state, increasing the possibility of chip damage during the thinning process. The provision of the accompanying chip structure 21 suppresses the warping of the chip to be thinned 10 during the thinning process, avoids severe warping of the chip to be thinned 10, and supports and disperses the polishing pressure, reducing damage to the chip to be thinned 10.

[0053] S104, using the first polishing liner, the chip to be thinned, and the companion structure as temporary components in the thinning process, and performing a thinning operation on the chip to be thinned;

[0054] In this embodiment, the first polishing liner 30, the chip to be thinned 10 and the accompanying chip structure 21 form a temporary assembly, and the temporary assembly is processed as a whole during the thinning process. For example, before the processing is completed, the temporary assembly always remains in a fixed state and is not disassembled. As a larger whole, the temporary assembly avoids the chip to be thinned 10, which is a smaller individual, from being repeatedly placed, bonded, and removed, making it easier to operate during the thinning process, and reducing the risk that the chip to be thinned 10 may be unevenly bonded during this process, resulting in uneven grinding during thinning.

[0055] S105, after the thinning operation is completed, the chip to be thinned is separated from the first polishing liner;

[0056] After the chip 10 to be thinned is removed from the first polishing liner 30 , subsequent processing such as cleaning can be performed.

[0057] During the polishing process, polishing liquid is usually required to be added, and the polishing liquid may stay around the chip to be thinned 10, especially when the chip to be thinned 10 is a hybrid chip, the polishing liquid is easily gathered at the circuit board 11. In order to ensure that the polishing liquid can flow smoothly and avoid its accumulation affecting the process consistency, in some embodiments, the accompanying chip structure 21 also includes a liquid guide channel 22, which is used for the liquid in the polishing process to pass through so as to guide the liquid at the chip to be thinned 10 outward.

[0058] Of course, the function of the liquid guide channel 22 is not limited to this. In the thinning process, any link where liquid may be applied can prevent the accumulation of related liquid at the chip 10 to be thinned. For example, in some thinning processes, a corrosion process can be introduced, and the liquid guide channel 22 can also allow the corrosion liquid to circulate.

[0059] The accompanying plate structure 21 may be an integrated structure, and the liquid-conducting channel 22 may be a groove-shaped channel or a hole-shaped channel opened on the accompanying plate structure 21. The accompanying plate structure 21 may also include a plurality of separated parts, and in such an example, the liquid-conducting channel 22 may also be a gap portion separated between the accompanying plate structures 21. That is, the present embodiment does not limit the specific structure of the liquid-conducting channel 22.

[0060] like Figure 3 As shown, in some embodiments, the accompanying strip structure 21 includes four accompanying strips, and the four accompanying strips are respectively arranged on the four sides of the chip 10 to be thinned; there is a gap between each accompanying strip to serve as a liquid guide channel 22. The four accompanying strips can be in a bar shape, and are arranged to fit the four sides of the chip 10 to be thinned. The separated multiple accompanying strips are easier to process and better fit with the edges of the chip 10 to be thinned, providing more effective support. It is only necessary to control the position of the accompanying strips when setting the accompanying strips, so that gaps can be formed between the accompanying strips, so that the accompanying strip structure has a liquid guide channel 22. This also simplifies the shape of the accompanying strips themselves, and the manufacturing difficulty and cost are very low. In practical applications, the liquid guide channels 22 can be configured with four, or less than four, for example, only two are set.

[0061] In order to ensure that effective support is provided to the chip 10 to be thinned, in some embodiments, the cross-sectional width of the liquid-conducting channel 22 is not greater than 3 mm, such as 1 mm, 2 mm, etc. Of course, in order to ensure that various liquids can be discharged smoothly during the thinning process, the cross-sectional width of the liquid-conducting channel 22 can also be configured to be greater than 1 mm, that is, between 1 mm and 3 mm.

[0062] In order to provide better support and reduce negative impacts during the thinning process, the companion structure 21 can be configured to have a smaller width and be close to the thickness of the chip 10 to be thinned.

[0063] Exemplarily, the chip 10 to be thinned includes a circuit board 11 and a chip wafer 12 disposed on the circuit board 11. In order to better support the chip 10 to be thinned and reduce the impact on the thinning process, the companion structure 21 meets at least one of the following conditions:

[0064] Condition 1: The width of the companion structure 21 is not less than one-fourth of the length of the side of the chip wafer 12 perpendicular thereto;

[0065] like Figure 4 As shown, the companion structure 21 includes four companion strips, which are arranged along the side wall of the chip 10 to be thinned. In this embodiment, the side of the chip wafer 12 perpendicular to the companion structure 21 can also be understood as the side of the chip wafer 12 perpendicular to the length direction of the companion structure 21. For example, the side perpendicular to the first companion strip 211 is L1, and the side perpendicular to the second companion strip 212 is L2. Then the width a of the first companion strip 211 is not less than one-fourth of the side length A of L1 (a≥1 / 4A), and the width b of the second companion strip 212 is not less than one-fourth of the side length B of L2 (b≥1 / 4B).

[0066] Condition 2: The difference between the thickness of the companion structure 21 and the chip to be thinned 10 is within a range of 30 μm to 50 μm;

[0067] Setting the thickness of the companion structure 21 to be the same or similar to the thickness of the chip to be thinned 10 can improve the process consistency during the thinning process. It should be understood that when the chip to be thinned 10 is a hybrid chip, its thickness is the total thickness of the circuit board 11 and the chip crystal.

[0068] When the chip 10 to be thinned is a hybrid chip, in order to prevent the circuit board 11 from being damaged during the thinning process, the circuit board 11 of the chip 10 to be thinned may be protected. Figure 5 As shown, in some embodiments, before performing a thinning operation on the chip 10 to be thinned, the method further includes:

[0069] S201, disposing a first protective layer on the circuit board, wherein the first protective layer covers an exposed area of ​​the circuit board and does not contact the chip wafer;

[0070] The first protective layer 24 is used to protect the circuit board 11, especially the important parts of the circuit board 11. The first protective layer 24 can be made of a material with good adhesion to the circuit board 11 and coated by a special tool.

[0071] S202, setting a second protective layer on the circuit board, the second protective layer is made of a material that is repellent to the semiconductor material, and the second protective layer covers all exposed areas of the circuit board and the first protective layer;

[0072] The second protective layer 25 will not cover the sidewalls and surface of the semiconductor material due to its phobic nature, thus preventing the subsequent process from affecting the uniformity of the semiconductor material portion (i.e., the chip wafer 12 portion) due to the shielding of the protective layer. The double-layer protection of the first protective layer 24 and the second protective layer 25 can specifically protect the important parts of the circuit board 11 during the corrosion process, improve the protection strength, and reduce the problem of low yield rate caused by circuit damage.

[0073] In some embodiments, the step of providing the companion structure 21 on the first polishing liner 30 further includes: accumulating the adhesive material on the periphery of the companion structure 21 to form a reinforcement structure 23 .

[0074] A reinforcement structure 23 is formed on the periphery of the accompanying strip structure 21, that is, on the side away from the chip 10 to be thinned. The reinforcement structure 23 can increase the firmness of the accompanying strip structure and reduce the side corrosion effect during the corrosion process. The reinforcement structure 23 can be formed by the accumulation of adhesive materials such as adhesive wax and adhesive glue. After the adhesive wax, adhesive glue and other materials are accumulated, they are cured to form a reinforcement structure 23 with a certain strength.

[0075] In some thinning processes, a process of rough polishing, fine polishing and then chemical polishing is usually adopted. Among them, the rough polishing process refers to the use of abrasives with larger particle sizes for grinding and polishing; while the fine polishing process uses abrasives with smaller particle sizes to remove the process damage caused by the rough polishing process and achieve high-quality surface preparation. The above-mentioned polishing process mainly relies on the matching of polishing pressure, rotation speed and various parameters of the abrasive to achieve the thinning of the chip 10 to be thinned. The grinding head presses the chip 10 to be thinned and connected to the polishing liner on the grinding and polishing disc. By applying a certain pressure and a certain period of revolution and rotation, the semiconductor material is consumed under the combined action of physical grinding chips and chemical corrosion. There is a certain resistance between the pressing and grinding process and the chip 10 to be thinned itself. The chip 10 to be thinned usually needs to resist its own deformation and the stress caused by the mechanical grinding head, and is prone to damage. The chip thinning method mentioned above in this embodiment can suppress the deformation of the chip 10 to be thinned and reduce the possibility of damage by setting a companion sheet structure 21 to share the stress.

[0076] In some embodiments, Figure 6 As shown, the thinning operation of the chip 10 to be thinned includes:

[0077] S301, placing a temporary assembly on the second polishing liner;

[0078] The second polishing plate 40 can be made of the same material as or different from the first polishing plate 30 .

[0079] S302, placing a second polishing liner on the polishing equipment to pre-polish the chip to be thinned;

[0080] Continue to see Figure 6 As shown, after the chip 10 to be thinned is pre-polished, the following steps are also included:

[0081] S303, removing the temporary assembly from the second polishing liner as a whole;

[0082] S304, placing the temporary component into a corrosive solution, and performing full surface etching on the chip to be thinned;

[0083] Continue to see Figure 6 As shown, after the temporary components are fully corroded, it also includes:

[0084] S305, placing a temporary assembly on the third polishing lining;

[0085] In practical applications, the third polishing liner can be the second polishing liner 40. Of course, a new polishing liner can also be replaced. In this embodiment, unless otherwise stated or in conflict with the solution, the descriptions such as "first" and "second" are only used to distinguish objects with the same name in different steps or expressions, and do not represent other limitations.

[0086] S306, placing the third polishing liner on the polishing equipment to perform subsequent polishing process;

[0087] The subsequent polishing process can be divided into rough polishing, fine polishing and other processes such as cleaning.

[0088] For better understanding, the present embodiment further describes the thinning process of the chip thinning method of the present embodiment in combination with specific process examples and schematic diagrams. Figure 7 as well as Figure 8 , the thinning process includes:

[0089] S401, bonding the chip to be thinned to the first grinding and polishing liner;

[0090] like Figure 8 As shown in (a), the chip to be thinned 10 is bonded to the first polishing backing plate. The bonding material can be a bonding glue, which can be pre-coated on the first polishing backing plate. After the bonding glue is melted by high temperature, the chip to be thinned 10 is set on the first polishing backing plate for bonding and fixing.

[0091] S402, bonding a companion chip structure around the chip to be thinned;

[0092] like Figure 8 As shown in (b), the accompanying film structure 21 of this embodiment is as described above. Figure 4 As shown, four strips are included. The length of each strip can cover the side edge of the chip 10 to be thinned, but during bonding, a butt joint gap of less than 3 mm can be left as a liquid guide channel 22.

[0093] S403, forming a reinforcement structure outside the accompanying piece structure;

[0094] like Figure 8 As shown in (c), adhesive resin or resin wax or other materials may be added to the outside of the accompanying sheet structure 21 and cured to form a reinforcement structure 23.

[0095] S404, providing a first protective layer and a second protective layer;

[0096] like Figure 8 As shown in (d), the first adhesive is coated on the surface of the key protection area of ​​the circuit board 11 by a special tool, and is baked and cured to form a first protective layer 24. The second adhesive is coated on the surface of the circuit board 11 by a special tool, and covers the first protective layer 24, and is baked and cured to form a second protective layer 25, thereby achieving full circuit protection. The first adhesive is different from the second adhesive. For example, the first adhesive may have better adhesion or fit to the circuit board 11, providing more effective protection; the second adhesive will be made of a material that is repellent to semiconductor materials so that it will not be coated on the side walls and surface of the semiconductor material. The baking and curing method may be to heat the entire device on a hot plate or other methods, which are not limited in this embodiment.

[0097] S405, placing a temporary assembly on the second polishing lining;

[0098] like Figure 8 As shown in (e), at this time, the second polishing liner 40, the first polishing liner 30, the companion structure 21 and the chip to be thinned 10 form a temporary operable unit.

[0099] S406, pre-polishing the chip to be thinned;

[0100] The second polishing liner 40 is placed on the polishing equipment to pre-polish the chip 10 to be thinned. The degree of pre-polishing can be polished until the surface of the chip 10 to be thinned is consistent when observed with the naked eye, that is, a relatively basic polishing treatment is performed on the surface of the chip 10 to be thinned. The pre-polishing process can provide a common surface for the subsequent full-surface etching process, ensure the high consistency and uniformity of the full-surface etching process, and improve the quality of thinning.

[0101] S407, removing the temporary assembly from the second polishing liner;

[0102] After pre-polishing, the temporary assembly (first polishing liner 30, accompanying sheet structure 21 and chip to be thinned 10) is separated from the second polishing liner 40. The first polishing liner 30, accompanying sheet structure 21 and chip to be thinned 10 are kept fixed to avoid repeated bonding and removal of these structures, and to ensure the stability of the posture between these structures.

[0103] S408, performing full surface etching on the chip to be thinned;

[0104] like Figure 8 As shown in (f), the temporary component is placed in an etching solution for full-surface etching, and the etching is performed at a specific time according to the etching rate to a preset thickness D1. By introducing full-surface etching, a portion of the thickness can be removed without stress, reducing the stress link in the entire thinning process, reducing the probability of microscopic or macroscopic damage to the chip 10 to be thinned due to stress, and reducing the problem of cracking of brittle semiconductor chips due to deformation and stress.

[0105] S409, reinstalling the temporary assembly back onto the second grinding and polishing lining;

[0106] After the corrosion is completed, the temporary assembly is mounted back on the second grinding and polishing liner. To facilitate the distinction between the different steps, it will be referred to as the third grinding and polishing liner in the following text in accordance with the above description.

[0107] S410, performing a rough polishing process on the chip to be thinned;

[0108] The third polishing liner is placed on the polishing equipment to perform a rough polishing process on the chip to be thinned 10. A polishing liquid with a larger particle size is used to continue polishing and thickening, and the surface is leveled at the same time until the preset thickness D2 is reached.

[0109] S411, performing fine polishing process on the chip to be thinned;

[0110] After the rough polishing process is completed, the fine polishing process is carried out, and a grinding and polishing liquid with a smaller particle size is used for chemical polishing to remove surface damage and thin the surface to the final thickness D3.

[0111] S412, removing the chip 10 to be thinned from the first polishing liner, and cleaning the chip 10 to be thinned;

[0112] The thinning process performed through the above process reduces the possibility of stress damaging the chip 10 to be thinned, thereby increasing the yield rate of chip manufacturing.

[0113] In addition, although exemplary embodiments have been described herein, the scope includes any and all embodiments based on the present disclosure that are equivalent, modified, omitted, combined (e.g., various embodiments intersecting), adapted or changed. It is not limited to the examples described in this specification or during the implementation of the present invention, and its examples will be interpreted as non-exclusive.

[0114] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more of them) can be used in combination with each other. For example, those of ordinary skill in the art may use other embodiments when reading the above description.

[0115] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A chip thinning method, characterized in that: include: Providing a first polishing liner; Placing the chip to be thinned on the first polishing liner; A companion sheet structure is arranged on the first polishing liner, wherein the companion sheet structure covers the four sides of the chip to be thinned; Using the first polishing liner, the chip to be thinned and the companion structure as temporary components in the thinning process, and performing a thinning operation on the chip to be thinned; After the thinning operation is completed, the chip to be thinned is separated from the first polishing liner.

2. The chip thinning method according to claim 1, characterized in that: The accompanying chip structure includes a liquid guiding channel, and the liquid guiding channel is used for allowing liquid to pass through during the grinding and polishing process so as to guide the liquid at the chip to be thinned outward.

3. The chip thinning method according to claim 2, characterized in that: The accompanying sheet structure includes four accompanying strips, and the four accompanying strips are respectively arranged on four sides of the chip to be thinned; and there is a gap between each of the accompanying strips to serve as the liquid guiding channel.

4. The chip thinning method according to claim 2, characterized in that: The cross-sectional width of the liquid-conducting channel is no greater than 3 mm.

5. The chip thinning method according to claim 1, characterized in that: The chip to be thinned includes a circuit board and a chip wafer arranged on the circuit board; The shape of the companion structure satisfies at least one of the following conditions: The width of the companion structure is not less than one quarter of the length of the side of the chip wafer perpendicular to it; The difference between the thickness of the companion chip structure and the chip to be thinned is in the range of 30 μm to 50 μm.

6. The chip thinning method according to claim 5, characterized in that: Before the thinning operation is performed on the chip to be thinned, the method further comprises: Disposing a first protective layer on the circuit board, wherein the first protective layer covers the exposed area of ​​the circuit board and does not contact the chip wafer; A second protective layer is arranged on the circuit board. The second protective layer is made of a material that is repellent to semiconductor materials. The second protective layer covers all exposed areas of the circuit board and the first protective layer.

7. The chip thinning method according to claim 1, characterized in that: The step of providing a companion plate structure on the first polishing liner also includes: The bonding material is accumulated on the periphery of the companion sheet structure to form a reinforcement structure.

8. The chip thinning method according to any one of claims 1 to 7, characterized in that: The thinning operation of the chip to be thinned comprises: placing the temporary assembly on the second polishing lining; The second polishing liner is arranged on the polishing equipment to pre-polish the chip to be thinned.

9. The chip thinning method according to claim 8, characterized in that: After the pre-polishing of the chip to be thinned, the method further comprises: Removing the temporary assembly from the second polishing liner as a whole; The temporary assembly is placed in an etching solution to perform full surface etching on the chip to be thinned.

10. The chip thinning method according to claim 9, characterized in that: After the temporary component is fully corroded, the method further comprises: The temporary assembly is arranged on the third polishing lining plate; The third polishing liner is arranged on the polishing equipment to carry out the subsequent polishing process.

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