Etching process detection device and method
By setting a group of transistors with different slit widths on the semiconductor substrate and measuring their electrical parameters to detect the accuracy of the etching process, the problem of etching residue detection caused by three-dimensional structure trenches is solved, and a high-accurate etching process detection is achieved.
Patent Information
- Application Number
- CN202411803256.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-11
AI Technical Summary
In semiconductor processing, the trench of the three-dimensional structure makes it difficult to ensure the accuracy of the etching process detection, making it difficult to accurately capture the etching residue, affecting the performance of the transistor and the yield of the product.
By providing a group of transistors with different slit widths on the substrate, their electrical parameters are measured to detect the accuracy of the etching process. This method uses the electrical parameter offset caused by different slit widths to reflect the severity of the etching residue, thereby improving the accuracy of the etching process detection.
This method effectively improves the accuracy of etching process detection, can accurately monitor changes in etching residues, and ensures transistor performance and product yield.
Smart Images
Figure CN119601490A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to an etching process detection device and method. Background Art
[0002] In the field of semiconductor processing, as the size of transistors decreases, the gate control ability of traditional field effect transistors with surface structures weakens, so new transistors with three-dimensional structures have emerged, such as fin field effect transistors (FinFETs). However, since these three-dimensional structures will form trenches with low aspect ratios (i.e., trenches with smaller widths and larger depths), it is more difficult for etching gases or etching liquids to enter the trenches when etching the deposited layers in the trenches, and it is also more difficult to remove the reactant debris formed after etching from the trenches. Therefore, etching the deposited layers in the trenches often requires more stringent etching process conditions (i.e., smaller process windows). If the process conditions (such as voltage, plasma gas concentration, pulses, etc.) fluctuate too much, it may lead to incomplete etching of the deposited layers in the trenches, forming residues in the trenches, thereby affecting the performance of the transistors and the yield of the products.
[0003] In the related art, the etching effect of semiconductor devices is generally monitored online by taking pictures with a microscope. However, due to the limitations of resolution, shooting angle, device size and other conditions, microscopic changes such as etching residues are difficult to capture accurately, and the accuracy of etching process detection is difficult to guarantee. Summary of the invention
[0004] In view of this, an embodiment of the present invention provides an etching process detection device and method, which can effectively improve the accuracy of etching process detection.
[0005] In a first aspect, an embodiment of the present invention provides an etching process detection device, comprising: a substrate, on which a transistor group is arranged, the transistor group comprising at least two transistors; each of the transistors corresponds to a slit associated with a gate of the transistor; in each of the slits, there are at least two target slits, wherein the slit widths of various target slits are different; and each of the transistors has the same structure except for the different slit widths of the target slits.
[0006] In one embodiment, the transistor includes a fin field-effect transistor (finFET), and the slit includes a slit formed between fins of adjacent transistors, wherein a gate of the transistor is disposed on each of the fins, and a portion between two active regions of the same transistor is surrounded by the gate from three sides.
[0007] In one embodiment, the transistor comprises a gate-all-around Field-Effect Transistor (GAAFET), and the slit comprises a slit formed between a plurality of nanowires or nanosheets passing through a gate of the transistor.
[0008] In one embodiment, the slit widths of the target slits are distributed in an arithmetic progression or a geometric progression.
[0009] In one implementation, each of the transistors is an N-type field effect transistor or a P-type field effect transistor.
[0010] In one embodiment, at least one crystal grain and at least one transistor group are disposed on the substrate, the crystal grains are distributed at intervals, and the transistor groups are disposed in the gaps between the crystal grains.
[0011] In one embodiment, the gate material of the transistor includes metal and / or polysilicon.
[0012] In a second aspect, an embodiment of the present invention further provides an etching process detection method, comprising: based on a preset process flow, manufacturing a transistor group on the same substrate, the transistor group comprising at least two transistors; each of the transistors corresponds to a slit associated with a gate of the transistor; in each of the slits, there are at least two target slits, wherein the slit widths of various target slits are different; except for the slit widths of the target slits, the other structures of the transistors are the same; measuring the preset electrical parameters of the transistor corresponding to each of the target slits to obtain the corresponding reference values of the preset electrical parameters; and detecting the etching process associated with the slits in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters.
[0013] In one embodiment, the detecting of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters includes: detecting the range of slit width applicable to the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters; or, detecting whether a process window is offset when etching is performed in the preset process flow under the etching process conditions related to the slit for a transistor corresponding to a target slit of a preset slit width according to the relative relationship between the reference values of each of the preset electrical parameters.
[0014] In one embodiment, the preset electrical parameters include a threshold voltage; the reference value of the preset electrical parameters includes a reference threshold voltage; the detection of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters includes: determining the minimum threshold voltage among the reference threshold voltages; searching for a target threshold voltage among the reference threshold voltages, wherein the ratio of the target threshold voltage to the minimum threshold voltage is less than or equal to a first ratio threshold; and determining the range of slit widths applicable to the etching process related to the slit in the preset process flow according to the maximum voltage among the target threshold voltages.
[0015] In one embodiment, determining the range of the slit width applicable to the slit-related etching process in the preset process flow based on the maximum voltage among the target threshold voltages includes: determining the transistor corresponding to the maximum voltage to obtain a first target transistor; and determining the slit width of the slit corresponding to the first target transistor as the lower limit of the slit width applicable to the slit-related etching process in the preset process flow.
[0016] In one embodiment, the preset electrical parameter includes a threshold voltage; the reference value of the preset electrical parameter includes a reference threshold voltage; the detection of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters includes: determining the minimum threshold voltage among the reference threshold voltages; searching for the transistor corresponding to the target slit of the preset slit width in the transistor group to obtain a second target transistor; based on whether the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is greater than a second ratio threshold, detecting whether the process window of the transistor corresponding to the target slit of the preset slit width is offset when etching is performed under the etching process conditions related to the slit in the preset process flow.
[0017] In one embodiment, the etching process related to the slit in the preset process flow includes a process of etching a gate material to form a gate pattern of the transistor.
[0018] In one embodiment, the manufacturing of transistor groups on the same substrate based on a preset process flow includes: manufacturing at least one crystal grain and at least one transistor group on the same substrate based on the preset process flow, wherein the crystal grains are spaced apart and the transistor groups are arranged in the gaps between the crystal grains.
[0019] In one embodiment, the transistor includes a fin field effect transistor, and the slit includes a slit formed between fins of adjacent transistors, wherein a gate of the transistor is disposed on each of the fins, and a portion between two active regions of the same transistor is surrounded by the gate from three sides.
[0020] In one embodiment, the transistor comprises a wrap-around gate field effect transistor, and the slit comprises a slit formed between a plurality of nanowires or nanosheets passing through a gate of the transistor.
[0021] In one implementation, the preset electrical parameters include a threshold voltage and / or a leakage current.
[0022] The etching process detection device and method provided by the embodiment of the present invention are provided with a transistor group on a substrate, and the transistor group includes at least two transistors; each transistor corresponds to a slit associated with the gate of the transistor; in each slit, there are at least two target slits, wherein the slit widths of each target slit are different. Since the transistors in the transistor group have the same structure except for the different slit widths of the target slits, the electrical properties of each transistor will be generally similar. Since the slit widths of the target slits are different, the amount of etching residues in different target slits will be different, thereby affecting the electrical properties of the transistors. Therefore, the electrical properties of each transistor will be different on the basis of being generally consistent, for example, some electrical parameters of the transistor may be offset. In this way, the offset degree of the electrical parameters can reflect the severity of the etching residues. By measuring the electrical parameters of transistors with different slit widths and knowing the relative offset of the electrical parameters of each transistor, the relative change of the etching residues of each transistor during etching under the current etching process conditions can be grasped, thereby effectively improving the accuracy of etching process detection. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0024] Figure 1 A schematic diagram of the structure of an etching process detection device according to an embodiment of the present invention; Figure 2 is a schematic diagram of the distribution of an etching process detection device in an embodiment of the present invention; Figure 3 is a schematic structural diagram of a transistor in an etching process detection device in an embodiment of the present invention; Figure 4 is a schematic structural diagram of another transistor in the etching process detection device in an embodiment of the present invention; Figure 5 is a schematic structural diagram of another transistor in the etching process detection device in an embodiment of the present invention; Figure 6 The present invention is a flowchart of an etching process detection method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0026] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0027] In a first aspect, an embodiment of the present invention provides an etching process detection device, which can effectively improve the accuracy of etching process detection.
[0028] like Figure 1 As shown, an embodiment of the present invention provides an etching process detection device, including: a substrate 10, on which a transistor group 20 is arranged, and the transistor group 20 includes at least two transistors 21; each transistor 21 corresponds to a slit 22 associated with a gate 210 of the transistor 21; in each slit 22, there are at least two target slits, wherein the slit widths of various target slits are different; each transistor 21 has the same structure except that the slit widths of the target slits are different.
[0029] Optionally, in an embodiment of the present invention, the substrate 10 may be any substrate capable of manufacturing transistors, such as a silicon wafer. The transistor group 20 may include a plurality of transistors 21, and there may or may not be an electrical connection relationship between the transistors 21. Each transistor 21 corresponds to a slit 22 associated with the gate 210 of the transistor 21. Here, the slit 22 is associated with the gate 210, which means that the slit 22 and the gate 210 are associated in spatial structure, and the slit 22 itself is a spatial gap and has no effect on the electrical properties of the transistor. Optionally, in an embodiment of the present invention, the gate material of the transistor 21 may include metal and / or polysilicon.
[0030] Specifically, the slit width corresponding to each slit 22 can be large or small, wherein there are at least two target slits, and the slit widths of various target slits are different from each other, for example, the slit width of target slit a is 5 nanometers, the slit width of target slit b is 6 nanometers, the slit width of target slit c is 7 nanometers, etc. Each target slit width can correspond to one or more transistors, for example, a target slit with a width of 6 nanometers can correspond to 10 transistors 21, a target slit with a width of 8 nanometers can correspond to 10 transistors 21, a target slit with a width of 15 nanometers can correspond to 20 transistors 21, and so on.
[0031] In the embodiment of the present invention, each transistor 21 has the same structure except for the different slit widths of the target slits. Since the slit 22 itself is a space gap and has no effect on the electrical properties of the transistor, theoretically, the electrical properties of each transistor 21 should also be the same. However, considering that slits 22 of different widths will also present different etching effects under the same semiconductor etching process conditions, for example, different degrees of etchant residues may appear in slits 22 of different widths, and therefore, the electrical properties of each transistor 21 may differ due to the influence of the residues.
[0032] The etching process detection device provided by the embodiment of the present invention has a transistor group 20 disposed on a substrate 10, and the transistor group 20 includes at least two transistors 21; each transistor 21 corresponds to a slit 22 associated with a gate 210 of the transistor 21; each slit 22 has at least two target slits, wherein the slit widths of each target slit are different. Since each transistor 21 in the transistor group 20 has the same structure except for the different slit widths of the target slits, the electrical properties of each transistor 21 will be substantially similar. Since the slit widths of the target slits are different, the amount of etching residues in different target slits will be different, which will further affect the electrical properties of the transistors. Therefore, the electrical properties of each transistor may be different on the basis of being substantially consistent, for example, some electrical parameters of the transistor may be offset. In this way, the degree of deviation of the electrical parameters can reflect the severity of the etching residues. By measuring the electrical parameters of transistors with different slit widths and obtaining the relative deviation of the electrical parameters of each transistor, the relative changes of the etching residues when etching each transistor under the current etching process conditions can be understood, thereby effectively improving the accuracy of etching process detection.
[0033] Specifically, in an embodiment of the present invention, the transistor group 20 can be relatively independently arranged on a substrate, or can be arranged on the same substrate together with other crystal grains. For example, in the initial exploration stage of etching process conditions, in order to reduce costs, the transistor group 20 can be relatively independently arranged on a small piece of substrate, so that it is convenient to use the transistor group 20 on the substrate to explore the etching process, so as to explore suitable etching conditions for the formal crystal grain etching. When a certain amount of process experience is acquired, the transistor group 20 can be arranged on the same substrate together with other crystal grains, and the transistor group 20 can go through the same process flow with the crystal grains, and the etching condition of the crystal grains can be detected through the transistor group 20. For example, if Figure 2 As shown, in one embodiment of the present invention, at least one crystal grain 30 and at least one transistor group 20 are arranged on the substrate 10, the crystal grains 30 are spaced apart, and the transistor groups 20 are arranged in the gaps between the crystal grains 30, for example, in the scribe grooves of the crystal grains. In this way, the etching process of the crystal grains can be accurately detected without occupying the precious crystal grain area.
[0034] like Figure 3 As shown, in one embodiment of the present invention, each transistor in the transistor group may include a fin field effect transistor, based on which, the slit 22 may specifically include a slit 22 formed between the fins 23 of adjacent transistors, wherein a gate 210 of the transistor is disposed on each fin 23, and a portion between two active regions (source region S, drain region D) of the same transistor is surrounded from three sides by the gate 210. Except for the different slit widths of the target slits, the other structures of the transistors are the same.
[0035] That is to say, in this embodiment, for the fin field effect transistor, since the fin has a three-dimensional structure and the fin pitch is small, the gap between adjacent fins forms a slit 22. The slit width of the slit 22 is different, and the degree of etching residue is also different. Taking the gate etching of the transistor as an example, when the gate material of the transistor is etched to generate a gate pattern, if the gate material in the slit 22 is not completely etched, the residue may change the electrical properties of the transistor, for example, it may cause the electrical parameters such as the threshold voltage or leakage current of the transistor to shift. By measuring the electrical parameters of each transistor in the transistor group composed of the fin field effect transistor, the different electrical parameters corresponding to the transistors with different slits 22 can be monitored, and according to the offset of the electrical parameters, the different etching effects of the same etching process on different slit widths can be determined, thereby realizing the detection of the etching process.
[0036] Optional, such as Figure 4 and Figure 5As shown, in another embodiment of the present invention, each transistor in the transistor group may include a wrap-around gate field effect transistor, based on which the slit may include a slit formed between a plurality of nanowires 211 or nanosheets 212 passing through the gate 210 of the transistor. Each transistor has the same structure except that the slit width of the target slit is different.
[0037] In this embodiment, for a wraparound gate field effect transistor, a plurality of nanowires 211 or nanosheets 212 passing through the gate 210 of the transistor are close to each other, so a slit can be formed between these nanowires 211 or nanosheets 212. The slit widths are different, and the etching residues are also different. Taking the gate etching of a transistor as an example, when the gate material of the transistor is etched to generate a gate pattern, if the gate material in the slit is not completely etched, the residue may change the electrical properties of the transistor, for example, it may cause the electrical parameters such as the threshold voltage or leakage current of the transistor to shift. Similarly, by measuring the electrical parameters of each transistor in a transistor group composed of wraparound gate field effect transistors, different electrical parameters corresponding to transistors with different slits can also be monitored, and according to the offset of the electrical parameters, the different etching effects of the same etching process on different slit widths can be determined, thereby realizing the detection of the etching process.
[0038] Whether it is a fin field effect transistor or a wrap-around gate field effect transistor, it can be classified as an N-type field effect transistor or a P-type field effect transistor according to the channel conductivity properties. In one embodiment of the present invention, the offset direction of the threshold voltage or leakage current offset caused by the etching residue can be different for different N and P types of transistors. For example, in one example, the residue will cause the threshold voltage of the N-type field effect transistor to be higher and the threshold voltage of the P-type field effect transistor to be lower.
[0039] To facilitate detection, in one embodiment of the present invention, each transistor 21 in the transistor group 20 may be arranged according to different slit widths. For example, each transistor 21 may be arranged in an array, with the slit widths of transistors 21 in the same row being the same, and the slit widths of transistors 21 in different rows increasing in sequence. Alternatively, each transistor 21 may be arranged in a queue, with the slit widths of each transistor 21 in the queue increasing in sequence or decreasing in sequence, etc.
[0040] Optionally, in an example, the slit width of the target slit of each transistor 21 may also vary according to a preset rule. For example, the slit width of each target slit may be distributed in an arithmetic progression or a geometric progression.
[0041] Furthermore, in one embodiment of the present invention, the influence of the slit width on the etching effect can be detected more accurately by increasing the number of slit widths, reducing the gap between adjacent slit widths, and the like.
[0042] Optionally, when performing etching process detection using the etching process detection device of the embodiment of the present invention, on the one hand, by measuring the electrical parameters of each transistor in the transistor group 20, it is possible to accurately determine under which slit width the etching effect is acceptable and under which slit width the etching effect is intolerable, thereby determining the slit width range applicable to the etching process conditions, matching the current etching process conditions with a suitable processing object, and avoiding device damage and resource waste caused by ineffective processing; on the other hand, it is also possible to measure the electrical parameters of transistors with a preset slit width to more accurately detect whether the etchant residue in the slit with a preset slit width is acceptable, thereby determining whether the etching process is suitable for etching transistors with a preset slit width. For example, if the etchant residue is intolerable, it means that the process window corresponding to the transistor 21 with the preset slit width has shifted and is no longer suitable for etching with the current etching process conditions.
[0043] In a second aspect, corresponding to the above-mentioned etching process detection device, an embodiment of the present invention further provides an etching process detection method, which can effectively improve the accuracy of etching process detection.
[0044] like Figure 6 As shown, the etching process detection method provided by the embodiment of the present invention may include: S41, based on a preset process flow, manufacturing a transistor group on the same substrate, wherein the transistor group includes at least two transistors; each of the transistors corresponds to a slit associated with a gate of the transistor; each of the slits has at least two target slits, wherein the slit widths of the target slits are different; and each of the transistors has the same structure except for the different slit widths of the target slits; The preset process flow may include a part or all of the process flow for manufacturing transistors on the substrate. Since each transistor in the transistor group is arranged on the same substrate, each transistor undergoes the same process flow and faces the same process conditions at each process step of the process flow.
[0045] Optionally, in one example, each transistor in the transistor group may include a fin field effect transistor, and the slit includes a slit formed between fins of adjacent transistors, wherein a gate of the transistor is disposed on each of the fins, and a portion between two active areas of the same transistor is surrounded by the gate from three sides.
[0046] Optionally, in another example, the transistor includes a wrap-around gate field effect transistor, and the slit includes a slit formed between a plurality of nanowires or nanosheets passing through a gate of the transistor.
[0047] The structural features of the transistor group can be found in the etching process detection device provided in the embodiment of the present invention, which has been described above and will not be repeated here.
[0048] S42, measuring the preset electrical parameters of the transistors corresponding to the target slits to obtain reference values of the corresponding preset electrical parameters; In this step, when measuring the preset electrical parameters of the transistor, the measurement can be performed based on tools such as a probe station, etc. Optionally, the preset electrical parameters can include various electrical parameters of the transistor such as voltage, current, power, etc.
[0049] Since the slit widths of various target slits are different, the etching residues in each target slit will be different due to the influence of the slits. Further, due to the influence of the residues, the electrical properties of the transistors corresponding to each target slit will also be different.
[0050] In one embodiment of the present invention, for each target slit width, there may be multiple transistors in a transistor group having a target slit of this width. Based on this, the reference values of the preset electrical parameters of each transistor corresponding to the target slit of this width measured can be averaged, and the average can be used as the preset electrical parameters of the transistor corresponding to the target slit of this width, thereby effectively reducing the measurement error.
[0051] S43, detecting the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters.
[0052] Optionally, the relative relationship between the reference values of the preset electrical parameters may include a ratio or a difference between the reference values.
[0053] The etching process related to the slit in the preset process flow may include a process of etching a gate material to form a gate pattern of the transistor.
[0054] The etching process detection method provided by the embodiment of the present invention can manufacture a transistor group on the same substrate based on a preset process flow, wherein the transistor group includes at least two transistors; each of the transistors corresponds to a slit associated with the gate of the transistor; each of the slits has at least two target slits, wherein the slit widths of the various target slits are different; the preset electrical parameters of the transistors corresponding to each of the target slits are measured to obtain the reference values of the corresponding preset electrical parameters, and the etching process associated with the slits in the preset process flow is detected according to the relative relationship between the reference values of the preset electrical parameters. Since the transistors in the transistor group have the same structure except for the different slit widths of the target slits, the electrical properties of the transistors will be generally similar, and since the slit widths of the target slits are different, the amount of etching residues in different target slits will be different, thereby affecting the electrical properties of the transistors. Therefore, the electrical properties of the transistors will be different on the basis of being generally consistent, for example, some electrical parameters of the transistors may be offset. In this way, the degree of deviation of the electrical parameters can reflect the severity of the etching residues. By measuring the electrical parameters of transistors with different slit widths and obtaining the relative deviation of the electrical parameters of each transistor, the relative changes of the etching residues when etching each transistor under the current etching process conditions can be understood, thereby effectively improving the accuracy of etching process detection.
[0055] Specifically, in one embodiment of the present invention, first, in step S41, the transistor group can be manufactured. Optionally, the transistor group can be manufactured relatively independently on a smaller substrate, or can be manufactured together with other crystals on a larger substrate, such as a wafer.
[0056] Exemplarily, in one example, in step S41, manufacturing a transistor group on the same substrate based on a preset process flow may specifically include: manufacturing at least one crystal grain and at least one transistor group on the same substrate based on the preset process flow, wherein the crystal grains are spaced and distributed, and the transistor groups are arranged in the gaps between the crystal grains. In this way, the etching process of the crystal grains can be accurately detected without occupying precious crystal grain area.
[0057] After obtaining the transistor group, the preset electrical parameters of the transistors corresponding to each of the target slits can be measured in step S42 to obtain the reference values of the corresponding preset electrical parameters. Optionally, the preset electrical parameters may include a variety of voltage, current, and power parameters. For example, in one embodiment of the present invention, the preset electrical parameters may include a threshold voltage and / or a leakage current. After obtaining the reference values of the preset electrical parameters, in step S43, the etching process related to the slit in the preset process flow can be detected according to the relative relationship between the reference values of each of the preset electrical parameters.
[0058] Specifically, in one embodiment of the present invention, detecting the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters may specifically include: detecting the range of slit widths applicable to the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters; or detecting whether the process window of the transistor corresponding to the target slit of the preset slit width is offset when etching is performed under the etching process conditions related to the slit in the preset process flow according to the relative relationship between the reference values of each of the preset electrical parameters.
[0059] The following description is made by taking the preset electrical parameters including the threshold voltage as an example.
[0060] Exemplarily, in one embodiment of the present invention, the preset electrical parameter may include a threshold voltage, and accordingly, the reference value of the preset electrical parameter may include a reference threshold voltage. Based on this, in step S43, according to the relative relationship between the reference values of the preset electrical parameters, the etching process related to the slit in the preset process flow is detected, which may specifically include: Determine the minimum threshold voltage among the reference threshold voltages; wherein the minimum threshold voltage is the reference threshold voltage of the transistor with the largest slit width; A target threshold voltage is searched for in each of the reference threshold voltages, wherein a ratio of the target threshold voltage to the minimum threshold voltage is less than or equal to a first ratio threshold; optionally, a specific value of the first ratio threshold can be set and adjusted as needed.
[0061] According to the maximum voltage among the target threshold voltages, a range of slit width applicable to the slit-related etching process in the preset process flow is determined.
[0062] Among them, determining the range of the slit width applicable to the etching process related to the slit in the preset process flow according to the maximum voltage among the target threshold voltages can specifically include: determining the transistor corresponding to the maximum voltage to obtain a first target transistor; determining the slit width of the slit corresponding to the first target transistor as the lower limit of the slit width applicable to the etching process related to the slit in the preset process flow.
[0063] For example, in one example, the measured reference threshold voltages are: 0.2 volts (slit width is 7 nanometers), 0.19 volts (slit width is 8 nanometers), 0.21 volts (slit width is 6 nanometers), 0.18 volts (slit width is 10 nanometers), and the minimum threshold voltage is 0.18 volts. If the first ratio threshold is 1.1, the ratios of the reference threshold voltages to the minimum threshold voltage are: 0.2 / 0.18=1.11, 0.19 / 0.18=1.19, 0.21 / 0.21 ... =1.06, 0.21 / 0.18=1.19, 0.18 / 0.18=1, where 1.06 and 1 are less than or equal to the first ratio threshold value 1.1, and it can be determined that the target threshold voltages include: 0.18 volts and 0.19 volts, and the maximum voltage among the target threshold voltages is 0.19 volts, and it can be determined that the transistor with a reference threshold voltage of 0.19 volts is the first target transistor, and the slit width (8 nanometers) of the first target transistor is determined to be the lower limit of the slit width used in the etching process. That is to say, for the current etching process conditions, the minimum slit width that can be used to etch a transistor is 8 nanometers, and for transistors with a slit width less than 8 nanometers (for example, transistors with a slit width of 7 nanometers or 6 nanometers), it is not suitable for etching using the current etching process conditions.
[0064] Optionally, in another embodiment of the present invention, the preset electrical parameter includes a threshold voltage; the reference value of the preset electrical parameter includes a reference threshold voltage; based on this, in step S43, detecting the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters may include: Determine the minimum threshold voltage among the reference threshold voltages; wherein the minimum threshold voltage is the reference threshold voltage of the transistor with the largest slit width; In the transistor group, searching for a transistor corresponding to a target slit with a preset slit width to obtain a second target transistor; According to whether the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is greater than the second ratio threshold, the transistor corresponding to the target slit of the preset slit width is detected to see whether the process window is offset when etching is performed under the etching process conditions related to the slit in the preset process flow. Optionally, if the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is greater than the second ratio threshold, it can be determined that the process window is offset, and if the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is less than or equal to the second ratio threshold, it can be determined that the process window is not offset. Optionally, the specific value of the second ratio threshold can be set and adjusted as needed.
[0065] For example, in one example, it is necessary to detect whether the current etching process conditions can be used to etch a transistor with a slit width of 8 nanometers. According to the measurement results, the measured reference threshold voltages are: 0.2 volts (slit width of 7 nanometers), 0.19 volts (slit width of 8 nanometers), 0.21 volts (slit width of 6 nanometers), and 0.18 volts (slit width of 10 nanometers), wherein the minimum threshold voltage is 0.18 volts, and the second ratio threshold is 1.1. Then, a transistor with a slit width of 8 nanometers is found in the transistor group to obtain a second target transistor. The reference threshold voltage measured by the second target transistor is 0.19 volts, and the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is 0.19 / 0.18=1.06, which is less than the second ratio threshold of 1.1. Therefore, it can be determined that under the current etching process conditions, there is no process window offset for etching a transistor with a slit width of 8 nanometers, and the current etching process conditions can be used to etch a transistor with a slit width of 8 nanometers.
[0066] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0067] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0068] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0069] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.
[0070] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. An etching process detection device, characterized in that: include: A substrate, on which a transistor group is arranged, wherein the transistor group includes at least two transistors; Each of the transistors has a corresponding slit associated with a gate of the transistor; Among the slits, there are at least two target slits, wherein the slit widths of the target slits are different; The transistors have the same structure except that the slit width of the target slit is different.
2. The device according to claim 1, characterized in that The transistor comprises a fin field effect transistor, and the slit comprises a slit formed between fins of adjacent transistors, wherein a gate of the transistor is arranged on each of the fins, and a portion between two active regions of the same transistor is surrounded by the gate from three sides.
3. The device according to claim 1, characterized in that The transistor comprises a wrap-around gate field effect transistor, and the slit comprises a slit formed between a plurality of nanowires or nanosheets passing through a gate of the transistor.
4. The device according to claim 1, characterized in that The slit widths of the target slits are distributed in an arithmetic progression or a geometric progression.
5. The device according to claim 1, characterized in that Each of the transistors is an N-type field effect transistor or a P-type field effect transistor.
6. The device according to claim 1, characterized in that At least one crystal grain and at least one transistor group are arranged on the substrate, the crystal grains are distributed at intervals, and the transistor groups are arranged in the gaps between the crystal grains.
7. The device according to claim 1, characterized in that The gate material of the transistor includes metal and / or polysilicon.
8. An etching process detection method, characterized in that: include: Based on a preset process flow, a transistor group is manufactured on the same substrate, wherein the transistor group includes at least two transistors; Each of the transistors has a corresponding slit associated with the gate of the transistor; there are at least two target slits in each of the slits, wherein the slit widths of the target slits are different; each of the transistors has the same structure except that the slit widths of the target slits are different; Measuring the preset electrical parameters of the transistor corresponding to each of the target slits to obtain a reference value of the corresponding preset electrical parameter; According to the relative relationship between the reference values of the preset electrical parameters, the etching process related to the slit in the preset process flow is detected.
9. The method according to claim 8, characterized in that The detecting of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters includes: Detecting a range of slit width applicable to an etching process related to the slit in the preset process flow according to a relative relationship between reference values of the preset electrical parameters; or According to the relative relationship between the reference values of the preset electrical parameters, the transistor corresponding to the target slit of the preset slit width is detected to see whether the process window is offset when etching is performed under the etching process conditions related to the slit in the preset process flow.
10. The method according to claim 8, characterized in that The preset electrical parameter includes a threshold voltage; the reference value of the preset electrical parameter includes a reference threshold voltage; The detecting of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters includes: Determining a minimum threshold voltage among the reference threshold voltages; searching for a target threshold voltage in each of the reference threshold voltages, wherein a ratio of the target threshold voltage to the minimum threshold voltage is less than or equal to a first ratio threshold; According to the maximum voltage among the target threshold voltages, a range of slit width applicable to the slit-related etching process in the preset process flow is determined.
11. The method according to claim 10, characterized in that Determining the range of the slit width applicable to the slit-related etching process in the preset process flow according to the maximum voltage among the target threshold voltages includes: Determine a transistor corresponding to the maximum voltage to obtain a first target transistor; The slit width of the slit corresponding to the first target transistor is determined as a lower limit of the slit width applicable to the etching process related to the slit in the preset process flow.
12. The method according to claim 8, characterized in that The preset electrical parameter includes a threshold voltage; the reference value of the preset electrical parameter includes a reference threshold voltage; The detecting of the etching process related to the slit in the preset process flow according to the relative relationship between the reference values of the preset electrical parameters includes: Determining a minimum threshold voltage among the reference threshold voltages; In the transistor group, searching for a transistor corresponding to a target slit with a preset slit width to obtain a second target transistor; Based on whether the ratio of the reference threshold voltage of the second target transistor to the minimum threshold voltage is greater than a second proportional threshold, the transistor corresponding to the target slit of the preset slit width is detected to see whether a process window is offset when etching is performed under the etching process conditions related to the slit in the preset process flow.
13. The method according to claim 8, characterized in that The etching process related to the slit in the preset process flow includes a process of etching the gate material to form a gate pattern of the transistor.
14. The method according to claim 8, characterized in that The method of manufacturing a transistor group on the same substrate based on a preset process flow includes: Based on the preset process flow, at least one crystal grain and at least one transistor group are manufactured on the same substrate, wherein the crystal grains are spaced apart and the transistor groups are arranged in the gaps between the crystal grains.
15. The method according to claim 8, characterized in that The transistor comprises a fin field effect transistor, and the slit comprises a slit formed between fins of adjacent transistors, wherein a gate of the transistor is arranged on each of the fins, and a portion between two active regions of the same transistor is surrounded by the gate from three sides.
16. The method according to claim 8, characterized in that The transistor comprises a wrap-around gate field effect transistor, and the slit comprises a slit formed between a plurality of nanowires or nanosheets passing through a gate of the transistor.
17. The method according to claim 8, characterized in that The preset electrical parameters include threshold voltage and / or leakage current.