Ion beam sputtering deposition method for metal layer of interconnection line of integrated circuit

Abstract

The invention discloses an ion beam sputtering deposition method for a metal layer of an integrated circuit interconnection line, and belongs to the technical field of micro-nano manufacturing. In the deposition process of the metal layer, a grazing angle ion beam sputtering (IBS) physical vapor deposition (PVD) mode is adopted; high-quality conformal filling of molybdenum (Mo), ruthenium (Ru) and other metal films in the groove structure with the characteristic size (CD) of tens of nanometers and the large aspect ratio (AR) can be achieved, namely the good hole filling capacity is achieved, the 100% side wall coverage rate can be achieved, and the occurrence of overhang, void and other bad modes is avoided. According to the method, the ion beam sputtering technology is introduced into the integrated circuit manufacturing process, and a new process solution is provided for deposition and filling of integrated circuit grid metal materials, middle-channel and rear-channel interconnection lining layers / barrier layers / seed layers / conductive metal materials and 3D-DRAM capacitor electrode materials.

Description

Technical Field

[0001] The invention belongs to the field of micro-nano manufacturing technology, and in particular relates to an ion beam sputtering deposition method for a metal layer of an integrated circuit interconnect line. Background Art

[0002] Ion beam sputtering (IBS), also known as ion beam deposition (IBD), is a process that uses a high-energy ion beam to bombard a target material in an ultra-high vacuum, causing its atoms to sputter out and deposit on a substrate to form a film. Because the ions in the ion beam of IBS have the same energy and high collimation, the film thickness can be precisely controlled and very dense, high-quality films can be deposited.

[0003] The background description provided herein is for the purpose of presenting an overall background of the present disclosure by way of example. The work of the presently designated inventors is neither explicitly nor implicitly claimed to be prior art against the present disclosure to the extent described in this background section and in aspects of the specification that were not determined to be prior art at the time the application was filed. Summary of the invention

[0004] The technical purpose of the present invention is to propose a method for ion beam sputtering deposition of metal layers of integrated circuit interconnects. The method comprises: depositing a multilayer structure on a substrate and then etching to form a patterned through hole or groove. The multilayer structure comprises an anti-reflection layer, a hard mask layer, a dielectric layer, and an etch stop layer in the photolithography process. The method also comprises: conformally covering or filling the sidewalls in the patterned through hole or groove with a conductive material; and using the material as a seed layer to fill the groove or through hole with a conductive material; and a process of flattening the material after filling. The specific steps are as follows: S1 Preparation of the etching stop layer in the process of etching dielectric materials: Based on a single-polished substrate, a SiCN film of a certain thickness (determined by the etching thickness of the dielectric material) is deposited on the front side (polished surface) by chemical vapor deposition (CVD); S2: preparing dielectric material: depositing SiCOH dielectric material with a certain thickness (depending on the application scenario of the through hole or trench) on the above SiCN film by chemical vapor deposition (CVD); S3: preparing a hard mask layer: on the above SiCOH material, using chemical vapor deposition (CVD) to deposit a certain thickness (depending on the thickness of the SiCOH material) of tetraethyl orthosilicate (TEOS) as a hard mask layer.

[0005] S4: preparing an anti-reflection layer and flattening the surface: spin coating a carbon coating (SOC) of a certain thickness on the substrate having the above-mentioned film layer structure; and then spin coating a silicon-based anti-reflection layer of a certain thickness.

[0006] S5 patterned substrate: spin-coat photoresist on the above-mentioned substrate with a multi-layer structure; then perform an exposure process to obtain a patterned photoresist after development; then use the photoresist as a mask and adopt an inductively coupled plasma (ICP) etching method to etch down the anti-reflective layer; then use the inductively coupled plasma (ICP) etching method to etch the hard mask layer; then in situ ashing and stripping the remaining photoresist on the upper layer and the bottom anti-reflective layer; then use a plasma etching device to etch the dielectric material until the stop layer is etched; finally, use a plasma etching device to etch the stop layer to complete the etching of the through hole / groove.

[0007] S6 ion beam sputtering deposition material: using grazing angle ion beam sputtering (IBS) physical vapor deposition (PVD) to deposit conductive material in the through hole / groove obtained in the previous step, wherein the conductive material includes but is not limited to tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), cobalt (Co), nickel (Ni), iron (Fe) platinum (Pt), ruthenium (Ru) or a combination thereof.

[0008] S7 planarizes the metal-filled substrate; uses chemical mechanical polishing equipment (CMP) to polish and grind the uneven surface of the filled substrate, planarize the surface and remove excess material to meet the needs of subsequent process flows.

[0009] As described above, the ion beam sputtering deposition method of an integrated circuit interconnect metal layer of the present invention has the following beneficial effects: 1. The obtained filling structure has the characteristics of denseness, smooth surface, and close combination with the matrix; 2. No need to worry about product changes caused by stress; 3. It can further expand the application scenarios of ion beam sputtering, such as the deposition of metal layers for integrated circuit interconnects. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic flow chart showing the steps of an ion beam sputtering deposition method for an integrated circuit interconnect metal layer of the present invention.

[0011] Figure 2 Schematic diagram of a cross section after preparing an etch stop layer in the process of etching a dielectric material corresponding to step 1.

[0012] Figure 3 Schematic diagram of the cross section after the dielectric material is prepared in step 2.

[0013] Figure 4 The cross-sectional view after the hard mask layer is prepared in step 3 is shown.

[0014] Figure 5Schematic diagram of the cross section of the first anti-reflection layer prepared in step 4 and after surface flattening Figure 6 Schematic diagram of the cross section after preparing the second silicon-based anti-reflection layer in step 4.

[0015] Figure 7 Schematic diagram of the cross section after the photoresist is patterned by coating, exposing and developing in step 5.

[0016] Figure 8 This is a schematic cross-sectional view of etching the bottom layer material using the patterned photoresist as a mask in step 5 to achieve the transfer of the pattern to the multi-layer structure.

[0017] Fig. 9 Schematic diagram of the cross section after filling the via / trench using ion beam sputtering in step 6.

[0018] Fig.10 The schematic cross-sectional view corresponds to step 6 after depositing the conductive material by ion beam sputtering (IBS) or filling the conductive material by other methods such as electroplating (EP).

[0019] Fig.11 The schematic cross-sectional view of the step 7 after the chemical mechanical polishing (CMP) method is used to remove the excess metal material and the excess film structure on the surface.

[0020] Fig.12 This is a SEM cross-sectional image after trench filling using ion beam sputtering. DETAILED DESCRIPTION

[0021] The following is an explanation of the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the diagram provided in the present embodiment only illustrates the basic concept of the present invention in a schematic manner, and the diagram only shows the relevant part of the process flow in the present invention rather than all the detailed process steps when the actual process flow is implemented. The various process flows and related experimental parameters during the actual implementation can be changed according to actual needs.

[0022] The technical solution adopted by the present invention is an ion beam sputtering deposition method for an integrated circuit interconnect metal layer, and the specific steps are as follows: Step 1, preparing a thin film on a substrate as an etching stop layer; Step 2, preparing a low dielectric constant (Low-K) material on the film as a dielectric between metals; Step 3, depositing a thin film on the dielectric to serve as a hard mask covering the dielectric material and transferring the exposure pattern; Step 4, spin-on carbon coating (SoC) to flatten the surface; Step 5, spin coating an anti-reflection layer (ARC) to absorb the photolithography reflected light at the interface; Step 6, spin-coating photoresist on the sample surface, and performing exposure and development to prepare a photoresist pattern; then using the photoresist pattern as a mask, performing a subsequent process of etching different materials in multiple steps; Step 7, depositing a sidewall insulating layer; Step 8, depositing a barrier layer / adhesion layer / seed layer, with specific control parameters as follows: substrate temperature of 20°C, sputtering pressure of 0.02~1Pa, Ar gas flow rate of 20~40sccm, substrate rotation speed of 10~20r / min, and depositing a film layer with a thickness of no more than 10nm; Step 9, filling the grooves and through holes with metal; In step 10, chemical mechanical planarization (CMP) is used to remove excess material and polish the surface.

[0023] Furthermore, in step 1, the substrate is a single-sided polished silicon substrate, and the doping type is not limited.

[0024] Furthermore, in step 1, the film is a SiCN film, which is deposited on the front side (polished side) of the substrate using a chemical vapor deposition (CVD) device.

[0025] Furthermore, in step 2, the low dielectric constant material is SiCOH, and the deposition method is CVD.

[0026] Furthermore, in the step 3, the hard mask material used for covering the dielectric material and transferring the exposure pattern is tetraethyl orthosilicate (TEOS), and the deposition method is CVD.

[0027] Furthermore, the anti-reflection coating in step 5 is Si-ARC, SoC, or developable bottom anti-reflection coating (DBARC).

[0028] Furthermore, the photoresist described in step 6 can be various photoresist materials such as PMMA, SU8, HSQ, ZEP, ARP, UV5, etc.

[0029] Furthermore, the method for depositing the barrier layer / adhesion layer / seed layer in step 8 is grazing angle ion beam sputtering physical vapor deposition, with an ion beam energy of 500-700 eV, a beam current of 5-10 mA, and an acceleration voltage of 200-500 V ion beam.

[0030] Furthermore, the barrier layer / adhesion layer / seed layer material may be molybdenum (Mo), ruthenium (Ru), cobalt (Co), copper (Cu), tungsten (W), tantalum (Ta), titanium (Ti) and other metals and their compounds.

[0031] Furthermore, the barrier layer / adhesion layer / seed layer has the ability of high-quality fill after deposition, and can achieve 100% sidewall coverage after filling in nano-feature size (CD) and large aspect ratio (AR) grooves, good thickness uniformity, and can avoid overhangs and voids that may cause failures.

[0032] Furthermore, the nano feature size is between about 50 nm and about 200 nm.

[0033] Furthermore, the high aspect ratio is between about 3 and 10.

[0034] Furthermore, the thickness uniformity is the thickness uniformity of the metal filled in the side wall and the bottom, and the uniformity is ≥0.5%.

[0035] Furthermore, the metal material filling method in step 9 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, and atomic layer deposition (ALD).

[0036] Furthermore, the metal material described in step 9 has the characteristics of no void, low stress, low resistivity, etc. after filling.

[0037] Furthermore, the polishing liquid described in step 10 contains deionized water, an oxidant, silicon oxide, cerium oxide, aluminum oxide, a pH regulator, a composite abrasive, and a dispersant.

[0038] Furthermore, the preparation method includes but is not limited to using the process flow mentioned in the above specific steps, and focuses on the technical solutions of "grazing angle ion beam sputtering deposition" and "small CD large AR groove conformal filling".

[0039] An ion beam sputtering deposition device, comprising: Ion beam source chamber; Vacuum system; A control system configured to provide instructions to perform the following operations; The control system bombards the target material with a high-energy ion beam through an ion beam source chamber in a vacuum system, so that atoms on the surface of the target material are separated from the target material and fall on a substrate to form a film.

[0040] The ion beam source has a higher deposition energy, so that the deposited film has the characteristics of higher density and fewer defects. The working pressure of the vacuum system can be lower than 1e-2Pa, and the ultimate pressure is ≤7.0e-5Pa.

[0041] The target material and the substrate in the ion beam source chamber have the characteristics of completely neutral surfaces and the ion beam being able to achieve complete neutralization.

[0042] The ion beam source chamber has the characteristic of being able to independently control ion energy and ion beam current.

[0043] The ion beam source chamber has the characteristic of being able to pre-clean the substrate to improve the bonding effect between the base material and the film material.

[0044] The control system has the characteristic of being able to individually and accurately control each parameter in the ion beam sputtering process.

[0045] Embodiment 1: A method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line: Step 1, preparing a hard mask layer: on a silicon substrate material, using a chemical vapor deposition (CVD) method, depositing 200 nm thick silicon oxide as a hard mask layer.

[0046] Step 2, patterning the substrate: spin coating a photoresist on the substrate obtained above; then performing an exposure process, and obtaining a patterned photoresist after development; then using the photoresist as a mask, etching the hard mask layer downward by an inductively coupled plasma (ICP) etching method; then etching the substrate material by an inductively coupled plasma (ICP) etching method to form a groove; Step 3, ion beam sputtering deposition material; after the back vacuum is evacuated to 1e-4Pa, the conductive material is deposited into the through hole / groove obtained in the previous step by grazing angle ion beam sputtering (IBS) physical vapor deposition (PVD), wherein the ion beam energy used is 500eV, the Ar gas flow rate is 10sccm, the beam current is 7mA, the substrate rotation speed is 10r / min, the substrate temperature is 15°C, the deposition time is 150s, and the deposited Mo film thickness is 90nm. Fig.12 This is a SEM image of the metal cross section obtained in Example 1. It can be seen that the sidewall coverage is 100%, the sidewall is steep after filling, the cross section is dense and flat, and it is tightly bonded to the substrate without voids or cracks.

[0047] The specific embodiments and their working principles and preparation methods described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is not intended to limit the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for ion beam sputtering deposition of metal layers of integrated circuit interconnects, characterized in that: The specific steps of this method are as follows: Step 1, preparing a thin film on a substrate as an etching stop layer; Step 2, preparing a low dielectric constant material on the film as a dielectric between metals; Step 3, depositing a thin film on the dielectric to serve as a hard mask covering the dielectric material and transferring the exposure pattern; Step 4, spin coating a carbon coating to planarize the surface; Step 5, spin coating an anti-reflection layer to absorb the photolithography reflected light at the interface; Step 6, spin-coating photoresist on the sample surface, and performing exposure and development to prepare a photoresist pattern; then using the photoresist pattern as a mask, performing a subsequent process of etching different materials in multiple steps; Step 7, depositing a sidewall insulating layer; Step 8, depositing a barrier layer / adhesion layer / seed layer, with specific control parameters as follows: substrate temperature of 20°C, sputtering pressure of 0.02~1Pa, Ar gas flow rate of 20~40sccm, substrate rotation speed of 10~20r / min, and depositing a film layer with a thickness of no more than 10nm; Step 9, filling the grooves and through holes with metal; Step 10: Use chemical mechanical planarization (CMP) to remove excess material and polish the surface.

2. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: In the step 1, the substrate is a single-sided polished silicon substrate; the film is a SiCN film, which is deposited on the front side of the substrate, i.e., the polished side, by using a chemical vapor deposition (CVD) device.

3. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: In the step 2, the low dielectric constant material is SiCOH, and the deposition method is CVD.

4. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: In the step 3, the hard mask material used for covering the dielectric material and transferring the exposure pattern is tetraethyl orthosilicate (TEOS), and the deposition method is CVD.

5. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: The anti-reflective coating described in step 5 is Si-ARC, SoC, or developable bottom anti-reflective coating DBARC.

6. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: The photoresist described in step 6 is PMMA, SU8, HSQ, ZEP, ARP, UV5 and other types of photoresist materials.

7. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: The method of depositing the barrier layer / adhesion layer / seed layer in step 8 is grazing angle ion beam sputtering physical vapor deposition, the ion beam energy is 500-700 eV, the beam current is 5-10 mA, and the acceleration voltage is 200-500 V ion beam; The barrier layer / adhesion layer / seed layer material is molybdenum, ruthenium, cobalt, copper, tungsten, tantalum, titanium metal and their compounds; The barrier layer / adhesion layer / seed layer has the ability of high-quality filling after deposition, and can achieve a sidewall coverage of 100% after filling in nano-feature size CD and large aspect ratio AR grooves; the nano-feature size is between 50nm and 200nm; the large aspect ratio is between 3 and 10; the thickness uniformity is the uniformity of the metal thickness filled on the sidewall and the bottom, and the uniformity is ≥0.5%.

8. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: The metal material filling method in step 9 includes physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, and atomic layer deposition.

9. The method for ion beam sputtering deposition of metal layer of integrated circuit interconnection line according to claim 1, characterized in that: The polishing liquid described in step 10 contains deionized water, an oxidant, silicon oxide, cerium oxide, aluminum oxide, a pH regulator, a composite abrasive, and a dispersant.

10. An ion beam sputtering deposition device for implementing the ion beam sputtering deposition method for an integrated circuit interconnect metal layer as claimed in any one of claims 1 to 9, characterized in that: The device comprises: Ion beam source chamber; Vacuum system; A control system configured to provide instructions to perform the following operations; The control system bombards the target material with a high-energy ion beam through the ion beam source chamber in the vacuum system, so that atoms on the surface of the target material are separated from the target material and fall on the substrate to form a film; The working pressure of the vacuum system can be lower than 1e-2Pa, and the ultimate pressure is ≤7.0e-5Pa; The target material and substrate in the ion beam source chamber have the characteristics of completely neutral surfaces, and the ion beam can be completely neutralized; The ion beam source chamber independently controls ion energy and ion beam current; The ion beam source chamber is capable of pre-cleaning the substrate to improve the adhesion between the base material and the film material; The control system has the capability of individually and accurately controlling each parameter in the ion beam sputtering process.

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