Three-phase inverter parallel reconnection topological structure and modulation method thereof

Abstract

The invention provides a three-phase inverter parallel reconnection topological structure and a modulation method thereof. Relates to the technical field of inverter control. In the invention, a bus capacitor C1 and a bus capacitor C2 are integrally connected in parallel with three insulated gate bipolar transistor modules, and each insulated gate bipolar transistor module comprises a plurality of insulated gate bipolar transistor half bridges which are connected in parallel; a choke inductor is connected between the insulated gate bipolar transistors of the upper arm and the lower arm of each insulated gate bipolar transistor half-bridge of each insulated gate bipolar transistor module, and the output of the choke inductor of each insulated gate bipolar transistor module is connected with a filter inductor. During control, phase shifting is carried out on the triangular carrier of the parallel half-bridge of each phase by 360 degrees / N to obtain an initial triangular carrier; and equally dividing the initial triangular carrier wave into 2N right-angle carrier waves, synchronously segmenting the modulation wave, and comparing the sizes of the right-angle carrier waves and modulation wave segments before and after mirroring in each period to obtain half-bridge driving signals of each insulated gate bipolar transistor.

Description

Technical Field

[0001] The present invention relates to the technical field of inverter control, and in particular to a three-phase inverter parallel re-connection topology structure and a modulation method thereof. Background Art

[0002] As the power of inverter equipment becomes higher and higher, single IGBT modules can no longer meet the power requirements. In order to increase the power of the inverter, IGBT modules are generally connected in parallel. The pure parallel topology of IGBT modules is simple in PWM modulation, and only the parallel PWM signals need to be consistent. However, the IGBT drive transmission must be completely consistent, otherwise there will be inconsistencies in the drive signals between the two bridge arms, resulting in the risk of short-circuiting the bridge arms and causing the machine to explode. Moreover, the pure parallel topology of IGBT modules can only increase the output power of the inverter, but cannot increase the output switching frequency and level number of the inverter, cannot provide assistance for the design of output filter inductors and harmonic suppression, and cannot reduce the material cost and design size of the output filter inductors. If the switching frequency is to be increased, the switching loss of the IGBT will inevitably increase, or the use of higher-specification switch tubes will also increase the material cost.

[0003] Another control method for parallel connection of IGBT modules is to adopt carrier phase-shift PWM modulation. However, due to the phase difference between the modulation waves caused by this modulation method, it will inevitably lead to the alternating conduction of the upper and lower tubes of different IGBT modules. Therefore, in order to suppress the short circuit of the two IGBT modules during alternating conduction, a filter inductor is generally connected in series in the IGBT module loop. The filter inductor not only needs to suppress the high-frequency circulating current problem caused by the cross-conduction of the switch tube by increasing the inductance, but also needs to filter the fundamental current. However, a large inductance will cause the voltage drop caused by the fundamental current on the inductor to be too large, affecting the total output of the topology and even causing the inductor to saturate. Therefore, using the filter inductor for high-frequency circulating current suppression and fundamental current filtering at the same time is not conducive to inductor design. In addition, a large inductance requires an increase in the core size and the number of winding turns, which will also increase material costs. In terms of software, the traditional digital PWM modulation method has a certain delay compared to analog PWM modulation because the control chip can only refresh the comparison result when the counter is zero or the period register TBPRD value. Therefore, the modulation accuracy is not high, and the modulation waveform cannot be perfectly replicated to achieve the desired output effect. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present invention provides a three-phase inverter parallel re-connection topology structure and a modulation method thereof.

[0005] In a first aspect, the present invention provides a three-phase inverter parallel regeneration topology structure, comprising:

[0006] A bus capacitor C1 and a bus capacitor C2 connected in series for providing energy to the circuit, the bus capacitor C1 and the bus capacitor C2 are integrally connected in parallel to three insulated gate bipolar transistor modules, each of which includes: a plurality of insulated gate bipolar transistor half bridges connected in parallel;

[0007] A choke inductor is connected between the upper arm and lower arm IGBTs of each IGBT half-bridge of each IGBT module, and a filter inductor is connected to the output of the choke inductor of each IGBT module.

[0008] Furthermore, the inductor coil in the choke inductor adopts a common mode winding method.

[0009] Furthermore, an air gap is provided in the inductor core of the choke inductor to enhance the ability to resist fundamental current bias saturation.

[0010] Furthermore, the insulated gate bipolar transistor half bridge includes an upper arm insulated gate bipolar transistor and a lower arm insulated gate bipolar transistor.

[0011] Furthermore, the outputs of the choke inductors of the three IGBT modules are connected to the filter inductor L7 , the filter inductor L8 , and the filter inductor L9 , respectively.

[0012] In a second aspect, the present invention provides a three-phase inverter parallel re-connection topology structure modulation method, which is applied to the three-phase inverter parallel re-connection topology structure, and is characterized by comprising:

[0013] The triangular carriers of the parallel-connected insulated gate bipolar transistor half-bridges of each phase are phase-shifted by 360° / N to obtain N groups of initial triangular carriers corresponding to the insulated gate bipolar transistor half-bridges; wherein N is the number of the parallel-connected insulated gate bipolar transistor half-bridges of each phase;

[0014] The initial triangular carrier is equally divided into 2N right-angle carriers, and the modulated wave is synchronously processed in segments, wherein the modulation wave segment processing rule is as follows: the carrier count-up part is the modulation wave successively reduced by the triangular carrier cycle * (N-1), N = 1, 2, 3...N; the carrier count-down part is the modulation wave successively reduced by the triangular carrier cycle * (N-1), N = N...3, 2, 1; and in the whole process, in each triangular carrier cycle, the modulated wave is mirrored after the triangular carrier cycle / 2;

[0015] The half-bridge driving signals of each insulated gate bipolar transistor are obtained by comparing the sizes of the right-angle carrier and the modulation wave segments before and after the mirror image of each cycle.

[0016] Before mirroring, the modulated wave segment is larger than the right-angle carrier, the drive signal takes a high level, the modulated wave segment is smaller than the right-angle carrier, the drive signal takes a low level; after mirroring, the modulated wave segment is larger than the right-angle carrier, the drive signal takes a low level, the modulated wave segment is smaller than the right-angle carrier, the drive signal takes a high level.

[0017] The above technical solution provided by the embodiment of the present invention has the following advantages compared with the prior art:

[0018] The present application adopts an insulated gate bipolar transistor half-bridge parallel connection combined with a carrier phase-shift PWM modulation strategy to achieve the purpose of increasing the output power and level number of a three-phase inverter without increasing the switching frequency of the insulated gate bipolar transistor, improving the equivalent output switching frequency of each phase and the output current waveform quality, reducing the design parameter requirements of the output choke inductor and the output filter inductor, and reducing the material cost and volume of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0020] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A schematic diagram of a three-phase inverter parallel re-connection topology structure provided in an embodiment of the present invention;

[0022] Figure 2 A modulation signal timing diagram of a three-phase inverter parallel re-connection topology structure provided in an embodiment of the present invention;

[0023] Figure 3 A flow chart of a three-phase inverter parallel heavy topology structure modulation method provided by an embodiment of the present invention;

[0024] Figure 4 A schematic diagram of a three-phase inverter parallel re-connection topology structure state 1 provided in an embodiment of the present invention;

[0025] Figure 5 A schematic diagram of a three-phase inverter parallel re-connection topology structure state 2 provided in an embodiment of the present invention;

[0026] Figure 6 A schematic diagram of a three-phase inverter parallel re-connection topology structure state 3 provided in an embodiment of the present invention;

[0027] Figure 7 A schematic diagram of a three-phase inverter parallel re-connection topology structure state 4 provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0030] Example 1

[0031] like Figure 1 As shown, the technology of the present invention realizes a three-phase inverter parallel heavy topology structure, and the present invention includes:

[0032] The bus capacitors C1 and C2 are connected in series and used to provide energy for the circuit. The bus capacitors C1 and C2 are connected in parallel to form three insulated gate bipolar transistor modules. Each insulated gate bipolar transistor module includes: a plurality of insulated gate bipolar transistor half bridges connected in parallel.

[0033] exist Figure 1 In the example given, each IGBT module consists of two IGBT half-bridges:

[0034] In the insulated gate bipolar transistor module corresponding to phase A, one insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GA1 and a lower arm insulated gate bipolar transistor GA2, and the other insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GA3 and a lower arm insulated gate bipolar transistor GA4.

[0035] In the insulated gate bipolar transistor module corresponding to phase B, one insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GB1 and a lower arm insulated gate bipolar transistor GB2, and the other insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GB3 and a lower arm insulated gate bipolar transistor GB4.

[0036] In the insulated gate bipolar transistor module corresponding to phase C, one insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GC1 and a lower arm insulated gate bipolar transistor GC2, and the other insulated gate bipolar transistor half-bridge includes an upper arm insulated gate bipolar transistor GC3 and a lower arm insulated gate bipolar transistor GC4.

[0037] Each insulated gate bipolar transistor module is respectively connected to a choke inductor, and the inductor coil in the choke inductor adopts a common-mode winding method. When suppressing high-frequency circulating current, the inductor coil in the choke inductor will have mutual inductance. Therefore, under the same inductor design parameters, the total inductance is twice that of the filter inductor. Under the same inductance, the choke inductor can be made smaller, and the cost and weight are lower. For the fundamental current, since the magnetic circuits of the choke inductor cancel each other out and do not affect the output of each phase, the decoupling of the fundamental current filtering and the suppression of high-frequency circulating current is achieved. In addition, an air gap is set in the inductor core of the choke inductor. Under the premise of meeting the inductance requirements and the inductance of each heavy inductor being almost the same, the ability to resist fundamental current bias saturation is enhanced. Therefore, there is no need to perform current sharing control for each insulated gate bipolar transistor half-bridge, which simplifies the control algorithm.

[0038] exist Figure 1 In the given example, a choke inductor is connected between the upper arm and lower arm insulated gate bipolar transistors of each insulated gate bipolar transistor half-bridge of each insulated gate bipolar transistor module. For any one of the two choke inductors of each insulated gate bipolar transistor module, its A port is connected to one insulated gate bipolar transistor half-bridge, its a port is connected to the b port of another choke inductor, and its B port is connected to the B port of another choke inductor. As outputs, the A ports of the two choke inductors are connected to different insulated gate bipolar transistor half-bridges.

[0039] During the specific implementation process, in the insulated gate bipolar transistor module corresponding to phase A: the A port of the choke inductor L1 is connected between the upper arm insulated gate bipolar transistor GA1 and the lower arm insulated gate bipolar transistor GA2, the a port of the choke inductor L1 is connected to the b port of the choke inductor L2, the B port of the choke inductor L1 is connected to the B port of the choke inductor L2, and serves as the output; the A port of the choke inductor L2 is connected between the upper arm insulated gate bipolar transistor GA3 and the lower arm insulated gate bipolar transistor GA4, the a port of the choke inductor L2 is connected to the b port of the choke inductor L1, the B port of the choke inductor L2 is connected to the B port of the choke inductor L1, and serves as the output.

[0040] In the insulated gate bipolar transistor module corresponding to phase B: the A port of the choke inductor L3 is connected between the upper arm insulated gate bipolar transistor GB1 and the lower arm insulated gate bipolar transistor GB2, the a port of the choke inductor L3 is connected to the b port of the choke inductor L4, the B port of the choke inductor L3 is connected to the B port of the choke inductor L4, and serves as the output; the A port of the choke inductor L4 is connected between the upper arm insulated gate bipolar transistor GB3 and the lower arm insulated gate bipolar transistor GB4, the a port of the choke inductor L4 is connected to the b port of the choke inductor L3, the B port of the choke inductor L4 is connected to the B port of the choke inductor L3, and serves as the output.

[0041] In the insulated gate bipolar transistor module corresponding to phase C: the A port of the choke inductor L5 is connected between the upper arm insulated gate bipolar transistor GC1 and the lower arm insulated gate bipolar transistor GC2, the a port of the choke inductor L5 is connected to the b port of the choke inductor L6, the B port of the choke inductor L5 is connected to the B port of the choke inductor L6, and serves as the output; the A port of the choke inductor L6 is connected between the upper arm insulated gate bipolar transistor GC3 and the lower arm insulated gate bipolar transistor GC4, the a port of the choke inductor L6 is connected to the b port of the choke inductor L5, the B port of the choke inductor L6 is connected to the B port of the choke inductor L5, and serves as the output.

[0042] The output of the choke inductor of each insulated gate bipolar transistor module is connected to a filter inductor, which mainly plays the role of output filtering. Figure 1 In the given example, the outputs of the choke inductors of the three insulated gate bipolar transistor modules are connected to the filter inductor L7, the filter inductor L8 and the filter inductor L9 respectively.

[0043] Example 2

[0044] like Figure 2 and Figure 3 As shown, the present invention provides a novel three-phase inverter parallel heavy topology modulation method, which adopts the insulated gate bipolar transistor half-bridge parallel connection and carrier phase shift PWM modulation strategy to achieve the purpose of improving the output power and level number of the three-phase inverter without increasing the switching frequency of the insulated gate bipolar transistor, improving the equivalent output switching frequency of each phase and the output current waveform quality, reducing the difficulty of designing the output choke inductor and the output filter inductor, and reducing the material cost and volume of the inverter. It includes:

[0045] The triangular carrier of the parallel insulated gate bipolar transistor half bridge of each phase is rotated 360°

[0046] / N phase shifting is performed to obtain N groups of initial triangular carriers corresponding to the insulated gate bipolar transistor half-bridges; wherein N is the number of the insulated gate bipolar transistor half-bridges connected in parallel in each phase.

[0047] The initial triangular carrier used for modulation of the two insulated gate bipolar transistor half bridges is equally divided into 2N right-angle carriers, and the modulated wave is synchronously segmented. The modulation wave segmentation processing rule is as follows:

[0048] The carrier count-up part is the modulation wave that decreases the triangular carrier cycle*(N-1) in sequence, N=1, 2, 3...N;

[0049] The carrier count down part is the modulation wave that decreases the triangular carrier cycle*(N-1) in sequence, N=N...3, 2, 1;

[0050] And in the whole process, in each triangular carrier cycle, the modulated wave is mirrored after the triangular carrier cycle / 2.

[0051] The size of the right-angle carrier and the modulation wave before and after each cycle mirroring is compared to obtain the half-bridge drive signal of each insulated gate bipolar transistor. Before mirroring, the modulation wave segment is larger than the right-angle carrier, the drive signal takes a high level, the modulation wave segment is smaller than the right-angle carrier, and the drive signal takes a low level; after mirroring, the modulation wave segment is larger than the right-angle carrier, the drive signal takes a low level, the modulation wave segment is smaller than the right-angle carrier, and the drive signal takes a high level. After the processing is completed, the PWM modulation frequency becomes 2N times the original carrier frequency, making the inverter output waveform closer to the modulation wave.

[0052] Taking the dual topology structure as an example, the construction process of the initial triangular carrier is explained. Figure 2 As shown, the triangular carriers of the parallel insulated gate bipolar transistor half-bridges of each phase are phase-shifted by 180° to obtain two groups of initial triangular carriers corresponding to the insulated gate bipolar transistor half-bridges.

[0053] like Figure 2 As shown, within one cycle of the initial triangle wave, it is divided into 4 right-angle carrier waves, and the modulated wave is synchronously processed in segments. The modulation wave segment processing rules are as follows: the carrier count-up part is the modulation wave that decreases the triangle carrier cycle * (N-1) in sequence, N = 1, 2, 3...N; the carrier count-down part is the modulation wave that decreases the triangle carrier cycle * (N-1) in sequence, N = N...3, 2, 1; and in the whole process, in each triangle carrier cycle, the modulation wave is mirrored after the triangle carrier cycle / 2.

[0054] Due to the carrier phase shift debugging strategy, the A-phase output level of the dual topology structure is 3 levels. Under the premise of unchanged switching loss, the equivalent output switching frequency is twice the switching frequency of the insulated gate bipolar transistor. In theory, the more insulated gate bipolar transistor half-bridges connected in parallel, the higher the equivalent output frequency, the smaller the inductance design, the lower the cost and volume; the more levels, the lower the output harmonic content.

[0055] The carrier phase-shift PWM modulation method of the dual topology structure is analyzed as follows:

[0056] like Figure 4 As shown, in a carrier cycle, when phase A is in state 1, the insulated gate bipolar transistor GA1 and the insulated gate bipolar transistor GA4 are at a high level. U1N = Udc, U2N = 0V, where U1N is the voltage between the insulated gate bipolar transistor GA1 and the insulated gate bipolar transistor GA2, U2N is the voltage between the insulated gate bipolar transistor GA3 and the insulated gate bipolar transistor GA4, and Udc is the voltage of the busbar capacitor as a whole. U1N>U2N, there must be a circulating current Δi between the two branches, and the circulating current path is shown by the blue line in the figure. When the circulating current Δi passes through the choke inductor, since it enters from the same-name end of the winding and outputs from the opposite-name end, the choke inductor plays a role in hindering the circulating current, and due to the existence of mutual inductance, the inductance of a single inductor is twice that of the filter inductor. When the choke inductor passes the fundamental current, one way flows in from the same-name end and the other way flows in from the opposite-name end, and the magnetic circuits cancel each other out, and the inductor does not play a choking role on the fundamental current. In addition, the inductor core is provided with an air gap. Under the premise of meeting the inductance requirements and the inductance of each heavy inductor being almost the same, the ability to resist fundamental current bias saturation is enhanced. When the peak-to-peak value of the branch current reaches 100A, the peak-to-peak value of the fundamental circulating current is only 7A. This circulating current has little effect on the saturation of the choke inductor and the heating problem of the insulated gate bipolar transistor half-bridge. Therefore, it is not necessary to perform current sharing control on each parallel insulated gate bipolar transistor half-bridge, making the control algorithm simpler. In state 1, the output voltage Ua of phase A is Udc / 2.

[0057] like Figure 5 As shown, in one carrier cycle, when phase A is in state 2, the insulated gate bipolar transistor GA1 and the insulated gate bipolar transistor GA3 are at a high level, 1N=U2N=Udc, the circulating current Δi maintains the original state, and in state 2, the output voltage Ua of phase A is Udc.

[0058] like Figure 6 As shown, in one carrier cycle, when phase A is in state 3, the insulated gate bipolar transistor GA2 and the insulated gate bipolar transistor GA3 are at a high level, U2N=Udc, U1N=0V, U2N>U1N, the circulating current Δi is reversed, and in state 3, the output voltage Ua of phase A is Udc / 2.

[0059] like Figure 7 As shown, in one carrier cycle, when phase A is in state 4, the insulated gate bipolar transistor GA2 and the insulated gate bipolar transistor GA4 are at a high level, U1N=U2N=0, the circulating current Δi remains unchanged, and in state 4, the output voltage Ua of phase A is 0.

[0060] Filter inductors L7, L8, and L9 filter the three-phase fundamental current. Since each phase is controlled by carrier phase shift, the equivalent output switching frequency is N times the actual switching frequency of the insulated gate bipolar transistor, and the number of output levels for each phase is N+1. Therefore, the inductance required for equal ripple is half of that for pure parallel connection, and the magnetic core and winding required for the designed inductor will be less.

[0061] In the embodiments provided by the present invention, it should be understood that the disclosed structures and methods can be implemented in other ways. For example, the structural embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, structures or units, which can be electrical, mechanical or other forms.

[0062] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0063] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0064] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A three-phase inverter parallel regeneration topology structure, characterized in that: include: A bus capacitor C1 and a bus capacitor C2 connected in series for providing energy to the circuit, the bus capacitor C1 and the bus capacitor C2 are integrally connected in parallel to three insulated gate bipolar transistor modules, each of which includes: a plurality of insulated gate bipolar transistor half bridges connected in parallel; A choke inductor is connected between the upper arm and lower arm IGBTs of each IGBT half-bridge of each IGBT module, and a filter inductor is connected to the output of the choke inductor of each IGBT module.

2. The three-phase inverter parallel regeneration topology structure according to claim 1, characterized in that: The inductor coil in the choke inductor adopts a common mode winding method.

3. The three-phase inverter parallel regeneration topology structure according to claim 1, characterized in that: An air gap is set in the inductor core of the choke inductor to enhance the ability to resist fundamental current bias saturation.

4. The three-phase inverter parallel regeneration topology structure according to claim 1, characterized in that: The insulated gate bipolar transistor half bridge includes an upper arm insulated gate bipolar transistor and a lower arm insulated gate bipolar transistor.

5. The three-phase inverter parallel regeneration topology structure according to claim 1, characterized in that: The outputs of the choke inductors of the three IGBT modules are connected to the filter inductor L7, the filter inductor L8 and the filter inductor L9 respectively.

6. A three-phase inverter parallel re-connection topology structure modulation method, applied to the three-phase inverter parallel re-connection topology structure described in any one of claims 1-5, characterized in that: include: The triangular carriers of the parallel-connected insulated gate bipolar transistor half-bridges of each phase are phase-shifted by 360° / N to obtain N groups of initial triangular carriers corresponding to the insulated gate bipolar transistor half-bridges; wherein N is the number of the parallel-connected insulated gate bipolar transistor half-bridges of each phase; The initial triangular carrier is equally divided into 2N right-angle carriers, and the modulated wave is synchronously processed in segments, wherein the modulation wave segment processing rule is as follows: the carrier count-up part is the modulation wave that sequentially reduces the triangular carrier cycle * (N-1), N = 1, 2, 3...N; the carrier count-down part is the modulation wave that sequentially reduces the triangular carrier cycle * (N-1), N = N...3, 2, 1; and in the whole process, in each triangular carrier cycle, the modulated wave is mirrored after the triangular carrier cycle / 2; The half-bridge driving signals of each insulated gate bipolar transistor are obtained by comparing the sizes of the right-angle carrier and the modulation wave segments before and after the mirror image of each cycle.

7. The three-phase inverter parallel heavy topology structure modulation method according to claim 6, characterized in that: Before mirroring, the modulated wave segment is larger than the right-angle carrier, the drive signal takes a high level, the modulated wave segment is smaller than the right-angle carrier, the drive signal takes a low level; after mirroring, the modulated wave segment is larger than the right-angle carrier, the drive signal takes a low level, the modulated wave segment is smaller than the right-angle carrier, the drive signal takes a high level.

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