Common-mode differential-mode operational amplifier circuit

Abstract

The invention discloses a common-mode differential-mode operational amplifier circuit. In the biasing circuit, the power supply supplies power to the current source; the output end of the current source is connected with the drain electrode and the grid electrode of the fifteenth NMOS tube M15 and is connected with a first bias voltage vbn at the same time; and the source electrode of the fifteenth NMOS tube is grounded. In the input stage circuit, the source electrode of a fifth PMOS tube M5 is connected with the power supply, the grid electrode of the fifth PMOS tube is connected with a second bias voltage vbp, and the drain electrode of the fifth PMOS tube is connected with the source electrode of a first PMOS tube M1, the source electrode of a second PMOS tube M2 and the source electrode of a sixth PMOS tube M6; the grid electrode of the first PMOS tube and the grid electrode of the second PMOS tube receive a pair of differential mode input signals vip and vin when being used for differential mode amplification, and receive a pair of common mode input signals vic and vic when being used for common mode amplification; the grid electrode of the sixth PMOS tube is always connected with a common-mode voltage vcom; and the drain electrode of the sixth PMOS tube is connected to the drain electrode of the fifteenth NMOS tube, namely a node Z. The whole circuit is simple in structure and can be used for differential mode amplification and common mode amplification.

Description

Technical Field

[0001] The present application relates to an operational amplifier circuit having two modes: common-mode amplification and differential-mode amplification. Background Art

[0002] See also Figure 1 This is a traditional operational amplifier circuit, which includes three parts from left to right: bias circuit, input stage circuit, and output stage circuit. The bias circuit is used to provide a suitable static operating point for the operational amplifier. The input stage circuit realizes the differential mode amplification (differential amplification) function. The output stage circuit is used to provide a small input impedance and sufficient output gain.

[0003] Figure 1 In the bias circuit shown, the power supply VCC supplies power to the current source A1. The output end of the current source A1 is connected to the drain and gate of the NMOS tube M15, and is also connected to the bias voltage vbn. The source of the NMOS tube M15 is grounded. The bias circuit provides static bias current for the subsequent input stage circuit and output stage.

[0004] Figure 1 In the input stage circuit shown, the source of the PMOS tube M5 is connected to the power supply VCC, the gate of the PMOS tube M5 is connected to the bias voltage vbp, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M1 and the source of the PMOS tube M2. The gate of the PMOS tube M1 and the gate of the PMOS tube M2 receive a pair of differential (i.e., differential) input signals vip and vin. A differential signal refers to a pair of signals of equal magnitude and opposite polarity. The drain of the PMOS tube M1 and the drain of the PMOS tube M2 are connected to the current source load in the output stage circuit, specifically, they are connected to the drain of the NMOS tube M13 (node ​​X) and the drain of the NMOS tube M14 (node ​​Y) respectively. The input stage circuit converts a pair of differential input signals vip and vin into differential currents and sends them to nodes X and Y, so that the voltages of nodes X and Y change accordingly.

[0005] Figure 1In the output stage circuit shown, the source of the PMOS tube M7 and the source of the PMOS tube M8 are both connected to the power supply VCC. The gate of the PMOS tube M7 and the gate of the PMOS tube M8 are both connected to the bias voltage vbp. The drain of the PMOS tube M7 and the drain of the PMOS tube M8 are respectively connected to the source of the PMOS tube M9 and the source of the PMOS tube M10. The gate of the PMOS tube M9 and the gate of the PMOS tube M10 are both connected to the bias voltage vbpc. The drain of the PMOS tube M9 and the drain of the PMOS tube M10 are respectively connected to the drain of the NMOS tube M11 and the drain of the NMOS tube M12, and output a pair of differential mode signals outn and outp after amplification. The gate of the NMOS tube M11 and the gate of the NMOS tube M12 are both connected to the bias voltage vbnc. The source of the NMOS tube M11 and the source of the NMOS tube M12 are respectively connected to the drain of the NMOS tube M13 (node ​​X) and the drain of the NMOS tube M14 (node ​​Y). The gate of the NMOS tube M13 and the gate of the NMOS tube M14 are both connected to the bias voltage vbn. The source of the NMOS tube M13 and the source of the NMOS tube M14 are both grounded. The output stage circuit amplifies the voltage changes of the node X and the node Y through the common gate amplifier (NMOS tube M11 and NMOS tube M12) to obtain a pair of differential output voltages outn and outp.

[0006] Figure 1 The operational amplifier circuit shown can only realize differential mode amplification function, but cannot realize common mode amplification function. Most of the existing operational amplifier circuits that can simultaneously amplify common mode signals and differential mode signals have complex structures. Summary of the invention

[0007] The technical problem to be solved by the present application is: how to realize an operational amplifier circuit with a simple structure and having both common-mode amplification and differential-mode amplification functions.

[0008] In order to solve the above technical problems, the present application proposes a common-mode differential-mode operational amplifier circuit, including a bias circuit, an input stage circuit, and an output stage circuit. In the bias circuit, the power supply is a current source; the output end of the current source is connected to the drain and gate of the fifteenth NMOS tube M15, and is connected to the first bias voltage vbn; the source of the fifteenth NMOS tube is grounded. In the input stage circuit, the source of the fifth PMOS tube M5 is connected to the power supply, the gate of the fifth PMOS tube is connected to the second bias voltage vbp, and the drain of the fifth PMOS tube is connected to the source of the first PMOS tube M1, the source of the second PMOS tube M2 and the source of the sixth PMOS tube M6; the gate of the first PMOS tube and the gate of the second PMOS tube receive a pair of differential mode input signals vip and vin when used for differential mode amplification, and receive a pair of common mode input signals vic and vic when used for common mode amplification; the gate of the sixth PMOS tube is always connected to the common mode voltage vcom; the drain of the first PMOS tube and the drain of the second PMOS tube are respectively connected to the drain of the thirteenth NMOS tube M13, i.e., the node X, and the drain of the fourteenth NMOS tube M14, i.e., the node Y; the drain of the sixth PMOS tube is connected to the drain of the fifteenth NMOS tube, i.e., the node Z.

[0009] Furthermore, in the input stage circuit, the first PMOS tube and the second PMOS tube constitute a common-source amplifier.

[0010] Furthermore, in the input stage circuit, the fifth PMOS tube, the first PMOS tube and the second PMOS tube constitute a differential mode input part; the fifth PMOS tube, the first PMOS tube, the second PMOS tube and the sixth PMOS tube constitute a common mode input part; the sixth PMOS tube pulls the current generated by the common mode voltage to the node Z.

[0011] Furthermore, in the bias circuit, the sum of the current output by the current source and the current output by the sixth PMOS tube flows through the fifteenth NMOS tube together.

[0012] Further, in the output stage circuit, the source of the seventh PMOS tube M7 and the source of the eighth PMOS tube M8 are both connected to the power supply; the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are both connected to the second bias voltage; the drain of the seventh PMOS tube and the drain of the eighth PMOS tube are respectively connected to the source of the ninth PMOS tube M9 and the source of the tenth PMOS tube M10; the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are both connected to the third bias voltage vbpc; the drain of the ninth PMOS tube and the drain of the tenth PMOS tube are respectively connected to the source of the ninth PMOS tube M9 and the source of the tenth PMOS tube M10; The drain of the eleventh NMOS tube M11 and the drain of the twelfth NMOS tube M12 respectively output a pair of differential mode or common mode signals outn and outp after amplification; the gate of the eleventh NMOS tube and the gate of the twelfth NMOS tube are both connected to the fourth bias voltage vbnc; the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are respectively connected to the node X and the node Y; the gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube are both connected to the first bias voltage; the source of the thirteenth NMOS tube and the source of the fourteenth NMOS tube are both grounded;

[0013] Furthermore, in the output stage circuit, the eleventh NMOS tube and the twelfth NMOS tube form a common gate amplifier.

[0014] Furthermore, in the output stage circuit, when used for differential mode amplification, the differential mode current generated by a pair of differential mode input signals charges or discharges the node X and the node Y respectively, and the differential mode changes of the node X and the node Y are amplified to obtain a pair of differential output signals; when used for common mode amplification, the common mode current generated by comparing the common mode input signal with the common mode level charges or discharges the node X and the node Y at the same time, and the common mode changes of the node X and the node Y are amplified to obtain a pair of common mode output signals.

[0015] Further, the fifth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube provide a static bias current; specifically, the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, and the gate of the eighth PMOS tube are all connected to the second bias voltage to form three current sources. The fifth PMOS tube provides a static bias current for the sixth PMOS tube, the first PMOS tube, and the second PMOS tube. The seventh PMOS tube provides a static bias current for the ninth PMOS tube, the eleventh NMOS tube, and the thirteenth NMOS tube. The eighth PMOS tube provides a static bias current for the tenth PMOS tube, the twelfth NMOS tube, and the fourteenth NMOS tube. The fifteenth NMOS tube, the thirteenth NMOS tube, and the fourteenth NMOS tube form a current mirror, mirroring the sum of the current output by the current source and the current output by the sixth PMOS tube to the output stage circuit. The static bias current flowing through the first PMOS tube and the static bias current flowing through the seventh PMOS tube, the ninth PMOS tube, and the eleventh NMOS tube flow into the node X together, and the static bias current of the node X flows to the ground through the thirteenth NMOS tube. The static bias current flowing through the second PMOS tube and the static bias current flowing through the eighth PMOS tube, the tenth PMOS tube, and the twelfth NMOS tube flow into the node Y together, and the static bias current of the node Y all flows to the ground through the fourteenth NMOS tube.

[0016] Furthermore, when used for differential mode amplification, a pair of differential mode input voltages enter the gate of the first PMOS tube and the gate of the second PMOS tube respectively, and the common mode voltage enters the gate of the sixth PMOS tube, respectively generating a first dynamic current and a second dynamic current in the first PMOS tube and the second PMOS tube; the current flowing through the sixth PMOS tube is still a static bias current. When the positive input voltage (vip) increases and the negative input voltage (vin) decreases, the absolute values ​​of the two voltages increase synchronously; the first dynamic current flowing into the node X decreases, discharges the node X, and reduces the voltage of the node X; the second dynamic current flowing into the node Y increases, charges the node Y, and increases the voltage of the node Y; the voltage of the node X is amplified by the common gate of the eleventh NMOS tube, so that the drain voltage (outn) of the eleventh NMOS tube decreases by ΔV; the voltage of the node Y is amplified by the common gate of the twelfth NMOS tube, so that the drain voltage (outp) of the twelfth NMOS tube increases by ΔV; the differential input signal (vip, vin) is amplified into a differential output signal (outp, outn).

[0017] Furthermore, when used for common-mode amplification, a pair of common-mode input voltages enter the gate of the first PMOS tube and the gate of the second PMOS tube respectively, and the common-mode voltage enters the gate of the sixth PMOS tube, generating a first dynamic current, a second dynamic current, and a third dynamic current in the first PMOS tube, the second PMOS tube, and the sixth PMOS tube respectively. When the common-mode input voltage decreases to be less than the common-mode voltage, the first dynamic current and the second dynamic current increase, and the third dynamic current decreases; after being mirrored by the current mirror, the dynamic current flowing through the thirteenth NMOS tube and the fourteenth NMOS tube decreases; the increased first dynamic current flows into node X, charges node X, and increases the voltage of node X; the increased second dynamic current flows into node Y, charges node Y, and increases the voltage of node Y; the voltage of node X is amplified by the common gate of the eleventh NMOS tube, so that the drain voltage (outn) of the eleventh NMOS tube increases by ΔV; the voltage of node Y is amplified by the common gate of the twelfth NMOS tube, so that the drain voltage (outp) of the twelfth NMOS tube increases synchronously by ΔV; thereby, the difference (vic-vcom) between the common-mode input voltage and the common-mode voltage is amplified to the variation of the common-mode output signal.

[0018] The technical effect achieved by the present application is that the overall circuit structure is simple and can be used for both differential mode amplification and common mode amplification. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The present invention is a circuit structure diagram of an existing operational amplifier which can only realize differential mode amplification.

[0020] Figure 2 It is a circuit structure diagram of a common-mode and differential-mode operational amplifier proposed in this application.

[0021] Figure 3 yes Figure 2 The schematic diagram of the principle of realizing differential mode amplification by the common-mode differential-mode operational amplifier shown.

[0022] Figure 4 yes Figure 2 The schematic diagram of the common-mode differential-mode operational amplifier for realizing common-mode amplification is shown.

[0023] Explanation of the reference numerals in the figure: VCC is the power supply; vip and vin are differential input signals; vic is the common-mode input voltage; vcom is the common-mode voltage; outp and outn are output signals; A1 is the current source; M1 to M15 are MOS tubes; vbn, vbp, vbpc, vbnc are bias voltages; X, Y, Z are nodes; Vx is the voltage of node X; Vy is the voltage of node Y. DETAILED DESCRIPTION

[0024] See also Figure 2The common-mode differential-mode operational amplifier circuit proposed in this application includes three parts from left to right: a bias circuit, an input stage circuit, and an output stage circuit. The bias circuit is used to provide a suitable static operating point for the operational amplifier. The input stage circuit realizes two functions of differential mode amplification and common mode amplification. The output stage circuit is used to provide a small input impedance and provide sufficient output gain.

[0025] Figure 2 In the bias circuit shown, the power source VCC supplies power to the current source A1. The output end of the current source A1 is connected to the drain and gate of the NMOS tube M15, and is also connected to the bias voltage vbn. The source of the NMOS tube M15 is grounded.

[0026] Figure 2 In the input stage circuit shown, the source of the PMOS tube M5 is connected to the power supply VCC, the gate of the PMOS tube M5 is connected to the bias voltage vbp, and the drain of the PMOS tube M5 is connected to the source of the PMOS tube M1, the source of the PMOS tube M2, and the source of the PMOS tube M6. The gate of the PMOS tube M1 and the gate of the PMOS tube M2 receive a pair of differential mode input signals vip and vin when used for differential mode amplification, and receive a pair of common mode input signals vic and vic when used for common mode amplification. Figure 2 (not shown in the figure). A differential mode signal refers to a pair of signals of equal magnitude and opposite polarity. A common mode signal refers to a pair of signals of equal magnitude and same polarity. The gate of the PMOS tube M6 is always connected to the common mode voltage vcom. The common mode voltage vcom is used to provide a reference object for comparison for the common mode input signal vic. The drain of the PMOS tube M1 and the drain of the PMOS tube M2 are connected to the current source load in the output stage circuit, specifically, to the drain of the NMOS tube M13 (node ​​X) and the drain of the NMOS tube M14 (node ​​Y). The drain of the PMOS tube M6 is connected to the drain of the NMOS tube M15 in the bias circuit (node ​​Z).

[0027] Figure 2 The output stage circuit shown is Figure 1 The structure of the output stage circuit shown is exactly the same, and will not be described here. However, outp and outn are no longer limited to differential mode output signals, but may also be common mode output signals. The output stage circuit adopts a common gate amplifier structure, which can not only reduce input impedance, but also improve speed, increase output impedance, and increase output gain.

[0028] Compare Figure 1 and Figure 2 It can be found that the difference in the input stage circuit is only Figure 2In the rounded rectangle 20, the present application adds a PMOS tube M6. In the input stage circuit of the present application, the three devices of PMOS tube M5, PMOS tube M1 and PMOS tube M2 constitute the differential mode input part, which is the same as the existing input stage circuit. In the input stage circuit of the present application, PMOS tube M5, PMOS tube M1, PMOS tube M2 and PMOS tube M6 constitute the common mode input part, which is not available in the existing input stage circuit. PMOS tube M6 pulls the current generated by the common mode voltage vcom to the node Z position in the bias circuit, and can realize the function of common mode amplification without affecting the differential mode amplification. This circuit structure for realizing common mode amplification is very simple.

[0029] Compare Figure 1 and Figure 2 It can be seen that the difference in the bias circuit is only Figure 2 In the rounded rectangle 10, the drain current of the newly added PMOS tube M6 in the present application flows into the drain of the NMOS tube M15, so the working state of the bias circuit of the present application changes, specifically, the sum of the current output by the current source A1 and the current output by the PMOS tube M6 flows through the NMOS tube M15. The working state of the existing bias circuit is: only the current output by the current source A1 passes through the NMOS tube M15.

[0030] Figure 1 and Figure 2 The structure of the output stage circuit in is the same, but the working state has changed. When used for differential mode amplification, the differential mode current generated by a pair of differential input signals vip and vin charges (or discharges) nodes X and Y respectively, and the output stage circuit amplifies the differential mode changes of nodes X and Y to obtain a pair of differential output signals outn and outp. This working state is the same for the existing output stage circuits and the output stage circuits of the present application. The output stage circuit of the present application adds a working state for common mode amplification. The common mode current generated by comparing the common mode input signal vic with the common mode level vcom charges (or discharges) nodes X and Y at the same time. The output stage circuit of the present application amplifies the common mode changes of nodes X and Y to obtain a pair of common mode output signals outn and outp, which is not available in the existing output stage circuits.

[0031] Figure 2In the common-mode differential-mode operational amplifier circuit shown, whether used for differential-mode amplification or common-mode amplification, PMOS tube M5, PMOS tube M7, PMOS tube M8, NMOS tube M13 and NMOS tube M14 all provide static bias current. Specifically, the gate of PMOS tube M5, the gate of PMOS tube M7 and the gate of PMOS tube M8 are all connected to a fixed bias voltage vbp to form three current sources. PMOS tube M5 provides static bias current for PMOS tube M6, PMOS tube M1 and PMOS tube M2. PMOS tube M7 provides static bias current for PMOS tube M9, NMOS tube M11 and NMOS tube M13. PMOS tube M8 provides static bias current for PMOS tube M10, NMOS tube M12 and NMOS tube M14. The NMOS tube M15, the NMOS tube M13 and the NMOS tube M14 form a current mirror, mirroring the sum of the current output by the current source A1 and the current output by the PMOS tube M6 to the output stage circuit, thereby providing a static bias current for the NMOS tube M13 and the NMOS tube M14. The static bias current flowing through the PMOS tube M1 and the static bias current flowing through the PMOS tube M7, the PMOS tube M9 and the NMOS tube M11 flow into the node X together, and the static bias current of the node X flows to the ground through the NMOS tube M13. The sum of the static bias current flowing through the PMOS tube M1 and the static bias current flowing through the PMOS tube M7, the PMOS tube M9 and the NMOS tube M11 is equal to the static bias current mirrored to the NMOS tube M13 by the current mirror. The static bias current flowing through the PMOS tube M2 and the static bias current flowing through the PMOS tube M8, the PMOS tube M10, and the NMOS tube M12 flow into the node Y together. The static bias current of the node Y all flows to the ground through the NMOS tube M14. The sum of the static bias current flowing through the PMOS tube M2 and the static bias current flowing through the PMOS tube M8, the PMOS tube M10, and the NMOS tube M12 is equal to the static bias current mirrored to the NMOS tube M14 by the current mirror.

[0032] See also Figure 3The principle of the common-mode differential-mode operational amplifier circuit proposed in this application to realize the differential-mode amplification function is as follows. When used for differential-mode amplification, a pair of differential-mode input voltages vip and vin enter the gate of the PMOS tube M1 and the gate of the PMOS tube M2 respectively, and the common-mode voltage vcom enters the gate of the PMOS tube M6. The positive input voltage vip generates a first dynamic current in the PMOS tube M1, and the negative input voltage vin generates a second dynamic current in the PMOS tube M2. The two dynamic currents are equal in magnitude and opposite in direction. The static bias current still flows through the PMOS tube M6, and there is no dynamic current. When the positive input voltage vip increases and the negative input voltage vin decreases (the absolute values ​​of the two voltages increase synchronously), the first dynamic current decreases, the second dynamic current increases, and the absolute values ​​of the two dynamic currents increase synchronously. At this time, the static bias current flowing through the PMOS tube M6 remains unchanged. The reduced first dynamic current flows into the node X, which is equivalent to the first dynamic current discharging the node X, so that the voltage Vx of the node X decreases (the absolute value increases). The increased second dynamic current flows into the node Y, which is equivalent to the second dynamic current charging the node Y, so that the voltage Vy of the node Y increases. The voltage Vx is amplified by the common gate of the NMOS tube M11, so that the drain voltage outn of the NMOS tube M11 decreases by ΔV. At the same time, the voltage Vy is amplified by the common gate of the NMOS tube M12, so that the drain voltage outp of the NMOS tube M12 increases by ΔV. After the above process, the differential input signals vip and vin are amplified into differential output signals outp and outn, that is, the differential mode amplification function is realized. Here, the differential mode input signal changes to illustrate the differential mode amplification function, and the differential mode amplification function can be realized even if the differential mode input signal does not change.

[0033] See also Figure 4The principle of the common-mode differential-mode operational amplifier circuit proposed in this application to realize the common-mode amplification function is as follows. When used for common-mode amplification, a pair of common-mode input voltages vic and vic enter the gate of the PMOS tube M1 and the gate of the PMOS tube M2 respectively, and the common-mode voltage vcom enters the gate of the PMOS tube M6. The common-mode input voltage vic generates a first dynamic current in the PMOS tube M1, the common-mode input voltage vic generates a second dynamic current in the PMOS tube M2, and the common-mode voltage vcom generates a third dynamic current in the PMOS tube M6. When the common-mode input voltage vic decreases, that is, when vic < vcom, the first dynamic current and the second dynamic current increase, and the third dynamic current decreases. Because the third dynamic current decreases, the dynamic current flowing through the NMOS tube M13 and the NMOS tube M14 is reduced after being mirrored by the current mirror formed by the NMOS tube M15 and the NMOS tube M13 and the NMOS tube M14. The increased first dynamic current flows into the node X, which is equivalent to charging the node X, so that the voltage Vx of the node X increases. The increased second dynamic current flows into node Y, which is equivalent to charging node Y, so that the voltage Vy of node Y increases. After the voltage Vx of node X is amplified by the common gate of NMOS tube M11, the drain voltage outn of NMOS tube M11 increases by ΔV. After the voltage of node Y is amplified by the common gate of NMOS tube M12, the drain voltage outp of NMOS tube M12 increases synchronously by ΔV. As a result, the difference vic-vcom between the common-mode input voltage vic and the common-mode voltage vcom (that is, the change of the common-mode input signal relative to the common-mode voltage) is amplified to the change of the common-mode output signal ΔV, that is, the common-mode amplification function is realized. Here, the change of the common-mode input signal is listed to illustrate the common-mode amplification function, and the common-mode amplification function can be realized even if the common-mode input signal does not change.

[0034] In summary, the present application proposes a common-mode differential-mode operational amplifier circuit, which only makes a small structural change on the basis of the existing differential-mode operational amplifier circuit, but greatly changes the working state of the overall circuit, so that the overall circuit adds a common-mode amplification function.

[0035] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should all be included in the protection scope of the present application.

Claims

1. A common-mode differential-mode operational amplifier circuit, characterized in that: Including bias circuit, input stage circuit, output stage circuit; In the bias circuit, the power supply is a current source; the output end of the current source is connected to the drain and gate of the fifteenth NMOS tube (M15), and is also connected to the first bias voltage (vbn); the source of the fifteenth NMOS tube is grounded; In the input stage circuit, the source of the fifth PMOS tube (M5) is connected to the power supply, the gate of the fifth PMOS tube is connected to the second bias voltage (vbp), and the drain of the fifth PMOS tube is connected to the source of the first PMOS tube (M1), the source of the second PMOS tube (M2) and the source of the sixth PMOS tube (M6); the gate of the first PMOS tube and the gate of the second PMOS tube receive a pair of differential mode input signals (vip, vin) when used for differential mode amplification, and receive a pair of common mode input signals (vic, vic) when used for common mode amplification; the gate of the sixth PMOS tube is always connected to the common mode voltage (vcom); the drain of the first PMOS tube and the drain of the second PMOS tube are respectively connected to the drain of the thirteenth NMOS tube (M13), i.e., node X, and the drain of the fourteenth NMOS tube (M14), i.e., node Y; the drain of the sixth PMOS tube is connected to the drain of the fifteenth NMOS tube, i.e., node Z.

2. The common-mode differential-mode operational amplifier circuit according to claim 1, characterized in that: In the input stage circuit, the first PMOS tube and the second PMOS tube form a common source amplifier.

3. The common-mode differential-mode operational amplifier circuit according to claim 1, characterized in that: In the input stage circuit, the fifth PMOS tube, the first PMOS tube and the second PMOS tube constitute a differential mode input part; the fifth PMOS tube, the first PMOS tube, the second PMOS tube and the sixth PMOS tube constitute a common mode input part; the sixth PMOS tube pulls the current generated by the common mode voltage to the node Z.

4. The common-mode differential-mode operational amplifier circuit according to claim 3, characterized in that: In the bias circuit, the sum of the current output by the current source and the current output by the sixth PMOS tube flows through the fifteenth NMOS tube together.

5. The common-mode differential-mode operational amplifier circuit according to claim 1, characterized in that: In the output stage circuit, the source of the seventh PMOS tube (M7) and the source of the eighth PMOS tube (M8) are both connected to the power supply; the gate of the seventh PMOS tube and the gate of the eighth PMOS tube are both connected to the second bias voltage; the drain of the seventh PMOS tube and the drain of the eighth PMOS tube are respectively connected to the source of the ninth PMOS tube (M9) and the source of the tenth PMOS tube (M10); the gate of the ninth PMOS tube and the gate of the tenth PMOS tube are both connected to the third bias voltage (vbpc); the drain of the ninth PMOS tube and the drain of the tenth PMOS tube are respectively connected to the source of the eleventh PMOS tube (M9). The drain of the NMOS tube (M11) and the drain of the twelfth NMOS tube (M12) respectively output a pair of differential mode or common mode signals (outn, outp) after amplification; the gate of the eleventh NMOS tube and the gate of the twelfth NMOS tube are both connected to a fourth bias voltage (vbnc); the source of the eleventh NMOS tube and the source of the twelfth NMOS tube are respectively connected to a node X and a node Y; the gate of the thirteenth NMOS tube and the gate of the fourteenth NMOS tube are both connected to the first bias voltage; the source of the thirteenth NMOS tube and the source of the fourteenth NMOS tube are both grounded.

6. The common-mode differential-mode operational amplifier circuit according to claim 5, characterized in that: In the output stage circuit, the eleventh NMOS tube and the twelfth NMOS tube form a common gate amplifier.

7. The common-mode differential-mode operational amplifier circuit according to claim 5, characterized in that: In the output stage circuit, when used for differential mode amplification, the differential mode current generated by a pair of differential mode input signals charges or discharges the node X and the node Y respectively, and the differential mode changes of the node X and the node Y are amplified to obtain a pair of differential output signals; when used for common mode amplification, the common mode current generated by comparing the common mode input signal with the common mode level charges or discharges the node X and the node Y at the same time, and the common mode changes of the node X and the node Y are amplified to obtain a pair of common mode output signals.

8. The common-mode differential-mode operational amplifier circuit according to claim 5, characterized in that: The fifth PMOS tube, the seventh PMOS tube, and the eighth PMOS tube provide a static bias current; specifically, the gate of the fifth PMOS tube, the gate of the seventh PMOS tube, and the gate of the eighth PMOS tube are all connected to the second bias voltage to form three current sources; The fifth PMOS tube provides a static bias current for the sixth PMOS tube, the first PMOS tube, and the second PMOS tube; The seventh PMOS tube provides a static bias current for the ninth PMOS tube, the eleventh NMOS tube and the thirteenth NMOS tube; The eighth PMOS tube provides a static bias current for the tenth PMOS tube, the twelfth NMOS tube and the fourteenth NMOS tube; The fifteenth NMOS tube, the thirteenth NMOS tube and the fourteenth NMOS tube form a current mirror, mirroring the sum of the current output by the current source and the current output by the sixth PMOS tube to the output stage circuit; The static bias current flowing through the first PMOS tube and the static bias current flowing through the seventh PMOS tube, the ninth PMOS tube, and the eleventh NMOS tube flow into the node X together, and the static bias current of the node X flows to the ground through the thirteenth NMOS tube; The static bias current flowing through the second PMOS tube and the static bias current flowing through the eighth PMOS tube, the tenth PMOS tube, and the twelfth NMOS tube flow into the node Y together, and the static bias current of the node Y all flows to the ground through the fourteenth NMOS tube.

9. The common-mode differential-mode operational amplifier circuit according to claim 8, characterized in that: When used for differential mode amplification, a pair of differential mode input voltages enter the gate of the first PMOS tube and the gate of the second PMOS tube respectively, and the common mode voltage enters the gate of the sixth PMOS tube, respectively generating a first dynamic current and a second dynamic current in the first PMOS tube and the second PMOS tube; the current flowing through the sixth PMOS tube is still a static bias current; When the positive input voltage (vip) increases and the negative input voltage (vin) decreases, the absolute values ​​of the two voltages increase synchronously; the first dynamic current flowing into node X decreases, discharging node X and reducing the voltage of node X; the second dynamic current flowing into node Y increases, charging node Y and increasing the voltage of node Y; the voltage of node X is amplified by the common gate of the eleventh NMOS tube, so that the drain voltage (outn) of the eleventh NMOS tube decreases by ΔV; the voltage of node Y is amplified by the common gate of the twelfth NMOS tube, so that the drain voltage (outp) of the twelfth NMOS tube increases by ΔV; the differential input signal (vip, vin) is amplified to a differential output signal (outp, outn).

10. The common-mode differential-mode operational amplifier circuit according to claim 8, characterized in that: When used for common-mode amplification, a pair of common-mode input voltages enter the gate of the first PMOS tube and the gate of the second PMOS tube respectively, and the common-mode voltage enters the gate of the sixth PMOS tube, generating a first dynamic current, a second dynamic current, and a third dynamic current in the first PMOS tube, the second PMOS tube, and the sixth PMOS tube respectively; When the common-mode input voltage decreases to be less than the common-mode voltage, the first dynamic current and the second dynamic current increase, and the third dynamic current decreases; after being mirrored by the current mirror, the dynamic current flowing through the thirteenth NMOS tube and the fourteenth NMOS tube decreases; the increased first dynamic current flows into node X, charges node X, and increases the voltage of node X; the increased second dynamic current flows into node Y, charges node Y, and increases the voltage of node Y; the voltage of node X is amplified by the common gate of the eleventh NMOS tube, so that the drain voltage (outn) of the eleventh NMOS tube increases by ΔV; the voltage of node Y is amplified by the common gate of the twelfth NMOS tube, so that the drain voltage (outp) of the twelfth NMOS tube increases synchronously by ΔV; thereby, the difference (vic-vcom) between the common-mode input voltage and the common-mode voltage is amplified to the variation of the common-mode output signal.

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