Data communication method, data communication system and domain controller

Abstract

The invention provides a data communication method, a data communication system and a domain controller, and relates to the technical field of data communication. The method comprises the steps that a microcontroller responds to a first general purpose input and output port of a microprocessor to be switched from a high level to a low level, and a second general purpose input and output port and a third general purpose input and output port are set to be high levels respectively; the microcontroller responds to the received first data sent by the microprocessor and switches the second general purpose input / output port from the high level to the low level; and the microcontroller switches the third universal input / output port from the high level to the low level in response to the failure of verification of the first data. The method can reduce the probability of data communication failure.

Description

Technical Field

[0001] The present disclosure relates to the field of data communication technology, and in particular to a data communication method, a data communication system and a domain controller. Background Art

[0002] In the vehicle environment, the data communication between the microprocessor unit (MPU) and the microcontroller unit (MCU) may be interfered by the internal and external environment, such as board-level and off-board electromagnetic interference, etc. When interfered, the communication between the microprocessor and the microcontroller will be abnormal. The illegal data generated by the abnormal communication cannot be correctly parsed, which will cause the corresponding function to be abnormal, and normal services cannot be provided, affecting the user experience. Summary of the invention

[0003] The embodiments of the present disclosure provide a data communication method, a data communication system, and a domain controller, which can reduce the probability of data communication failure.

[0004] In a first aspect, an embodiment of the present disclosure proposes a data communication method, including: in response to a first general purpose input / output port of a microprocessor switching from a high level to a low level, a microcontroller sets a second general purpose input / output port and a third general purpose input / output port to high levels respectively; in response to receiving first data sent by the microprocessor, the microcontroller switches the second general purpose input / output port from a high level to a low level; in response to a failure to verify the first data, the microcontroller switches the third general purpose input / output port from a high level to a low level.

[0005] In a second aspect, an embodiment of the present disclosure proposes a data communication system, comprising: a microprocessor and a microcontroller. The microcontroller is configured to perform the following operations: in response to the first general purpose input / output port of the microprocessor switching from a high level to a low level, the second general purpose input / output port and the third general purpose input / output port are respectively set to a high level; in response to receiving the first data sent by the microprocessor, the second general purpose input / output port is switched from a high level to a low level; in response to the first data verification failure, the third general purpose input / output port is switched from a high level to a low level.

[0006] In a third aspect, an embodiment of the present disclosure provides a domain controller, including: a data communication system as described in any implementation method in the second aspect above.

[0007] The data communication method, data communication system and domain controller provided by the embodiments of the present disclosure, when the microcontroller detects that the first GPIO of the microprocessor is switched from a high level to a low level, the microcontroller sets its second GPIO port and the third GPIO port to a high level respectively, so that when it is known that the microprocessor has triggered or started data communication with the microcontroller, the microprocessor is informed that it is ready for data communication by making its second GPIO port and the third GPIO port at a high level, and further, when the first data sent by the microprocessor is received, the second GPIO port can be level-switched to inform the microprocessor that it has received the first data and needs to verify the first data, that is, error detection, and when the data verification fails, the third GPIO port is switched from the previous high level to a low level, so as to inform the microprocessor that the verification of the received data has failed by level switching the third GPIO port of the microcontroller. In this way, the state interaction in the data communication process is realized by using the dynamic level switching of the three GPIO ports. When the data is checked abnormally, the level of one of the GPIO ports of the microcontroller is switched to inform the opposite microprocessor, thereby realizing dynamic detection of data abnormalities for further processing, thereby reducing the probability of data communication failure.

[0008] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present disclosure will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0010] Figure 1 is an exemplary system architecture in which the present disclosure may be applied;

[0011] Figure 2 A flow chart of a data communication method provided by an embodiment of the present disclosure;

[0012] Figure 3 A flowchart of another data communication method provided by an embodiment of the present disclosure;

[0013] Figure 4 A schematic diagram of the connection relationship between the microprocessor and the microcontroller based on SPI provided in an embodiment of the present disclosure;

[0014] Figure 5 A schematic diagram of a flow chart of a data communication method in an application scenario provided by an embodiment of the present disclosure;

[0015] Figure 6 A structural block diagram of a data communication system provided by an embodiment of the present disclosure;

[0016] Figure 7 A structural block diagram of a domain controller provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description. It should be noted that the embodiments in the present disclosure and the features in the embodiments may be combined with each other without conflict.

[0018] It should be pointed out that in the technical solution of the present disclosure, the collection, acquisition, storage, processing, transmission, provision, disclosure and application of user personal information (such as information required by the corresponding vehicle system when the user logs into the vehicle, etc.) are all carried out with the user's knowledge and explicit authorization, comply with the relevant laws and regulations, and do not violate public order and good morals.

[0019] Figure 1 An exemplary system architecture 100 is shown to which embodiments of the data communication method, data communication system, and domain controller of the present disclosure can be applied, and a vehicle can be applied.

[0020] like Figure 1 As shown, the system architecture 100 may include but is not limited to a first domain controller (Domain Control Unit, DCU) 101 and a second domain controller 102 that establish a communication connection, wherein the first domain controller 101 and the second domain controller 102 may establish a communication connection via Ethernet, and of course, may also establish a communication connection via other types of network protocols. It should be noted that Figure 1 The number of the first domain controller 101 and the second domain controller 102 in the system architecture 100 shown does not constitute a limitation. According to specific implementation requirements, there can be any number of the first domain controller 101 and the second domain controller 102.

[0021] In some optional implementations of the disclosed embodiments, the first domain controller 101 may be implemented as a cockpit domain controller (CDC), and the second domain controller 102 may be implemented as an intelligent driving domain controller. The cockpit domain controller may provide infotainment functions, driving data display functions, driving assistance functions, etc., to enhance the user's driving experience. The intelligent driving domain controller may integrate and manage the vehicle's autonomous driving related functions, such as adaptive cruise control, collision warning functions, lane departure related functions, etc.

[0022] Furthermore, in some optional implementations of the embodiments of the present disclosure, the first domain controller 101 and the second domain controller 102 may respectively include a microcontroller (Micro Control Unit, MCU) and a microprocessor (Microprocessor Unit, MPU) (or system-on-chip (System on Chips, SoC) (also known as system on chip)) in hardware architecture, and the microcontroller and the microprocessor (or SoC) may communicate and interact with each other.

[0023] Among them, the above-mentioned SoC means that it is a product, an integrated circuit with a dedicated purpose, which contains all the contents of a complete system and embedded software. In a narrow sense, SoC is the chip integration of the core of the information system, which integrates the key components of the system on a chip; in a broad sense, SoC is a micro-system. Generally speaking, SoC can be defined as the integration of a microprocessor, analog IP (Intellectual Property) core, digital IP core and memory (or off-chip storage control interface) on a single chip. It is usually customized by the user or a standard product for specific purposes.

[0024] Furthermore, in some optional implementations of the embodiments of the present disclosure, at least one of an Android operating system, a UNIX-like operating system (Linux), a UNIX-like real-time operating system (Quick UNIX, QNX) and the like can be deployed and run on the above-mentioned microprocessor or system-level chip.

[0025] In the related art, the data communication between the microcontroller and the microprocessor (or SoC) in the vehicle environment may be interfered by the internal and external environment, such as board-level and off-board electromagnetic interference, etc. When interfered, the communication between the microprocessor and the microcontroller will be abnormal, and the illegal data generated by the abnormal communication cannot be correctly parsed, which will cause the corresponding function to be abnormal, and normal services cannot be provided, affecting the user experience.

[0026] Please refer to Figure 2 , Figure 2A flow chart of a data communication method provided in an embodiment of the present disclosure can be applied to but not limited to vehicles, and the process 200 includes the following steps:

[0027] Step 201: In response to the first GPIO port of the microprocessor switching from a high level to a low level, the microcontroller sets the second GPIO port and the third GPIO port to high levels respectively.

[0028] This step is intended to be performed by a microcontroller (e.g. Figure 1 When the MCU deployed in the first domain controller 101 or the second domain controller 102 shown detects that the microprocessor switches its first general purpose input / output (GPIO) port from a high level to a low level, it can be known that the microprocessor has triggered or started data communication with the microcontroller, and it is necessary to set its second GPIO port and the third GPIO port to a high level to prepare for data communication with the microprocessor. Among them, setting the second GPIO port and the third GPIO port to a high level can also be understood as determining the second GPIO port and the third GPIO port to be a high level respectively. The specific implementation method can be that if the second GPIO port and / or the third GPIO port are already at a high level when the first GPIO port is detected to be switched from a high level to a low level, they continue to remain at a high level, and if the second GPIO port and / or the third GPIO port are at a low level when the first GPIO port is detected to be switched from a high level to a low level, they are switched to a high level accordingly.

[0029] Step 202: In response to receiving the first data sent by the microprocessor, the microcontroller switches the second general purpose input / output port from a high level to a low level.

[0030] On the basis of the above step 201, when the microcontroller sets its second GPIO port and the third GPIO port to high levels respectively to prepare for data communication with the microprocessor, the microcontroller can receive the first data sent by the microprocessor, and after receiving the first data, switch the above second GPIO port from the previous high level to a low level, so as to inform the microprocessor through level switching that it has successfully received the first data.

[0031] Step 203: In response to the failure of verifying the first data, the microcontroller switches the third general purpose input / output port from a high level to a low level.

[0032] On the basis of the above step 202, the microcontroller needs to verify the first data sent by the microprocessor after receiving it, and in the case that the verification of the first data fails, the above third GPIO port needs to be switched from the previous high level to a low level, so as to inform the microprocessor through the level switching that the verification of the received data has failed, which means that an abnormality has occurred in the data during transmission or after storage and cannot be correctly parsed.

[0033] The data communication method provided by the embodiment of the present disclosure is that when the microcontroller detects that the first GPIO of the microprocessor is switched from a high level to a low level, the microcontroller sets its second GPIO port and the third GPIO port to a high level respectively, so that when it is known that the microprocessor has triggered or started the data communication with the microcontroller, the second GPIO port and the third GPIO port are at a high level to inform the microprocessor that it is ready for data communication, and further, when the first data sent by the microprocessor is received, the second GPIO port is level-switched to inform the microprocessor that it has received the first data and needs to verify the first data, that is, error detection, and when the data verification fails, the third GPIO port is switched from the previous high level to a low level, so as to inform the microprocessor that the verification of the received data fails by level switching the third GPIO port of the microcontroller. In this way, the state interaction in the data communication process is realized by using the dynamic level switching of the three GPIO ports, and when the data verification is abnormal, the level of one of the GPIO ports of the microcontroller is switched to inform the opposite microprocessor, so as to realize the dynamic detection of data abnormality, so as to facilitate further processing, thereby reducing the probability of data communication failure.

[0034] Please refer to Figure 3 , Figure 3 A flowchart of another data communication method provided in an embodiment of the present disclosure can be applied to but not limited to vehicles, and the process 300 includes the following steps:

[0035] Step 301: In response to the first GPIO port of the microprocessor switching from a high level to a low level, the microcontroller sets the second GPIO port and the third GPIO port to high levels respectively.

[0036] Step 302: In response to receiving the first data sent by the microprocessor, the microcontroller switches the second general purpose input / output port from a high level to a low level.

[0037] Step 303: In response to a failure in verifying the first data, the microcontroller switches the third general purpose input / output port from a high level to a low level.

[0038] The above steps 301-303 are similar to Figure 2 Steps 201-203 shown are consistent, and for the same contents, please refer to the corresponding parts of the previous embodiment, which will not be repeated here.

[0039] Step 304: The microprocessor switches the first general purpose input / output port from a high level to a low level again in response to at least one of the following being satisfied: the third general purpose input / output port is switched from a high level to a low level; the microprocessor fails to verify the second data received from the microcontroller.

[0040] Step 305: The microprocessor resends the first data to the microcontroller in response to the first GPIO port switching from high level to low level again; and / or the microcontroller resends the second data to the microprocessor in response to the first GPIO port switching from high level to low level again.

[0041] Based on the above step 303, in one case, the microprocessor (e.g. Figure 1 When the MPU or SOC deployed in the first domain controller 101 or the second domain controller 102 shown detects that the third GPIO interface of the microcontroller is switched from the previous high level to the low level, it can be learned that the microcontroller fails to verify the first data sent to it by the microprocessor. At this time, the microprocessor can switch its first GPIO port from the high level to the low level again to efficiently trigger or start the data retransmission between the microcontroller. In another case, after the microprocessor switches its first GPIO port from the high level to the low level, it can receive the second data sent by the microcontroller and verify the received second data. In the case of failure to verify the second data, the microprocessor can also switch its first GPIO port from the high level to the low level again to efficiently trigger or start the data retransmission between the microcontroller. In this way, the reliability of data communication between the microcontroller and the microprocessor can be ensured, thereby reducing the probability of communication failure.

[0042] In the data communication method provided by the embodiment of the present disclosure, the microprocessor detects that the third GPIO port of the microcontroller is switched from a previous high level to a low level, and when it is learned that the microcontroller fails to verify the first data received from the microprocessor, and / or when the microprocessor fails to verify the second data received from the microcontroller, the microprocessor can switch its first GPIO port from a high level to a low level again to efficiently trigger or start data retransmission with the microcontroller; further, the microprocessor can resend the above-mentioned first data to the microcontroller and / or the microcontroller can resend the above-mentioned second data to the microprocessor, so as to ensure the reliability of data communication between the microcontroller and the microprocessor, thereby reducing the probability of communication failure.

[0043] In some optional implementations of the embodiments of the present disclosure, the following content may also be included: the microcontroller performs a restart operation in response to the number of retransmissions of the second data reaching a preset threshold. In this way, by limiting the number of data retransmissions by the microcontroller, the microcontroller performs a corresponding restart operation when the upper limit of the number of retransmissions, i.e., the preset threshold, is reached, and the efficiency of data communication can be further guaranteed. Furthermore, in some optional implementations of the embodiments of the present disclosure, the value of the preset threshold includes 1 or 2, that is, the microcontroller can be allowed to retransmit the second data once or twice.

[0044] In some optional implementations of the embodiments of the present disclosure, the following content may also be included: the microprocessor performs a restart operation in response to the number of retransmissions of the first data reaching a preset threshold. In this way, by limiting the number of data retransmissions by the microprocessor, the microprocessor performs a corresponding restart operation when the upper limit of the number of retransmissions, i.e., the preset threshold, is reached, and the efficiency of data communication can be further guaranteed. Furthermore, in some optional implementations of the embodiments of the present disclosure, the value of the preset threshold includes 1 or 2, that is, the microprocessor may be allowed to retransmit the first data once or twice.

[0045] It should be noted that the value of the above preset threshold can also be set to other values ​​according to actual needs, depending on the specific situation.

[0046] In some optional implementations of the embodiments of the present disclosure, the following content may also be included: the above-mentioned microprocessor maintains the first general input and output port at a high level within a preset time period in response to successful verification of the second data and the third general input and output port not switching from a high level to a low level within a preset time period.

[0047] In this embodiment, the process in which the microprocessor triggers data communication between the microprocessor and the microcontroller by switching its first GPIO port from a high level to a low level can be a periodic process, that is, when there is no abnormality in the data communication between the microprocessor and the microcontroller, the microprocessor switches its first GPIO port from a high level to a low level once at intervals of the above preset time length, and then maintains the level of the port at a high level within the preset time length. The value of the preset time length can be set according to actual needs and is not specifically limited here; in some optional implementations, the value of the preset time length can be set to 10ms.

[0048] In the above Figure 2 The corresponding embodiments and Figure 3On the basis of the corresponding embodiment, the following content may also be included: in response to the successful verification of the first data, the microcontroller maintains the third general purpose input and output port at a high level within the preset time. In this embodiment, when there is no abnormality in the data communication between the microcontroller and the microprocessor, the third GPIO port can be maintained at a high level during the current data communication cycle.

[0049] In the above Figure 2 The corresponding embodiments and Figure 3 On the basis of the corresponding embodiment, the microcontroller can perform a cyclic redundancy check (CRC) on the first data received from the microprocessor, and the microprocessor can perform a cyclic redundancy check on the second data received from the microcontroller, so as to detect data errors that may occur during the transmission process of data communication between the microcontroller and the microprocessor or after the data is saved. Since CRC is an algorithm that uses software for verification, it has the advantages of fast verification speed and low verification bit error rate, so it can improve the data transmission speed during data communication.

[0050] In the above Figure 2 The corresponding embodiments and Figure 3 On the basis of the corresponding embodiments, the microprocessor and the microcontroller communicate based on a serial peripheral interface (SPI), thereby realizing high-speed, full-duplex, synchronous data transmission. There are two working modes based on the SPI communication mode, namely, master mode and slave mode. In some optional implementations of the embodiments of the present disclosure, the microprocessor is a host based on SPI communication and the microcontroller is a slave based on SPI communication. Specifically, the host, namely the microprocessor, can start the synchronous communication of the slave, namely the microcontroller, thereby completing the transmission and exchange of data, wherein the number of the slave microprocessors can be one or more.

[0051] Furthermore, in some optional implementations of the embodiments of the present disclosure, the SPI-based communication between the microprocessor and the microcontroller is as follows: Figure 4 The GPIO_MCU1, GPIO_MCU2 and GPIO_MPU shown (can correspond to the above Figure 2 and Figure 3 In addition to the second GPIO port, the third GPIO port and the first GPIO port in the corresponding embodiment, it also involves four common ports (or pins), such as Figure 4As shown, it includes: (1) a serial clock (SCLK) port, through which the host microprocessor can provide the serial clock it generates to the slave microcontroller for synchronous data transmission; (2) a master input / slave output (MISO) port, through which the slave microcontroller can input its output data to the host microprocessor; (3) a master output / slave input (MOSI) port, through which the host microprocessor can input its output data to the slave microcontroller; (4) a slave select (SS / NSS) port, also known as a chip select (CS) port, which is an enable port of the slave microcontroller and is controlled by the host microprocessor. When it is in a predetermined enable signal (such as a low voltage), it means that the slave is selected, that is, the operation of the slave microcontroller is valid, that is, the slave microcontroller can transmit data with the host microprocessor at this time.

[0052] To deepen understanding, the present disclosure also provides a specific implementation scheme of a data communication method in combination with a specific application scenario. In this specific implementation scheme, the microcontroller can be an MCU, the microprocessor can be an MPU, and data can be bidirectionally communicated between the MCU and the MPU. This bidirectional communication can be based on the SPI channel and protocol (hereinafter referred to as SPI communication, such as information of small data volume between the instrument panel of the vehicle and the vehicle infotainment system), wherein the MPU is the host and the MCU is the slave. When the two communicate, at least four lines of SCLK (or SCK), MISO, MOSI and NSS can be used, and the baud rate can be set to 5Mbps (megabits per second). In normal mode, the above-mentioned SPI communication is carried out in a round-robin manner, such as once every 10ms on average (that is, the time interval between every two communications is at least 10ms, as close to 10ms as possible), and the amount of data for each communication can include 768 bytes.

[0053] In this specific implementation, in order to increase the communication quality, improvements can be made from both hardware and software aspects. In terms of hardware, three GPIO ports are used for error retransmission, and in terms of software, logical protection is performed according to the defined retransmission rules. The GPIO ports output by the MCU end can be called GPIO_MCU1 and GPIO_MCU2, and the GPIO ports output by the MPU end can be called GPIO_MPU. When there is no communication, ports GPIO_MCU1, GPIO_MCU2, and GPIO_MPU are all at a high level. Furthermore, the process 500 of this specific implementation may at least include the following contents:

[0054] Step 501: Before the MPU initiates communication, the level of the GPIO_MPU port is first pulled down, that is, the GPIO_MPU port is switched from a high level to a low level to trigger the SPI data interaction with the MCU.

[0055] Step 502: Determine whether the SPI communication is successful; if not, proceed to step 503; otherwise, proceed to step 504.

[0056] After the MPU pulls down the level of its GPIO_MPU port, the MPU and MCU perform CRC check on the data received by each after completing the interaction of a frame of data. Specifically, for the MCU, after receiving data from the MPU, the level of its GPIO_MCU1 port can be pulled down, and the MCU performs data verification. If the verification fails, it can be determined that the current SPI communication has failed, and step 503 can be executed; if the verification succeeds, it means that the SPI communication is successful, and the level of the MCU's GPIO_MCU2 port can be kept at a high level.

[0057] Step 503: The MCU can pull the level of its GPIO_MCU2 port from a high level to a low level to trigger data retransmission between the MCU and the MPU, that is, initiate secondary communication. Specifically, the MPU in the above step 501 can pull down the level of its GPIO_MPU port to trigger data communication between the two. Among them, when retransmission is performed after SPI communication fails, a maximum of 1 retransmission, 2 retransmissions or no retransmission is allowed.

[0058] It should be noted that in the above step 502, for the MPU, after receiving the data from the MCU, the data verification is also performed. If the verification fails, it can be determined that the current SPI communication has failed, and further, the MPU in the above step 501 can also trigger the data communication between the two by lowering the level of its GPIO_MPU port; if the verification is successful, it means that the SPI communication is successful, and the MPU will not lower the level of the GPIO_MPU port again in the current round-robin cycle. In addition, in this specific implementation, after the SPI data interaction between the MCU and the MPU, the MPU has not received feedback from the MCU side. For example, after the MPU sends data to the MCU, it is necessary to reserve a processing (such as data verification) time (such as 1ms) for the MCU. If the MPU does not receive feedback from the MCU after the processing time, it can also be considered that the SPI communication between the MCU is abnormal, and further, the MPU in the above step 501 can trigger the data communication between the two by lowering the level of its GPIO_MPU port. Thus, in the SPI communication, as long as one party determines that the data is wrong, a second communication can be triggered immediately, and the content of the second communication can be exactly the same as the previous one. Furthermore, if the data retransmission also fails, the MCU and MPU can be restarted.

[0059] Step 504: The MPU and MCU may perform corresponding data processing operations on the data received respectively.

[0060] In this specific implementation, after a successful communication or retransmission, the MPU can pull up the level of the GPIO_MPU port to indicate that the SPI communication of this cycle is completed, and the MCU can also pull up the levels of the GPIO_MCU1 and GPIO_MCU2 ports to prepare for the next round of SPI communication.

[0061] In this specific implementation scheme, the specific application scenario may include a vehicle control scenario, such as an air conditioning control scenario, a window control scenario, a vehicle camera control scenario, etc. Taking the air conditioning control scenario as an example, in response to the vehicle computer (corresponding to the MPU) screen receiving a trigger operation for turning on the air conditioning, that is, the MPU receives a command to control turning on the air conditioning, then the MPU can pull down the level of its GPIO_MPU port before sending the command to the MCU through the SPI, so that the MCU responds to the level switching of the GPIO_MPU port to ensure that the levels of its GPIO_MCU1 and GPIO_MCU2 are at a high level, and further, after confirming that the command has been received, the MCU can pull down the level of the GPIO_MCU1 port, and in the case of a successful CRC of the command, it can be sent to the vehicle's air conditioning controller through the controller area network (Controller Area Network, CAN) bus or other means to perform the operation of turning on the air conditioning. If the CRC of the command fails, it is necessary to pull the level of its GPIO_MCU2 port from a high level to a low level to trigger the MPU to resend the command. The process of other vehicle control scenarios is similar to that of the air conditioning control scenario, and will not be repeated here.

[0062] It should be noted that the above implementation scheme can also be applied to other scenarios. The MCU forwards the vehicle's CAN message to the MPU through the SPI channel, where the vehicle's CAN message can specifically include the vehicle's fuel level, mileage and other status information.

[0063] Through this specific data communication scheme, protection against SPI communication failure can be achieved without affecting the original SPI communication. That is, when an abnormality occurs, the abnormality can be detected through software CRC, and the other party in communication can be notified through the GPIO port. That is, protection is provided through the above three GPIO ports for further processing, so as to realize dynamic detection of abnormalities in SPI communication between dual chips, thereby reducing the communication failure rate.

[0064] Further references Figure 6 As an implementation of the methods shown in the above figures, the present disclosure provides an embodiment of a data communication system. The system embodiment corresponds to the above method embodiment. The system can be specifically applied to various electronic devices, such as a domain controller in a vehicle.

[0065] like Figure 6 As shown, the data communication system 600 of this embodiment may include: a microcontroller 602 and a microprocessor 601 .

[0066] The microcontroller 602 is configured to perform the following operations: in response to the first general input / output port 6011 of the microprocessor 601 being switched from a high level to a low level, the second general input / output port 6021 and the third general input / output port 6022 are respectively set to high levels; in response to receiving the first data sent by the microprocessor 601, the second general input / output port 6021 is switched from a high level to a low level; in response to a failure in verifying the first data, the third general input / output port 6022 is switched from a high level to a low level.

[0067] In the data communication system 600, the specific processing of the microcontroller 602 and the microprocessor 601 and the technical effects thereof can be referred to in Figure 2 The relevant descriptions of steps 201 - 203 in the corresponding embodiment are not repeated here.

[0068] In some optional implementations of the embodiments of the present disclosure, the above-mentioned microprocessor 601 is configured to switch the first general input and output port 6011 from a high level to a low level again in response to at least one of the following being met: the third general input and output port 6022 is switched from a high level to a low level; the microprocessor 601 fails to verify the second data sent by the microcontroller 602.

[0069] In some optional implementations of the embodiments of the present disclosure, the above-mentioned microprocessor 601 is further configured to resend the first data to the microcontroller 602 in response to the first general input / output port 6011 switching from a high level to a low level again; and / or the above-mentioned microcontroller 602 is further configured to resend the second data to the microprocessor 601 in response to the first general input / output port 6011 switching from a high level to a low level again.

[0070] In the present embodiment, in the data communication system 500, the specific processing of the microcontroller 602501 and the microprocessor 601502 and the technical effects thereof can be referred to in Figure 3 The relevant descriptions of steps 301 - 305 in the corresponding embodiment are not repeated here.

[0071] In some optional implementations of the embodiments of the present disclosure, the microcontroller 602 is further configured to perform a restart operation in response to the number of retransmissions of the second data reaching a preset threshold.

[0072] In some optional implementations of the embodiments of the present disclosure, the microprocessor 601 is further configured to execute a restart operation in response to the number of retransmissions of the first data reaching a preset threshold.

[0073] In some optional implementations of the embodiments of the present disclosure, the value of the above-mentioned preset threshold includes 1 or 2.

[0074] In some optional implementations of the embodiments of the present disclosure, the above-mentioned microprocessor 601 is further configured to maintain the first general input and output port 6011 at a high level within a preset time period in response to successful verification of the second data and the third general input and output port 6022 not switching from a high level to a low level within a preset time period.

[0075] In some optional implementations of the embodiments of the present disclosure, the microprocessor 601 and the microcontroller 602 communicate with each other based on a serial peripheral interface, and the microprocessor 601 is a host based on the serial peripheral interface communication, and the microcontroller 602 is a slave based on the serial peripheral interface communication.

[0076] This embodiment exists as a system embodiment corresponding to the above method embodiment. In the data communication system 600 provided by this embodiment, when the microcontroller 602 detects that the first GPIO of the microprocessor 601 is switched from a high level to a low level, the microcontroller 602 sets its second GPIO port and the third GPIO port to a high level respectively, so that when it is known that the microprocessor 601 triggers or starts data communication with the microcontroller 602, the microprocessor 601 is informed that it is ready for data communication by making its second GPIO port and the third GPIO port at a high level. Further, when the first data sent by the microprocessor 601 is received, the second GPIO port can be level-switched to inform the microprocessor 601 that it has received the first data and needs to verify the first data, that is, error detection, and when the data verification fails, the third GPIO port is switched from the previous high level to a low level, so as to inform the microprocessor 601 that the verification of the received data has failed by level switching the third GPIO port of the microcontroller 602. In this way, the state interaction in the data communication process is realized by using the dynamic level switching of the three GPIO ports, and when an abnormality is found in the data verification, the level of one of the GPIO ports of the microcontroller 602 is switched to inform the opposite microprocessor 601, thereby realizing dynamic detection of data abnormality, so as to facilitate further processing, thereby reducing the probability of data communication failure.

[0077] Further references Figure 7 Corresponding to the implementation of the system shown in the above embodiment, the present disclosure provides an embodiment of a domain controller, which is consistent with the above embodiment. Figure 6 Corresponding to the system embodiment shown, the domain controller can be specifically applied to various vehicles.

[0078] like Figure 7 As shown, the domain controller 700 of this embodiment may include: Figure 6The technical effects of the data communication system 600 shown in any implementation of the corresponding embodiment can be referred to Figure 6 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0079] In a specific implementation, the domain controller 700 may include: Figure 1 The first domain controller 101 (such as a cockpit domain controller) or the second domain controller 102 (such as an intelligent driving domain controller) shown in the corresponding embodiment.

[0080] Further, corresponding to the implementation of the domain controller shown in the above embodiment, the present disclosure provides an embodiment of a vehicle. Specifically, the vehicle includes: Figure 7 The domain controller 700 provided in the corresponding embodiment can provide technical effects as shown in FIG. Figure 7 The relevant descriptions in the corresponding embodiments will not be repeated here.

[0081] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0082] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0083] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0084] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0085] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0086] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship between the client and the server is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and virtual private servers (VPS) services.

[0087] According to the technical solution of the embodiment of the present disclosure, when the microcontroller detects that the first GPIO of the microprocessor is switched from a high level to a low level, the second GPIO port and the third GPIO port are respectively set to a high level, so that when the microprocessor is informed that the data communication with the microcontroller is triggered or started, the second GPIO port and the third GPIO port are at a high level to inform the microprocessor that it is ready for data communication, and further, when the first data sent by the microprocessor is received, the second GPIO port is level-switched to inform the microprocessor that it has received the first data and needs to verify the first data, that is, error detection, and when the data verification fails, the third GPIO port is switched from the previous high level to a low level, so as to inform the microprocessor that the verification of the received data fails by level switching the third GPIO port of the microcontroller. In this way, the state interaction in the data communication process is realized by using the dynamic level switching of the three GPIO ports, and when the data verification is abnormal, the level of one of the GPIO ports of the microcontroller is switched to inform the opposite microprocessor, so as to realize the dynamic detection of data abnormality, so as to facilitate further processing, thereby reducing the probability of data communication failure.

[0088] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the expected results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit them here; and the terms "first", "second", "third", "fourth", etc. (if any) in the records of this disclosure are used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor do they constitute specific limitations.

[0089] It should also be understood that expressions such as "comprises," "including," "having," "includes," and / or "comprising" are open rather than closed expressions in the present disclosure, indicating the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present disclosure, "may" is used to mean "one or more embodiments of the present disclosure." And, the term "exemplary" is intended to refer to an example or illustration.

[0090] Unless otherwise defined, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as commonly understood by ordinary technicians in the field to which the present disclosure belongs. It should also be understood that unless explicitly stated in the present disclosure, words defined in commonly used dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0091] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A data communication method, comprising: In response to the first general purpose input / output port of the microprocessor switching from a high level to a low level, the microcontroller sets the second general purpose input / output port and the third general purpose input / output port to high levels respectively; In response to receiving the first data sent by the microprocessor, the microcontroller switches the second general input and output port from a high level to a low level; In response to a failure in verifying the first data, the microcontroller switches the third general purpose input / output port from a high level to a low level.

2. The method according to claim 1, further comprising: In response to at least one of the following being satisfied, the microprocessor switches the first general purpose input / output port from a high level to a low level again: The third general purpose input / output port is switched from a high level to a low level; The microprocessor fails to verify the second data received from the microcontroller.

3. The method according to claim 2, further comprising at least one of the following: In response to the first general purpose input / output port being switched from a high level to a low level again, the microprocessor resends the first data to the microcontroller; In response to the first general purpose input / output port being switched from a high level to a low level again, the microcontroller resends the second data to the microprocessor.

4. The method according to claim 3, further comprising: In response to the retransmission number of the second data reaching a preset threshold, the microcontroller performs a restart operation.

5. The method according to claim 3, further comprising: In response to the retransmission times of the first data reaching a preset threshold, the microprocessor performs a restart operation.

6. The method according to claim 4 or 5, wherein: The value of the preset threshold includes 1 or 2.

7. The method according to claim 2, further comprising: In response to successful verification of the second data and the third GPIO port not switching from a high level to a low level within a preset time period, the microprocessor maintains the first GPIO port at a high level within the preset time period.

8. The method according to any one of claims 1 to 7, wherein: The microprocessor and the microcontroller communicate with each other based on a serial peripheral interface, and the microprocessor is a host based on the serial peripheral interface communication, and the microcontroller is a slave based on the serial peripheral interface communication.

9. A data communication system comprising a microprocessor and a microcontroller, wherein: The microcontroller is configured to perform the following operations: In response to the first general purpose input / output port of the microprocessor switching from a high level to a low level, setting the second general purpose input / output port and the third general purpose input / output port to high levels respectively; In response to receiving the first data sent by the microprocessor, switching the second general input and output port from a high level to a low level; In response to a failure in verifying the first data, the third general input / output port is switched from a high level to a low level.

10. A domain controller, comprising: The data communication system as claimed in claim 9.

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