Data transmission system and method, storage medium and electronic equipment

Abstract

The invention discloses a data transmission system and method, a storage medium and electronic equipment, and the method comprises the steps: an interconnection endpoint can determine a to-be-transmitted data packet, determines a virtual MAC address corresponding to a target interconnection endpoint according to a video memory address corresponding to the target interconnection endpoint contained in the to-be-transmitted data packet, and uses the virtual MAC address as a target MAC address. And sending the data packet to be transmitted and the target MAC address to the interconnection switching node. The interconnection switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address, thereby reducing the complexity and transmission delay of network configuration, saving the cache space, reducing the storage cost and hardware cost, and reducing the network overhead. Moreover, the data transmission process is simple and standardized, no exclusive drive program or operation system support is needed, data transmission of various network devices is easy to realize, and the compatibility and interoperability of the network devices are improved.

Description

Technical Field

[0001] The present specification relates to the field of computer technology, and in particular to a data transmission system, method, storage medium and electronic device. Background Art

[0002] With the continuous development of science and technology, large models are being used more and more widely.

[0003] Since both the task of training a large model and the computing tasks related to the large model usually involve a large amount of computing and data processing, high requirements are placed on the servers that perform these tasks. However, traditional servers that only rely on central processing units (CPUs) to perform tasks can no longer meet the requirements. However, graphics processing units (GPUs) can provide parallel computing capabilities, so GPU servers can be used to perform these tasks. The GPU server refers to a server equipped with a high-performance GPU.

[0004] In order to give full play to the computing efficiency of GPU, multiple GPU servers can be interconnected, and data can be transmitted between the interconnected GPU servers to jointly perform tasks. Therefore, how to transmit data between the interconnected GPU servers is a very important issue.

[0005] Based on this, this specification provides a data transmission system. Summary of the invention

[0006] This specification provides a data transmission system, method, storage medium and electronic device to partially solve the above problems existing in the prior art.

[0007] This manual adopts the following technical solutions:

[0008] The present specification provides a data transmission system, the system comprising an interconnection switching node and a plurality of interconnection endpoints, each interconnection endpoint being pre-configured with a virtual media access control MAC address, the virtual MAC address being configured based on a shared video memory space constructed by video memories of the interconnection endpoints, the interconnection switching node being a node that only provides a layer 2 Ethernet switching function, and the interconnection endpoint being a GPU server; wherein:

[0009] The interconnection endpoint is used to determine a data packet to be transmitted; determine a virtual MAC address corresponding to the target interconnection endpoint according to a video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use the virtual MAC address as the target MAC address; send the data packet to be transmitted and the target MAC address to the interconnection switching node;

[0010] The interconnection switching node is used to receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0011] Optionally, the interconnection endpoint is specifically used to determine a video memory address corresponding to a target interconnection endpoint contained in the data packet to be transmitted; and calculate a virtual MAC address corresponding to the video memory address using a preset calculation rule, and use it as the target MAC address of the target interconnection endpoint.

[0012] Optionally, the data packet to be transmitted is a data packet generated by a transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP;

[0013] The interconnection endpoint is specifically used to encapsulate the data packet to be transmitted and the target MAC address by using tunnel technology, determine the target data packet of a specified type; and send the target data packet to the interconnection switching node.

[0014] Optionally, before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, the interconnection endpoint is further used to determine a first credit value corresponding to the target interconnection endpoint at a current moment; when the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

[0015] The present specification provides a data transmission method, the method is applied to an interconnection endpoint in a data transmission system, the data transmission system includes an interconnection switching node and a plurality of interconnection endpoints, each interconnection endpoint is pre-configured with a virtual media access control MAC address, the virtual MAC address is configured based on a shared video memory space constructed by the video memory of each interconnection endpoint, the switching node is a node that only provides a layer 2 Ethernet switching function, and the interconnection endpoint is a GPU server, the method includes:

[0016] Determine the data packet to be transmitted;

[0017] Determine a virtual MAC address corresponding to the target interconnect endpoint according to the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and use it as the target MAC address;

[0018] The data packet to be transmitted and the target MAC address are sent to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0019] Optionally, according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, determining a virtual MAC address corresponding to the target interconnection endpoint and using it as the target MAC address, specifically includes:

[0020] Determine a video memory address corresponding to a target interconnection endpoint included in the data packet to be transmitted;

[0021] A preset calculation rule is used to calculate a virtual MAC address corresponding to the video memory address and use it as the target MAC address of the target interconnection endpoint.

[0022] Optionally, the data packet to be transmitted is a data packet generated by a transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP;

[0023] Sending the data packet to be transmitted and the target MAC address to the interconnection switching node specifically includes:

[0024] Using tunnel technology, encapsulating the data packet to be transmitted and the target MAC address, and determining a target data packet of a specified type;

[0025] The target data packet is sent to the interconnection switching node.

[0026] Optionally, the method further comprises:

[0027] Before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, determining a first credit value corresponding to the target interconnection endpoint at a current moment;

[0028] When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

[0029] This specification provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the above-mentioned method for data transmission is implemented.

[0030] This specification provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned data transmission method when executing the program.

[0031] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0032] In the data transmission system provided in this specification, the interconnection endpoint can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The data packet to be transmitted and the target MAC address are sent to the interconnection switching node. Then, the interconnection switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0033] It can be seen from the above method that when the present application performs data transmission, the interconnection endpoint can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The data packet to be transmitted and the target MAC address are sent to the interconnection switching node. Then, the interconnection switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address. The interconnection endpoint first determines the data packet to be transmitted, and then determines the target MAC address of the target interconnection endpoint according to the video memory address of the target interconnection endpoint in the shared video memory space in the data packet to be transmitted, and then sends the data packet to be transmitted and the target MAC address to the interconnection switching node, thereby eliminating the steps of establishing a connection with the CPU and asynchronous communication, avoiding the performance of data transmission being affected by the CPU, simplifying the process of data transmission, improving the performance of data transmission, and reducing the complexity of network configuration and transmission delay. In addition, the interconnection endpoint directly sends the data packet to be transmitted and the target MAC address directly to the interconnection switching node, saving cache space and reducing storage costs. Afterwards, the interconnection switching node sends the data packet to be transmitted and the target MAC address to the target interconnection endpoint. The interconnection switching node only provides Layer 2 Ethernet switching functions, without network layer and transport layer, and also removes Layer 3 parsing, Layer 3 table lookup and forwarding, thereby reducing forwarding delay and hardware cost, and reducing network overhead. In addition, the above data transmission process is simple and standardized, and does not require any exclusive driver and operating system primitive support, which makes it easy for a variety of network devices to achieve data transmission, improving the compatibility and interoperability of network devices. In addition, the above data transmission process does not require software or applications to be in the critical path, and data transmission is completely performed by hardware with performance advantages, thereby bringing high bandwidth. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The illustrative embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation on this specification. In the drawings:

[0035] Figure 1A schematic diagram of a data transmission system provided in this specification;

[0036] Figure 2 A schematic diagram of a data transmission process provided in this specification;

[0037] Figure 3 A schematic diagram of a data transmission system provided in this specification;

[0038] Figure 4 A flowchart of a data transmission method provided in this specification;

[0039] Figure 5 A flowchart of another data transmission method provided in this specification;

[0040] Figure 6 A method corresponding to the Figure 4 or Figure 5 Schematic diagram of the structure of an electronic device. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of this specification more clear, the technical solutions of this specification will be clearly and completely described below in combination with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this specification.

[0042] At present, the GPU servers in the intelligent computing center used to provide computing services are generally interconnected GPU servers, and the interconnection between the GPU servers generally adopts Remote Direct Memory Access (RDMA) technology. RDMA is a technology that allows computing nodes in the network to read or write data directly from the memory to the memory of other computers without the extensive involvement of the operating system kernel and the CPU. Later, with the development of artificial intelligence (AI) and intelligent computing technology, GPU Direct RDMA technology, that is, GPU direct remote direct memory access technology, further emerged. The GPU Direct RDMA is a technology that allows direct data transmission between GPUs or between GPUs and remote hosts without passing through the host's CPU or system memory. In other words, this technology allows devices in the network to directly access the GPU's memory without the intervention of the CPU and system memory.

[0043] In addition, the main ways to implement RDMA technology at present are Remote Direct Memory Access over Ethernet (RDMA over Converged Ethernet version 2, referred to as RoCE V2) technology and InfiniBand (IB) technology. RoCE v2 is the second generation version of RoCE (RDMA over Converged Ethernet). Since IB implementation requires special switches and dedicated hardware, the cost is high and the management is complex. RoCE can use mature Ethernet infrastructure for easy deployment and management. In the construction of intelligent computing centers, RoCE V2 technology has become the mainstream technology for GPU server interconnection.

[0044] However, firstly, the network configuration of RoCE is complex because the use of RoCE technology requires the switch to support and configure the priority flow control function, namely the Priority Flow Control (PFC) function, to support effective congestion control strategies to avoid performance degradation or packet loss under high load conditions. Secondly, if there are other types of traffic in the network or the network equipment is not optimally configured, the performance may be affected, that is, the performance of RoCE depends on the network conditions. Then, since RoCE supports three-layer network communication, it is necessary to introduce additional processing overhead, especially increased processing delay, resulting in large network overhead. Furthermore, since network equipment from different manufacturers may have slight differences when implementing RoCE v2, poor interoperability results. In addition, despite the emergence of GPU Direct RDMA technology, RDMA management and connection establishment channels still require GPU processing, and the CPU may affect the overall performance of RDMA, so the performance of RoCE will be affected by the CPU. Moreover, since the communication between RoCE and GPU is asynchronous, semantic synchronization is required through interrupts (or doorbells), polling, etc. This not only makes the processing flow of RoCE complex, but also makes the logic of RoCE network cards complex and costly. In addition, RoCE requires driver and operating system support, and application optimization is required to fully utilize the performance advantages of RoCE. In addition, in pursuit of extreme performance, the driver and corresponding operating system functions that support RoCE are still being continuously iterated and updated. When using RoCE, it is necessary to keep the latest updates and patches of the driver and operating system, which will lead to software compatibility issues when using RoCE.

[0045] Based on this, this specification provides a data transmission system, method, storage medium and electronic device. The following is a detailed description of the technical solutions provided by each embodiment of this specification in conjunction with the accompanying drawings.

[0046] Figure 1is a schematic diagram of a data transmission system provided in this specification, Figure 1 The system shown includes an interconnection switching node 100 and a plurality of interconnection endpoints 101. Each interconnection endpoint 101 is pre-configured with a virtual media access control MAC address. The virtual MAC address is configured based on a shared video memory space constructed by the video memory of each interconnection endpoint 101. The interconnection switching node 100 is a node that only provides a layer 2 Ethernet switching function, and the interconnection endpoint 101 is a GPU server.

[0047] First, the interconnection endpoint 101 can determine the data packet to be transmitted. Among them, the interconnection endpoint 101 can be a GPU server, and the GPU server has at least one GPU. The specific number of GPUs is not specifically limited in this specification. The above-mentioned data packet to be transmitted can be sent to the interconnection endpoint 101 by other devices, programs or networks. The specific device, program or network sent is not specifically limited in this specification. The data packet to be transmitted contains the video memory address corresponding to the target interconnection endpoint. Of course, the data packet to be transmitted may also include data to be transmitted, which is not specifically limited in this specification. The data to be transmitted may be business data related to the large model, such as sample data, gradients or large model parameters for training the large model, and the task results obtained when the large model is used to perform tasks, and the model parameters of the large model are at the level of hundreds of billions or tens of billions. The business is related to the large model, and the business can be training the large model, or using the large model to perform tasks. The specific business scenario and the use of the large model are not limited in this specification. The above-mentioned target interconnection endpoint is the destination of the data to be transmitted, and the target interconnection endpoint is any interconnection endpoint 101 in the above-mentioned data transmission system. The video memory address is the video memory address of the target interconnection endpoint in the shared video memory space, and the video memory address may be pre-set. The shared video memory space is pre-constructed by the video memories of the interconnection endpoints 101, that is, the video memories of the interconnection endpoints 101 are pre-mapped to the same space, that is, the shared video memory space. And each interconnection endpoint 101 has a corresponding pre-set video memory address in the shared video memory space, that is, each interconnection endpoint 101 is pre-set with a video memory address in the shared video memory space.

[0048] Then, the interconnection endpoint 101 can determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The above-mentioned virtual MAC address is pre-configured based on the above-mentioned shared video memory space, and each interconnection endpoint 101 is pre-configured with a virtual MAC address, that is, according to the above-mentioned shared video memory space, a static MAC address is allocated to the interconnected GPU server, that is, the interconnection endpoint 101. The virtual MAC address is the MAC address corresponding to the virtual interconnection endpoint 101, which is used to characterize the interconnection endpoint 101. In addition, the virtual MAC address has a corresponding relationship with the above-mentioned video memory address. Therefore, the interconnection endpoint 101 can first determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, determine the virtual MAC address that has a corresponding relationship with the video memory address, and use it as the target MAC address corresponding to the target interconnection endpoint. Specifically, the interconnection endpoint 101 can first determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, determine the virtual MAC address corresponding to the video memory address according to the pre-constructed conversion table, and use it as the target MAC address corresponding to the target interconnection endpoint. The above conversion table is pre-built, and includes the correspondence between the virtual MAC address and the video memory address.

[0049] In addition, the interconnection endpoint 101 can also determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and then use the preset calculation rule to calculate the virtual MAC address corresponding to the video memory address, and use it as the target MAC address of the target interconnection endpoint. Among them, the calculation rule is preset, and the calculation rule is used to calculate the virtual MAC address corresponding to the video memory address, that is, to convert the video memory address into a virtual MAC address.

[0050] Afterwards, the interconnection endpoint 101 may send the data packet to be transmitted and the target MAC address to the interconnection switching node 100. The interconnection switching node 100 is a node that only provides a layer 2 Ethernet switching function, that is, a node that only provides a data link layer function, and the interconnection switching node may be a switch. In addition, the interconnection switching node 100 has no topology self-learning function. The interconnection endpoint 101 may directly send the data packet to be transmitted and the target MAC address to the interconnection switching node 100.

[0051] Then, the interconnection switching node 100 can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address. Specifically, the interconnection switching node 100 can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address using a pre-configured forwarding table. The forwarding table is pre-configured.

[0052] It can be seen from the above data transmission system that the interconnection endpoint can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The data packet to be transmitted and the target MAC address are sent to the interconnection switching node. Then, the interconnection switching node can receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address. The interconnection endpoint first determines the data packet to be transmitted, and then determines the target MAC address of the target interconnection endpoint according to the video memory address of the target interconnection endpoint in the shared video memory space in the data packet to be transmitted, and then sends the data packet to be transmitted and the target MAC address to the interconnection switching node, thereby eliminating the steps of establishing a connection with the CPU and asynchronous communication, avoiding the performance of data transmission being affected by the CPU, simplifying the process of data transmission, improving the performance of data transmission, and reducing the complexity of network configuration and transmission delay. In addition, the interconnection endpoint directly sends the data packet to be transmitted and the target MAC address directly to the interconnection switching node, saving cache space and reducing storage costs.

[0053] Afterwards, the interconnection switching node sends the data packet to be transmitted and the target MAC address to the target interconnection endpoint. The interconnection switching node only provides a layer 2 Ethernet switching function, without a network layer and a transport layer, and also removes the three-layer parsing, three-layer table lookup and forwarding links, thereby reducing forwarding delays and hardware costs, and reducing network overhead. In addition, the above data transmission process is simple and standardized, and does not require any exclusive driver and operating system primitive support, which makes it easy for a variety of network devices to achieve data transmission, improving the compatibility and interoperability of network devices. In addition, the above data transmission process does not require software or applications to be in the critical path, and data transmission is completely performed by hardware with performance advantages, thereby bringing high bandwidth.

[0054] In this specification, it should be noted that the above-mentioned data transmission system is used in the scenario of interconnection of GPU servers of a preset type of intelligent computing center. First of all, the GPU servers of the preset type of intelligent computing center are distributed in a single computer room or several computer rooms, and belong to one organization, which is different from the completely open characteristics of the Internet. Therefore, the interconnection area corresponding to the GPU server of the preset type of intelligent computing center is closed. That is, the above-mentioned interconnection endpoints 101 can be distributed in a single computer room or several computer rooms, and belong to the same organization, so the interconnection area corresponding to the above-mentioned interconnection endpoints 101 is closed.

[0055] Secondly, although the intelligent computing data center will be continuously upgraded and constructed, the GPU servers and switches in the intelligent computing center that are put into operation generally have fixed topology. Except for the cause of the failure, the topology will not change randomly, which is inconsistent with the unpredictable and frequently changing characteristics of the Internet topology. Therefore, the interconnection topology of the GPU servers in the preset type of intelligent computing center is quasi-static. That is, the interconnection topology between the above-mentioned interconnection endpoints 101 and the interconnection switching nodes 100 is quasi-static.

[0056] Then, the GPU servers of this preset type of intelligent computing center are interconnected by optical fiber or coaxial cable, which has strict standards in terms of physical medium selection and transmission noise suppression, and can ensure that the physical link transmission bit error rate is within 10 -12 The following. This feature makes the probability of network packet loss caused by transmission errors extremely small. Therefore, the physical characteristics of the interconnection link between the GPU servers in the preset type of intelligent computing center are good. That is, the above-mentioned interconnection endpoints 101 and the interconnection switching node 100 are connected by optical fiber or coaxial cable.

[0057] In this specification, the above-mentioned data packet to be transmitted may be a data packet generated by a transaction layer in a specified bus standard, and the specified bus standard may be a peripheral component interconnect high-speed standard PCIe, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP. The above-mentioned PCIe (Peripheral Component Interconnect Express), usually referred to as PCI Express, is a high-speed serial computer expansion bus standard for connecting internal components of a computer. The above-mentioned TLP (Transaction Layer Packet) is a data packet format defined in PCI Express, i.e., PCIe specification, for transmitting data and commands between PCIe devices. TLP is a core component of PCIe communication, and it is a data packet generated by the transaction layer in PCIe.

[0058] Therefore, in order to make the above-mentioned data packet to be transmitted better transmitted on the interconnection exchange node 100, when sending the data packet to be transmitted and the target MAC address to the interconnection exchange node 100, the above-mentioned interconnection endpoint 101 can use tunneling technology to encapsulate the data packet to be transmitted and the target MAC address, determine the target data packet of the specified type, and then send the target data packet to the interconnection exchange node. Among them, the above-mentioned tunneling technology (Tunneling) refers to the technology of encapsulating a data packet of one protocol in a data packet of another protocol in network communication. This technology allows data of one protocol to be transmitted on the network of another protocol, thereby realizing cross-network or cross-protocol data transmission. The tunneling technology is a pre-set technology. The tunneling technology is used to encapsulate the data packet to be transmitted and the target MAC address. The above-mentioned specified type is the type of data that can be supported for transmission on the interconnection exchange node 100, that is, the data packet of the above-mentioned specified type can be transmitted on the interconnection exchange node 100, and the data packet of the specified type can be an Ethernet frame.

[0059] Based on this, Figure 2 As shown, Figure 2 A schematic diagram of a data transmission process provided in this specification, Figure 2 The interconnection endpoint 101 in the example can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The tunneling technology is used to encapsulate the data packet to be transmitted and the target MAC address, determine the target data packet of the specified type, and send the target data packet to the interconnection switching node 100. The interconnection switching node 100 can receive the target data packet sent by the interconnection endpoint 101, and then send the target data packet to the target interconnection endpoint 101 according to the target MAC address in the target data packet. It should be noted that since the target interconnection endpoint is one of the above-mentioned interconnection endpoints 101, Figure 2 The target interconnect endpoint in is also labeled 101.

[0060] In this specification, the interconnection of GPU servers in the above-mentioned data transmission system can be regarded as a layer 2 network, which integrates the advantages of both layer 2 Ethernet switching function and PCIe, and adopts tunnel technology, so that the data transmission process fully utilizes the transmission, switching, and flexibility of Ethernet. The interconnection transmission semantics of GPU servers are PCIe semantics, which avoids the problem of asynchronous communication in the network. In addition, since the PCIe semantics of GPU servers are generally asynchronous direct memory access (DMA) operations, from an end-to-end perspective, it has a video memory to video memory communication model. Therefore, the reliability and end-to-end flow control problems of the layer 2 network can be shared with the corresponding mechanisms of PCIe.

[0061] In this specification, when data is transmitted, the network may be overloaded due to insufficient storage space at the target interconnection endpoint, resulting in network congestion. Therefore, a global credit-based flow control mechanism can be used to avoid network congestion through precise load control in advance. The global credit flow control mechanism is a method for managing and controlling data flow in a network. This mechanism controls the sending and receiving of data through information, ensuring that each node in the network can effectively manage and schedule data flow to avoid congestion and improve overall network performance.

[0062] Specifically, before sending the data packet to be transmitted and the target MAC address to the interconnection switching node 100, the interconnection endpoint 101 may also determine the first credit value corresponding to the target interconnection endpoint at the current moment. When the first credit value is greater than the preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node 100. The first credit value is the credit value at the current moment, and the first credit value may be sent by the target interconnection endpoint to the interconnection endpoint 101. Of course, it may also be calculated based on the credit value sent by the target interconnection endpoint to the interconnection endpoint 101. The first credit value represents the remaining storage space corresponding to the interconnection endpoint 101 in the target interconnection endpoint, that is, the remaining storage space refers to the remaining space of the space in the target interconnection endpoint for storing the data sent by the interconnection endpoint 101. The preset threshold is a preset value. When the first credit value is greater than the preset threshold, it means that the remaining space of the space in the target interconnection endpoint for storing the data sent by the interconnection endpoint 101 is sufficient, and the interconnection endpoint 101 may send the data packet to be transmitted and the target MAC address to the interconnection switching node 100, so as to send the data packet to be transmitted and the target MAC address to the target interconnection endpoint through the interconnection switching node 100. When the first credit value is not greater than the preset threshold, it indicates that the remaining space in the target interconnection endpoint for storing the data sent by the interconnection endpoint 101 is insufficient, and the interconnection endpoint 101 needs to wait until the remaining space is sufficient, that is, the interconnection endpoint 101 needs to execute the waiting instruction until the remaining space is sufficient, and then send the data packet to be transmitted and the target MAC address to the interconnection switching node 100, so as to send the data packet to be transmitted and the target MAC address to the target interconnection endpoint through the interconnection switching node 100, so as to avoid network congestion and cause long waiting. The waiting instruction is preset, and the waiting instruction is used to make the interconnection endpoint 101 process the waiting state.

[0063] When determining the first credit value corresponding to the target interconnect endpoint at the current moment, if the current moment is the first time that the interconnect endpoint 101 transmits data to the target interconnect endpoint, the interconnect endpoint 101 may receive the credit value sent by the target interconnect endpoint through the interconnection switching node 100 and use it as the first credit value corresponding to the target interconnect endpoint at the current moment. The first credit value is the credit value sent by the target interconnect endpoint. However, if the current moment is not the first time that the interconnect endpoint 101 transmits data to the target interconnect endpoint, the interconnect endpoint 101 may determine the credit value sent by the target interconnect endpoint through the interconnection switching node and use it as the initial credit value. Determine the number of transmissions of data to the target interconnect endpoint before the current moment, and determine the first credit value corresponding to the target interconnect endpoint at the current moment based on the number of transmissions and the initial credit value. The first credit value is calculated based on the initial credit value and the number of transmissions. The more the number of transmissions, the less the remaining storage space of the target interconnect endpoint, and the smaller the first credit value. Conversely, the fewer the number of transmissions, the more the remaining storage space of the target interconnect endpoint, and the larger the first credit value.

[0064] When determining the first credit value corresponding to the target interconnection endpoint at the current moment according to the number of transmissions and the initial credit value, the interconnection endpoint 101 may determine the transmission credit value according to the number of transmissions and the unit credit value, and then determine the difference between the initial credit value and the transmission credit value, and use it as the first credit value corresponding to the target interconnection endpoint at the current moment. The unit credit value is preset, and the unit credit value may be preset by the target interconnection endpoint and sent to the interconnection endpoint 101.

[0065] In addition, the target interconnection endpoint can also send the current remaining storage space, that is, the current credit value, to the interconnection endpoint 101 in real time. Therefore, when determining the first credit value corresponding to the target interconnection endpoint at the current moment, the interconnection endpoint 101 can receive the credit value sent by the target interconnection endpoint through the interconnection switching node 100 and use it as the first credit value corresponding to the target interconnection endpoint at the current moment.

[0066] In this specification, the above-mentioned data transmission system is implemented based on GPU server interconnection, that is, the interconnection endpoints in the data transmission system are interconnected through interconnection switching nodes. In addition, the data transmission system is used in the scenario of GPU server interconnection of a preset type of intelligent computing center, so it is designed with "simple network" as the concept, and the data transmission system is implemented based on a two-layer Ethernet exchange GPU server interconnection structure with shared video memory space. The GPU server interconnection structure is also the structure of the data transmission system, that is, it is composed of interconnection switching nodes and a number of interconnection endpoints. Among them, the interconnection switching node only has a two-layer Ethernet switching function and no topology self-learning function. And the interconnection switching node includes the use of manual configuration to establish a MAC forwarding table, and the interconnection endpoint can use tunneling technology to realize the standard PCIe tlp carrying into the Ethernet MAC packet. In addition, the congestion control mechanism of the data transmission process can adopt a full-network credit mechanism. Network reliability can adopt an end-to-end retransmission mechanism, which is shared with the retransmission mechanism of the data link layer of PCIe.

[0067] In this specification, since the interconnection of GPU servers (i.e., interconnection endpoints) is closed and the interconnection topology is quasi-static, all GPU memory in the entire GPU server interconnection area can be statically mapped to the same memory space, i.e., shared memory space. And static mac addresses are allocated to each interconnection endpoint in the interconnection according to the shared memory space. Based on this, the above data transmission system can also include a management node 102, specifically as follows Figure 3 As shown, Figure 3 This is a schematic diagram of a data transmission system provided in this specification. The management node can be a pre-set program. The management node can build a shared video memory space according to the video memory of each interconnected endpoint. Then, according to the shared video memory space, a virtual media access control MAC address is configured for each interconnected endpoint and sent to each interconnected endpoint. The virtual MAC address can be randomly configured by the management node or configured according to a preset rule, which is not specifically limited in this specification.

[0068] In this specification, the above-mentioned data transmission system adopts the design concept of "simple network", and regards the entire GPU server interconnection area as a simple network. It only needs to have "simple" transmission and switching functions, and does not require complex network layer and transport layer. The network layer generally realizes the interconnection and intercommunication between different subnets, and the transport layer realizes end-to-end communication between peer business entities. In the open Internet scenario, the network layer and the transport layer are necessary. However, due to the closed nature of the GPU server interconnection, it is not necessary to artificially divide the closed interconnection endpoints into multiple subnets, and there is no problem of subnet communication. A unified two-layer network can be built. Since the interconnection endpoint adopts the TLP over MAC tunnel technology, PCIe has its own end-side switching mechanism inside the CPU or GPU, so there is no need for a transport layer. The TLP over MAC refers to encapsulating the PCIe TLP data packet into a data packet that can be transmitted at the MAC layer of the Ethernet.

[0069] In addition, Ethernet switching is used to take advantage of the mature Ethernet ecosystem. However, Layer 2 Ethernet has the problem of broadcast storms. Considering the quasi-static topology of GPU server interconnection, the above data transmission system abandons the topology self-learning function of Layer 2 Ethernet and adopts a static configuration method to fundamentally avoid the broadcast storm problem.

[0070] In this specification, the GPU server interconnection structure in the above data transmission system only has a two-layer protocol structure, which is completely transparent to the upper layer application, and therefore does not require any special driver and operating system primitive processing. The use of the GPU server interconnection by the upper layer application is the use of the PCIe endpoint.

[0071] In the present specification, the above-mentioned data transmission system may include a plurality of interconnected switching nodes 100, each interconnected switching node 100 stores a preset forwarding table, and each interconnected switching node 100 has a connected interconnected endpoint 101, and the interconnected switching nodes 100 may also be connected to each other. How the interconnected switching nodes 100 are specifically connected, and how the interconnected switching nodes 100 are connected to the interconnected endpoints 101, can be determined based on the actual connection status of the preset type of intelligent computing center.

[0072] In this specification, firstly, the interconnection endpoint 101 in the above data transmission system, i.e., the network card side, removes the links of establishing connection with the CPU and asynchronous communication, and the interconnection switching node 100, i.e., the switching side, removes the links of three-layer parsing, three-layer table lookup and forwarding, thereby simplifying the processing links and bringing low latency. At the same time, the above data transmission system uses the whole network credit flow control mechanism to reduce the probability of network congestion and reduce the average network delay.

[0073] Secondly, because the bandwidth of the PCIe interface is greater than the bandwidth of the network interface, the PCIe interface can make full use of the bandwidth of the network interface, so that the above data transmission system can bring high bandwidth by reusing PCIe semantics, thereby better executing services related to large models. In this data transmission system, no software is in the critical path, and data transmission is completely performed by hardware with performance advantages, that is, the data transmission system performs data transmission through end-to-end full hardware, thereby bringing high bandwidth. In addition, the above data transmission system uses a full-network credit flow control mechanism to reduce the probability of network congestion, so that the data transmission system has a higher bandwidth utilization rate.

[0074] Then, the interconnection endpoint 101 in the above data transmission system, that is, the network card side, avoids expensive large amounts of on-chip cache, and only needs to perform streaming processing. In addition, the interconnection switching node 100, that is, the switching side, avoids expensive three-layer forwarding switching related functional logic and topology discovery logic, thereby reducing the hardware cost of data transmission. In addition, the GPU server interconnection structure of the above data transmission system only has a two-layer protocol structure, without a network layer and a transport layer structure, and has PCIe semantics, and does not require any exclusive driver and operating system primitive support, thereby reducing the software cost and maintenance cost of data transmission. In addition, the interconnection switching node 100 in the above data transmission system adopts a two-layer Ethernet switching function, that is, it can make full use of the transmission, switching, and flexibility of Ethernet, and is also convenient for using a mature Ethernet ecosystem, with many cost-effective solutions.

[0075] In addition, the data transmission system is based on the Layer 2 Ethernet switching function of the "simple network", which is simple and standardized, and has good compatibility with equipment from various manufacturers. Moreover, the data transmission system is transparent to upper-layer applications, and there is no compatibility problem at the software level.

[0076] Based on the above data transmission system, this specification also provides a data transmission method, such as Figure 4 As shown, Figure 4 A flowchart of a data transmission method provided in this specification is shown in FIG. Figure 4 The method shown is applied to an interconnection endpoint in the above data transmission system, namely, the interconnection endpoint 101. The data transmission system includes an interconnection switching node and a plurality of interconnection endpoints. Each interconnection endpoint is pre-configured with a virtual media access control MAC address. The virtual MAC address is configured based on a shared video memory space constructed by the video memory of each interconnection endpoint. The switching node is a node that only provides a layer 2 Ethernet switching function. The interconnection endpoint is a GPU server. The method includes the following steps:

[0077] S100: Determine a data packet to be transmitted.

[0078] The interconnection endpoint can determine the data packet to be transmitted. The data packet to be transmitted includes the video memory address corresponding to the target interconnection endpoint. Of course, the data packet to be transmitted can also include data to be transmitted, which is not specifically limited in this specification. Figure 1 The data packets to be transmitted of the data transmission system shown are consistent and will not be described in detail here.

[0079] S102: Determine a virtual MAC address corresponding to the target interconnection endpoint according to a video memory address corresponding to the target interconnection endpoint included in the data packet to be transmitted, and use the virtual MAC address as the target MAC address.

[0080] The interconnection endpoint can determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. The above-mentioned virtual MAC address is pre-configured based on the above-mentioned shared video memory space, and the virtual MAC address is the MAC address corresponding to the virtual interconnection endpoint, which is used to characterize the interconnection endpoint. Moreover, there is a corresponding relationship between the virtual MAC address and the above-mentioned video memory address. Therefore, the interconnection endpoint can first determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, determine the virtual MAC address that has a corresponding relationship with the video memory address, and use it as the target MAC address corresponding to the target interconnection endpoint.

[0081] Specifically, the interconnection endpoint may first determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and determine the virtual MAC address corresponding to the video memory address according to the pre-constructed conversion table, and use it as the target MAC address corresponding to the target interconnection endpoint. The conversion table is pre-constructed, and the conversion table contains the correspondence between the virtual MAC address and the video memory address.

[0082] In addition, the interconnection endpoint can also determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and then use the preset calculation rule to calculate the virtual MAC address corresponding to the video memory address and use it as the target MAC address of the target interconnection endpoint. Among them, the calculation rule is preset, and the calculation rule is used to calculate the virtual MAC address corresponding to the video memory address, that is, to convert the video memory address into a virtual MAC address.

[0083] S104: Send the data packet to be transmitted and the target MAC address to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0084] The interconnection endpoint can send the data packet to be transmitted and the target MAC address to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

[0085] In this specification, the interconnection switching nodes and interconnection endpoints are switches and GPU servers of a preset type of intelligent computing center, and the preset type of intelligent computing center is consistent with the above Figure 1 The preset type of intelligent computing center in the data transmission system shown is consistent and will not be repeated here.

[0086] In this specification, the data packet to be transmitted may be a data packet generated by a transaction layer in a specified bus standard, and the specified bus standard may be a peripheral component interconnect high-speed standard PCIe, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP. Therefore, in order to make the data packet to be transmitted better transmitted on the interconnection switching node, when the data packet to be transmitted and the target MAC address are sent to the interconnection switching node, the interconnection endpoint may use tunneling technology to encapsulate the data packet to be transmitted and the target MAC address, determine the target data packet of the specified type, and then send the target data packet to the interconnection switching node. Among them, the specified type is the type of data that can be supported for transmission on the interconnection switching node, that is, the data packet of the specified type can be transmitted on the interconnection switching node, and the data packet of the specified type may be an Ethernet frame.

[0087] Based on this, the interconnection endpoint can determine the data packet to be transmitted, and determine the virtual MAC address corresponding to the target interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use it as the target MAC address. Using tunneling technology, the data packet to be transmitted and the target MAC address are encapsulated, the target data packet of the specified type is determined, and the target data packet is sent to the interconnection switching node so that the interconnection switching node can receive the target data packet sent by the interconnection endpoint, and then the target data packet is sent to the target interconnection endpoint according to the target MAC address in the target data packet.

[0088] In the present specification, before the interconnection endpoint sends the data packet to be transmitted and the target MAC address to the interconnection switching node, it can also determine the first credit value corresponding to the target interconnection endpoint at the current moment. When the first credit value is greater than the preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node. Among them, the first credit value is the credit value at the current moment. The first credit value can be sent by the target interconnection endpoint to the interconnection endpoint. Of course, it can also be calculated based on the credit value sent by the target interconnection endpoint to the interconnection endpoint 101. The first credit value represents the remaining storage space of the target interconnection endpoint. The remaining storage space refers to the remaining space in the target interconnection endpoint for storing the data sent by the interconnection endpoint. The preset threshold is a pre-set value. The above process of determining the first credit value corresponding to the target interconnection endpoint at the current moment is the same as the above process. Figure 1 The process of the interconnection endpoint 101 determining the first credit value corresponding to the target interconnection endpoint at the current moment in the data transmission system shown is the same, and will not be repeated here.

[0089] In addition, based on the above data transmission system, this specification also provides a data transmission method, such as Figure 5 As shown, Figure 5 is a flowchart of another data transmission method provided in this specification, Figure 5 The method shown is applied to an interconnection switching node in the above data transmission system, namely, the interconnection switching node 100. The data transmission system includes an interconnection switching node and a plurality of interconnection endpoints. Each interconnection endpoint is pre-configured with a virtual media access control MAC address. The virtual MAC address is configured based on a shared video memory space constructed by the video memory of each interconnection endpoint. The switching node is a node that only provides a layer 2 Ethernet switching function. The interconnection endpoint is a GPU server. The method includes the following steps:

[0090] S200: Receive a data packet to be transmitted and a target MAC address; wherein the data packet to be transmitted is determined by an interconnection endpoint, the target MAC address is determined by the interconnection endpoint according to a video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and the target MAC address is a virtual MAC address corresponding to the target interconnection endpoint.

[0091] S202: Send the data packet to be transmitted to the target interconnection end according to the target MAC address.

[0092] The interconnection switching node can receive a data packet to be transmitted and a target MAC address, and send the data packet to be transmitted to a target interconnection endpoint according to the target MAC address. The interconnection switching node is a node that only provides a layer 2 Ethernet switching function, that is, a node that only provides a data link layer function, and the interconnection switching node can be a switch. In addition, the interconnection switching node has no topology self-learning function. The above-mentioned data packet to be transmitted is determined by the interconnection endpoint, the target MAC address is determined by the interconnection endpoint according to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and the target MAC address is a virtual MAC address corresponding to the target interconnection endpoint.

[0093] Specifically, the interconnection switching node 100 can receive a data packet to be transmitted and a target MAC address, and send the data packet to be transmitted to a target interconnection endpoint according to the target MAC address using a pre-configured forwarding table, wherein the forwarding table is pre-configured.

[0094] This specification also provides a computer-readable storage medium, which stores a computer program, which can be used to execute the above Figure 4 or Figure 5 A method of data transmission is provided.

[0095] This manual also provides Figure 6 The one shown corresponds to Figure 4 or Figure 5 A schematic diagram of the electronic device. Figure 6 As shown, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and may also include other hardware required for the business. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to achieve the above Figure 4 or Figure 5 A method of data transmission is provided.

[0096] Of course, in addition to software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc., that is to say, the executor of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0097] In the 1990s, improvements to a technology could be clearly distinguished as hardware improvements (for example, improvements to the circuit structure of diodes, transistors, switches, etc.) or software improvements (improvements to the method flow). However, with the development of technology, many improvements to the method flow today can be regarded as direct improvements to the hardware circuit structure. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement in a method flow cannot be implemented using a hardware entity module. For example, a programmable logic device (PLD) (such as a field programmable gate array (FPGA)) is such an integrated circuit whose logical function is determined by the user's programming of the device. Designers can "integrate" a digital system on a PLD by programming it themselves, without having to ask a chip manufacturer to design and produce a dedicated integrated circuit chip. Moreover, nowadays, instead of manually making integrated circuit chips, this kind of programming is mostly implemented by "logic compiler" software, which is similar to the software compiler used when developing and writing programs, and the original code before compilation must also be written in a specific programming language, which is called hardware description language (HDL). There is not only one HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones are VHDL (Very-High-Speed ​​Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also know that it is only necessary to program the method flow slightly in the above-mentioned hardware description languages ​​and program it into the integrated circuit, and then it is easy to obtain the hardware circuit that implements the logic method flow.

[0098] The controller can be implemented in any appropriate manner, for example, the controller can take the form of a microprocessor or processor and a computer-readable medium storing a computer-readable program code (such as software or firmware) that can be executed by the (micro)processor, a logic gate, a switch, an application-specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of controllers include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in a purely computer-readable program code manner, the controller can be implemented in the form of a logic gate, a switch, an application-specific integrated circuit, a programmable logic controller, and an embedded microcontroller by logically programming the method steps. Therefore, this controller can be considered as a hardware component, and the devices included therein for implementing various functions can also be regarded as structures within the hardware component. Or even, the devices for implementing various functions can be regarded as both software modules for implementing the method and structures within the hardware component.

[0099] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0100] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0101] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems, or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0102] This specification is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of this specification. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0103] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0104] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0105] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0106] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0107] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0108] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0109] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0110] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0111] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0112] The above description is only an embodiment of the present specification and is not intended to limit the present specification. For those skilled in the art, the present specification may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present specification shall be included in the scope of the claims of the present specification.

Claims

1. A data transmission system, characterized in that: The system comprises an interconnection switching node and a plurality of interconnection endpoints, each interconnection endpoint is pre-configured with a virtual media access control MAC address, the virtual MAC address is configured based on a shared video memory space constructed by the video memory of each interconnection endpoint, the interconnection switching node is a node that only provides a layer 2 Ethernet switching function, and the interconnection endpoint is a GPU server; wherein: The interconnection endpoint is used to determine a data packet to be transmitted; determine a virtual MAC address corresponding to the target interconnection endpoint according to a video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, and use the virtual MAC address as the target MAC address; send the data packet to be transmitted and the target MAC address to the interconnection switching node; The interconnection switching node is used to receive the data packet to be transmitted and the target MAC address, and send the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

2. The system according to claim 1, characterized in that The interconnection endpoint is specifically used to determine the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted; use a preset calculation rule to calculate the virtual MAC address corresponding to the video memory address and use it as the target MAC address of the target interconnection endpoint.

3. The system according to claim 1, characterized in that The data packet to be transmitted is a data packet generated by a transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP; The interconnection endpoint is specifically used to encapsulate the data packet to be transmitted and the target MAC address by using tunnel technology, determine the target data packet of a specified type; and send the target data packet to the interconnection switching node.

4. The system according to claim 1, characterized in that The interconnection endpoint is further used to determine a first credit value corresponding to the target interconnection endpoint at a current moment before sending the data packet to be transmitted and the target MAC address to the interconnection switching node; when the first credit value is greater than a preset threshold, send the data packet to be transmitted and the target MAC address to the interconnection switching node.

5. A method for data transmission, characterized in that: The method is applied to an interconnection endpoint in a data transmission system, wherein the data transmission system includes an interconnection switching node and a plurality of interconnection endpoints, each interconnection endpoint is pre-configured with a virtual media access control MAC address, the virtual MAC address is configured based on a shared video memory space constructed by video memories of each interconnection endpoint, the switching node is a node that only provides a layer 2 Ethernet switching function, and the interconnection endpoint is a GPU server, and the method includes: Determine the data packet to be transmitted; Determine a virtual MAC address corresponding to the target interconnect endpoint according to the video memory address corresponding to the target interconnect endpoint contained in the data packet to be transmitted, and use it as the target MAC address; The data packet to be transmitted and the target MAC address are sent to the interconnection switching node, so that the interconnection switching node receives the data packet to be transmitted and the target MAC address, and sends the data packet to be transmitted to the target interconnection endpoint according to the target MAC address.

6. The method according to claim 5, characterized in that According to the video memory address corresponding to the target interconnection endpoint contained in the data packet to be transmitted, determining the virtual MAC address corresponding to the target interconnection endpoint and using it as the target MAC address, specifically includes: Determine a video memory address corresponding to a target interconnection endpoint included in the data packet to be transmitted; A preset calculation rule is used to calculate a virtual MAC address corresponding to the video memory address and use it as the target MAC address of the target interconnection endpoint.

7. The method according to claim 5, characterized in that The data packet to be transmitted is a data packet generated by a transaction layer in a specified bus standard, and the data packet format of the data packet to be transmitted is a transaction layer data packet TLP; Sending the data packet to be transmitted and the target MAC address to the interconnection switching node specifically includes: Using tunnel technology, encapsulating the data packet to be transmitted and the target MAC address, and determining a target data packet of a specified type; The target data packet is sent to the interconnection switching node.

8. The method according to claim 5, characterized in that The method further comprises: Before sending the data packet to be transmitted and the target MAC address to the interconnection switching node, determining a first credit value corresponding to the target interconnection endpoint at a current moment; When the first credit value is greater than a preset threshold, the data packet to be transmitted and the target MAC address are sent to the interconnection switching node.

9. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 5 to 8 is implemented.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the method according to any one of claims 5 to 8 is implemented.

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