SiC MOSFET device for improving switching loss and preparation method thereof

Abstract

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device for improving switching loss and a preparation method, and relates to the technical field of semiconductors. By adopting the gate trench with the inverted trapezoidal structure, the overlapping area of the gate and the drain is reduced, so that the purpose of reducing the gate-drain capacitance is achieved, the Miller plateau time is reduced, and the switching loss of the device is improved. In addition, the thicker gate oxide layer is designed at the bottom of the gate trench, the thickness value of the thicker gate oxide layer is 60-70 nm, the purpose of further reducing the gate-drain capacitance is achieved, and meanwhile the risk that the gate oxide is broken down by a voltage peak can be relieved through the deposited thick gate oxide layer 7.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SiC MOSFET device with improved switching loss and a preparation method thereof. Background Art

[0002] As an advanced semiconductor material, SiC has many advantages that traditional silicon materials cannot match. First, the band gap of SiC is larger than that of silicon, which means that it has higher efficiency and lower loss in electrical conductivity. Secondly, the thermal conductivity of SiC is higher than that of Si, which enables it to work stably at higher temperatures. Furthermore, the electron mobility of SiC is also better than that of Si, which makes it perform well in high-frequency applications. In addition, SiC also has good chemical stability and wear resistance.

[0003] In the field of power devices, overall loss is the core indicator for evaluating performance, which includes conduction loss and switching loss. Conduction loss is mainly related to the characteristics and operating conditions of the device itself, while switching loss is affected by more factors. There are three main factors that affect the total switching loss of the device: turn-on energy Eon, turn-off energy Eoff and reverse recovery energy Erec. The proportion of these factors usually depends on the characteristics of the device, operating conditions and external circuits. In addition, other losses may occur during the switching process, such as losses caused by parasitic conduction. Therefore, how to improve the switching loss of SiC MOSFET devices is a technical problem that technicians in this field need to solve urgently. Summary of the invention

[0004] In view of the above problems, a SiC MOSFET device is provided which reduces gate-drain capacitance and shortens the Miller platform time to improve switching losses.

[0005] The technical solution of the present invention is: A method for preparing a SiC MOSFET device for improving switching loss comprises the following steps: S100, growing an N-epitaxial layer on the N+ substrate layer, and ion implanting Al ions on the top of the N-epitaxial layer to form a P-body region; S200, etching a groove in an inverted trapezoidal shape extending downward from the top surface of the P-body region to form a gate trench region; S300, forming an N+ region in the P-body region of the gate trench region; S400, implanting into the P-body region to form a P+ region connected to the N+ region; S500, growing a gate oxide layer on the sidewall and bottom of the gate trench region, and depositing a Poly layer on the gate oxide layer; S600, depositing oxide on the top of the N-epitaxial layer to form an isolation dielectric layer; S700, forming an ohmic metal layer by sputtering deposition on the top surfaces of the N+ region and the P+ region, and forming an ohmic contact alloy layer by high temperature annealing; S800, depositing a front electrode metal layer on the isolation dielectric layer and the ohmic contact alloy layer by sputtering metal Al as a source electrode lead.

[0006] Specifically, the concentration range of the P-body region is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.

[0007] Specifically, the etching depth of the gate trench region is 1.8-2 um.

[0008] Specifically, the concentration range of the N+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

[0009] Specifically, the concentration range of the P+ region is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

[0010] Specifically, in step S500, the thickness of the gate oxide layer increases from top to bottom.

[0011] Specifically, the bottom surface of the gate oxide layer is a plane.

[0012] Specifically, in step S700, annealing is performed at a high temperature of 1000° C. for 5 minutes.

[0013] A SiC MOSFET device for improving switching loss, comprising an N+ substrate layer, an N-epitaxial layer, a P-body region, an ohmic contact alloy layer and a front electrode metal layer arranged in sequence from bottom to top; The top surface of the P-body region 3) is provided with a gate trench region with an inverted trapezoidal structure extending downward; a gate oxide layer with a thickness increasing from top to bottom is provided in the gate trench region; a Poly layer with an inverted trapezoidal structure is provided in the gate oxide layer; The top surface of the P-body region is provided with an N+ region extending downward and connected to the gate oxide layer; the width of the N+ region increases from top to bottom and is spaced apart from the bottom surface of the P-body region; The top surface of the P-body region is provided with a P+ region formed by downward extension and injection; the side surface connecting the P+ region and the N+ region is an inclined surface; An isolation dielectric layer is provided on the top surfaces of the N+ region, the gate oxide layer and the Poly layer, and the isolation dielectric layer is connected to the ohmic contact alloy layer.

[0014] Specifically, the bottom surface of the front electrode metal layer is connected to the isolation dielectric layer and the ohmic contact alloy layer respectively.

[0015] The present invention adopts a gate trench with an inverted trapezoidal structure, which reduces the overlapping area of ​​the gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance, reducing the Miller platform time, and improving the switching loss of the device. In addition, the present invention designs a thicker gate oxide layer at the bottom of the gate trench, and its thickness is 60-70nm, which further reduces the gate-drain capacitance. At the same time, the thick gate oxide layer 7 deposited can alleviate the risk of gate oxide being broken down by voltage spikes.

[0016] Instruction Manual Figure 1 It is a schematic diagram of the structure for preparing an N-epitaxial layer; Figure 2 It is a schematic diagram of the structure of the preparation of the P-body region; Figure 3 is a schematic diagram of the structure for preparing a gate trench region; Figure 4 It is a schematic diagram of the structure for preparing the N+ region; Figure 5 It is a schematic diagram of the structure for preparing the P+ region; Figure 6 is a schematic diagram of the structure for preparing a gate oxide layer; Figure 7 It is a schematic diagram of the structure of preparing the Poly layer; Figure 8 is a schematic diagram of the structure for preparing an isolation dielectric layer; Fig. 9 It is a schematic diagram of the structure for preparing an ohmic contact alloy layer; Fig.10 It is a schematic diagram of the structure for preparing the front electrode metal layer; In the figure, 1 is the N+ substrate layer, 2 is the N- epitaxial layer, 3 is the P-body region, 4 is the gate trench region, 5 is the N+ region, 6 is the P+ region, 7 is the gate oxide layer, 8 is the Poly layer, 9 is the isolation dielectric layer, 10 is the ohmic contact alloy layer, and 11 is the front electrode metal layer. DETAILED DESCRIPTION

[0017] The present invention is described in detail below in conjunction with specific practical cases. Examples of the embodiments are shown in the accompanying drawings, and the schematic implementation methods of the present invention and their descriptions are only used to explain the present invention and are not intended to limit the present invention.

[0018] A SiC MOSFET device for improving switching loss comprises the following steps: S100, such as Figure 1 As shown, an N-epitaxial layer 2 is grown on the N+ substrate layer 1, and Al ions are implanted on the top of the N-epitaxial layer to form a P-body region 3. The concentration range of the P-body region 3 is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um, such as Figure 2 As shown; S200, such as Figure 3 As shown, an inverted trapezoidal groove is etched downward from the top surface of the P-body region 3 to form a gate trench region 4, and the etching depth is 1.8-2um (the etching depth refers to the groove bottom from the top surface of the P-body region 3 to the gate trench region 4), and the inclination angle of the inverted trapezoid is adjusted according to the actual process; S300, such as Figure 4 As shown, with photoresist and SiO 2 As a mask, N ions are implanted multiple times in the P-body region 3 of the gate trench region 4 to form an N+ region 5 with a concentration range of 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um; S400, such as Figure 5 As shown, with photoresist and SiO 2 As a mask, Al ions are implanted multiple times on the top surface of the P-body region 3 to form a P+ region 6 connected to the N+ region 5; The concentration range of P+ region 6 is 1E 18 cm -2 -1E 19 cm -2 The implantation depth is 0.4-0.8um. ​​After the implantation is completed, the mask is removed. Then a thin layer of graphite is deposited on the surface of the device as protection. It is annealed at a high temperature of 1650℃-1690℃ for 15 minutes to activate the implanted ions. S500, such as Figure 6 As shown, a photoresist is used as a mask, and a gate oxide layer 7 is grown on the sidewall and bottom of the gate trench region 4 by dry oxygen thermal oxidation, and annealing is performed in a NO atmosphere at a temperature of 1250° C. for 1 hour to improve the compactness of the gate oxide layer and reduce defects; The thickness of the gate oxide layer 7 in step S500 increases with the increase of the depth of the gate trench, which can reduce the gate-drain capacitance and does not affect the formation of the channel. The gate oxide at the bottom of the gate trench 4 is the thickest, with a thickness of 60-70nm, and the gate oxide at the top of the N-epitaxial layer 2 is the thinnest, with a thickness of 25-40nm.

[0019] The photoresist in step S500 utilizes the diffraction effect of light passing through a photoresist plate with slits to diffract the light passing through the slit area outward, so that after the photolithography and development process, a gentle bevel area is formed at the edge of the photoresist.

[0020] S600, such as Figure 7 As shown, polysilicon is deposited in the gate trench region 4 by LPCVD to form a Poly layer 8, which is used as a gate electrode lead; S700, such as Figure 8 As shown, an oxide is deposited on the top of the N-epitaxial layer to form an isolation dielectric layer 9; In step S700 , both ends of the isolation dielectric layer 9 are respectively overlapped on the upper end of the N+ region 5 , with no limitation on the overlap distance, and the bottom is in contact with the top of the N− epitaxial layer 2 .

[0021] S800, such as Fig. 9 As shown, an ohmic metal layer is formed on the N-epitaxial layer 2 by Ni metal sputtering deposition, and then annealed at a high temperature of 1000° C. for 5 minutes to form an ohmic contact alloy layer 10, which forms an ohmic contact with the upper parts of the N+ region 5 and the P+ region 6; In step S800, the ohmic contact alloy layer 14 is respectively disposed on both sides of the isolation dielectric layer 9 and contacts the side wall of the isolation dielectric layer 9; S900, such as Fig.10 As shown, a front electrode metal layer 11 is deposited on the isolation dielectric layer 9 and the ohmic contact alloy layer 10 by sputtering metal Al to be led out as a source electrode.

[0022] A SiC MOSFET device for improving switching loss, comprising an N+ substrate layer 1, an N-epitaxial layer 2, a P-body region 3, an ohmic contact alloy layer 10 and a front electrode metal layer 11 arranged in sequence from bottom to top; The top surface of the P-body region 3 is provided with a gate trench region 4 with an inverted trapezoidal structure extending downward; a gate oxide layer 7 with a thickness increasing from top to bottom is provided in the gate trench region 4; a Poly layer 8 with an inverted trapezoidal structure is provided in the gate oxide layer 7; The top surface of the P-body region 3 is provided with an N+ region 5 extending downward and connected to the gate oxide layer 7; the width of the N+ region 5 increases from top to bottom, and a gap is provided between the N+ region 5 and the bottom surface of the P-body region 3; The top surface of the P-body region 3 is provided with a P+ region 6 extending downward and connected to the gate oxide layer 7; the side surface of the P+ region 6 connected to the N+ region 5 is an inclined surface; An isolation dielectric layer 9 is provided on the top surfaces of the N+ region 5 , the gate oxide layer 7 and the Poly layer 8 , and the isolation dielectric layer 9 is connected to the ohmic contact alloy layer 10 .

[0023] The bottom surface of the front electrode metal layer 11 is connected to the isolation dielectric layer 9 and the ohmic contact alloy layer 10 respectively.

[0024] The present invention adopts a gate trench 4 of an inverted trapezoidal structure, which reduces the overlapping area of ​​the gate and the drain, thereby achieving the purpose of reducing the gate-drain capacitance, reducing the Miller platform time, and improving the switching loss of the device. In addition, the present invention designs a thicker gate oxide layer 7 at the bottom of the gate trench, and its thickness is 60-70nm, which further reduces the gate-drain capacitance. At the same time, the deposited thick gate oxide layer 7 can alleviate the risk of gate oxide being broken down by voltage spikes.

[0025] Regarding the contents disclosed in this case, there are a few points that need to be explained: (1) The drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general ones; (2) In the absence of conflict, the embodiments and features of the embodiments disclosed in this case can be combined with each other to obtain new embodiments; The above are only specific implementation methods disclosed in this case, but the protection scope of the present disclosure is not limited thereto. The protection scope disclosed in this case shall be based on the protection scope of the claims.

Claims

1. A method for preparing a SiC MOSFET device for improving switching loss, characterized in that: The steps include: S100, growing an N-epitaxial layer (2) on the N+ substrate layer (1), and ion implanting Al ions on the top of the N-epitaxial layer to form a P-body region (3); S200, etching a groove in an inverted trapezoidal shape extending downward from the top surface of the P-body region (3) to form a gate trench region (4); S300, forming an N+ region (5) in the P-body region (3) of the gate trench region (4); S400, implanting into the P-body region (3) to form a P+ region (6) connected to the N+ region (5); S500, growing a gate oxide layer (7) on the sidewalls and bottom of the gate trench region (4), and depositing a Poly layer (8) on the gate oxide layer (7); S600, depositing oxide on the top of the N-epitaxial layer to form an isolation dielectric layer (9); S700, forming an ohmic metal layer by sputtering deposition on the top surfaces of the N+ region (5) and the P+ region (6), and forming an ohmic contact alloy layer (10) by high temperature annealing; S800, depositing a front electrode metal layer (11) on the isolation dielectric layer (9) and the ohmic contact alloy layer (10) by sputtering metal Al, as a source electrode lead.

2. The method for preparing a SiC MOSFET device for improving switching loss according to claim 1, characterized in that: The concentration range of the P-body region (3) is 1E 17 cm -2 -1E 18 cm -2 , the injection depth is 0.8-1.5um.

3. The method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: The etching depth of the gate trench region (4) is 1.8-2 um.

4. The method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: The concentration range of the N+ region (5) is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

5. The method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: The concentration range of the P+ region (6) is 1E 18 cm -2 -1E 19 cm -2 , the injection depth is 0.4-0.8um.

6. The method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: In step S500, the thickness of the gate oxide layer (7) increases from top to bottom.

7. A method for preparing a SiC MOSFET device with improved switching loss according to claim 1 or 6, characterized in that: The bottom surface of the gate oxide layer (7) is a plane.

8. The method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: In step S700, annealing is performed at a high temperature of 1000°C for 5 minutes.

9. A SiC MOSFET device with improved switching loss, prepared by the method for preparing a SiC MOSFET device with improved switching loss according to claim 1, characterized in that: It comprises an N+ substrate layer (1), an N-epitaxial layer (2), a P-body region (3), an ohmic contact alloy layer (10) and a front electrode metal layer (11) which are arranged in sequence from bottom to top; The top surface of the P-body region (3) is provided with a gate trench region (4) with an inverted trapezoidal structure extending downward; a gate oxide layer (7) with a thickness increasing from top to bottom is provided in the gate trench region (4); and a Poly layer (8) with an inverted trapezoidal structure is provided in the gate oxide layer (7); The top surface of the P-body region (3) is provided with an N+ region (5) extending downward and connected to the gate oxide layer (7); the width of the N+ region (5) increases from top to bottom and is spaced apart from the bottom surface of the P-body region (3); The top surface of the P-body region (3) is provided with a P+ region (6) extending downward; the side surface of the P+ region (6) connecting to the N+ region (5) is in the form of an inclined surface; An isolation dielectric layer (9) is provided on the top surfaces of the N+ region (5), the gate oxide layer (7) and the Poly layer (8), and the isolation dielectric layer (9) is connected to the ohmic contact alloy layer (10).

10. A SiC MOSFET device for improving switching loss according to claim 9, characterized in that: The bottom surface of the front electrode metal layer (11) is connected to the isolation dielectric layer (9) and the ohmic contact alloy layer (10) respectively.

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