Classification method and equipment for static time sequence analysis reports

Abstract

The invention relates to the technical field of microcircuit analysis, and discloses a classification method and equipment for static time sequence analysis reports. The method comprises the following steps: determining the type of a static time sequence analysis report of a target time sequence path; if the static time sequence analysis report is of an establishment time type, dividing a data path of the target time sequence path into an intra-module path and a cross-module path; dividing violations existing in the paths in the modules to the corresponding modules to obtain a first violation division result; determining a plurality of target modules corresponding to the cross-module path with violation; calculating the violation value contribution degree of each target module; according to the violation value contribution degree of each target module, dividing violations existing in the cross-module path to the corresponding target modules to obtain a second violation division result; and determining the violation of the target time sequence path belonging to each module according to the first violation division result and the second violation division result. The static time sequence analysis report can be efficiently processed, and efficiency and accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the field of microcircuit analysis technology, and in particular to a classification method and device for static timing analysis reports. Background Art

[0002] In fully flattened static timing analysis, there are currently two main processing methods to effectively deliver the analysis results to different module designers so that they can perform subsequent processing according to their respective design responsibilities.

[0003] The first method is to let the designer of each module directly analyze the original static timing analysis report and extract the parts related to their own module. Although this method is direct, as the number of chip transistors increases dramatically, the amount of information in a single report becomes very large, resulting in a significant increase in the time and machine resources required to open the report, making it increasingly difficult for designers to extract the content they care about.

[0004] The second method is to add path combinations when running the static timing analysis task, or reopen the stored database to adjust the report options to make the static timing analysis tool generate a report with clearer classification. Although this method improves the readability of the report to a certain extent, there are still some problems. For example, using the add path combination method requires presetting many combinations for the static timing analysis task, which increases the complexity of the task, and for some types of reports, classification cannot be performed by adding path combinations. In addition, reopening the stored database to customize the report options is a secondary operation, which increases the time for project iteration. Summary of the invention

[0005] In view of this, the present invention provides a classification method and device for static timing analysis reports, which can efficiently process static timing analysis reports and improve efficiency and accuracy.

[0006] In a first aspect, the present invention provides a classification method for static timing analysis reports, comprising: determining the type of static timing analysis report of a target timing path; if the static timing analysis report is a setup time type, dividing the data path of the target timing path into an intra-module path and a cross-module path; dividing the violations existing in the intra-module path to the corresponding modules to obtain a first violation division result; determining multiple target modules corresponding to the cross-module path with violations; calculating the violation value contribution of each target module according to the logic level, delay, ratio of delay and logic level of each target module, and whether there are abnormal points; dividing the violations existing in the cross-module path to the corresponding target module according to the violation value contribution of each target module to obtain a second violation division result; determining the violations of the target timing path belonging to each module according to the first violation division result and the second violation division result.

[0007] The classification method for static timing analysis reports provided in this embodiment performs preliminary classification according to the type of static timing analysis reports, and divides the data path of the target timing path into intra-module paths and cross-module paths, so that the violations of the target timing path can be accurately located on specific modules, and the violation value contribution of each target module is calculated, and the violations of the cross-module path are further divided according to this contribution, which further improves the accuracy of classification. By calculating the violation value contribution, it can be clear which modules contribute more to the violations. For violations of cross-module paths, by calculating the contribution of each target module, it is helpful to accurately divide the modules to which the violations in the cross-module paths belong. For cross-module paths with violations, by analyzing the contribution of each target module instead of judging the belonging module according to the path logic level, it is possible to avoid being too arbitrary in classification, thereby preventing the violation module displayed in the report from being inconsistent with the module that actually needs to be repaired.

[0008] In an optional embodiment, the violation value contribution of each target module is calculated according to the logic level, delay, ratio of delay and logic level, and whether there are abnormal points of each target module, including: calculating the basic score of the violation value contribution of each target module according to the logic level, delay and ratio of delay and logic level of each target module; if there are no abnormal points in the target module, determining the basic score as the violation value contribution of the target module; if there are abnormal points in the target module, calculating the additional score of the violation value contribution according to the delay of the standard cell of the abnormal point and the delay of all standard cells on the data path of the target timing path, and determining the sum of the basic score and the additional score as the violation value contribution of the target module.

[0009] The classification method for static timing analysis reports provided in this embodiment calculates a basic score according to the number of logic levels, delay, and the ratio of delay to logic level of each target module. The basic score can reflect the basic performance of the target module in terms of logic complexity and delay performance. By judging whether the target module has an abnormal point, the situation where the delay of a certain level or several levels of standard cells in the violation path is abnormally large can be accurately identified. If the target module has an abnormal point, the additional score is calculated according to the delay of the standard cell of the abnormal point and the delay of all standard cells on the data path of the target timing path. The additional score can correct the basic score, and finally calculate the final score to comprehensively reflect the actual situation of the target module, so that the final score is more objective and fair. Giving additional points to the module with abnormal points can highlight the importance of the abnormal point. Generally, the logic level with abnormal delay is the one that needs to be repaired first in actual engineering, so as to avoid the abnormal points in the module with more logic levels being hidden in the calculation of the basic score, thereby improving the accuracy of the violation attribution of the target timing path.

[0010] In an optional embodiment, a basic score of the violation value contribution of each target module is calculated based on the logic level, delay, and ratio of the delay to the logic level of each target module, including: determining a weight vector corresponding to the level based on the level of the data path of the target timing path, the weight vector containing weight values ​​corresponding to the logic level, delay, and ratio of the delay to the logic level, respectively, and different weight vectors corresponding to different levels are different; based on the weight vector, performing normalized weighted average calculation on the logic level, delay, and ratio of the delay to the logic level of each target module at the logic level of the standard unit on the data path of the target timing path, to obtain a basic score of the violation value contribution of each target module.

[0011] The classification method for static timing analysis reports provided in this embodiment determines a weight vector for each level interval according to the level of the data path of the target timing path. The introduction of the weight vector can comprehensively and accurately evaluate the contribution of the target module to the violation value. The weight vector is determined according to the level of the data path, and can flexibly adapt to the different effects of various factors on the contribution of the violation value at different levels, thereby improving the flexibility and applicability of the evaluation. The determined weight vector is used to normalize the logic level, delay, and ratio of the delay to the logic level of each target module. A weighted average calculation is performed based on the normalized value and the corresponding weight to obtain a basic score for the contribution of the violation value of each target module. The normalized weighted average calculation eliminates the dimensional differences between different factors, making the evaluation result more accurate and reliable.

[0012] In an optional implementation, it includes: if the number of standard cell levels in the data path of the target timing path is less than a preset value, determining that there are no abnormal points in the data path of the target timing path; if the number of standard cell levels in the data path of the target timing path is greater than or equal to the preset value, calculating the average value and standard deviation of the delays of all standard cells in the data path of the target timing path; judging whether the delay of each standard cell meets the set conditions according to the delay, average value and standard deviation of each standard cell; if the delay of the standard cell meets the set conditions, determining that the standard cell is an abnormal point; and determining the module containing the abnormal point as a module with an abnormal point.

[0013] The classification method for static timing analysis reports provided in this embodiment can exclude data paths with fewer standard cell levels by judging whether the number of standard cell levels is less than a preset value, thereby avoiding calculation errors caused by a small sample size. By calculating the average delay value and the standard deviation and combining the set conditions to judge whether the delay of each standard cell is abnormal, the abnormal points in the data path can be located more accurately.

[0014] In an optional embodiment, if the static timing analysis report is of the hold time type, it includes: determining the logical level at which the end point of the data path of the target timing path is located; and determining the violations of the target timing path belonging to each module based on the logical level at which the end point of the data path of the target timing path is located.

[0015] The classification method for static timing analysis reports provided in this embodiment is based on the logical level at which the end point of the data path of the target timing path is located. The repair of violations based on the hold time type is usually performed in the module corresponding to the logical level at which the end point is located. This classification method reduces the complexity of attribution judgment while ensuring classification accuracy.

[0016] In an optional implementation, if the static timing analysis report is design rules and other types, it includes: determining specific violation entries of design rules and other types of violations; determining violations of specific entries belonging to each module according to the logical level at which the specific violation entries of design rules and other types of violations are located.

[0017] The classification method for static timing analysis reports provided in this embodiment, since design rule and other types of violations are ultimately reflected as single-point violations such as a certain level of standard unit, a certain interconnect line, or a certain pin, the module to which the violation belongs can be quickly found through single-point violation location, thereby allowing module designers to more quickly and clearly obtain design rule and other types of violation entries in their respective modules.

[0018] In an optional implementation, it includes: determining the violations of the timing paths or specific items belonging to each module based on each static timing analysis report in the fully flattened static timing analysis; dividing the report content of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis into corresponding modules in combination with the modules to which the violations belong after classification, and generating module analysis reports for each module; integrating the module analysis reports in all analysis scenarios of each module to generate a global summary report.

[0019] The classification method for static timing analysis reports provided in this embodiment makes the report content clearer and more organized, and improves the readability of the report by dividing the static timing analysis report into module analysis reports of each module and further generating a global summary report. The separate module analysis report helps to quickly locate the problem.

[0020] In an optional implementation, in combination with the modules to which the violations belong after classification, the report contents of each violation path or specific violation entry in each static timing analysis report in the fully flattened static timing analysis are divided into corresponding modules, and a module analysis report for each module is generated, including: if the static timing analysis report is a timing check report, the first-level category type of the static timing analysis report is determined according to the check type of the scenario of the static timing analysis report; the second-level sub-category type of the static timing analysis report is determined according to the physical type of the starting point and the end point of the data path of the target timing path, and the second-level sub-category includes the input port to register, the register to Register, register to output port and input port to output port; according to the module to which the violation of the target timing path belongs, divide the static timing analysis report of the target timing path into the three-level subclasses corresponding to the module to which it belongs, establish the correspondence between the static timing analysis report and the module, and each module corresponds to a three-level subclass; if the second-level subclass divided by the static timing analysis report of the target timing path is register to register, then determine whether the reference names of the modules to which the starting point and the end point of the data path of the target timing path belong are the same, and determine the further four-level subclass of the static timing analysis report of the target timing path in the corresponding third-level subclass module.

[0021] The classification method for static timing analysis reports provided in this embodiment determines the first-level category type of the static timing analysis report according to the inspection type of the scenario of the static timing analysis report, specifically, the MAX or MIN type, which corresponds to the two types of setup time inspection and hold time inspection, respectively, reflecting the programmatic classification of the timing inspection report. According to the physical type of the starting point and the end point of the data path of the target timing path, the report is further subdivided into second-level categories, and the second-level categories represent different types of data flow paths. In the hierarchical module design, the different types of timing paths that the module designers are concerned about are further classified, which helps the designers of each module to perform decoupling analysis on the distribution performance of different types of timing paths. According to the module to which the violation of the target timing path belongs, by dividing the static timing of the target timing path into the target timing path, the violation of the target timing path is classified into the second-level category. The analysis report is divided into three levels of subcategories corresponding to the modules to which it belongs, and a corresponding relationship between the report and the module is established so that each module can obtain a detailed timing analysis report related to it. For the second-level subcategory of register-to-register data path, further classification is performed after the three-level classification is completed. This is because the register-to-register data path is the part that the designers of each module in the hierarchical module design are most concerned about, and its performance can best reflect the pros and cons of each module design. According to whether the reference names of the modules to which the starting point and the end point of the target timing path belong are the same, the static timing analysis report of the target timing path is further determined in the corresponding third-level subcategory module. The further fourth-level subcategory, this subdivision helps to obtain more detailed reports from registers to registers within each module and across different modules more quickly and comprehensively.

[0022] In an optional implementation, in combination with the modules to which the violations belong after classification, the report contents of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis are divided into corresponding modules, and module analysis reports for each module are generated, including: if the static timing analysis report is a design rule check and other types of check reports, a set name directory is created, and the set name directory is used as the first-level category of the static timing analysis report; according to the modules corresponding to the logical levels of the specific violation items in the static timing analysis report, the static timing analysis report is divided into second-level subcategories of the modules, and a corresponding relationship between the static timing analysis report and the modules is established, with each module corresponding to a second-level subcategory; according to the violation types contained in the static timing analysis report, the third-level subcategory of the static timing analysis report in the corresponding module is determined.

[0023] The classification method for static timing analysis reports provided in this embodiment creates a set name directory as the first-level category of static timing analysis reports, and uniformly classifies different design rule checks and other types of inspection reports into corresponding directories for easy management and search. The report is divided into second-level subcategories of modules according to the modules corresponding to the logical levels of specific violation items in the static timing analysis report, and a corresponding relationship between the report and the module is established, so that each module can obtain a detailed inspection report related to it, which also helps to quickly locate the module where the problem is located and improve the efficiency of problem solving. According to the violation types contained in the static timing analysis report, the third-level subcategories of the report in the corresponding module are further determined. By subdividing the three-level subcategories, the problem can be identified and analyzed more accurately.

[0024] In a second aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the upgrade method of the above-mentioned first aspect or any corresponding embodiment thereof by executing the computer instructions. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is a flow chart of a classification method for static timing analysis reports according to an embodiment of the present invention;

[0027] Figure 2is a flow chart of another classification method for static timing analysis reports according to an embodiment of the present invention;

[0028] Figure 3 is a flow chart of another classification method for static timing analysis reports according to an embodiment of the present invention;

[0029] Figure 4 is a flow chart of yet another classification method for static timing analysis reports according to an embodiment of the present invention;

[0030] Figure 5 It is a schematic diagram of the directory structure of a timing check report according to an embodiment of the present invention;

[0031] Figure 6 It is a schematic diagram of the contents of a module summary report of a timing check report according to an embodiment of the present invention;

[0032] Figure 7 is a flowchart of another classification method for static timing analysis reports according to an embodiment of the present invention;

[0033] Figure 8 It is a schematic diagram of the directory structure of the design rule check and other types of check reports according to the embodiment of the present invention;

[0034] Fig. 9 It is a schematic diagram of the contents of a module summary report of a design rule check and other types of check reports according to an embodiment of the present invention;

[0035] Fig.10 is a schematic diagram of the contents of a global summary report according to an embodiment of the present invention;

[0036] Fig.11 It is a schematic diagram of the contents of the global summary report of the global coordination according to an embodiment of the present invention;

[0037] Fig.12 is a schematic diagram of the contents of a global summary report of a top-level module of an embodiment of the present invention;

[0038] Fig.13 It is a schematic diagram of the contents of a global summary report of one of the modules in an embodiment of the present invention;

[0039] Fig.14 It is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0040] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0041] At present, in the fully flattened static timing analysis, in order to pass the report results to different module designers to achieve the purpose of division of labor, the existing processing methods are roughly divided into two types: the first method is that the designer of each module analyzes the original static timing analysis report and extracts the part about himself; the second method is to add path combinations when running the static timing analysis task, or reopen the stored database to adjust the report options to make the static timing analysis tool report a report with clearer classification. Due to the increase in the number of chip transistors, the amount of information in the generated report content is huge, resulting in a significant increase in the time and resources required to open and process the report. It is difficult for designers to quickly locate the required information, and designers of different modules process the same report separately, resulting in duplication of work and low efficiency. In addition, due to the inconsistent caliber, it is easy to cause confusion in project management. Due to the use of the method of adding path combinations, the second processing method requires many combinations to be preset for the static timing analysis task, which increases the complexity of the task, and for some types of reports, it is impossible to classify by adding path combinations.

[0042] According to an embodiment of the present invention, an embodiment of a classification method for static timing analysis reports is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0043] In this embodiment, a classification method for static timing analysis reports is provided. Figure 1 FIG. 1 is a flow chart of a classification method for static timing analysis reports according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0044] Step S101, determining the type of the static timing analysis report of the target timing path.

[0045] In an optional embodiment, the types of the static timing analysis report of the target timing path include setup time type, hold time type, design rules and other types.

[0046] Step S102: if the static timing analysis report is of the establishment time type, the target timing path is divided into an intra-module path and a cross-module path.

[0047] In an optional embodiment, the setup time type includes setup time violation, recovery time violation, maximum delay violation and data check violation.

[0048] In an optional embodiment, according to the similarities and differences of the modules where the logic levels of the starting point, the passing point and the ending point on the data path of the target timing path are located, the paths can be divided into intra-module and cross-module paths. The starting point on the data path of the target timing path is the emission edge trigger on the data path of the target timing path, the passing point on the data path of the target timing path is each standard unit passed by the data path of the target timing path, and the ending point on the data path of the target timing path is the receiving edge trigger on the data path of the target timing path. The logic level is divided according to the complexity and functional requirements of the design. For example, the logic level where the emission edge trigger is located may be "top-level name / module a's instantiation name a1 / a 11 / a 111 ”.

[0049] In an optional embodiment, if the starting point, the passing point, and the ending point on the data path of the target timing path are all located in the same module, then this path is an intra-module path. For example, in "top-level name / instantiation name a1 / a of module a", 11 / a 111 " Under this naming rule, if the starting point, passing point and ending point of the data path of the target timing path are all at the level of "top-level name / instantiation name a1 of module a", and all logics at this level are in the submodule with reference name a, then this path is the intra-module path of module a. If the starting point, passing point and ending point on the data path of the target timing path span different modules, then this path is the cross-module path. For example, in "top-level name / instantiation name a1 / a 11 / a 111 " Under this naming rule, if the starting point and subsequent passing points of the data path of the target timing path are at the level of "top-level name / instantiation name a1 of module a", and the passing points and ending points of the remaining part are at the level of "top-level name / instantiation name b1 of module b", then this path is a cross-module path, and its data path crosses two modules with reference names a and b respectively. By dividing the target timing path into intra-module paths and cross-module paths, violations of the target timing path can be accurately attributed to specific modules.

[0050] In an optional embodiment, preliminary classification is performed according to the type of static timing analysis report, and the data path of the target timing path is divided into intra-module path and cross-module path, so that violations of the target timing path can be accurately located on a specific module.

[0051] Step S103, classifying the violations existing in the paths within the modules into corresponding modules to obtain a first violation classification result.

[0052] In an optional embodiment, for a path within a module, the violation generated by the path belongs to the module.

[0053] Step S104, determining multiple target modules corresponding to the cross-module paths with violations.

[0054] In an optional embodiment, for a cross-module path with a violation, the violation is attributed to the module that contributes the most to the violation. The cross-module path involves interactions and connections between modules. When a violation is detected, it is necessary to ensure that all modules involved in the violation are accurately located. By determining multiple target modules corresponding to the cross-module path with a violation, it can be ensured that no module related to the violation is missed, thereby improving the accuracy of problem location.

[0055] Step S105 , calculating the violation value contribution of each target module according to the logic level, delay, ratio of delay to logic level, and whether there is an abnormal point of each target module.

[0056] In an optional embodiment, since the situation is relatively complicated when judging the contribution of a module to a violation, for example, it is necessary to analyze from multiple levels such as clock tree skew, data path standard cell level, standard cell placement, standard cell threshold voltage, standard cell selection, interconnect winding quality, whether the interconnect is bypassed, interconnect crosstalk, and early design planning. Since the above-mentioned multiple factors may ultimately cause changes in apparent factors such as logic levels and delays, the present invention selects three dimensions of logic levels, delays, and the ratio of delays to logic levels to calculate the violation value contribution of each target module.

[0057] Step S106 , classifying the violations existing in the cross-module path into corresponding target modules according to the violation value contribution of each target module, and obtaining a second violation classification result.

[0058] In an optional embodiment, violations existing in cross-module paths are further divided based on the calculated violation value contribution of each target module, thereby improving the accuracy of classification. By calculating the violation value contribution, it can be determined which modules contribute more to the violations, which helps to accurately divide the modules to which violations existing in cross-module paths belong.

[0059] Step S107 , determining violations of target timing paths belonging to each module according to the first violation classification result and the second violation classification result.

[0060] The present embodiment provides a classification method for static timing analysis reports, which performs preliminary classification according to the type of static timing analysis reports, divides the data path of the target timing path into intra-module paths and cross-module paths, so that violations of the target timing path can be accurately located on specific modules, and further divides the violations of the cross-module paths according to the contribution by calculating the violation value contribution of each target module, thereby further improving the accuracy of classification. By calculating the violation value contribution, it can be determined which modules contribute more to the violations. For violations of cross-module paths, by calculating the contribution of each target module, it is helpful to accurately divide the modules to which the violations in the cross-module paths belong. For cross-module paths with violations, by analyzing the contribution of each target module instead of judging the belonging module according to the path logic level, it can avoid being too arbitrary in classification, thereby preventing the violation module displayed in the report from being inconsistent with the module that actually needs to be repaired.

[0061] In this embodiment, a classification method for static timing analysis reports is provided. Figure 2 FIG. 1 is a flow chart of another classification method for static timing analysis reports according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0062] Step S201, determine the type of static timing analysis report of the target timing path. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0063] Step S202: If the static timing analysis report is of the setup time type, the data path of the target timing path is divided into intra-module paths and cross-module paths. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0064] Step S203, classify the violations existing in the paths within the module into corresponding modules to obtain a first violation classification result. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0065] Step S204: Determine the multiple target modules corresponding to the cross-module paths with violations. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0066] Step S205 , calculating the basic score of the violation value contribution of each target module according to the logic level, delay, and the ratio of the delay to the logic level of each target module.

[0067] In an optional embodiment, the logic level, delay and the ratio of delay to logic level of each target module refer to the level, sum of delays and the ratio of sum of delays to the level of standard cells in each target module at the logic level of the standard cells on the data path of the target timing path. Each module refers to a design module with a specific reference name artificially divided for parallel design. The basic score is calculated based on the logic level, delay and the ratio of delay to logic level of each target module. The basic score can reflect the basic performance of the target module in logic complexity and delay performance.

[0068] Specifically, the above step S205 includes:

[0069] Step S2051, according to the level of the data path of the target timing path, determine the weight vector corresponding to the level, the weight vector includes the weight values ​​corresponding to the logic level, the delay and the ratio of the delay to the logic level, and different weight vectors correspond to different levels.

[0070] In an optional embodiment, different weight vectors corresponding to different levels are determined, including, for different logical level intervals, constructing respective evaluation series, calculating the weight value of each variable in the intervals of different logical levels, calculating the consistency ratio, judging whether the weight value is reasonable, and determining the final weight vector of the logical level, delay, and the ratio of the delay to the logical level.

[0071] In an optional embodiment, when calculating the basic score of the target module, it is necessary to combine the ratio of the delay and the number of logic levels of the target module for calculation. When the number of logic levels of the target module is small, the delay of each logic level will have a greater impact on the ratio of the delay and the number of logic levels. However, when the number of logic levels of the target module is large, even if there is a large delay in a certain logic level in the target module, the ratio of the delay and the number of logic levels finally calculated will not change significantly. At this time, if the ratio of the delay and the number of logic levels is still kept with a larger weight, the basic score finally calculated will not be able to reflect the abnormal delay existing in the logic level. For example, if the total number of levels is 30, 10 of which are in module a with an average delay of 10ps, and the other 20 are in module b with an average delay of 9ps, if the weight of the ratio of delay to logic level is increased, the violation of the timing path should be attributed to module a, but the actual situation is that the delay of some levels in module b is larger. For example, the delay of 3 levels is 20ps, 19ps, and 21ps respectively, which is much larger than the average delay. However, because module b has more levels and the delay of the remaining levels is relatively low, this calculation result will hide the impact of these 3 logic levels on the overall performance. Therefore, different weight vectors should be set for different levels.

[0072] In an optional embodiment, an evaluation sequence of each target module is constructed, and the variables are the logic level, delay, and the ratio of the delay to the logic level of each target module. All variables are compared in pairs, and the comparison scale uses 1 to 9 and its reciprocal, where 1 represents equal importance, 3 represents that the former is slightly more important than the latter, 5 represents that the former is obviously more important than the latter, 7 represents that the former is strongly more important than the latter, and 9 represents that the former is extremely important than the latter. 2, 4, 6, and 8 are the intermediate values ​​of the above adjacent judgments. The weight vectors corresponding to different logic levels in the present invention are only examples. For example, in the present invention, combined with the interval distribution of the total logic level on the data path, the evaluation sequence is constructed as follows:

[0073] Total number of levels ≤ 10 series Delay Delay / Level series 1 1 / 2 1 / 4 Delay 2 1 1 / 3 Delay / Level 4 3 1

[0074] 10<Total number of levels≤20 series Delay Delay / Level series 1 1 1 / 4 Delay 1 1 1 / 2 Delay / Level 4 2 1

[0075] Total levels ≥ 20 series Delay Delay / Level series 1 1 1 / 3 Delay 1 1 1 / 2 Delay / Level 3 2 1

[0076] In an optional embodiment, the weight value of each variable is calculated, including calculating the geometric mean of the elements in each row of the evaluation series and normalizing them to obtain the weight value. Exemplarily, the weight value of each variable in the evaluation series with a total level ≤10 is calculated.

[0077] Compute the geometric mean of the elements in each row:

[0078] For series:

[0079] For delay:

[0080] For Delay / Progression:

[0081] Normalization process to get the weight value:

[0082] The weight of the series:

[0083]

[0084] Delay / level weights:

[0085] In an optional embodiment, the consistency ratio is calculated to determine whether the weight value is reasonable, including using the "sum method" to calculate the maximum eigenvalue of the above matrix. Exemplarily, the consistency ratio of the evaluation series with a total level ≤ 10 is calculated to determine whether the weight value of the evaluation series with a total level ≤ 10 is reasonable.

[0086] The evaluation matrix is ​​normalized by column, that is, the elements of each column are divided by the sum of the elements of the column, and the result is:

[0087]

[0088] Sum the normalized evaluation matrix row by row to get:

[0089]

[0090] Normalize the rows and vectors of the evaluation matrix to obtain the eigenvectors:

[0091]

[0092] Calculate the judgment evaluation matrix and multiply it by the eigenvector to get:

[0093]

[0094] Compute the largest eigenvalue:

[0095]

[0096] In an optional embodiment, calculating the maximum eigenvalue includes calculating a consistency index, finding an average random consistency index RI of a corresponding third-order matrix, calculating a consistency ratio, and determining whether the matrix has satisfactory consistency.

[0097] Calculate the consistency index CI and get:

[0098] In a third-order matrix, n=3

[0099] Find the average random consistency index RI of the corresponding third-order matrix:

[0100] RI≈0.58

[0101] Calculate the consistency ratio CR and get:

[0102]

[0103] The judgment matrix has satisfactory consistency.

[0104] The consistency ratio CR<0.1, so the calculated weights of 0.137, 0.239, and 0.724 are reasonable.

[0105] A weight vector is used to determine the final number of levels, delay, and ratio of delay to logic level.

[0106] After calculation, the final weight vector is:

[0107]

[0108] In an optional embodiment, a weight vector is determined for each level interval based on the level of the data path of the target timing path. The introduction of the weight vector can comprehensively and accurately evaluate the contribution of the target module to the violation value. The weight vector is determined based on the level of the data path, and can flexibly adapt to the different effects of various factors on the contribution of the violation value at different levels, thereby improving the flexibility and applicability of the evaluation.

[0109] Step S2052, according to the weight vector, the logic level, delay, and ratio of delay to logic level of the standard cells on the data path of the target timing path are respectively calculated by normalized weighted average to obtain the basic score of the violation value contribution of each target module.

[0110] In an optional embodiment, illustratively, the data path of the target timing path passes through m modules, namely module 1, module 2, ..., module m. By calculation, there are k levels on the data path of the target timing path. The selected weight vector is (a1, a2, a3). According to the module distribution, the maximum logic level of a single module is k. max , the maximum delay of a single module is d max , the ratio of the maximum delay of a single module to the number of logic levels is (d / k) max .

[0111] The level of a module i is k i , the delay is d i , then the module uses the normalized weighted average algorithm to calculate the basic score S i , S i The basic score is based on a percentage system:

[0112]

[0113] In an optional embodiment, a determined weight vector is used to normalize the logic level, delay, and ratio of delay to logic level of each target module, and a weighted average calculation is performed based on the normalized values ​​and the corresponding weights to obtain a basic score for the violation value contribution of each target module. The normalized weighted average calculation eliminates the dimensional differences between different factors, making the evaluation results more accurate and reliable.

[0114] Step S206 , determining whether the number of standard cell levels of the data path of the target timing path is less than a preset value.

[0115] If the number of standard cell levels of the data path of the target timing path is less than a preset value, it is determined that there is no abnormal point in the data path of the target timing path;

[0116] If the number of standard cell levels of the data path of the target timing path is greater than or equal to the preset value,

[0117] Calculate the mean and standard deviation of the delays of all standard cells in the data path of the target timing path.

[0118] In an optional embodiment, exemplarily, the preset value can be set to level 5. When the number of standard cells in the data path of the target timing path is less than level 5, only the delay data of a few standard cells are available for analysis. At this time, if the average value and standard deviation of the delays of all standard cells in the data path of the target timing path are calculated, the calculated result is easily affected by extreme values. When the number of standard cells in the data path of the target timing path is greater than level 5, it means that there are more standard cell delay data available for analysis. The larger the sample size, the closer the estimated mean and standard deviation are to the true value, and the higher the significance of the statistical results, so that the calculated statistics are more reliable.

[0119] In an optional embodiment, by determining whether the number of standard cell levels is less than a preset value, data paths with fewer standard cell levels can be excluded, thereby avoiding calculation errors caused by a small sample size.

[0120] Step S207 , judging whether the delay of each standard cell meets a set condition according to the delay, average value and standard deviation of each standard cell.

[0121] If the delay of the standard cell meets the set conditions, the standard cell is determined to be an abnormal point;

[0122] If the delay of the standard cell does not meet the set condition, it is determined that there is no abnormal point in the data path of the target timing path.

[0123] In an optional embodiment, the setting conditions are x>1.5μ and x>μ+3δ, x is the delay of each standard cell, μ is the average value of all standard cells, δ is the standard deviation of all standard cells, and the setting conditions are based on the properties of normal distribution to determine whether there are abnormal points in the data path of the target timing path. In statistics, approximately 99.7% of the data will fall within the range of three standard deviations on both sides of the average value. When x>μ+3δ, it means that the delay x of the standard cell exceeds the third standard deviation on the right side of the average value μ, and 1.5μ can identify delays that significantly deviate from the normal range. Therefore, if the delay of a certain level of standard cells in the data path of the target timing path is x, when x>1.5μ and x>μ+3δ, it is determined that there are abnormal points on the data path of this target timing path. By calculating the delay average and standard deviation, and combining the setting conditions to determine whether the delay of each standard cell is abnormal, the abnormal points in the data path can be more accurately located.

[0124] Step S208: determine the module containing the abnormal point as a module with abnormal points.

[0125] Step S209: If there is no abnormal point in the target module, the basic score is determined as the violation value contribution of the target module.

[0126] In an optional embodiment, by determining whether there are abnormal points in the target module, the situation where the delay of a certain level or several levels of standard cells in the violation path is abnormally large can be accurately identified.

[0127] Step S210 , if there is an abnormal point in the target module, an additional score of the violation value contribution is calculated according to the standard unit delay of the target module, and the sum of the basic score and the additional score is determined as the violation value contribution of the target module.

[0128] In an optional embodiment, assuming that the module with the outlier is module i, the module will receive an additional score S add :

[0129]

[0130] Among them, S add is the extra score of the module, x is the delay of a certain level of standard cell in the data path of the target timing path, μ i It is the average delay of all standard cells in the data path of the target timing path.

[0131] Calculated score S for module i i for:

[0132]

[0133] In an optional embodiment, by calculating the average value and standard deviation of the delay and combining the set conditions to determine whether the delay of each standard unit is abnormal, the abnormal point in the data path can be located more accurately.

[0134] In an optional embodiment, if there is an abnormal point in the target module, the additional score is calculated based on the delay of the standard cell of the abnormal point and the delay of all standard cells on the data path of the target timing path. The additional score can correct the basic score, and finally calculate the final score to fully reflect the actual situation of the target module, making the final score more objective and fair. Giving additional points to the module with abnormal points can highlight the importance of the abnormal point. Usually, the logic level with abnormal delay is the priority to be repaired in the actual project, avoiding the abnormal points in the module with more logic levels from being hidden in the calculation of the basic score, and improving the accuracy of the violation attribution of the target timing path.

[0135] Step S211 , according to the violation value contribution of each target module, the violations existing in the cross-module path are divided into corresponding target modules to obtain a second violation division result.

[0136] In an optional embodiment, for example, if the contribution of target module 1 to the target violation existing in the cross-module path is 90, and the contribution of target module 2 to the target violation existing in the cross-module path is 10, 90>10, so the violation existing in the cross-module path is classified into target module 1.

[0137] Step S212, determining the violations of the target timing paths belonging to each module according to the first violation classification result and the second violation classification result.

[0138] In this embodiment, a classification method for static timing analysis reports is provided. Figure 3 FIG. 1 is another flow chart of a classification method for static timing analysis reports according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0139] Step S301, determine the type of static timing analysis report of the target timing path. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0140] Step S302: If the static timing analysis report is of the setup time type, the data path of the target timing path is divided into intra-module paths and cross-module paths. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0141] Step S303: classify the violations existing in the paths within the module into corresponding modules to obtain a first violation classification result. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0142] Step S304: Determine the multiple target modules corresponding to the cross-module paths that have violations. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0143] Step S305, calculate the violation value contribution of each target module according to the logic level, delay, ratio of delay and logic level, and whether there is an abnormal point of each target module. Figure 2 Steps S205 to S207 of the illustrated embodiment are not described in detail here.

[0144] Step S306: According to the violation value contribution of each target module, the violations existing in the cross-module path are divided into corresponding target modules to obtain a second violation division result. Figure 1 Step S106 of the illustrated embodiment will not be described in detail here.

[0145] Step S307 , determining violations of target timing paths belonging to each module according to the first violation classification result and the second violation classification result.

[0146] If the static timing analysis report is a hold time type, then step S308 - step S309 are executed.

[0147] In an optional embodiment, the hold time type includes a hold time violation, a removal time violation, and a minimum delay violation.

[0148] Step S308, determining the logic level at which the end point of the data path of the target timing path is located.

[0149] In an optional embodiment, the most common repair method for the hold time type in engineering is to add a delay in the previous stage of the end point. Therefore, in the present invention, the module to which the hold type violation belongs is the module corresponding to the logical level where the end point is located.

[0150] Step S309 , determining the violation of the target timing path belonging to each module according to the logic level at which the end point of the data path of the target timing path is located.

[0151] In an optional embodiment, based on the logical level at which the end point of the data path of the target timing path is located, the repair of violations based on the hold time type is usually performed in the module corresponding to the logical level at which the end point is located. This classification method reduces the complexity of attribution judgment while ensuring classification accuracy.

[0152] If the static timing analysis report is a design rule or other type, then step S310 - step S311 are executed.

[0153] In an optional embodiment, the design rule type and other types include violations of checks for maximum clock signal transition time, maximum data signal transition time, maximum clock load capacitance, maximum data load capacitance, crosstalk, minimum period, double switching, and minimum waveform width.

[0154] Step S310, determining specific violation items of design rules and other types of violations.

[0155] Step S311 , determining the violations of specific items belonging to each module according to the logical levels at which the specific violation items of the design rules and other types of violations are located.

[0156] In an optional embodiment, specific violation entries of the design rule type violation include a maximum clock signal conversion time violation, a maximum data signal conversion time violation, a maximum clock load capacitance violation, a maximum data load capacitance violation, a crosstalk violation, a minimum period violation, a double switching violation, and a minimum waveform width violation. The specific violation entries of the design rule and other types of violations are specifically reflected as violations generated by a certain level of standard cells, a certain interconnection line, or a certain pin of a certain module. For example, the maximum clock load capacitance violation may be reflected as a certain pin load capacitance of a standard cell a1 of module a being too large. Therefore, at this time, the module to which the maximum clock load capacitance violation of the pin of the standard cell a1 belongs is module a. Because the design rule and other types of violations are finally reflected as specific single-point violations, the module to which the violation entry of this type belongs is the module corresponding to the logical level where the violation entry is located. By locating the single-point violation, the module to which the violation belongs can be quickly found, so that the module designer can more quickly and clearly obtain the violation entries about the design rule and other types in their respective modules.

[0157] Step S312 , determining violations of target timing paths or specific items belonging to each module according to each static timing analysis report in the fully flattened static timing analysis.

[0158] In an optional embodiment, the chip usually adopts multiple working modes, illustratively including functional mode, test mode, high voltage mode, low voltage mode, etc. At the same time, the chip is also affected by multiple fluctuations, illustratively including chip manufacturing process fluctuations, voltage fluctuations, temperature fluctuations, and changes in chip parasitic parameters caused by manufacturing process fluctuations. In response to the above complex scenarios, the strategy usually adopted by the industry is to use different working modes, different extreme processes, voltages, temperatures, and different extreme parasitic parameter conditions, combined with inspection types to form different analysis scenarios, reflecting the specific timing analysis scenarios that the report focuses on. In each specific timing analysis scenario, a static timing analysis report will be generated, so the fully flattened static timing analysis contains multiple types of static timing analysis reports for multiple analysis scenarios.

[0159] Step S313 , combining the modules to which the violations are classified, divide the report contents of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis into corresponding modules, and generate module analysis reports for each module.

[0160] Step S314, integrating the module analysis reports of all analysis scenarios of each module to generate a global summary report.

[0161] In an optional embodiment, by dividing the static timing analysis report into module analysis reports for each module and further generating a global summary report, the report content is made clearer and more organized, and the readability of the report is improved. The separate module analysis report helps to quickly locate the problem.

[0162] In this embodiment, a classification method for static timing analysis reports is provided. Figure 4 FIG. 1 is a flow chart of another classification method for static timing analysis reports according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0163] Step S401, determine the type of static timing analysis report of the target timing path. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0164] Step S402: If the static timing analysis report is of the setup time type, the data path of the target timing path is divided into intra-module paths and cross-module paths. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0165] Step S403: classify the violations existing in the paths within the module into corresponding modules to obtain a first violation classification result. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0166] Step S404: Determine the multiple target modules corresponding to the cross-module paths with violations. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0167] Step S405, calculate the violation value contribution of each target module according to the logic level, delay, ratio of delay and logic level, and whether there is an abnormal point of each target module. Figure 2 Steps S205 to S207 of the illustrated embodiment are not described in detail here.

[0168] Step S406: According to the violation value contribution of each target module, the violations existing in the cross-module path are divided into corresponding target modules to obtain a second violation division result. Figure 1 Step S106 of the illustrated embodiment will not be described in detail here.

[0169] Step S407 , determining violations of target timing paths belonging to each module according to the first violation classification result and the second violation classification result.

[0170] Step S408 , determining violations of target timing paths attributable to each module according to each static timing analysis report in the fully flattened static timing analysis.

[0171] Step S409 , combining the modules to which the violations are classified, dividing each static timing analysis report in the fully flattened static timing analysis into corresponding modules, and generating a module analysis report for each module.

[0172] Specifically, the above step S409 includes:

[0173] Step S4091: If the static timing analysis report is a timing check report, determine the primary category type of the static timing analysis report according to the check type of the scenario of the static timing analysis report.

[0174] In an optional embodiment, the timing check report in the static timing analysis report is a check report of setup time violation, hold time violation, recovery time violation, removal time violation, maximum delay violation, minimum delay violation and data check violation, and the check types of the static timing analysis report are setup time type and check time type.

[0175] In an optional embodiment, according to the inspection type of the scenario of the static timing analysis report, its first-level category type is determined, specifically MAX or MIN type, which respectively correspond to the two types of setup time check and hold time check, reflecting the programmatic classification of the timing check report.

[0176] Step S4092, determine the secondary subclass type of the static timing analysis report according to the physical type of the starting point and the end point of the data path of the target timing path, the secondary subclass includes input port to register, register to register, register to output port and input port to output port.

[0177] In an optional embodiment, the report is further subdivided into secondary subcategories according to the physical types of the starting point and the ending point of the data path of the target timing path, and the secondary subcategories respectively represent different types of data flow paths.

[0178] In an optional embodiment, if the physical type of the starting point of the data path of the target timing path in the first-level category type is an input port, and the physical type of the end point is a register, then the static timing analysis report of the target timing path is divided into input port to register, if the physical type of the starting point of the data path of the target timing path in the first-level category type is a register, and the physical type of the end point is also a register, then the static timing analysis report of the target timing path is divided into register to register, if the physical type of the starting point of the data path of the target timing path in the first-level category type is a register, and the physical type of the end point is an output port, then the static timing analysis report of the target timing path is divided into register to output port, if the physical type of the starting point of the data path of the target timing path in the first-level category type is an input port, and the physical type of the end point is an output port, then the static timing analysis report of the target timing path is divided into input port to output port, the input port is used to receive input signals outside the module, the register is a standard unit with data latching and transmission functions triggered by a clock, and the output port is used for the module to output signals to the outside.

[0179] In an optional embodiment, the report is further subdivided into secondary subcategories based on the physical types of the starting point and the end point of the data path of the target timing path. The secondary subcategories represent different types of data flow paths. In the hierarchical module design, the different types of timing paths that the module designers are concerned about are further classified, which helps the module designers to perform decoupling analysis on the distribution performance of different types of timing paths.

[0180] Step S4093, according to the module to which the violation of the target timing path belongs, the static timing analysis report of the target timing path is divided into three-level subcategories corresponding to the module, and a corresponding relationship between the static timing analysis report and the module is established, and each module corresponds to a three-level subcategory.

[0181] In an optional embodiment, according to the module to which the violation of the target timing path belongs, a correspondence between the report and the module is established by dividing the static timing analysis report of the target timing path into three levels of subcategories corresponding to the module, so that each module can obtain a detailed timing analysis report related to it.

[0182] Step S4094, if the second-level subclass divided by the static timing analysis report of the target timing path is register to register, then determine the fourth-level subclass of the static timing analysis report of the target timing path in the module corresponding to the third-level subclass based on whether the reference names of the modules to which the starting point and the end point of the data path of the target timing path belong are the same.

[0183] If the reference name of the module to which the start point and the end point of the data path of the target timing path belong is the same, the static timing report is divided into a four-level subclass named internal;

[0184] If the reference names of the modules to which the start point and the end point of the data path of the target timing path belong are different, the static timing report is divided into a four-level subclass named interface.

[0185] In an optional embodiment, if the reference names of the modules to which the starting point and the ending point of the data path of the target timing path from register to register of the second-level subcategory belong are the same, that is, they belong to the same module, then the static timing report of the target timing path is divided into a four-level subcategory named internal. This path usually indicates that the signal is transmitted between registers within the same module and does not involve the interface between the modules. In some cases, the reference names of the modules to which the starting point and the ending point of the target timing path belong are the same, but the reference names of the modules to which the through points of some levels belong are different from them. In order to simplify the classification, this situation is also divided into a four-level subcategory named internal. If the reference names of the modules to which the starting point and the ending point of the data path of the target timing path belong are different, that is, they belong to different modules, then the static timing report is divided into a four-level subcategory named interface. This path indicates that the signal has a transmission interface between different modules.

[0186] In an optional embodiment, the second-level subcategory of register-to-register data path is further classified after the third-level classification is completed, because the register-to-register data path is the part that the designers of each module in the hierarchical module design are most concerned about, and its performance can best reflect the quality of the design of each module.

[0187] In an optional embodiment, for a target timing path whose second-level subclass is register to register, the fourth-level subclass of the static timing analysis report in the corresponding module is further determined based on whether the reference names of the modules to which the starting point and the end point of the target timing path belong are the same. This subdivision helps to more quickly and comprehensively obtain more detailed reports from register to register within each module and across different modules, as well as to more accurately identify and analyze the connections between modules of the target timing path.

[0188] In an optional embodiment, directories with corresponding names are set for the above four levels of classification, and a collection of static timing analysis reports that meet the target timing paths of all terminal subcategories are written into different reports. The names of the reports are composed of reference names of modules corresponding to the logical levels of IN, OUT, the starting point and the end point according to the types of the starting point and the end point, separated by four underscores, and a module summary report is generated at the same time. The module summary report is located in parallel with the third-level directory.

[0189] In an alternative embodiment, if Figure 5 As shown, Figure 51 is a schematic diagram of the directory structure of the timing check report of an embodiment of the present invention, wherein MAX / or MIN / respectively represents the check type of the setup time or hold time in a certain scenario; IN2REG / represents the secondary subclass name from input port to register, REG2REG / represents the secondary subclass name from register to register, REG2OUT represents the secondary subclass name from register to output port, and IN2OUT / represents the secondary subclass name from input port to output port; TOP_ONLY / represents the top-level module, BLOCK_1 / to BLOCK_N / represents module 1 to module N, BLOCK_1 represents module 1, and BLOCK_N represents module N, where N is a variable representing any number of modules; IN____OUT.rpt represents the report text of the static timing report of the target timing path from all input ports to output ports belonging to a certain module, which is printed and output by the collection, and IN____BLOCK_k.rpt represents all input ports belonging to a certain module. The report text printed and output by the collection of static timing reports of the target timing path from the port to the end point of the module with the reference name BLOCK_k where the logic level is located, BLOCK_m____OUT.rpt represents the report text printed and output by the collection of static timing analysis reports of the target timing path from the starting point of the module with the reference name BLOCK_m to the output port of all logic levels belonging to a certain module, BLOCK_m____BLOCK_n.rpt represents the report text printed and output by the collection of static timing analysis reports of the target timing path from the starting point of the module with the reference name BLOCK_m to the end point of the module with the reference name BLOCK_n where the logic level is located; IN2OUT.sum represents the summary report of all modules belonging to the IN2OUT secondary subclass, IN2REG.sum represents the summary report of all modules belonging to the IN2REG secondary subclass, REG2OUT.su m represents the summary report of all modules belonging to the REG2OUT secondary subclass, REG2REG.sum represents the summary report of all modules belonging to the REG2REG secondary subclass; the first, second, third, and fourth levels represent different directory structure levels. For example, MAX / IN2OUT / TOP_ONLY / IN____OUT.rpt represents the report text of the static timing report of the target timing path from all input ports to output ports of the top-level module that belongs to the establishment time type check in a certain analysis scenario, the starting point of the data path is the input port and the end point is the output port, and its violation belongs to the collection of static timing reports printed and output. MIN / REG2REG / TOP_ONLY / INTERNAL / TOP_ONLY____TOP_ONLY.rpt indicates that in a certain analysis scenario, it belongs to the hold time type check, the data path starting point is a register and the end point is a register, the module it belongs to is the top-level module, the reference name of the module where the starting point and the end point logic level are located is the same and the static timing analysis report of all target timing paths of the top-level module is printed and output. .

[0190] In an alternative embodiment, if Figure 6 As shown, Figure 6 yes Figure 5 A schematic diagram of the contents of the module summary report of the timing check report of the embodiment of the present invention mentioned, wherein WNS represents the worst negative margin, TNS represents the total negative margin, FEP represents the total number of violation end points, the step value of the WNS distribution is only for illustration and needs to be dynamically adjusted according to the timing status, the Overall row is always located in the first row of the content part, and is a summary of the rows below it, the value of the WNS column of the Overall row is the minimum value of the values ​​below this column, and the values ​​of other value columns of the Overall row are the sum of the values ​​below this column.

[0191] Step S410, integrating the module analysis reports of all analysis scenarios of each module to generate a global summary report.

[0192] In this embodiment, a classification method for static timing analysis reports is provided. Figure 7 is a flow chart of another classification method for static timing analysis reports according to an embodiment of the present invention. Figure 7 As shown, the process includes the following steps:

[0193] Step S701, determine the type of static timing analysis report of the target timing path. For details, see Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0194] Step S702: If the static timing analysis report is of the setup time type, the data path of the target timing path is divided into intra-module paths and cross-module paths. Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0195] Step S703: Classify the violations existing in the paths within the module into corresponding modules to obtain a first violation classification result. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0196] Step S704: Determine the multiple target modules corresponding to the cross-module paths that have violations. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0197] Step S705, calculate the violation value contribution of each target module according to the logic level, delay, ratio of delay and logic level, and whether there is an abnormal point of each target module. Figure 2 Steps S205 to S207 of the illustrated embodiment are not described in detail here.

[0198] Step S707: According to the violation value contribution of each target module, the violations existing in the cross-module path are divided into corresponding target modules to obtain a second violation division result. Figure 1 Step S107 of the illustrated embodiment will not be described in detail here.

[0199] Step S707 , determining violations of target timing paths belonging to each module according to the first violation classification result and the second violation classification result.

[0200] Step S708 , determining violations of target timing paths belonging to each module according to each static timing analysis report in the fully flattened static timing analysis.

[0201] Step S709 , combining the modules to which the violations are classified, dividing each static timing analysis report in the fully flattened static timing analysis into corresponding modules, and generating a module analysis report for each module.

[0202] Specifically, the above step S709 includes:

[0203] Step S7091, if the static timing analysis report is a design rule check or other type of check report, create a set name directory and use the set name directory as a primary category of the static timing analysis report.

[0204] In an optional embodiment, illustratively, a first-level directory named drv is created as a classification basis for the first-level categories, and a set name directory is created as a first-level category for static timing analysis reports. Different design rule checks and other types of check reports are uniformly classified into corresponding directories for easy management and search.

[0205] Step S7092, divide the static timing analysis report into secondary subcategories of the module according to the module corresponding to the logical level of the specific violation entry in the static timing analysis report, establish a corresponding relationship between the static timing analysis report and the module, and each module corresponds to a secondary subcategory.

[0206] In an optional embodiment, exemplarily, a secondary subdirectory named TOP_ONLY and each block reference name is created, wherein TOP_ONLY represents the top-level module and block represents the module. If the module corresponding to the logical level at which the specific violation entry in the static timing analysis report is located is a top-level module, then the report of the specific violation entry in the static timing analysis report is divided into the secondary subdirectory named TOP_ONLY. If the module corresponding to the logical level at which the specific violation entry in the static timing analysis report is located is a non-top-level module, exemplarily, the module corresponding to the logical level at which the specific violation entry in the static timing analysis report is located is module 1, then the report of the specific violation entry in the static timing analysis report is divided into the secondary subdirectory named BLOCK_1.

[0207] In an optional embodiment, the report is divided into secondary subcategories of modules according to the modules corresponding to the logical levels of specific violation entries in the static timing analysis report, and a corresponding relationship between the report and the modules is established, so that each module can obtain a detailed inspection report related to it, which also helps to quickly locate the module where the problem is located and improve the efficiency of problem solving.

[0208] Step S7093, determining the third-level subclass of the static timing analysis report in the corresponding module according to the violation type included in the static timing analysis report.

[0209] In an optional embodiment, exemplarily, according to the type of violation, the static timing report is divided into three levels of subcategories named clk_tran, data_tran, clk_cap, data_cap, noise, min_period, double_switch, and min_pulse_width, where clk_tran represents the maximum transition time violation of the clock signal, data_tran represents the maximum transition time violation of the data signal, clk_cap represents the maximum load capacitance violation of the clock, data_cap represents the maximum load capacitance violation of the data, noise represents the crosstalk violation, min_period represents the minimum period violation, double_switch represents the double switching violation, and min_pulse_width represents the minimum waveform width violation.

[0210] In an optional embodiment, all reports of items classified into the third-level subcategories are printed and output to files corresponding to the third-level subcategories. For design rule checking and other types of checking reports, a module summary report is generated, and the location of the report is parallel to the second-level directory, such as Figure 8 As shown, Figure 8 Schematic diagram of the directory structure of the design rule check and other types of check reports in the embodiment of the present invention, such as Fig. 9 As shown, Fig. 9 It is a schematic diagram of the contents of a module summary report of a design rule check and other types of check reports according to an embodiment of the present invention.

[0211] In an optional embodiment, according to the violation types included in the static timing analysis report, three levels of subcategories reported in the corresponding module are further determined. By subdividing the three levels of subcategories, the problem can be identified and analyzed more accurately.

[0212] Step S710, integrating the module analysis reports of all analysis scenarios of each module to generate a global summary report.

[0213] In an optional embodiment, the module analysis reports of all analysis scenarios of each module are integrated to generate a global summary report, where scenario represents the analysis scenario, such as Fig.10 As shown, Fig.10 is a schematic diagram of the contents of the global summary report of an embodiment of the present invention. The global summary report includes information of all modules. In order to allow designers of each module to focus on the parts that they are more concerned about, the present invention can also split the report at the same time, such as Fig.11 As shown, Fig.11 is a schematic diagram of the contents of the global summary report of the global coordination of an embodiment of the present invention, such as Fig.12 As shown, Fig.12 Schematic diagram of the contents of the global summary report of the top-level module of the embodiment of the present invention, such as Fig.13 As shown, Fig.13 It is a schematic diagram of the contents of a global summary report of one of the modules in an embodiment of the present invention.

[0214] Fig.14 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.14 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.14 A processor 10 is taken as an example.

[0215] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0216] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0217] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0218] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0219] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0220] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0221] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0222] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A classification method for static timing analysis reports, characterized in that: The method comprises: Determine the type of static timing analysis report for the target timing path; If the static timing analysis report is of a setup time type, dividing the data path of the target timing path into an intra-module path and a cross-module path; Classify the violations existing in the paths within the module into corresponding modules to obtain a first violation classification result; Determine multiple target modules corresponding to the cross-module paths where violations exist; Calculate the violation value contribution of each target module according to the logic level, delay, ratio of delay and logic level, and whether there is an abnormal point of each target module; According to the violation value contribution of each target module, the violations existing in the cross-module path are divided into corresponding target modules to obtain a second violation division result; Violations of target timing paths belonging to each module are determined according to the first violation classification result and the second violation classification result.

2. The method according to claim 1, characterized in that The calculation of the violation value contribution of each target module according to the logic level, delay, ratio of delay to logic level, and whether there is an abnormal point of each target module includes: Calculate the basic score of the violation value contribution of each target module according to the logic level, delay and the ratio of delay to logic level of each target module; If the target module does not have an abnormal point, the basic score is determined as the violation value contribution of the target module; If the target module has an abnormal point, the additional score of the violation value contribution is calculated based on the standard cell delay of the abnormal point and the standard cell delay on the data path of the target timing path, and the sum of the basic score and the additional score is determined as the violation value contribution of the target module.

3. The method according to claim 2, characterized in that The step of calculating the basic score of the violation value contribution of each target module according to the logic level, delay, and the ratio of delay to logic level of each target module comprises: Determine a weight vector corresponding to the number of levels of the data path of the target timing path, wherein the weight vector includes weight values ​​corresponding to the number of logic levels, the delay, and the ratio of the delay to the number of logic levels, and different weight vectors correspond to different levels; According to the weight vector, the logic level, delay and ratio of the delay to the logic level of the standard cells on the data path of the target timing path are respectively calculated by normalized weighted average to obtain the basic score of the violation value contribution of each target module.

4. The method according to claim 2, characterized in that: include: If the number of standard cell levels of the data path of the target timing path is less than a preset value, determining that there is no abnormal point in the data path of the target timing path; If the number of standard cell levels of the data path of the target timing path is greater than or equal to a preset value, Calculate the average value and standard deviation of delays of all standard cells in the data path of the target timing path; According to the delay of each standard unit, the average value and the standard deviation, respectively judging whether the delay of each standard unit meets the set conditions; If the delay of the standard cell meets the set condition, the standard cell is determined to be an abnormal point; The module including the abnormal point is determined as the module having the abnormal point.

5. The method according to claim 1, characterized in that If the static timing analysis report is of a hold time type, the method includes: Determine the logic level at which the end point of the data path of the target timing path is located; Violations of the target timing paths belonging to each module are determined according to the logic level at which the end point of the data path of the target timing path is located.

6. The method according to claim 1, characterized in that If the static timing analysis report is a design rule or other type, the method includes: Determine specific violation items of the design rules and other types of violations; According to the logical levels at which the specific violation items of the design rules and other types of violations are located, the violations of the specific items belonging to each module are determined.

7. The method according to claim 1, characterized in that The method further comprises: According to each static timing analysis report in the fully flattened static timing analysis, determine the violation of the timing path or specific item belonging to each module; In combination with the modules to which the violations are classified, report contents of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis are divided into corresponding modules, and module analysis reports of each module are generated; Integrate the module analysis reports under all analysis scenarios of each module to generate a global summary report.

8. The method according to claim 7, characterized in that In combination with the modules to which the violations are classified, the report contents of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis are divided into corresponding modules, and a module analysis report of each module is generated, including: If the static timing analysis report is a timing check report, Determine the primary category type of the static timing analysis report according to the inspection type of the scenario of the static timing analysis report; Determine the secondary subclass type of the static timing analysis report according to the physical type of the starting point and the ending point of the data path of the target timing path, wherein the secondary subclass includes input port to register, register to register, register to output port, and input port to output port; According to the module to which the violation of the target timing path belongs, the static timing analysis report of the target timing path is divided into three-level subcategories corresponding to the module to which it belongs, and a corresponding relationship between the static timing analysis report and the module is established, where each module corresponds to a three-level subcategories; If the second-level subclass of the static timing analysis report of the target timing path is register to register, then the fourth-level subclass of the static timing analysis report of the target timing path in the corresponding third-level subclass module is determined based on whether the reference names of the modules to which the starting point and the end point of the data path of the target timing path belong are the same.

9. The method according to claim 8, characterized in that In combination with the modules to which the violations are classified, the report contents of each violation path or specific violation item in each static timing analysis report in the fully flattened static timing analysis are divided into corresponding modules, and a module analysis report of each module is generated, including: If the static timing analysis report is a design rule check or other type of check report, Creating a set name directory, and using the set name directory as a primary category of the static timing analysis report; According to the modules corresponding to the logical levels of the specific violation entries in the static timing analysis report, the static timing analysis report is divided into secondary subcategories of the modules, and a corresponding relationship between the static timing analysis report and the modules is established, where each module corresponds to a secondary subcategory; According to the violation types included in the static timing analysis report, the third-level subclasses of the static timing analysis report in the corresponding module are determined.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 9 by executing the computer instructions.

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