Automatic wiring method, device and equipment for flip chip and storage medium
Through automated node composition generation and edge building operations, the problem of flip chip global wiring relies on manual intervention is solved, and efficient and accurate automatic wiring is achieved, reducing maintenance costs.
Patent Information
- Application Number
- CN202411680067.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-14
AI Technical Summary
In the prior art, the global wiring of flip chips requires human intervention, which is inefficient and error-prone, and the composition results rely on personal habits, resulting in overall wiring inconsistency and high maintenance costs.
By obtaining the pad layout diagram of the flip chip, generating the initial node composition, and performing edge building operations on it, the target wiring composition is automatically generated, thereby realizing automatic wiring of the flip chip.
It saves human and material resources, improves the efficiency of generating target wiring composition, avoids inefficiency and errors in manual edge construction, and ensures the consistency and stability of wiring.
Smart Images
Figure CN119623404A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and in particular to an automatic wiring method, device, equipment and storage medium for a flip chip. Background Art
[0002] Flip chip is a technology that arranges the entire chip active surface into a pin array and prefabricates solder bumps, and then interconnects them through a flip chip process. Compared with traditional wire bonding technology, it has higher assembly density and signal transmission rate. Among them, wiring is a key part of flip chip packaging.
[0003] The wiring method generally includes global wiring and detailed wiring. Global wiring is the core link, and its input is the wiring pattern constructed based on the flip chip. At present, human intervention is usually required to construct the wiring pattern, which occupies 80% of the entire wiring time and consumes a lot of manpower and material resources. Summary of the invention
[0004] In view of the deficiencies in the above-mentioned prior art, the present application provides a flip chip automatic wiring method, device, equipment and storage medium to solve the problems existing in the prior art.
[0005] The technical solution adopted in the embodiment of the present application is as follows:
[0006] In a first aspect, an embodiment of the present application provides an automatic wiring method for a flip chip, comprising:
[0007] Obtaining a pad layout diagram of a flip chip, wherein the pad layout diagram has a plurality of pad nodes, and the plurality of pad nodes respectively correspond to a plurality of pads on the flip chip;
[0008] Generate an initial node pattern of the flip chip according to the information of the plurality of pad nodes, wherein the initial node pattern has the plurality of pad nodes and virtual nodes, and the virtual nodes are virtual nodes between different pad nodes;
[0009] Performing an edge building operation on each node in the initial node graph to obtain a target wiring graph, so that the target wiring graph has an edge relationship between nodes, and the edge relationship between nodes is used to represent a wiring path at a corresponding position of the node;
[0010] The flip chip is automatically wired according to the target wiring pattern to obtain a packaging structure of the flip chip.
[0011] In a second aspect, an embodiment of the present application provides an automatic wiring device for a flip chip, comprising:
[0012] An acquisition module, used for acquiring a pad layout diagram of a flip chip, wherein the pad layout diagram has a plurality of pad nodes, and the plurality of pad nodes respectively correspond to a plurality of pads on the flip chip;
[0013] A generating module, configured to generate an initial node pattern of the flip chip according to information of the plurality of pad nodes, wherein the initial node pattern has the plurality of pad nodes and virtual nodes, and the virtual nodes are virtual nodes between different pad nodes;
[0014] An edge building module, used for performing an edge building operation on each node in the initial node graph to obtain a target wiring graph, so that the target wiring graph has an edge relationship between nodes, and the edge relationship between nodes is used to characterize the wiring path of the corresponding position of the node;
[0015] A wiring module is used to automatically wire the flip chip according to the target wiring pattern to obtain a packaging structure of the flip chip.
[0016] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor communicates with the storage medium via the bus, and the processor executes the program instructions to implement the automatic wiring method of the flip chip described in the above embodiment.
[0017] In a fourth aspect, an embodiment of the present application provides a readable storage medium having program instructions stored thereon, and when the program instructions are executed by a processor, the automatic wiring method for a flip chip described in the above embodiment is implemented.
[0018] The beneficial effect of the present application is as follows: the present application provides an automatic wiring method for a flip chip, which can generate an initial node composition of the flip chip according to information of multiple pad nodes on a pad layout diagram of the flip chip, and then perform edge building operations on each node in the initial node composition to automatically generate a target wiring composition of the flip chip, thereby saving manpower and material resources and improving the efficiency of generating a target wiring composition. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1(a) is a schematic diagram of a flip chip;
[0021] Figure 1(b) is a schematic diagram of a flip chip package;
[0022] Figure 2 One of the flow charts of the automatic wiring method of the flip chip provided in the embodiment of the present application;
[0023] Figure 3 One of the pad layout diagrams provided in the embodiment of the present application;
[0024] Figure 4 A second flow chart of the automatic wiring method for a flip chip provided in an embodiment of the present application;
[0025] Figure 5 The second pad layout diagram provided in the embodiment of the present application;
[0026] Figure 6 A schematic diagram of a virtual node provided in an embodiment of the present application;
[0027] Figure 7 A third flow chart of the automatic wiring method for a flip chip provided in an embodiment of the present application;
[0028] Figure 8 A fourth flowchart of the automatic wiring method for a flip chip provided in an embodiment of the present application;
[0029] Fig. 9 A schematic diagram of the structure of the initial wiring pattern provided in an embodiment of the present application;
[0030] Fig.10 A fifth flow chart of the automatic wiring method for a flip chip provided in an embodiment of the present application;
[0031] Fig.11 A schematic diagram of the structure of a first wiring pattern provided in an embodiment of the present application;
[0032] Fig.12 A sixth flow chart of the automatic wiring method for a flip chip provided in an embodiment of the present application;
[0033] Fig.13 One of the schematic diagrams of edge construction of the second wiring pattern provided in the embodiment of the present application;
[0034] Fig.14 A second schematic diagram of edge construction of the second wiring pattern provided in an embodiment of the present application;
[0035] Fig.15 The third schematic diagram of the edge construction of the second wiring pattern provided in the embodiment of the present application;
[0036] Fig.16 A schematic diagram of the structure of a third wiring pattern provided in an embodiment of the present application;
[0037] Fig.17 A schematic diagram of the structure of the fourth side relationship provided in the embodiment of the present application;
[0038] Fig.18 A schematic diagram of the structure of the target wiring pattern provided in an embodiment of the present application;
[0039] Fig.19 A schematic diagram of the structure of an automatic wiring device for a flip chip provided in an embodiment of the present application;
[0040] Fig. 20 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.
[0042] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0043] In addition, the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0044] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.
[0045] FIG1(a) is a schematic diagram of a flip chip, and FIG1(b) is a schematic diagram of a flip-chip package. As shown in FIG1(b), the flip-chip packaging technology achieves more I / O connection areas while ensuring high performance and signal integrity by flipping the flip chip and directly mounting it on a package carrier or printed circuit board. Before flip-chip packaging, the flip chip needs to be wired.
[0046] Routing is generally divided into two steps: global routing and detailed routing. The role of global routing is to provide a rough path for each network, solve the overall layout and congestion problems, and optimize the line length and resource allocation; detailed routing is to accurately locate the wires based on global routing to ensure that the wires meet the design rules. The input data of global routing is the wiring pattern built based on the flip chip, and the existing method relies on staff to build the wiring pattern, which has the following problems:
[0047] 1. When the number of nodes in the bump pad layer or wire bonding pad layer changes, the composition needs to be replanned.
[0048] 2. Manual graph construction is inefficient and error-prone.
[0049] 3. The composition results depend on personal habits, which will cause inconsistency in the overall wiring and high maintenance costs.
[0050] Therefore, an embodiment of the present application provides an automatic wiring method for a flip chip, which can solve the above-mentioned problem. The method can be generated by any electronic device with computing and processing capabilities, and the electronic device can be, for example, a terminal-oriented computer device or a back-end server.
[0051] The following is a specific example description of the automatic wiring method of the flip chip provided by the present application through multiple examples in combination with the accompanying drawings.
[0052] Figure 2 One of the flow charts of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Figure 2 As shown, the method includes:
[0053] S101, obtaining a pad layout diagram of a flip chip.
[0054] The wire bonding pad information of the flip chip includes position information (expressed in the form of coordinates) of multiple nodes on the wire bonding pad, and the bump pad information includes position information (expressed in the form of coordinates) of multiple nodes on the bump pad.
[0055] The wire bonding pad information and the bump pad information are stored in a preset database. When executing the method of this embodiment, the wire bonding pad information and the bump pad information of the flip chip can be obtained from the preset database, and then the pad layout diagram of the flip chip can be generated according to the wire bonding pad information and the bump pad information. Figure 3 shown.
[0056] Reference Figure 3 The pad layout diagram has multiple pad nodes, and the multiple pad nodes correspond to multiple pads on the actual flip chip respectively. For example, the pad layout diagram includes wire bonding pad nodes and bump pad nodes, wherein the wire bonding pad nodes correspond to nodes on the wire bonding pad layer of the flip chip, the bump pad nodes correspond to nodes on the bump pad layer of the flip chip, and the bump pad nodes are surrounded by the wire bonding pad nodes.
[0057] S102 : Generate an initial node pattern of the flip chip according to information of the plurality of pad nodes.
[0058] Based on the pad layout diagram, an initial node composition of the flip chip is further generated. The initial node composition has multiple pad nodes and virtual nodes, that is, compared with the pad layout diagram, the initial node composition has additional virtual nodes.
[0059] The role of the virtual node is to facilitate the construction of edges for each node in the initial node composition, and the virtual node is located between different pad nodes.
[0060] S103 , performing an edge building operation on each node in the initial node graph to obtain a target wiring graph, so that the target wiring graph has edge relationships between nodes.
[0061] By performing edge building operations on each node in the initial node graph, a target wiring graph can be obtained, so that the target wiring graph has edge relationships between nodes.
[0062] The edge relationship between the nodes is used to characterize the wiring path of the corresponding position of the node, that is, the flip chip can be wired according to the edge relationship between the nodes, so that each node of the flip chip can be electrically connected on the wired line.
[0063] S104 , automatically routing the flip chip according to the target routing pattern to obtain a packaging structure of the flip chip.
[0064] After the target wiring pattern is obtained, the flip chip is automatically wired according to the target wiring pattern, so that the packaging of the flip chip can be completed and the packaging structure of the flip chip can be obtained.
[0065] In summary, the embodiment of the present application provides an automatic wiring method for a flip chip, which can generate an initial node composition of the flip chip based on the information of multiple pad nodes on the pad layout diagram of the flip chip, and then perform edge building operations on each node in the initial node composition to automatically generate a target wiring composition of the flip chip, thereby saving manpower and material resources and improving the efficiency of generating the target wiring composition.
[0066] Figure 4 The second flow chart of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Figure 4 As shown, the step S102 generates an initial node pattern of the flip chip according to the information of the plurality of pad nodes, including:
[0067] S201, sectorizing the pad layout diagram to obtain a plurality of sectors.
[0068] like Figure 5 As shown, the pad layout diagram is divided to obtain multiple sectors, and then subsequent operations are performed on the multiple sectors respectively. The subsequent operations may be, for example, automatic generation of wiring patterns based on a network flow algorithm.
[0069] The purpose of dividing into multiple sectors is that when subsequent operations are performed according to the pad layout diagram to construct the wiring composition, if the network flow algorithm is wrong, the execution of the network flow algorithm can be stopped at the first sector, thereby discovering the problem faster and reducing the trial and error cost.
[0070] It should also be noted that Figure 5 The example of four identical sectors does not limit the number of sectors. In fact, the number of sectors can be determined according to actual needs.
[0071] S202: Generate an initial node composition corresponding to each sector according to information of each pad node in each sector.
[0072] Specifically, according to the information of each pad node in each sector, a first virtual node can be created between two adjacent pad nodes on the same pad layer, and a second virtual node can be created between every two adjacent pad nodes between different pad layers. The pad nodes are regarded as the four vertices of a rectangle, and the second virtual node is located at the center of this matrix, so as to obtain the initial node composition corresponding to each sector.
[0073] Figure 6 A schematic diagram of a virtual node provided in an embodiment of the present application, such as Figure 6As shown, for example, a first virtual node can be created between every two adjacent wire bonding pad nodes on the wire bonding pad layer, a first virtual node can also be created between every two adjacent bump pad nodes on the bump pad layer, a second virtual node can be created between the nodes of two adjacent wire bonding pad layers, and a second virtual node can also be created between the nodes of two adjacent bump pad layers.
[0074] The first virtual node is named as an intermediate node (Intermediate Node), and the second virtual node is named as a tile node (Tile Node).
[0075] It should be noted that Figure 6 Not all nodes on the initial node composition are shown, but only a part of the nodes are used as an exemplary illustration. It can be understood that after adding the first virtual node and the second virtual node correspondingly between the nodes on the pad layout diagram according to the above rules, the initial node composition can be obtained. That is, the actual initial node composition includes Figure 3 All nodes on the pad layout diagram shown, and the first virtual node and the second virtual node at the corresponding position.
[0076] Then, performing an edge building operation on each node in the initial node graph to obtain a target wiring graph in S103 may include: S203, performing an edge building operation on each node in the initial node graph corresponding to each sector to obtain a target wiring graph corresponding to each sector.
[0077] The automatic wiring of the flip chip according to the target wiring pattern in S104 to obtain the packaging structure of the flip chip may include: S204, automatically wiring the multiple sectors of the flip chip according to the target wiring pattern corresponding to the multiple sectors to obtain the packaging structure of the flip chip.
[0078] exist Figure 6 On the basis of Figure 7 The third flow chart of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Figure 7 As shown, the step of performing edge building operation on each node in the initial node graph corresponding to each sector to obtain the target wiring graph corresponding to each sector in S203 may include:
[0079] S301, performing an edge building operation on a wire bonding pad node and a first virtual node of a bump pad layer to obtain a first wiring pattern corresponding to each sector, so that the first wiring pattern has a first edge relationship.
[0080] Among them, the first edge relationship is used to characterize the wiring path between the wire bonding pad node and the corresponding position of the first virtual node of the bump pad layer. According to the first edge relationship, the wire bonding pad node of the flip chip and the corresponding position of the first virtual node of the bump pad layer can be wired.
[0081] S302, performing an edge building operation on the wire bonding pad nodes and the bump pad nodes on the first wiring pattern to obtain a second wiring pattern corresponding to each sector, so that the second wiring pattern has a second edge relationship between the wire bonding pad nodes and the bump pad nodes.
[0082] The second edge relationship is used to characterize the wiring path between the corresponding positions of the wire bonding pad nodes and the bump pad nodes. The corresponding positions of the wire bonding pad nodes and the bump pad nodes of the flip chip can be wired according to the second edge relationship.
[0083] S303. Perform edge building operations on the first virtual node of the lead-built pad layer and all nodes on the bump pad layer on the second wiring pattern to obtain a third wiring pattern corresponding to each sector, so that the third wiring pattern has a third edge relationship between the first virtual node of the lead-built pad layer and all nodes on the bump pad layer.
[0084] The third edge relationship is used to characterize the wiring path between the first virtual node of the wire bonding pad layer and the corresponding positions of all nodes on the bump pad layer. According to the third edge relationship, the first virtual node of the wire bonding pad layer of the flip chip and the corresponding positions of all nodes on the bump pad layer can be wired.
[0085] S304, performing an edge building operation on adjacent pad layers in the third wiring pattern according to the second virtual nodes between adjacent pad layers of the same type to obtain a target wiring pattern corresponding to each sector, so that the target wiring pattern also has a fourth edge relationship.
[0086] Among them, the fourth edge relationship is used to characterize the pad nodes of adjacent pad layers and the wiring paths of the corresponding positions of the first virtual node and the second virtual node. According to the fourth edge relationship, the pad nodes of the adjacent pad layers of the flip chip and the corresponding positions of the second virtual node can be wired.
[0087] Figure 8 The fourth flow chart of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Figure 8 As shown, the step of performing an edge building operation on the wire bonding pad node and the first virtual node of the bump pad layer in step S301 to obtain a first wiring pattern corresponding to each sector may include:
[0088] S401. Perform edge building operations on all first virtual nodes of all wire bonding pad nodes and bump pad layers to obtain an initial wiring composition, so that the initial wiring composition has multiple first edge relationships, each first edge relationship has a corresponding wiring cost parameter and a wiring capacity parameter, and the nodes connected by the first edge relationships have demand parameters.
[0089] The edge building operation is performed on all the first virtual nodes of all the wire bonding pad nodes and the bump pad layer, and the initial wiring pattern obtained is as follows: Fig. 9 As shown, the wiring cost parameter of the first edge relationship represents the actual length of the first edge relationship, the demand parameter of the wire bonding pad node connected to the first edge relationship is always -1, indicating that the maximum number of wirings sent out of the node is 1, and the first virtual node demand parameter of the bump pad layer connected to the first edge relationship is given by a preset parameter, which is a positive value, indicating the maximum number of wirings received by the node.
[0090] It should be noted that Fig. 9 Not all nodes on the initial wiring pattern are shown, but only a part of the nodes are shown as examples.
[0091] S402, according to the demand parameters of each node in the initial wiring composition, and the wiring cost parameters and wiring capacity parameters of multiple first edge relationships, a preset minimum wiring cost flow algorithm is used to delete the first edge relationship with a wiring capacity parameter of 0 in the initial wiring composition to obtain a first wiring composition corresponding to each sector.
[0092] This step converts the edge building problem into a minimum wiring cost flow problem. Specifically, given a directed graph G (not shown in the attached figure) containing a wiring cost parameter (Cost) and a wiring capacity parameter (Capacity), each node has a demand parameter (demand), indicating that the node wants to send in or send out a certain amount of wiring. If the demand parameter is a negative value, it indicates the number of wirings that the node needs to send out. If the demand parameter is a positive value, it indicates the number of wirings that the node needs to be sent in. If the net flow of each node matches its demand, the flow on the graph G meets the needs of all nodes, and the first wiring pattern corresponding to each sector is obtained.
[0093] Specifically, the present application also provides a specific implementation method for setting demand parameters. Fig.10 The fifth flow chart of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Fig.10 As shown, the required parameters may be pre-set before S402, including:
[0094] S501, setting the required parameter of each wire bonding pad node in the initial wiring composition to -1.
[0095] The demand parameter of the wire bonding pad node is -1, which means that the number of wires sent out by each wire bonding pad node is 1.
[0096] S502, setting the required parameters of each first virtual node of the bump pad layer in the initial wiring pattern to a preset value.
[0097] According to actual wiring requirements, the requirement parameters of each first virtual node of the bump pad layer in the initial wiring pattern are set to preset values, and the preset values are used to indicate the number of wirings received by each first virtual node of the bump pad layer.
[0098] In practical applications, evenly allocating wire bonding pads to the first virtual nodes of the bump pad layer can meet the wiring requirements in most scenarios, but it can also be adjusted according to special scenarios.
[0099] For example, taking the case that there are three first virtual nodes in the bump pad layer, the demand parameters of the three first virtual nodes are set to [2, 1, 2], indicating that the maximum receiving traffic of the three first virtual nodes in the bump pad layer is [2, 1, 2] respectively. The demand parameters are only used to determine the number of incoming or outgoing edges of the node, and the specific edge relationship between the nodes is automatically given by the network flow algorithm.
[0100] S503, setting the demand parameters of the remaining nodes in the initial wiring diagram to 0.
[0101] Except for each wire bonding pad node and each first virtual node of the bump pad layer, the requirement parameters of the remaining nodes in the initial wiring diagram are set to 0, and then step S402 is executed to delete the initial wiring pattern ( Fig. 9 ) in which the wiring capacity parameter is 0, the first wiring pattern corresponding to each sector is obtained, such as Fig.11 shown.
[0102] It should be noted that Fig.11 Not all nodes on the first wiring pattern are shown, but only a part of the nodes are used as examples. By adjusting the required parameters of each first virtual node of the bump pad layer in the initial wiring pattern, the wiring density of the local area corresponding to each first virtual node of the bump pad layer can also be flexibly controlled.
[0103] Fig.12 The sixth flow chart of the automatic wiring method of the flip chip provided in the embodiment of the present application is as follows: Fig.12 As shown, the step S302 of performing an edge building operation on the wire bonding pad nodes and the bump pad nodes on the first wiring pattern to obtain a second wiring pattern corresponding to each sector may include:
[0104] S601, dividing the adjacent wire bonding pad layer and bump pad layer on the first wiring pattern into a first part and a second part, respectively corresponding to the first side and the second side.
[0105] like Fig.13 As shown, based on the first wiring pattern, the adjacent wire bonding pad layer and bump pad layer on the first wiring pattern are approximately evenly divided into a first part and a second part, corresponding to the first side and the second side respectively.
[0106] S602: Perform an edge building operation on each wire bonding pad node in the first part and a bump pad node corresponding to the first virtual node close to the first side.
[0107] Then, since there is already a first edge relationship between each wire bonding pad node of the wire bonding pad layer and each first virtual node of the bump pad layer, in the first part, an edge building operation is performed between each wire bonding pad node and the bump pad node close to the first side of the corresponding first virtual node, such as Fig.14 It should be noted that the established edge relationship does not overlap or intersect with other edge relationships.
[0108] S603 , performing an edge building operation on each wire bonding pad node in the second part and a bump pad node corresponding to the first virtual node close to the second side, to obtain a second wiring pattern corresponding to each sector.
[0109] In the second part, each wire bonding pad node and the bump pad node corresponding to the first virtual node close to the second side are subjected to an edge building operation, such as Fig.15 As shown in the figure, the established edge relationship does not overlap or intersect with other edge relationships.
[0110] In this embodiment, the adjacent wire bonding pad layer and bump pad layer on the first wiring composition are divided into a first part and a second part, so that the second side relationship in the second wiring composition can be made more symmetrical, the circuit board welding is simpler, and the signal anomalies caused by messy wiring are avoided, so that the performance of the flip chip obtained after the final wiring is more stable.
[0111] It should be noted that steps S602 and S603 are not used to limit the order of building edges between the first part and the second part. In actual operation, S602 can be executed first to build an edge on the first part, or S603 can be executed first to build an edge on the second part. S602 and S603 can also be executed at the same time to build an edge on the first part and the second part at the same time.
[0112] exist Fig.15On the basis of, without crossing the existing edge relationship, all the first virtual nodes of the lead pad layer on the second wiring pattern and all the nodes on the bump pad layer are maximized to obtain the following: Fig.16 The third wiring pattern corresponding to each sector is shown. The third edge relationship is used to characterize the wiring path between the first virtual node of the wire bonding pad layer and the corresponding positions of all nodes on the bump pad layer.
[0113] Optionally, the step of performing an edge building operation on adjacent pad layers in the third wiring pattern according to the second virtual nodes between adjacent pad layers to obtain a target wiring pattern corresponding to each sector, so that the target wiring pattern also has a fourth edge relationship, may include: on the basis of the third wiring pattern ( Fig.16 Only a part of the third wiring pattern is shown, not all of the third wiring pattern. The adjacent pad layers of the same type in the third wiring pattern are edge-built to obtain the target wiring pattern corresponding to each sector, such as Fig.17 As shown, the target wiring pattern also has a fourth side relationship.
[0114] Specifically, as mentioned above, the required parameter value is used to control the number of node outgoing and incoming edges. Due to the high symmetry of the patterning of adjacent wire bonding pad layers and adjacent bump pad layers, given a flip chip, the required parameter is determined, such as Fig.17 As shown, the required parameters of each layer node are fixed values according to its location, so the final composition result can be directly obtained.
[0115] Fig.17 is only part of the target wiring pattern, and Fig.17 Only the adjacent wire bonding pad layer is shown, and the adjacent bump pad layer is not shown. The composition principle of the adjacent bump pad layer is the same as Fig.17 Similarly, we construct edge relationships for all nodes in the flip chip, and finally obtain the complete target wiring graph, such as Fig.18 shown.
[0116] In summary, the present application provides an automatic wiring method for a flip chip, which has the following advantages:
[0117] 1. Automatically generate the target wiring pattern of the flip chip, saving manpower and material resources, and improving the efficiency of generating the target wiring pattern.
[0118] 2. It can effectively avoid the problems caused by manual edge building, such as low efficiency, high error rate, and poor adaptability.
[0119] 3. By adjusting the required parameters of each first virtual node of the bump pad layer in the initial wiring pattern, the wiring density of the local area corresponding to each first virtual node of the bump pad layer can also be flexibly controlled.
[0120] 4. The adjacent wire bonding pad layer and bump pad layer on the first wiring pattern are divided into a first part and a second part, so that the wiring is more symmetrical, which makes the circuit board welding simpler and avoids signal anomalies caused by messy wiring. Finally, the flip chip performance obtained after wiring is more stable.
[0121] The following is a corresponding explanation of the device, equipment and storage medium for executing the automatic wiring method of the flip chip provided by any of the above embodiments of the present application. Its specific implementation process and the technical effects produced are the same as those of the corresponding method embodiments mentioned above. For the sake of brief description, for the parts not mentioned in the following embodiments, reference can be made to the corresponding contents in the method embodiments.
[0122] like Fig.19 As shown, the present application also provides an automatic wiring device for a flip chip, comprising:
[0123] The acquisition module 10 is used to acquire a pad layout diagram of the flip chip, wherein the pad layout diagram has a plurality of pad nodes, and the plurality of pad nodes respectively correspond to a plurality of pads on the flip chip.
[0124] The generating module 20 is used to generate an initial node pattern of the flip chip according to information of a plurality of pad nodes. The initial node pattern has a plurality of pad nodes and virtual nodes, and the virtual nodes are virtual nodes between different pad nodes.
[0125] The edge building module 30 is used to perform edge building operations on each node in the initial node graph to obtain a target wiring graph, so that the target wiring graph has edge relationships between nodes, and the edge relationships between nodes are used to represent wiring paths at corresponding positions of the nodes.
[0126] The wiring module 40 is used to automatically wire the flip chip according to the target wiring pattern to obtain the packaging structure of the flip chip.
[0127] Optionally, the generating module 20 is used to divide the pad layout diagram into sectors to obtain a plurality of sectors; and generate an initial node composition corresponding to each sector according to information of each pad node in each sector.
[0128] The edge building module 30 is used to perform edge building operations on each node in the initial node graph corresponding to each sector to obtain a target wiring graph corresponding to each sector.
[0129] The wiring module 40 is used to automatically wire the multiple sectors of the flip chip according to the target wiring patterns corresponding to the multiple sectors, so as to obtain the packaging structure of the flip chip.
[0130] Optionally, the generation module 20 is used to create a first virtual node between two adjacent pad nodes on the same pad layer and a second virtual node between every two adjacent pad nodes on different pad layers based on the information of each pad node in each sector, so as to obtain an initial node composition corresponding to each sector.
[0131] Optionally, the initial node composition corresponding to each sector includes: a wire bonding pad node in the wire bonding pad layer, a first virtual node in the wire bonding pad layer, a bump pad node in the bump pad layer, a first virtual node in the bump pad layer, and a second virtual node between adjacent pad layers of the same type.
[0132] The edge building module 30 is used to perform an edge building operation on the first virtual node of the wire bonding pad layer and the bump pad layer to obtain a first wiring pattern corresponding to each sector, so that the first wiring pattern has a first edge relationship, and the first edge relationship is used to characterize the wiring path between the wire bonding pad node and the first virtual node corresponding to the bump pad layer; perform an edge building operation on the wire bonding pad node and the bump pad node on the first wiring pattern to obtain a second wiring pattern corresponding to each sector, so that the second wiring pattern has a second edge relationship between the wire bonding pad node and the bump pad node, and the second edge relationship is used to characterize the wiring path between the wire bonding pad node and the first virtual node corresponding to the bump pad node; perform an edge building operation on the wire bonding pad node and the bump pad node on the second wiring pattern to obtain a second wiring pattern corresponding to each sector, so that the second wiring pattern has a second edge relationship between the wire bonding pad node and the bump pad node, and the second edge relationship is used to characterize the wiring path between the wire bonding pad node and the first virtual node corresponding to the bump pad node An edge building operation is performed on the virtual nodes and all the nodes on the bump pad layer to obtain a third wiring pattern corresponding to each sector, so that the third wiring pattern has a third edge relationship between the first virtual node of the wire bonding pad layer and all the nodes on the bump pad layer, and the third edge relationship is used to characterize the wiring path between the first virtual node of the wire bonding pad layer and the corresponding positions of all the nodes on the bump pad layer; according to the second virtual nodes between adjacent pad layers of the same type, an edge building operation is performed on adjacent pad layers in the third wiring pattern to obtain a target wiring pattern corresponding to each sector, so that the target wiring pattern also has a fourth edge relationship, and the fourth edge relationship is used to characterize the pad nodes of adjacent pad layers and the wiring path of the corresponding positions of the first virtual node and the second virtual node.
[0133] Optionally, the edge building module 30 is used to perform edge building operations on all first virtual nodes of all wire bonding pad nodes and bump pad layers to obtain an initial wiring composition, so that the initial wiring composition has multiple first edge relationships, each first edge relationship has a corresponding wiring cost parameter and a wiring capacity parameter, and the nodes connected by the first edge relationship have demand parameters; according to the demand parameters of each node in the initial wiring composition, and the wiring cost parameters and wiring capacity parameters of the multiple first edge relationships, a preset minimum wiring cost flow algorithm is used to delete the first edge relationship with a wiring capacity parameter of 0 in the initial wiring composition to obtain the first wiring composition corresponding to each sector.
[0134] Optionally, the edge building module 30 is used to set the demand parameter of each wire bonding pad node in the initial wiring composition to -1, which is used to indicate that the number of outgoing wirings of the wire bonding pad node is 1; set the demand parameter of each first virtual node of the bump pad layer in the initial wiring composition to a preset value, which is used to indicate the number of wirings received by each first virtual node of the bump pad layer; and set the demand parameters of the remaining nodes in the initial wiring diagram to 0.
[0135] Optionally, the edge building module 30 is used to divide the adjacent wire bonding pad layer and bump pad layer on the first wiring pattern into a first part and a second part, corresponding to the first side and the second side respectively; perform an edge building operation on each wire bonding pad node in the first part and the bump pad node corresponding to the first virtual node close to the first side; perform an edge building operation on each wire bonding pad node in the second part and the bump pad node corresponding to the first virtual node close to the second side, to obtain a second wiring pattern corresponding to each sector.
[0136] Optionally, the edge building module 30 is used to maximize the edge building operation on all first virtual nodes of the lead pad layer and all nodes on the bump pad layer on the second wiring pattern without crossing the existing edge relationship, so as to obtain a third wiring pattern corresponding to each sector.
[0137] The above-mentioned device is used to execute the method provided by the aforementioned embodiment, and its implementation principle and technical effect are similar, which will not be repeated here.
[0138] The above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), or one or more microprocessors, or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented in the form of a processing element scheduling program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).
[0139] Fig. 20 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application, such as Fig. 20 As shown, the present application also provides an electronic device, including: a processor 100, a storage medium 200 and a bus 300, the storage medium stores program instructions executable by the processor, when the electronic device is running, the processor and the storage medium communicate through the bus, and the processor executes the program instructions to implement the automatic wiring method of the flip chip of the above embodiment.
[0140] The embodiment of the present application further provides a readable storage medium, on which program instructions are stored. When the program instructions are executed by a processor, the automatic wiring method of the flip chip of the above embodiment is implemented.
[0141] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0142] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0143] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.
[0144] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor (English: processor) to perform some steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English: Read-Only Memory, abbreviated: ROM), random access memory (English: Random Access Memory, abbreviated: RAM), disk or optical disk and other media that can store program codes.
[0145] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A flip chip automatic wiring method, characterized in that: include: Obtaining a pad layout diagram of a flip chip, wherein the pad layout diagram has a plurality of pad nodes, and the plurality of pad nodes respectively correspond to a plurality of pads on the flip chip; Generate an initial node pattern of the flip chip according to the information of the plurality of pad nodes, wherein the initial node pattern has the plurality of pad nodes and virtual nodes, and the virtual nodes are virtual nodes between different pad nodes; Performing an edge building operation on each node in the initial node graph to obtain a target wiring graph, so that the target wiring graph has an edge relationship between nodes, and the edge relationship between nodes is used to represent a wiring path at a corresponding position of the node; The flip chip is automatically wired according to the target wiring pattern to obtain a packaging structure of the flip chip.
2. The method according to claim 1, characterized in that: The step of generating an initial node pattern of the flip chip according to the information of the plurality of pad nodes comprises: Dividing the pad layout diagram into sectors to obtain a plurality of sectors; Generate an initial node composition corresponding to each sector according to information of each pad node in each sector; The step of performing an edge building operation on each node in the initial node graph to obtain a target wiring graph includes: Performing edge building operation on each node in the initial node graph corresponding to each sector to obtain the target wiring graph corresponding to each sector; The method of automatically wiring the flip chip according to the target wiring pattern to obtain a packaging structure of the flip chip includes: According to the target wiring patterns corresponding to the multiple sectors, the multiple sectors of the flip chip are automatically wired respectively to obtain the packaging structure of the flip chip.
3. The method according to claim 2, characterized in that The step of generating an initial node pattern corresponding to each sector according to information of each pad node in each sector includes: According to the information of each pad node in each sector, a first virtual node is created between two adjacent pad nodes on the same pad layer, and a second virtual node is created between every two adjacent pad nodes between different pad layers to obtain the initial node composition corresponding to each sector.
4. The method according to claim 2, characterized in that The initial node pattern corresponding to each sector includes: a wire bonding pad node in a wire bonding pad layer, a first virtual node in the wire bonding pad layer, a bump pad node in a bump pad layer, a first virtual node in the bump pad layer, and a second virtual node between adjacent pad layers of the same type; The performing edge building operation on each node in the initial node graph corresponding to each sector to obtain the target wiring graph corresponding to each sector includes: Performing an edge building operation on the wire bonding pad node and the first virtual node of the bump pad layer to obtain a first wiring pattern corresponding to each sector, so that the first wiring pattern has a first edge relationship, and the first edge relationship is used to characterize a wiring path between the wire bonding pad node and the corresponding position of the first virtual node of the bump pad layer; Performing an edge building operation on the wire bonding pad node and the bump pad node on the first wiring pattern to obtain a second wiring pattern corresponding to each sector, so that the second wiring pattern has a second edge relationship between the wire bonding pad node and the bump pad node, and the second edge relationship is used to characterize a wiring path between corresponding positions of the wire bonding pad node and the bump pad node; Performing an edge building operation on the first virtual node of the wire bonding pad layer and all nodes on the bump pad layer on the second wiring pattern to obtain a third wiring pattern corresponding to each sector, so that the third wiring pattern has a third edge relationship between the first virtual node of the wire bonding pad layer and all nodes on the bump pad layer, and the third edge relationship is used to characterize a wiring path between the first virtual node of the wire bonding pad layer and corresponding positions of all nodes on the bump pad layer; According to the second virtual node between adjacent pad layers of the same type, an edge building operation is performed on the adjacent pad layers in the third wiring composition to obtain the target wiring composition corresponding to each sector, so that the target wiring composition also has a fourth edge relationship, and the fourth edge relationship is used to characterize the pad nodes of the adjacent pad layers and the wiring paths corresponding to the first virtual nodes and the second virtual nodes.
5. The method according to claim 4, characterized in that The step of performing an edge building operation on the wire bonding pad node and the first virtual node of the bump pad layer to obtain a first wiring pattern corresponding to each sector includes: Performing edge building operations on all the wire bonding pad nodes and all the first virtual nodes of the bump pad layer to obtain an initial wiring pattern, so that the initial wiring pattern has a plurality of first edge relationships, each first edge relationship has a corresponding wiring cost parameter and a wiring capacity parameter, and the nodes connected by the first edge relationships have demand parameters; According to the demand parameters of each node in the initial wiring composition, and the wiring cost parameters and wiring capacity parameters of the multiple first edge relationships, a preset minimum wiring cost flow algorithm is used to delete the first edge relationship with a wiring capacity parameter of 0 in the initial wiring composition to obtain the first wiring composition corresponding to each sector.
6. The method according to claim 5, characterized in that Before obtaining the first wiring pattern corresponding to each sector, the method further comprises: Setting the required parameter of each wire bonding pad node in the initial wiring pattern to -1, which is used to indicate that the number of outgoing wirings of the wire bonding pad node is 1; Setting the demand parameter of each first virtual node of the bump pad layer in the initial wiring pattern to a preset value, which is used to indicate the number of wirings received by each first virtual node of the bump pad layer; Set the required parameters of the remaining nodes in the initial wiring diagram to 0.
7. The method according to claim 4, characterized in that The step of performing an edge building operation on the wire bonding pad nodes and the bump pad nodes on the first wiring pattern to obtain the second wiring pattern corresponding to each sector includes: Dividing the adjacent wire bonding pad layer and bump pad layer on the first wiring pattern into a first part and a second part, respectively corresponding to the first side and the second side; Performing an edge building operation on each wire bonding pad node of the first part and a bump pad node corresponding to the first virtual node close to the first side; An edge building operation is performed on each wire bonding pad node of the second part and a bump pad node corresponding to the first virtual node close to the second side to obtain a second wiring pattern corresponding to each sector.
8. The method according to claim 4, characterized in that The step of performing an edge construction operation on the first virtual node of the lead-built pad layer on the second wiring pattern and all nodes on the bump pad layer to obtain a third wiring pattern corresponding to each sector includes: Under the premise of not intersecting with the existing edge relationship, a maximum edge construction operation is performed on all first virtual nodes of the lead construction pad layer on the second wiring pattern and all nodes on the bump pad layer to obtain a third wiring pattern corresponding to each sector.
9. An electronic device, characterized in that: include: A processor, a storage medium and a bus, wherein the storage medium stores program instructions executable by the processor, and when the electronic device is running, the processor and the storage medium communicate via the bus, and the processor executes the program instructions to implement the automatic wiring method of the flip chip as described in any one of claims 1 to 8.
10. A readable storage medium, characterized in that: The readable storage medium stores program instructions, and when the program instructions are executed by a processor, the automatic wiring method for flip chips according to any one of claims 1 to 8 is implemented.