Method and device for quickly repairing set-up time violation in static time sequence analysis

Abstract

The invention relates to the technical field of integrated circuit design and verification, and discloses a quick repair method and device for establishing time violation in static time sequence analysis. The method comprises the following steps: acquiring a static time sequence analysis report; extracting a target time sequence path according to the static time sequence analysis report; calculating multiple types of redundancy values of each module passed by the target time sequence path; calculating a redundancy value set of a data path of the target time sequence path and a redundancy value subset corresponding to each module according to the redundancy value of each module corresponding to the target time sequence path; determining a repair sequence of each module according to the redundancy value of each module corresponding to the target time sequence path; according to the redundancy value set and the redundancy value subset of each module, analyzing each module in sequence, and determining a repair scheme of each module; and obtaining a repair strategy of the target time sequence path according to the repair scheme of each module passed by the target time sequence path. The invention provides an efficient solution for establishing the early stage of time repair.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design and verification, and in particular to a method and device for quickly repairing a time violation in static timing analysis. Background Art

[0002] With the continuous application of large-scale and ultra-large-scale integrated circuits, the process size has been continuously reduced, and the mainstream process has reached the nanometer level, which makes the design of integrated circuit chips face higher challenges. In the chip design process, establishing good timing convergence is crucial to the performance and stability of the chip. However, timing violations may occur due to unreasonable standard unit selection, unreasonable layout and routing, inadequate logic optimization, and algorithm deviations between different tools. Setup time violation is a specific type of timing violation, which may cause data sampling errors or circuit performance degradation.

[0003] Existing setup time repair tools can provide relatively accurate solutions in promoting designs close to timing convergence to accelerate final timing compliance. However, the repair capabilities of these tools are mainly limited to adjustments at the standard cell level, such as adjusting the threshold voltage of standard cells, changing their size, inserting or deleting buffers, and performing high fan-out decomposition. For deeper layout and routing related issues, such as lengthy logic levels, long paths, unreasonable standard cell layout, crosstalk interference between interconnects, and clock tree skew, these tools cannot provide effective risk warnings or direct repair strategies. Therefore, existing setup time repair tools are more suitable for the later stages of timing convergence rather than the early stages.

[0004] The solution to the above layout and routing defects still depends on the experience of engineers. Due to the different qualifications of engineers, the solutions provided are sometimes not the most efficient and economical. As the scale of design increases sharply, the cycle of manually providing repair solutions is getting longer and longer, which greatly increases the R&D time of the project. Summary of the invention

[0005] In view of this, the present invention provides a method and device for quickly repairing setup time violations in static timing analysis, which can effectively identify and solve setup time violation problems in the early stage of timing convergence, reduce the need for human intervention, and significantly reduce the risk of human error.

[0006] In a first aspect, the present invention provides a method for quickly repairing setup time violations in static timing analysis, comprising: obtaining a static timing analysis report; extracting a target timing path according to the static timing analysis report, the target timing path having a setup time violation, and a target timing path passing through at least one module; calculating multiple types of redundant values ​​of each module passed by the target timing path; calculating a redundant value set of a data path of the target timing path and a redundant value subset corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path; determining a repair order of each module according to the redundant values ​​of each module corresponding to the target timing path; analyzing each module in turn according to the repair order of the modules according to the redundant value set and the redundant value subset of each module to determine a repair plan for each module; obtaining a repair strategy for the target timing path according to the repair plan of each module passed by the target timing path.

[0007] The embodiment of the present invention provides a rapid repair method for setup time violations in static timing analysis. The method obtains a static timing analysis report, identifies a target timing path with a setup time violation, calculates redundancy values ​​for each module passed by the target timing path, quantifies the degree of influence of each module in the timing path, determines a repair order by calculating the redundancy value of each module based on a redundancy value set and a redundancy value subset of each module, prevents the occurrence of setup time violations in the early stage of timing convergence, forms a systematic repair process, analyzes and repairs each module in turn according to the repair order, formulates a globally optimal repair strategy by comprehensively considering the redundancy value and repair scheme of each module, and reduces the need for manual intervention in the automated calculation and repair process.

[0008] In an optional embodiment, after the step of calculating the redundant value set of the data path of the target timing path and the redundant value subsets corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path, and before the step of determining the repair order of each module according to the redundant values ​​of each module corresponding to the target timing path, it includes: calculating the clock tree skew value of the target timing path; determining the redundant value sum of the target timing path according to the sum of each element in the redundant value set of the data path of the target timing path; if the redundant value sum is greater than or equal to the first preset violation value, executing the step of determining the repair order of each module according to the redundant value of each module corresponding to the target timing path; if the redundant value sum is less than the first preset violation value, and the sum of the redundant value sum and the preset multiple of the clock tree skew value is greater than the first preset violation value, determining the repair strategy of the target timing path according to the engineering operations corresponding to each element in the redundant value set of the target timing path and the repair strategy of the clock tree skew value; if the redundant value sum is less than the first preset violation value, and the sum of the redundant value sum and the preset multiple of the clock tree skew value is less than the first preset violation value, sending the target timing path to the target user.

[0009] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis. By calculating the clock tree skew value of the target timing path, the delay difference of the clock signal on the path can be understood. The clock tree skew is one of the key factors affecting timing convergence. Therefore, accurately evaluating the skew value helps to discover and solve potential problems in the design stage. By calculating the redundancy value and of the target timing path, the additional resources that can be used for repair or optimization on the path can be evaluated, which helps to determine whether it is possible to solve the timing problem by adjusting the redundant resources without more complex redesign or adding additional hardware resources. According to the relationship between the redundancy value and and the clock tree skew value, the process can intelligently select the repair strategy. Omitted. For example, if the redundancy value and is greater than or equal to the first preset violation value, the repair order can be determined according to the redundancy value of each module, and the modules with the most redundant resources are given priority to improve the repair efficiency and success rate. If the redundant resources are insufficient but close to the first preset violation value, and considering the impact of the clock tree skew, the engineering operations corresponding to the redundant values ​​and the repair strategy of the clock tree skew can be comprehensively considered to formulate a comprehensive repair plan. If the redundant resources are seriously insufficient, even the repair strategy of the clock tree skew cannot meet the requirements. The process will promptly send the target timing path information to the target user, which will help the user to promptly understand the problems in the design and take further measures to solve these problems.

[0010] In an optional implementation, the clock tree skew value of the target timing path is calculated, including: determining a first delay according to the sum of the delays of each standard cell along the clock path and the delays of each interconnection line; determining a second delay according to the sum of the delays of each standard cell along the clock path and the delays of each interconnection line; if the clock is a non-ideal clock, and the first delay is greater than the second delay, determining the clock tree skew value of the target timing path according to the difference between the first delay and the second delay; if the clock is an ideal clock, or if the clock is a non-ideal clock, and the first delay is less than or equal to the second delay, determining the clock tree skew value of the target timing path to be 0.

[0011] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis. By considering the delay difference between the transmitting edge and the receiving edge of the clock path, as well as the ideal and non-ideal states of the clock, the clock tree skew value of the target timing path can be accurately evaluated. When the clock is non-ideal and the delay difference is large, the clock tree skew value can be automatically adjusted to adapt to the actual situation. The skew value is set to handle the situation of ideal clock or favorable delay difference, thereby simplifying the design process.

[0012] In an optional implementation, the redundancy value includes one or more of a logic level redundancy value, a standard cell delay redundancy value, an interconnection line crosstalk delay redundancy value, and a path detour redundancy value.

[0013] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis. By considering the logic level redundancy value and the standard cell delay redundancy value, the circuit can better cope with performance fluctuations caused by external factors such as process changes and temperature changes. By considering the interconnection line crosstalk delay redundancy value and the path detour redundancy value, the signal transmission path and performance can be optimized, signal loss and interference can be reduced, and the signal integrity and stability can be improved.

[0014] In an optional embodiment, the step of calculating the logic level redundancy value of any module in the target timing path includes: extracting the level of standard cells of the data path of the target timing path in the module, and a third delay, the third delay being determined according to the sum of the standard cell delay and the interconnection delay of the data path of the target timing path; determining the typical value of the standard cell delay according to the median of all standard cell delay information sets in the static timing analysis report; determining the typical value of the sum of the delays of the standard cells and the interconnection according to the ratio of the delay of the standard cells to the delay of the interconnection, and the typical value of the standard cell delay; calculating the ideal maximum level of each module according to the typical value of the sum of the delays of the standard cells and the interconnection in the module, and the third delay; if the level of the standard cells is greater than the ideal maximum level, calculating the logic level redundancy value according to the level of the standard cells, the ideal maximum level, the ratio of the delay of the standard cells to the delay of the interconnection, and the third delay; if the level of the standard cells is less than or equal to the ideal maximum level, determining the logic level redundancy value to be 0.

[0015] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis. By calculating the total delay of standard cells and interconnects, and considering the delay ratio and typical value, the delay of the target timing path can be accurately evaluated, the accuracy of timing analysis can be improved, and the timing performance of the circuit can be better understood by calculating the ideal maximum level and logic level redundancy value, and the optimized design can be performed as needed to meet the performance requirements.

[0016] In an optional embodiment, the step of calculating the standard cell delay redundancy value of any module in the target timing path includes: extracting the delay of each standard cell in the module, and calculating the standard cell delay redundancy value according to the delay of each standard cell in the module and the typical value of the standard cell delay; if the calculated standard cell delay redundancy value is greater than the set delay redundancy value, determining the calculated standard cell delay redundancy value as the standard cell delay redundancy value; if the calculated standard cell delay redundancy value is less than or equal to the set delay redundancy value, determining the standard cell delay redundancy value as 0.

[0017] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis. By setting an upper limit of acceptable delay and calculating the delay redundancy value of the standard cell, it is ensured that the delay of each standard cell is within a preset safety limit, thereby improving the stability, reliability and performance of the circuit. For standard cells with larger delay redundancy values, manual optimization design is required.

[0018] In an optional embodiment, the step of calculating the path detour redundancy value of any module in the target timing path includes: extracting the length of the standard cell string of the module, the sum of any adjacent standard cell distances, and a fourth delay, the standard cell string length is the Manhattan distance between the adjacent starting standard cell position and the end standard cell position of the standard cell string of the module, the sum of any adjacent standard cell distances in the standard cell string is the sum of the Manhattan distances of any two adjacent standard cells between the starting standard cell position and the end standard cell position, the fourth delay is the sum of the delays of all standard cells in the standard cell string and the delay of the interconnection line, the standard cell string of the module is a series of continuous standard cells on the data path of the module in the target timing path; if any standard cell string If the sum of the distances between adjacent standard cells is less than the set distance, the path detour redundancy value is determined to be 0; if the sum of the distances between any adjacent standard cells in the standard cell string is greater than or equal to the set distance, and the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is greater than the set ratio, the path detour redundancy value of the standard cell string is calculated based on the sum of the distances between any adjacent standard cells in the standard cell string and the length of the standard cell string; if the sum of the distances between any adjacent standard cells in the standard cell string is greater than the set distance, and the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is less than or equal to the set ratio, the path detour redundancy value of the standard cell string is determined to be 0; the path detour redundancy value of the module is determined based on the sum of the path detour redundancy values ​​of the standard cell strings of each standard cell string in the module.

[0019] The embodiment of the present invention provides a fast repair method for establishing timing violations in static timing analysis. By considering factors such as the length of the standard cell string, the sum of the distances between any adjacent standard cells, and delay, the impact of path detours on circuit timing performance is accurately evaluated, thereby improving the accuracy of timing analysis. For standard cell strings with large path detour redundancy values, manual optimization of layout and routing is required to reduce unnecessary detours.

[0020] In an optional embodiment, a redundant value set of a data path of a target timing path and redundant value subsets corresponding to each module are calculated based on the redundant values ​​of each module corresponding to the target timing path, including: the redundant value subset of the module includes first weighted values ​​corresponding to each type of redundant value of the module, and the second weighted value of the redundant value is obtained by weighting the type of redundant value; the redundant value set of the target timing path includes second weighted values ​​corresponding to each type of redundant value, and the second weighted value of the redundant value is obtained by summing the first weighted values ​​of the type of redundant value in each module.

[0021] The fast repair method for establishing time violations in static timing analysis provided by the embodiment of the present invention accurately evaluates the impact of different types of redundancy values ​​on the overall performance of the target timing path by introducing weighted values.

[0022] In an optional implementation, the repair order of each module is determined according to the redundancy value of each module corresponding to the target timing path, including: establishing redundant value series corresponding to each module according to each type of redundant value of each module, in which one column is used to represent one type of redundant value; performing column operations on the redundant value series corresponding to each module, and adding the column elements to obtain the sum of the elements of each column; weighting the sum of the elements of each column in the redundant value series to obtain an evaluation series of each module; establishing an evaluation matrix of the target timing path according to the evaluation series of each module; processing the evaluation matrix using an entropy weight method to obtain an evaluation score of each module in the target timing path; and determining the repair order of each module according to the evaluation score of each module.

[0023] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis, processes the evaluation matrix through the entropy weight method, objectively determines the weight of each redundant value type, avoids the deviation caused by subjective weighting, improves the objectivity of the evaluation, and determines the repair order according to the evaluation score. It can give priority to processing modules with poor performance or large redundancy values, thereby more effectively improving the performance and stability of the overall circuit.

[0024] In an optional implementation, each module is analyzed in turn according to the repair order of the modules and according to the redundant value set and the redundant value subset of each module to determine the repair scheme of each module, including: traversing the sum of all elements in the redundant value subset of each module in turn according to the repair order of the modules, and comparing the sum of all elements in the redundant value subset with the second preset violation value; if the sum of all elements in the redundant value subset of the current module is greater than the second preset violation value, stopping the traversal, performing a greedy algorithm on the redundant subset of the current module, and determining the elimination amount of each type of redundant value in the current module, so that each type of redundant value is eliminated. The sum of the amounts of eliminated values ​​is greater than the second preset violation value and less than the third preset violation value; each time a module is traversed, the sum of all elements in the redundant value subset of the previous module is subtracted from the current second preset violation value to obtain an updated second preset violation value, and the sum of all elements in the redundant value subset of the previous module is subtracted from the current third preset violation value to obtain an updated third preset violation value; according to the engineering operations corresponding to the amounts of eliminated values ​​of various types of redundant values ​​of the current module and the engineering operations corresponding to all elements in the redundant value subsets of all modules traversed previously, a repair plan for each module is determined.

[0025] The embodiment of the present invention provides a fast repair method for establishing time violations in static timing analysis, which utilizes a greedy algorithm to process a redundant subset of the current module, and can accurately control the amount of elimination of various redundant values ​​to ensure that over-optimization does not occur while eliminating redundancy. It dynamically updates preset violation values ​​during the traversal process, and can make subsequent judgments based on the redundant values ​​that have been eliminated, thereby ensuring the accuracy and effectiveness of the entire repair process. It comprehensively considers the amount of redundant value elimination of the current module and all previously traversed modules and the corresponding engineering operations, and can formulate a more comprehensive and optimized repair strategy.

[0026] In a second aspect, the present invention provides a device for quickly repairing setup time violations in static timing analysis, including: an acquisition module for acquiring a static timing analysis report; an extraction module for extracting a target timing path according to the static timing analysis report, the target timing path having a setup time violation, and a target timing path passing through at least one module; a redundant value calculation module for calculating multiple types of redundant values ​​of each module passed by the target timing path; a redundant value set calculation module for calculating a redundant value set of a data path of the target timing path and a redundant value subset corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path; a repair order determination module for determining a repair order of each module according to the redundant values ​​of each module corresponding to the target timing path; a repair scheme determination module for analyzing each module in turn according to the repair order of the module, according to the redundant value set and the redundant value subset of each module, and determining a repair scheme for each module; a repair strategy determination module for obtaining a repair strategy for the target timing path according to the repair scheme of each module passed by the target timing path.

[0027] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to execute the method for quickly repairing time violations in the static timing analysis of the first aspect or any corresponding embodiment thereof.

[0028] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a method for quickly repairing establishment time violations in static timing analysis of the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 is a flow chart of a method for quickly repairing a setup time violation in static timing analysis according to an embodiment of the present invention;

[0031] Figure 2 is a flow chart of a method for quickly repairing a setup time violation in another static timing analysis according to an embodiment of the present invention;

[0032] Figure 3 is a flow chart of a method for quickly repairing a setup time violation in static timing analysis according to another embodiment of the present invention;

[0033] Figure 4 Schematic diagram of a process for quickly repairing a time violation in static timing analysis according to another embodiment of the present invention

[0034] Figure 5 is a structural block diagram of a fast repair device for establishing time violations in static timing analysis according to an embodiment of the present invention;

[0035] Figure 6 It is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0037] The embodiment of the present invention provides a rapid repair method for setup time violations in static timing analysis, which is applied to the key stage of processing static timing analysis reports to improve chip performance. By obtaining the static timing analysis report, a target timing path with setup time violations is identified. By calculating the redundancy value of each module passed by the target timing path, the influence of each module in the timing path is quantified. The repair order is determined by calculating the redundancy value of each module based on the redundancy value set and the redundancy value subset of each module. The occurrence of setup time violations is prevented in the early stage of timing convergence, and a systematic repair process is formed. Each module is analyzed and repaired in turn according to the repair order. By comprehensively considering the redundancy value and repair scheme of each module, a globally optimal repair strategy is formulated. The automated calculation and repair process reduces the need for manual intervention and reduces the risk of human error.

[0038] At present, the quick repair methods for setup time violations in static timing analysis are mostly used to provide solutions for the later stages of design. The solution to defects in layout and routing still relies on the experience of engineers. Due to the different qualifications of engineers, the solutions provided are sometimes not the most efficient and economical. With the rapid increase in the scale of design, the cycle of manually providing repair solutions is getting longer and longer, which greatly increases the R&D time of the project.

[0039] According to an embodiment of the present invention, an embodiment of a method for quickly repairing build time violations in static timing analysis is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0040] In this embodiment, a method for quickly repairing a setup time violation in static timing analysis is provided. Figure 1 is a flow chart of a method for quickly repairing a time violation in static timing analysis according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0041] Step S101, obtaining a static timing analysis report.

[0042] In an optional embodiment, to ensure the accuracy of the mathematical statistics in the present invention, illustratively, the timing paths obtained in the static timing analysis report must include at least 1w. Including more timing paths means that various situations in the design can be more comprehensively covered, thereby obtaining more accurate timing analysis results. By increasing the number of timing paths, the impact of accidental errors on the overall results can be reduced, the accuracy of the analysis can be improved, and it is also helpful to more comprehensively detect timing problems in the design.

[0043] In an optional embodiment, the static timing analysis report should include the location information of the standard cell, the interconnection crosstalk information, the expanded clock path information, the standard cell delay information and the interconnection delay information. The above information is used to help calculate the clock tree skew value of the target timing path, the logic level redundancy value, the standard cell delay redundancy value, the interconnection crosstalk redundancy value, the path detour redundancy value and other redundancy values.

[0044] Step S102, extracting a target timing path according to the static timing analysis report, wherein the target timing path has a setup time violation, and a target timing path passes through at least one module.

[0045] In an optional embodiment, based on the static timing analysis report, a target timing path with a setup time violation is extracted, and the target timing path does not meet the minimum stabilization time requirement required before the signal reaches the target logic gate, that is, the setup time requirement. Since the fully flattened timing path is based on the entire chip, the target timing path may pass through different design modules. Since each module and the top-level module are physically seamlessly connected, the target timing path will pass through at least one module.

[0046] Step S103, calculating multiple types of redundancy values ​​of each module that the target timing path passes through.

[0047] In an optional embodiment, the redundancy value includes one or more of a logic level redundancy value, a standard cell delay redundancy value, an interconnect crosstalk delay redundancy value, and a path detour redundancy value. The redundancy value provides specific information about each module in the timing path. Understanding the redundancy value of each module helps to formulate a more effective repair strategy.

[0048] Step S104 , calculating a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy value of each module corresponding to the target timing path.

[0049] Step S105 , determining the repair order of each module according to the redundancy value of each module corresponding to the target timing path.

[0050] Step S106 , analyzing each module in turn according to the repair sequence of the modules and based on the redundant value set and the redundant value subset of each module, and determining a repair solution for each module.

[0051] Step S107, obtaining a repair strategy for the target timing path according to the repair solutions of the modules that the target timing path passes through.

[0052] The present embodiment provides a rapid repair method for setup time violations in static timing analysis, which obtains a static timing analysis report, identifies a target timing path with a setup time violation, quantifies the influence of each module in the timing path by calculating the redundancy value of each module passed by the target timing path, determines the repair order by calculating the redundancy value of each module based on the redundancy value set and the redundancy value subset of each module, forms a systematic repair process, analyzes and repairs each module in turn according to the repair order, formulates a globally optimal repair strategy by comprehensively considering the redundancy value and repair plan of each module, and reduces the need for manual intervention in the automated calculation and repair process.

[0053] In this embodiment, a method for quickly repairing a setup time violation in static timing analysis is provided. Figure 2 FIG. 4 is a flowchart of a method for quickly repairing a time violation in static timing analysis according to another embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0054] Step S201, obtain a static timing analysis report. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0055] Step S202: extract the target timing path according to the static timing analysis report. The target timing path has a setup time violation. A target timing path passes through at least one module. For details, see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0056] Step S203, calculating multiple types of redundancy values ​​of each module that the target timing path passes through.

[0057] In an optional embodiment, the redundancy value includes one or more of a logic level redundancy value, a standard cell delay redundancy value, an interconnection line crosstalk redundancy value, and a path detour redundancy value.

[0058] The calculation of the delay redundancy value of the standard cell can help identify standard cells with excessive delay that affect the overall timing performance. By setting an upper limit on the acceptable delay, it ensures that the delay of each standard cell is within the preset safety limit, thereby improving circuit performance to achieve the expected frequency.

[0059] Interconnects are the key path for signal transmission. The performance of interconnects directly affects the quality and speed of signal transmission. Crosstalk is an important indicator of interconnect performance, which describes the unwanted voltage or current noise interference generated on adjacent transmission lines due to electromagnetic coupling during signal transmission. By extracting and recording the crosstalk delay redundancy value of each interconnect, the crosstalk performance of the interconnect can be comprehensively evaluated, thereby identifying potential signal integrity issues.

[0060] The path detour redundancy value is used to measure whether there is unnecessary detour in the path of a module in the target timing path. This detour may increase the transmission delay of the signal and reduce the performance of the circuit.

[0061] Step S204 , calculating a redundant value set of a data path of the target timing path and redundant value subsets corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path.

[0062] Step S205 , calculating the clock tree skew value of the target timing path.

[0063] In an optional embodiment, by calculating the clock tree skew value of the target timing path, the delay difference of the clock signal on the path can be understood. The clock tree skew is one of the key factors affecting timing convergence. Therefore, accurately evaluating the skew value helps to discover and solve potential problems in the design stage. If the skew value is too large, it may cause timing violations.

[0064] Step S206 , determining the redundancy value sum of the target timing path according to the sum of each element in the redundancy value set of the data path of the target timing path.

[0065] In an optional embodiment, by calculating the sum of the redundancy values ​​of the target timing path, the additional resources available for repair or optimization on the path can be evaluated, which helps to determine whether it is possible to resolve the timing problem by adjusting the redundant resources without more complex redesign or adding additional hardware resources.

[0066] Step S207, determining whether the sum of the redundancy values ​​is greater than or equal to a first preset violation value.

[0067] If the sum of the redundancy values ​​is greater than or equal to the first preset violation value, executing step S209;

[0068] If the sum of the redundancy values ​​is less than the first preset violation value, the next step is executed.

[0069] In an optional embodiment, the preset violation value is used to determine whether the effect of eliminating the redundant value has reached the standard for repairing the violation. Exemplarily, the first preset violation value is 1.2 times the preset violation value, wherein the preset violation value is a value pre-set according to circuit design specifications and performance requirements, that is, if the sum of the redundant values ​​is greater than or equal to 1.2 times the preset violation value, the repair order of each module is determined according to the redundant value of each module corresponding to the target timing path; if the sum of the redundant values ​​is less than 1.2 times the preset violation value, the next step is executed.

[0070] In an optional embodiment, if the sum of the redundancy values ​​is greater than or equal to the first preset violation value, it means that there is a large room for optimization in the circuit, and it is necessary to determine the repair order based on the redundancy values ​​of each module to prioritize the most affected parts. If the sum of the redundancy values ​​is less than the first preset violation value, it means that the redundant delay in the circuit is relatively small, and it may be necessary to consider the impact of other factors on timing performance.

[0071] Step S208 , determining whether the sum of the redundancy value and the preset multiple of the clock tree skew value is greater than a first preset violation value.

[0072] If the sum of the redundancy value and the preset multiple of the clock tree skew value is greater than the first preset violation value, determining the repair strategy of the target timing path according to the engineering operations corresponding to each element in the redundancy value set of the target timing path and the repair strategy of the clock tree skew value;

[0073] If the sum of the redundancy value and the preset multiple of the clock tree skew value is less than the first preset violation value, the target timing path is sent to the target user.

[0074] In an optional embodiment, each element in the redundancy value set of the target timing path represents a different type of redundancy value in different modules, and the engineering operation represents the specific measures or steps that need to be taken to eliminate the redundancy values ​​represented by the elements in the redundancy value set of the target timing path. For example, the layout of the interconnection lines is adjusted to reduce crosstalk delay, the design of the standard cells is optimized to reduce delay, the path is modified to eliminate detour redundancy, and the logic circuit is redesigned to reduce level delay. In addition, it may also include adjusting the skew value of the clock tree to further improve the timing performance.

[0075] In an optional embodiment, a repair strategy can be intelligently selected based on the relationship between the redundancy value and the clock tree skew value. For example, if the redundancy value is greater than or equal to the first preset violation value, the repair order can be determined based on the redundancy value of each module, and the modules with the most redundant resources are given priority to improve the repair efficiency and success rate. If the redundant resources are insufficient but close to the first preset violation value, and considering the impact of the clock tree skew, the engineering operations corresponding to the redundant values ​​and the repair strategy for the clock tree skew can be comprehensively considered to formulate a comprehensive repair plan. If the redundant resources are seriously insufficient, even the repair strategy for the clock tree skew cannot meet the requirements. The process will promptly send information about the target timing path to the target user, which will help the user to promptly understand the problems in the design and take further measures to solve these problems.

[0076] In an optional embodiment, exemplarily, if the sum of the redundancy value and 0.1 times the clock tree skew value is greater than 1.2 times the preset violation value, the repair strategy of the target timing path is determined according to the engineering operations corresponding to each element in the redundancy value set of the target timing path and the repair strategy of the clock tree skew value; if the sum of the redundancy value and 0.1 times the clock tree skew value is less than 1.2 times the preset violation value, the target timing path is sent to the target user.

[0077] In an optional embodiment, when the sum of the redundancy values ​​is less than the first preset violation value, it is further determined whether the sum of the redundancy values ​​and the preset multiple of the clock tree skew value is greater than the first preset violation value. This is to comprehensively consider the impact of the redundant delay and the clock tree skew value on the timing performance. If the sum of the two is still greater than the first preset violation value, it means that the timing performance of the circuit can still be optimized, and it is necessary to determine the repair strategy of the target timing path based on the engineering operations corresponding to each element in the redundant value set and the repair strategy of the clock tree skew value. If the sum of the redundancy values ​​and the preset multiples of the clock tree skew value of all modules is still less than the first preset violation value, it means that the violation of the circuit cannot be repaired by this method and needs to be sent to the target user for manual analysis from more levels.

[0078] Step S209, determining the repair order of each module according to the redundancy value of each module corresponding to the target timing path.

[0079] Step S210 , analyzing each module in turn according to the repair order of the modules and based on the redundant value set and the redundant value subset of each module, and determining a repair solution for each module.

[0080] Specifically, the above step S210 includes:

[0081] Step S2101, according to the repair order of the modules, traverse the sum of all elements in the redundant value subset of each module in turn.

[0082] In an optional embodiment, since there is a certain priority in engineering for the order of eliminating four types of redundant values, namely, interconnect crosstalk delay redundancy, standard cell delay redundancy, path detour redundancy, and logic level redundancy, this priority relationship can be reflected by a weight coefficient. By way of example, a weight coefficient of {1.0, 0.8, 0.5, 0.3} is used to determine the order of eliminating redundant values.

[0083] In an optional embodiment, the sum of all elements in the redundant value subset of each module is traversed in turn according to the repair order of the modules, ensuring that the module with the greatest impact on timing performance is processed first, and key problems are solved first, thereby improving the overall repair efficiency.

[0084] Step S2102: Whether the sum of all elements in the redundant value subset is greater than a second preset violation value.

[0085] If the sum of all elements in the redundant value subset of the current module is greater than the second preset violation value, the traversal is stopped, and the redundant subset of the current module is processed by a greedy algorithm to determine the amount of elimination of each type of redundant value in the current module so that the sum of the amount of elimination of each type of redundant value is greater than the second preset violation value and less than the third preset violation value.

[0086] If the sum of all elements in the redundant value subset of the current module is less than or equal to the second preset violation value, then the sum of all elements in the redundant value subset of the previous module is subtracted from the current second preset violation value to obtain an updated second preset violation value, and the sum of all elements in the redundant value subset of the previous module is subtracted from the current third preset violation value to obtain an updated third preset violation value, and then the next module is traversed in sequence.

[0087] In an optional embodiment, the sum of the eliminated amounts of the redundant values ​​of the target timing path can be expressed as:

[0088]

[0089] The constraints are: 1.2*|slack| <F(x)<1.5*|slack|。

[0090] Among them, x i represents the redundant value eliminated in the i-th iteration step, k represents the total number of iterations, F(x) represents the sum of the eliminated redundant values ​​of the target timing path, and |slack| represents the preset violation value.

[0091] In an optional embodiment, exemplarily, the second preset violation value is the difference between 1.2 times the first preset violation value and the sum of all elements in the redundant value subset of the previous module, and the third preset violation value is the difference between 1.5 times the first preset violation value and the sum of all elements in the redundant value subset of the previous module.

[0092] For example, taking module a as an example, we get the redundant value subset U a , judge U a Is the sum of all elements in greater than 1.2 times the preset violation value? If so, the redundant value subset U of module a is a Perform the greedy algorithm; if not, deduct U from both sides of the constraint condition. a The sum of all elements in U minus U a All elements in , and then enter the next module analysis. The analysis of the next module still follows the above principles until a certain module n satisfies the constraint of the minimum threshold of the inequality, then the greedy algorithm operation can be performed. At this time, the constraint condition of the redundancy value and of the target timing path can be rewritten as:

[0093]

[0094] Where t is an arbitrary module, U t is the subset of elements in U that belong to module t, n represents the module in the target timing path that satisfies the constraint of the minimum threshold of the inequality, and F(x) represents the sum of the redundant values ​​of the target timing path.

[0095] Assuming that module n needs to be processed by the greedy algorithm, in each iteration, the U that maximizes the redundancy value and the target timing path will be selected. n The element values ​​in , until all constraints of F(x) are satisfied, where U n is a subset of the subordinate modules n in U, assuming that the feasible solution X at the kth iteration k ={x1,x2,…,x k}, then the k+1th iteration needs to be in {U n not X k}, select the value that maximizes F(x), while satisfying that F(x) is less than 1.5 times the preset violation value, that is:

[0096]

[0097] Among them, x k+1 is the element selected in the k+1th iteration that satisfies specific constraints and maximizes the sum of the target timing path redundancy values, U n is a subset of the subordinate modules n in U, X k is the feasible solution of the kth iteration, and F(x) represents the sum of the redundant values ​​of the target timing path.

[0098] Then the feasible solution X of the k+1th iteration is k+1 ={x1,x2,…,x k ,x k+1}. If, at the k+1th iteration, F(x) exceeds 1.2 times of the preset violation value for the first time, and at the same time F(x) is less than 1.5 times of the preset violation value, it means that the greedy algorithm has found the optimal solution. At this time, the engineering operations mapped by all the elements participating in the addition of F(x) in all previous modules are returned, and the currently selected timing path analysis ends.

[0099] In an optional embodiment, exemplarily, the target timing path passes through module a, module b, and module c. The repair order is determined to be b→c→a according to the entropy weight method. Assuming that 1.2 times the target timing path violation value is 60ps, the optional repair operations in module b can respectively remove three interconnect crosstalk redundancy values ​​of 5ps, 3ps, and 2ps, two 10ps standard unit delay redundancy values, and one 20ps path detour redundancy value. Calculation shows that 5+3+2+10+10+20 cannot completely repair the violation value of 60ps.

[0100] Further analyzing module c, module c is needed to repair the remaining 10ps violation value. The available operations are to remove an 8ps standard unit delay redundancy value, three interconnection line crosstalk redundancy values ​​of 5ps, 3ps, and 1ps, and a 30ps logic level redundancy value. Within the available optional range of 30ps, 8ps, 5ps, 3ps, and 1ps, the remaining 10ps violation value must be repaired, but the sum of all operations of module b must not exceed 1.5 times the preset violation value, that is, 75ps. The sum of all redundant values ​​that can be removed by all operations of this module, 30+8+5+3+1, is greater than the remaining 10ps violation value, so the greedy algorithm will be triggered. According to the principle of selecting the most violation values ​​that can be repaired in each iteration, but the total must not exceed 75ps, and finally the 8ps and 5ps operations will be selected in module c.

[0101] Finally, combined with the operations in module b, this timing path will eventually return to repair the engineering operations corresponding to all the redundant values ​​that can be removed in module b and the engineering operations corresponding to the two redundant values ​​of 8ps and 5ps in module c.

[0102] Step S2103, determining a repair plan for each module according to the engineering operation corresponding to the amount of elimination of each type of redundant value of the current module and the engineering operations corresponding to all elements in the redundant value subsets of all modules traversed previously.

[0103] In an optional embodiment, a greedy algorithm is used to process the redundant subset of the current module, which can accurately control the amount of elimination of various redundant values, ensure that over-optimization is not achieved while eliminating redundancy, dynamically update the preset violation value during the traversal process, and make subsequent judgments based on the redundant values ​​that have been eliminated, thereby ensuring the accuracy and effectiveness of the entire repair process. By comprehensively considering the amount of redundant value elimination of the current module and all previously traversed modules and the corresponding engineering operations, a more comprehensive and optimized repair strategy can be formulated.

[0104] Step S211, according to the repair scheme of each module that the target timing path passes through, obtain the repair strategy of the target timing path. Figure 1 Step S107 of the illustrated embodiment will not be described in detail here.

[0105] In this embodiment, a method for quickly repairing a setup time violation in static timing analysis is provided. Figure 3 FIG. 1 is a flow chart of a method for quickly repairing a time violation in static timing analysis according to another embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0106] Step S301, obtain a static timing analysis report. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0107] Step S302: extract the target timing path according to the static timing analysis report. The target timing path has a setup time violation. A target timing path passes through at least one module. For details, see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0108] Step S303, calculate multiple types of redundancy values ​​of each module that the target timing path passes through. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0109] Step S304 , calculating a redundant value set of a data path of the target timing path and redundant value subsets corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path.

[0110] In an optional embodiment, the redundancy value subset of the module includes first weighted values ​​corresponding to each type of redundancy value of the module, and the second weighted value of the redundancy value is obtained by weighting the type of redundancy value; the redundancy value set of the data path of the target timing path includes second weighted values ​​corresponding to each type of redundancy value, and the second weighted value of the redundancy value is obtained by summing the first weighted values ​​of the type of redundancy value in each module.

[0111] In an optional embodiment, by calculating a subset of redundancy values ​​for each module to form a set of redundancy values ​​for the data path of the target timing path, the contribution of each module to the overall timing performance can be understood in detail. In actual circuits, different types of redundancy values ​​may have different degrees of impact on timing performance. For example, certain types of redundancy values ​​may be more likely to cause timing violations or have a greater impact on power consumption and area. By introducing a first weighted value and a second weighted value, different types of redundancy values ​​are weighted to reflect their relative importance in the overall timing performance.

[0112] Step S305 , calculating the clock tree skew value of the target timing path.

[0113] Specifically, the above step S305 includes:

[0114] Step S3051, determining a first delay according to the sum of delays of each standard cell along the clock path and delays of each interconnection line.

[0115] In an optional embodiment, the first delay D cl The standard cell delay X along the clock path is emitted cli and the interconnection delay N clj The sum of , where i is any standard unit and j is any interconnection line, that is:

[0116] D cl =∑X cli +∑N clj

[0117] Step S3052: determine a second delay according to the sum of delays of each standard cell along the clock path and delays of each interconnection line.

[0118] In an optional embodiment, the second delay D cc The standard cell delay X along the clock path is received cci and the interconnection delay N ccj The sum of , where i is any standard unit and j is any interconnection line, that is:

[0119] D cc =∑X cci +∑N ccj

[0120] Step S3053, determining whether the clock is an undesirable clock, and whether the first delay is greater than the second delay.

[0121] If the clock is a non-ideal clock and the first delay is greater than the second delay, a clock tree skew value of the target timing path is determined according to a difference between the first delay and the second delay;

[0122] In an optional embodiment, the clock tree skew value f(S) of the target timing path is:

[0123] f(S)=D cl -D cc

[0124] Among them, D cl is the first delay, D cc The second delay.

[0125] If the clock is an ideal clock, or if the clock is a non-ideal clock and the first delay is less than or equal to the second delay, the clock tree skew value of the target timing path is determined to be 0.

[0126] In an optional embodiment, the clock signal is often not completely ideal. For example, there may be problems such as jitter and offset. If the clock is not ideal and the first delay is greater than the second delay, it usually means that the clock signal has been interfered or delayed to some extent during the propagation process. The first delay being greater than the second delay is not favorable for the establishment time check. It is necessary to determine the clock tree skew value based on the difference between the first delay and the second delay. This can fully consider the non-ideality of the clock signal and make the calculation result more in line with the actual situation. In order to simplify the calculation and improve efficiency, a reasonable threshold is set for the clock tree skew. When the calculated skew value is less than or equal to this threshold, it is considered that the synchronization of the clock signal meets the requirements and no further adjustment or optimization is required.

[0127] In an optional embodiment, by considering the delay difference between the transmitting edge and the receiving edge of the clock path, as well as the ideal and non-ideal states of the clock, the clock tree skew value of the target timing path can be accurately evaluated. When the clock is non-ideal and the delay difference is large, the clock tree skew value can be automatically adjusted to adapt to the actual situation. By setting the skew value to handle the situation of an ideal clock or a favorable delay difference, the design process is simplified.

[0128] Step S306, determining the repair order of each module according to the redundancy value of each module corresponding to the target timing path.

[0129] Specifically, the above step S306 includes:

[0130] Step S3061, establishing redundant value series corresponding to each module according to each type of redundant value of each module, wherein one column in the redundant value series is used to represent one type of redundant value.

[0131] In an optional embodiment, illustratively, the logic level redundancy value f(L n ), standard unit delay margin value f(X ni ), interconnection crosstalk delay redundancy value f(C ni ), path detour redundancy value f(Dn ) is combined into the redundant value sequence S of the current module n n , the number of columns is 4, the number of rows is determined by the maximum number of redundant values ​​recorded in each of the above redundancy types, and the columns with redundant values ​​less than the maximum value are supplemented by 0. For example, module a can be combined into the following redundant value sequence S a , redundant value sequence S a The number of rows is determined by the number of redundant values ​​recorded for the interconnect crosstalk.

[0132]

[0133] Among them, S a represents the redundant value sequence of module a, f(L n ) represents the logic level redundancy value, f(X ni ) represents the delay margin value of the standard unit, f(C ni ) represents the interconnection crosstalk delay margin value, f(D n )Path detour redundancy value.

[0134] Step S3062, performing column operations on the redundant value sequences corresponding to each module, and adding the column elements to obtain the sum of the column elements.

[0135] In an optional embodiment, illustratively, the sum of the elements in each column is:

[0136]

[0137] Among them, t represents the number of rows of redundant value series, S a1 represents the sum of all interconnection crosstalk delay redundancy values ​​of module a in the target timing path, S a2 represents the sum of all standard cell delay redundancy values ​​of module a in the target timing path, S a3 represents the sum of all path detour redundancy values ​​of module a in the target timing path, S a4 Represents the sum of all logic level redundancy values ​​of module a in the target timing path.

[0138] Step S3063, weighting the sum of the elements in each column of the redundant value series to obtain the evaluation series of each module.

[0139] In an optional embodiment, the sum of the elements in each column is multiplied by the preset weight values ​​{k1, k2, k3, k4} of the interconnection crosstalk delay redundancy value, the standard cell delay redundancy value, the path detour redundancy value, and the logic level redundancy value, respectively. For example, {1.0, 0.8, 0.5, 0.3} is used to obtain the evaluation number series A of module a. a :

[0140]

[0141] Where S a1 , S a2 , S a3 , S a4 Corresponding to the sequence S a 1, 2, 3, 4. Rewrite the above 1×4 sequence as:

[0142] A a ={F(C a )F(X a )F(D a )F(L a )}

[0143] Step S3064, establishing an evaluation matrix of the target timing path according to the evaluation series of each module.

[0144] In an optional embodiment, illustratively, the target timing path includes n modules, and the evaluation series of all modules of the target timing path can be combined as follows:

[0145]

[0146] Step S3065, using the entropy weight method to process the evaluation matrix to obtain the evaluation score of each module in the target timing path.

[0147] In an optional embodiment, illustratively, i and j represent the evaluation sequence A respectively. all The i-th row and j-th column of the above item corresponding to the i-th row and j-th column is F ij , the data is standardized using the range standardization method, and each item after standardization is:

[0148]

[0149] where F j are all the values ​​in the jth column.

[0150] Use the following formula to calculate the index proportion P of each item ij .

[0151]

[0152] Where n is the number of rows in the evaluation sequence.

[0153] Calculate the information entropy E of each column j .

[0154]

[0155] If 0×ln(0) is encountered in the above accumulated term, the term is ignored.

[0156] Calculate the information entropy redundancy of each column.

[0157] d j =1-E j

[0158] Calculate the indicator weight for each column.

[0159]

[0160] Calculate the evaluation score Z of each module i .

[0161]

[0162] Step S3066, determining the repair order of each module according to the evaluation score of each module.

[0163] In an optional embodiment, exemplarily, the target timing path passes through module a, module b, and module c at the physical level. The above parameters are extracted and the evaluation score of each module is determined by the entropy weight method in descending order as module b, module c, and module a. The order of repair is b→c→a, that is, if b can be repaired, modules c and a will not be repaired. If b cannot be completely repaired, then repair will continue in c, and so on.

[0164] In an optional embodiment, the evaluation matrix is ​​processed by the entropy weight method to objectively determine the weight of each redundant value type, thereby avoiding the deviation caused by subjective weighting and improving the objectivity of the evaluation. The repair order determined according to the evaluation scores can give priority to modules with poor performance or large redundancy values, thereby more effectively improving the performance and stability of the overall circuit.

[0165] Step S307: Analyze each module in turn according to the repair order of the modules and the redundant value set and the redundant value subset of each module to determine the repair solution for each module. Figure 1 Step S106 of the illustrated embodiment will not be described in detail here.

[0166] Step S308: Obtain the repair strategy of the target timing path according to the repair solutions of each module that the target timing path passes through. Figure 1 Step S107 of the illustrated embodiment will not be described in detail here.

[0167] In this embodiment, a method for quickly repairing a setup time violation in static timing analysis is provided. Figure 4 FIG. 1 is a flow chart of a method for quickly repairing a time violation in static timing analysis according to another embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0168] Step S401, obtain a static timing analysis report. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0169] Step S402: extract the target timing path according to the static timing analysis report. The target timing path has a setup time violation. A target timing path passes through at least one module. For details, see Figure 1 Step S102 of the illustrated embodiment will not be described in detail here.

[0170] Step S403, calculating multiple types of redundancy values ​​of each module that the target timing path passes through.

[0171] Specifically, the above step S403 includes:

[0172] Step S4031, calculating the logic level redundancy value of any module in the target timing path.

[0173] In some optional implementations, the above step S4031 includes:

[0174] Step a1, extracting the number of levels of standard cells of the data path of the target timing path in the module and the third delay.

[0175] In an optional embodiment, the third delay D da It is determined based on the sum of the delay of the standard cell on the data path of the target timing path and the delay of the interconnection line, and the number of standard cells of the data path of the target timing path in the extraction module is L. a And the third delay D da , understand the delay composition of the target timing path.

[0176] Step a2, determining a typical value of standard cell delay according to the median of all standard cell delay information sets U0 in the static timing analysis report.

[0177] In an optional embodiment, the typical delay value X of the standard cell is determined by the median of all standard cell delay information sets U0 in the static timing analysis report. m , the mathematical expression is:

[0178] X m =Median(U0)

[0179] In an optional embodiment, the median of all standard cell delay information sets in the static timing analysis report is used to determine the typical value of standard cell delay, thereby reducing the impact of extreme values ​​on the results and making delay evaluation more accurate.

[0180] Step a3, determining a typical value of the sum of the delays of the standard cell and the interconnection line according to the ratio of the delay of the standard cell to the delay of the interconnection line and the typical value of the delay of the standard cell.

[0181] In an alternative embodiment, the typical value of the sum of the delays of the standard cell and the interconnection line is 1.1×X m .

[0182] Step a4, calculating the ideal maximum number of levels of each module according to the typical value of the sum of delays of the standard cells and interconnection lines in the module and the third delay.

[0183] In an optional embodiment, for example, the ideal maximum number of stages L in module a can be calculated amax D da With 1.1×X m To make the result credible, we add 20% model margin and round it up, that is:

[0184]

[0185] Among them, D da is the sum of the standard cell delay and interconnection delay in module a, X m is the typical value of the standard unit delay, and ceil is the rounding function.

[0186] If the number of levels of the standard cell is greater than the ideal maximum number of levels, a logic level redundancy value is calculated according to the number of levels of the standard cell, the ideal maximum number of levels, a ratio of a delay of the standard cell to a delay of an interconnection line, and a third delay;

[0187] In an optional embodiment, the logic level redundancy value f(L a )for:

[0188]

[0189] Among them, L a is the number of standard units in module a, L amax is the ideal maximum number of levels in module a.

[0190] If the number of levels of the standard cell is less than or equal to the ideal maximum number of levels, the logic level redundancy value is determined to be 0.

[0191] In an optional embodiment, the ideal maximum number of levels of each module can be calculated based on the typical value of the sum of delays of standard cells and interconnects in the module and the third delay. The ideal maximum number of levels of each module represents the maximum number of standard cells that the module can accommodate without increasing additional delay.

[0192] In an optional embodiment, by calculating the total delay of standard cells and interconnects, as well as typical values, the delay of the target timing path can be accurately evaluated, improving the accuracy of timing analysis. By calculating the ideal maximum number of levels and logic level redundancy values, the timing performance of the circuit can be better understood, and the design can be optimized as needed to meet performance requirements.

[0193] Step S4032, calculating the standard cell delay margin value of any module in the target timing path.

[0194] In some optional implementations, the above step S4032 includes:

[0195] Step b1, extracting the delay of each standard cell in the module, and calculating the standard cell delay redundancy value according to the delay of each standard cell in the module and the typical value of the standard cell delay.

[0196] In an optional embodiment, illustratively, the delay of the i-th standard unit in module a is taken and recorded as X ai , take the typical value of standard unit delay X m The delay margin value f(X ai ) is:

[0197] f(X ai )=X ai -2*X m

[0198] In an optional embodiment, the delay of each standard cell in the module is extracted. By setting a set multiple of the typical value of the standard cell delay as the upper limit of the acceptable delay, it can be ensured that the delay of each standard cell does not exceed this limit. The set multiple can be determined based on the specific requirements of the circuit design and the actual situation of the standard cell. Based on the delay of each standard cell in the module and the typical value of the standard cell delay, the delay redundancy value of the standard cell is calculated to reflect the degree of difference between the standard cell delay and the typical value.

[0199] Step b2, determining whether the calculated standard unit delay margin value is greater than the set delay margin value.

[0200] If the calculated standard unit delay redundancy value is greater than the set delay redundancy value, the calculated standard unit delay redundancy value is determined as the standard unit delay redundancy value;

[0201] If the calculated standard unit delay margin value is less than or equal to the set delay margin value, the calculated standard unit delay margin value is determined to be 0.

[0202] In an optional embodiment, by calculating the delay redundancy value of the standard cell, the standard cell with larger delay is identified, and corresponding measures are taken to optimize it. For example, the delay of the standard cell can be reduced by adjusting the parameters of the standard cell, improving the circuit design or adopting a more suitable optimization method.

[0203] In an optional embodiment, by setting an upper limit of acceptable delay and calculating the delay redundancy value of the standard cell, it is ensured that the delay of each standard cell is within a preset safety limit, thereby improving the performance of the circuit. For standard cells with larger delay redundancy values, manual optimization design is required.

[0204] Step S4033, calculating the path detour redundancy value of any module in the target timing path.

[0205] In some optional implementations, the above step S4033 includes:

[0206] Step c1, extracting the length of the standard cell string of the module, the sum of the distances between any adjacent standard cells, and the fourth delay.

[0207] In an optional embodiment, the length of the standard cell string is the Manhattan distance between the starting standard cell position and the ending standard cell position of the standard cell string in the module, the sum of the distances of any adjacent standard cells in the standard cell string is the sum of the Manhattan distances of any two adjacent standard cells between the starting standard cell position and the ending standard cell position, and the fourth delay is the sum of the delays of all standard cells in the standard cell string and the delay of the interconnection line.

[0208] Step c2, determining whether the sum of distances between any adjacent standard cells in the standard cell string is less than a set distance.

[0209] If the sum of the distances between any adjacent standard cells in the standard cell string is less than the set distance, the detour redundancy value of the standard cell string path is determined to be 0;

[0210] If the sum of the distances between any adjacent standard cells in the standard cell string is greater than or equal to the set distance, the next step is executed.

[0211] In an optional embodiment, illustratively, if the sum of the distances between any adjacent standard cells in the standard cell string is less than 50 microns, the standard cell string path detour redundancy value is determined to be 0; if the sum of the distances between any adjacent standard cells in the standard cell string is greater than or equal to the set distance, the next step is executed.

[0212] Step c3: whether the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is greater than a set ratio.

[0213] If the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is greater than the set ratio, the standard cell string path detour redundancy value is calculated according to the sum of the distances between any adjacent standard cells in the standard cell string and the length of the standard cell string;

[0214] In an optional embodiment, illustratively, the length of the standard cell string in the standard cell string i of module a is D aise , the sum of the distances between any adjacent standard cells in the standard cell string ∑D ainb , the fourth delay N ai If the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is greater than 2.5, the detour redundancy value of the standard cell string path is calculated according to the sum of the distances between any adjacent standard cells in the standard cell string and the length of the standard cell string.

[0215]

[0216] If the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is less than or equal to the set ratio, the detour redundancy value of the standard cell string path is determined to be 0.

[0217] In an optional embodiment, illustratively, if the ratio of the sum of distances between any adjacent standard cells to the length of the standard cell string is less than or equal to 2.5, the standard cell string path detour redundancy value is determined to be 0.

[0218] Step c4, determining the path detour redundancy value of the module according to the sum of the standard cell string path detour redundancy values ​​of each standard cell string in the module.

[0219] In an optional embodiment, the path detour redundancy value of the module is:

[0220]

[0221] Where n is any module and i is any continuous string of standard cells in the module.

[0222] In an optional embodiment, by considering factors such as the length of the standard cell string, the sum of the distances between any adjacent standard cells, and delay, the impact of path detours on circuit timing performance is accurately evaluated, thereby improving the accuracy of timing analysis. For standard cell strings with large path detour redundancy values, manual optimization of layout and routing is required to reduce unnecessary detours.

[0223] Step S4034, extracting and recording each interconnection line crosstalk delay redundancy value of each module, and determining the interconnection line crosstalk delay redundancy value of the module according to the sum of each interconnection line crosstalk delay redundancy value in the module.

[0224] In an optional embodiment, the crosstalk delay redundancy value of each interconnection line in each module is extracted and recorded as f(C ni), n is any module, i is the crosstalk delay redundancy value of any interconnection line in the module.

[0225] Step S404, calculate the redundancy value set of the data path of the target timing path and the redundancy value subsets corresponding to each module according to the redundancy values ​​of each module corresponding to the target timing path. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0226] Step S405: Determine the repair order of each module according to the redundancy value of each module corresponding to the target timing path. Figure 1 Step S105 of the illustrated embodiment will not be described in detail here.

[0227] Step S406: Analyze each module in turn according to the repair order of the modules and the redundant value set and the redundant value subset of each module to determine the repair solution for each module. Figure 1 Step S106 of the illustrated embodiment will not be described in detail here.

[0228] Step S407: Obtain the repair strategy of the target timing path according to the repair solutions of each module that the target timing path passes through. Figure 1 Step S107 of the illustrated embodiment will not be described in detail here.

[0229] This embodiment provides a fast repair device for setting up time violations in static timing analysis. Figure 5 is a structural block diagram of a fast repair device for establishing time violations in static timing analysis according to an embodiment of the present invention, such as Figure 5 As shown, the system includes:

[0230] An acquisition module 501 is used to acquire a static timing analysis report;

[0231] An extraction module 502 is used to extract a target timing path according to a static timing analysis report, wherein the target timing path has a setup time violation, and a target timing path passes through at least one module;

[0232] A redundancy value calculation module 503, used to calculate multiple types of redundancy values ​​of each module passed by the target timing path;

[0233] A redundancy value set calculation module 504, configured to calculate a redundancy value set of a data path of a target timing path and a redundancy value subset corresponding to each module according to the redundancy values ​​of each module corresponding to the target timing path;

[0234] A repair order determination module 505, used to determine the repair order of each module according to the redundancy value of each module corresponding to the target timing path;

[0235] A repair solution determination module 506 is used to analyze each module in turn according to the repair order of the modules and the redundant value set and the redundant value subset of each module to determine a repair solution for each module;

[0236] The repair strategy determination module 507 is used to obtain the repair strategy of the target timing path according to the repair solutions of each module that the target timing path passes through.

[0237] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0238] Figure 6 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 6 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 6 A processor 10 is taken as an example.

[0239] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0240] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0241] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0242] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0243] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 5 The example of connecting through bus is taken in the following.

[0244] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0245] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0246] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A fast repair method for setup time violation in static timing analysis, characterized in that: The method comprises: Get static timing analysis report; Extracting a target timing path according to the static timing analysis report, wherein the target timing path has a setup time violation, and a target timing path passes through at least one module; Calculating multiple types of redundancy values ​​of each module passed by the target timing path; Calculating a redundant value set of a data path of the target timing path and redundant value subsets corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path; Determining a repair order of each module according to the redundancy value of each module corresponding to the target timing path; According to the repair order of the modules, each module is analyzed in turn according to the redundant value set and the redundant value subset of each module to determine a repair solution for each module; A repair strategy for the target timing path is obtained according to the repair solutions of the modules passed by the target timing path.

2. The method according to claim 1, characterized in that After the step of calculating the redundant value set of the data path of the target timing path and the redundant value subsets corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path, and before the step of determining the repair order of each module according to the redundant values ​​of each module corresponding to the target timing path, the method further includes: Calculating a clock tree skew value of the target timing path; Determine the sum of the redundancy values ​​of the target timing path according to the sum of each element in the redundancy value set of the data path of the target timing path; If the sum of the redundancy values ​​is greater than or equal to the first preset violation value, executing the step of determining the repair order of each module according to the redundancy value of each module corresponding to the target timing path; If the sum of the redundancy values ​​is less than a first preset violation value, and the sum of the redundancy value and a preset multiple of the clock tree skew value is greater than the first preset violation value, determining a repair strategy for the target timing path according to the engineering operations corresponding to each element in the redundancy value set of the target timing path and a repair strategy for the clock tree skew value; If the sum of the redundancy values ​​is less than a first preset violation value, and the sum of the sum of the redundancy values ​​and a preset multiple of the clock tree skew value is less than the first preset violation value, the target timing path is sent to the target user.

3. The method according to claim 2, characterized in that The calculating the clock tree skew value of the target timing path includes: Determine the first delay according to the sum of the delays of each standard cell along the clock path and the delays of each interconnection line; Determine the second delay according to the sum of the delays of each standard cell along the clock path and the delays of each interconnection line; If the clock is a non-ideal clock and the first delay is greater than the second delay, determining a clock tree skew value of the target timing path according to a difference between the first delay and the second delay; If the clock is an ideal clock, or if the clock is a non-ideal clock and the first delay is less than or equal to the second delay, the clock tree skew value of the target timing path is determined to be 0.

4. The method according to claim 1, characterized in that: The redundancy value includes one or more of a logic level redundancy value, a standard cell delay redundancy value, an interconnection line crosstalk delay redundancy value, and a path detour redundancy value.

5. The method according to claim 4, characterized in that The step of calculating the logic level redundancy value of any module in the target timing path includes: Extracting the number of levels of standard cells of the data path of the target timing path in the module and a third delay, wherein the third delay is determined according to the sum of the standard cell delay and the interconnection line delay of the data path of the target timing path; Determine the typical delay value of the standard cell according to the median of all standard cell delay information sets in the static timing analysis report; Determining a typical value of the sum of the delays of the standard cell and the interconnection line according to the ratio of the delay of the standard cell to the delay of the interconnection line and the typical value of the delay of the standard cell; Calculating the ideal maximum number of levels of each module according to a typical value of the sum of delays of standard cells and interconnects in the module and the third delay; If the number of levels of the standard cells is greater than the ideal maximum number of levels, then calculating the logic level redundancy value according to the number of levels of the standard cells, the ideal maximum number of levels, the ratio of the delay of the standard cells to the delay of the interconnection line, and the third delay; If the number of levels of the standard cell is less than or equal to the ideal maximum number of levels, the logic level redundancy value is determined to be 0.

6. The method according to claim 4, characterized in that The step of calculating the standard cell delay redundancy value of any module in the target timing path comprises: Extracting the delay of each standard cell in the module; Calculate the standard unit delay redundancy value according to the delay of each standard unit in the module and the set multiple of the typical value of the standard unit delay; If the calculated standard unit delay redundancy value is greater than the set delay redundancy value, determining the calculated standard unit delay redundancy value as the standard unit delay redundancy value; If the calculated standard cell delay margin value is less than or equal to the set delay margin value, the standard cell delay margin value is determined to be 0.

7. The method according to claim 4, characterized in that The step of calculating the path detour redundancy value of any module in the target timing path includes: Extracting the length of the standard cell string of the module, the sum of any adjacent standard cell distances, and the fourth delay, wherein the length of the standard cell string is the Manhattan distance between the starting standard cell position and the ending standard cell position of the standard cell string of the module, the sum of any adjacent standard cell distances in the standard cell string is the sum of the Manhattan distances of any two adjacent standard cells between the starting standard cell position and the ending standard cell position, and the fourth delay is the sum of the delays of all standard cells in the standard cell string and the delay of the interconnection line, and the standard cell string of the module is a series of continuous standard cells in the module on the data path of the target timing path; If the sum of the distances between any adjacent standard cells in the standard cell string is less than the set distance, the path detour redundancy value is determined to be 0; If the sum of the distances of any adjacent standard cells in the standard cell string is greater than or equal to the set distance, and the ratio of the sum of the distances of any adjacent standard cells to the length of the standard cell string is greater than the set ratio, the standard cell string path detour redundancy value is calculated according to the sum of the distances of any adjacent standard cells in the standard cell string and the length of the standard cell string; If the sum of the distances between any adjacent standard cells in the standard cell string is greater than the set distance, and the ratio of the sum of the distances between any adjacent standard cells to the length of the standard cell string is less than or equal to the set ratio, the detour redundancy value of the standard cell string path is determined to be 0; The path detour redundancy value of the module is determined according to the sum of the standard cell string path detour redundancy values ​​of each standard cell string in the module.

8. The method according to claim 1, characterized in that Calculating a redundant value set of a data path of the target timing path and a redundant value subset corresponding to each module according to the redundant values ​​of each module corresponding to the target timing path, including: The redundancy value subset of the module includes first weighted values ​​corresponding to each type of redundancy value of the module, and the second weighted value of the redundancy value is obtained by weighting the redundancy value of the type; The redundancy value set of the target timing path includes second weighted values ​​corresponding to each type of redundancy value, and the second weighted value of the redundancy value is obtained by summing up the first weighted values ​​of the type of redundancy value in each module.

9. The method according to claim 1, characterized in that: The determining the repair order of each module according to the redundancy value of each module corresponding to the target timing path includes: According to each type of redundancy value of each module, a redundancy value series corresponding to each module is established, wherein one column in the redundancy value series is used to represent one type of redundancy value; Perform column operations on the redundant value sequences corresponding to each module respectively, and add the column elements to obtain the sum of the elements in each column; Perform weighted processing on the sum of the elements in each column of the redundant value series to obtain the evaluation series of each module; Establishing an evaluation matrix of the target timing path according to the evaluation series of each module; The evaluation matrix is ​​processed by using an entropy weight method to obtain an evaluation score of each module in the target timing path; The repair order of each module is determined according to the evaluation score of each module.

10. The method according to claim 1, characterized in that The method of analyzing each module in turn according to the repair order of the modules and the redundant value set and the redundant value subset of each module to determine a repair solution for each module includes: According to the repair order of the modules, the sum of all elements in the redundant value subset of each module is traversed in turn, and the sum of all elements in the redundant value subset is compared with the second preset violation value; If the sum of all elements in the redundant value subset of the current module is greater than the second preset violation value, stop traversing, perform greedy algorithm processing on the redundant subset of the current module, and determine the amount of elimination of various types of redundant values ​​in the current module, so that the sum of the elimination amounts of various types of redundant values ​​is greater than the second preset violation value and less than the third preset violation value; each time a module is traversed, the sum of all elements in the redundant value subset of the previous module is subtracted from the current second preset violation value to obtain an updated second preset violation value, and the sum of all elements in the redundant value subset of the previous module is subtracted from the current third preset violation value to obtain an updated third preset violation value; The repair plan for each module is determined based on the engineering operations corresponding to the amount of elimination of various redundant values ​​in the current module and the engineering operations corresponding to all elements in the redundant value subsets of all modules traversed previously.

11. A device for quickly repairing a timing violation in static timing analysis, characterized in that: The device comprises: Acquisition module, used to obtain static timing analysis report; An extraction module, configured to extract a target timing path according to the static timing analysis report, wherein the target timing path has a setup time violation, and a target timing path passes through at least one module; A redundancy value calculation module, used to calculate multiple types of redundancy values ​​of each module passed by the target timing path; A redundancy value set calculation module, used to calculate a redundancy value set of a data path of the target timing path and a redundancy value subset corresponding to each module according to the redundancy values ​​of each module corresponding to the target timing path; A repair order determination module, used to determine the repair order of each module according to the redundancy value of each module corresponding to the target timing path; A repair scheme determination module, used to analyze each module in turn according to the repair order of the modules and the redundant value set and the redundant value subset of each module to determine a repair scheme for each module; The repair strategy determination module is used to obtain the repair strategy of the target timing path according to the repair solutions of each module passed by the target timing path.

12. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the method according to any one of claims 1 to 10 by executing the computer instructions.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 10.

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