JBIG arithmetic coding and decoding method and system

Abstract

The invention relates to a JBIG arithmetic coding and decoding method and system, the method is realized based on a system structure of a QM encoder and a decoder, the QM encoder comprises a self-adaptive coding module and a coding unit, and the decoder comprises a self-adaptive decoding module and a decoding unit; the method comprises the following steps: step 1) generating a context CX; step 2) performing a JBIG arithmetic coding process; and step 3) performing a JBIG arithmetic decoding process. According to the JBIG arithmetic coding and decoding method and system, the throughput of an engine is improved, the problem of data dependence conflicts in an assembly line is solved, images can be processed at the speed close to one pixel in each clock period, the processing speed is high, the performance can be improved by about 40%, the image compression and processing efficiency is improved, compatibility is high, and the method and system are suitable for popularization and application. And interaction and communication with other JBIG compatible equipment can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of image encoding and decoding in computers, and in particular to a JBIG arithmetic encoding and decoding method and system. Background Art

[0002] The basic principle of data compression is to decompose a data set into a set of independent events and then represent these events with as few symbols as possible. If a shorter codeword can be used to represent more likely events and a longer codeword to represent less likely events, then compression is achieved. Given a source that outputs a set of independent events A from a data set S, the average number of bits required to encode the source's output is: H(S) = -∑P(A i )log P(A i ), where P(Aj) is the probability of event A occurring, and the quantity H is called the entropy of s. Shannon proved that for lossless compression, the minimum average number of bits that an algorithm can use to encode the output of a source is equal to the entropy of the source. Arithmetic coding is a commonly used method for generating variable-length codes that can encode data at a rate arbitrarily close to the entropy; when dealing with sources with highly skewed probabilities, arithmetic coding provides better compression rates than other coding methods (such as Huffman coding); arithmetic coding can also be used in conjunction with an adaptive model that provides probability estimates of events based on the statistical history of the source; these characteristics make arithmetic coding very suitable as an encoder for image compression.

[0003] In arithmetic coding, a unique identifier or codeword is assigned to the data sequence being encoded, and the codeword is selected from the unit interval [0,1); since there are infinitely many codewords available in this interval, any data sequence can be uniquely identified, and longer sequences are more precise than shorter ones, and therefore longer fractional representations; when encoding a data sequence, the unit interval is first divided into subintervals using the cumulative distribution function of a random variable associated with the source, and the size of the subinterval is proportional to the probability of the symbol appearing; the algorithm selects the corresponding interval as the current interval based on the first symbol in the sequence; the current interval is again divided into subintervals using the same method, and the next symbol in the sequence indicates which subinterval to select; this process is repeated until the end of the sequence is reached.

[0004] In 1993, the Joint Bi-level Image Experts Group (JBIG) of the International Organization for Standardization (ISO), the International Electrotechnical Commission (IEC), and the International Telephone and Telegraph Consultative Committee (CCITT) developed a set of standard bi-level image coding standards. This standard is informally called JBIG or JBIG1. The JBIG standard is a lossless compression method based on arithmetic coding and contextual CX modeling; the method has adaptive image characteristics and is robust to different types of images such as scanned images, printed characters, and halftone images. JBIG provides performance improvements over algorithms based on Huffman coding. Although designed for binary images, the JBIG standard can also be used to compress grayscale and color images by encoding each bit independently as if each bit was a separate binary image. The compression engine defined by JBIG in its standard is called the QM encoder, which is a limited precision implementation of the binary adaptive arithmetic encoder. Arithmetic coding represents a data sequence by sequentially dividing the interval into sub-intervals, the size of which is proportional to the probability of occurrence of each symbol in the sequence, and then selecting the sub-interval based on the occurrence of each symbol in the sequence.

[0005] The QM encoder (QM-Encoder in the encoding engine and QM-Decoder in the decoding engine) performs all arithmetic processing in the JBIG image compression algorithm. As the most complex unit in the JBIG image compression algorithm, the design of the QM encoder is crucial to the performance of the engine. Since the QM encoder is a hardware implementation of the QM encoder algorithms provided by JBIG, these algorithms have been carefully studied to exploit as much parallelism as possible to obtain the best performance. Summary of the invention

[0006] In view of the problems in the prior art, on the one hand, the present invention provides a JBIG arithmetic coding and decoding method, which is implemented based on the architecture of a QM encoder and a decoder, wherein the QM encoder includes an adaptive coding module and an encoding unit, and the decoder includes an adaptive decoding module and a decoding unit;

[0007] The method comprises: step 1) generating context CX, step 2) JBIG arithmetic coding process and step 3) JBIG arithmetic decoding process; the step 2) is composed of step S2-1: processing flow of adaptive coding module and step S2-2: processing flow of coding unit, and the step 3) is composed of step S3-1 processing flow of adaptive decoding module and step S3-2 processing flow of decoding unit;

[0008] The step 1) generates a context CX, including: a context CX construction module reads pixels in an image strip from a memory to generate a 12-bit context CX and a pixel to be encoded D;

[0009] In the step 2), the step S2-1: adaptive coding module processing flow includes:

[0010] After receiving the request for pixel encoding, the adaptive coding module reads the address from the context CX with a decimal value and stores it in the first context CX memory; then performs simplified reading to generate a 7-bit valid context CX, generates an index value Index with the decimal value corresponding to the valid context CX, and uses the index value Index as the write address to store the context CX, the valid context CX and the index value Index in the first context CX memory;

[0011] The first selector reads the index value Index and the high-probability symbol MPS corresponding to the given context CX from the lookup table of the first context CX memory, and the first selector determines whether to update the index value Index according to the first determination rule, and then outputs the updated or unupdated new index value Index, and selects the new high-probability symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new high-probability symbol MPS and the probability table Qe; and then the second selector determines the index value Index, the high-probability symbol MPS and the probability table Qe to be fed back to the encoding unit for arithmetic encoding;

[0012] The first determination rule is: determine whether the target pixel is a high-probability symbol; if the target pixel is a high-probability symbol, do not update the index value Index, and directly output the index value Index; if the target pixel is not a high-probability symbol, update the index value Index, and output a new index value Index;

[0013] In the step 2), the step S2-1: encoding unit processing flow includes:

[0014] The pixel to be encoded D, the high probability symbol MPS, the index value Index and the probability table Qe transmitted by the adaptive encoding module are arithmetic encoded;

[0015] Secondly, it is determined whether the first register A and the first register C need to be renormalized. The probability table Qe assigns A to the first register A, and the A corresponds to the low probability symbol LPS; and when A=A<<1, the renormalization stage is executed; the renormalization stage doubles the values ​​of the first register C and the first register A until A is greater than 0x8000;

[0016] Next, perform the arithmetic coding, which includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations and are then updated into the first register A and the first register C; finally, after encoding all the pixels in the strip, the QM encoder executes the FLUSH process to output the compressed pixel SCD;

[0017] The precisions of the first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, where Clow represents the lower 16 bits of the first register C and Chigh represents the higher 12 bits of the first register C;

[0018] At the end of each strip arithmetic coding, the flush of the first register C executed includes a CLEARBITS process that clears the trailing bits in the compressed data stream to zero. The CLEARBITS process is as follows: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0;

[0019] Where A is the assignment of the first register A and C is the assignment of the first register C.

[0020] In the present invention, the most probable symbol MPS is a 1-bit value representing the more probable color in the pixel, and the index value Index is a 7-bit value used to index the probability table Qe containing the numerical values required for encoding.

[0021] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, in the arithmetic coding, the arithmetic operations and logical operations performed by the first register C and the first register A are as follows:

[0022] A temp = A - Qe (1)

[0023] C temp = C + A temp (2)

[0024] A temp < Qe (3)

[0025] A < 2 * Qe (4)

[0026] Where the implementation of equation (4) takes precedence over equation (3), and the addition operation in equation (2) is implemented as a carry-select adder.

[0027] Further, in the JBIG arithmetic coding and decoding method of the present invention, in the step 3), the step S3-1: the adaptive decoding module processing flow includes: reading the first 8 bits of the context CX from the context CX register as the address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values ​​Index0 and Index1, which correspond to two high-probability symbols MPS0 and high-probability symbols MPS1, respectively, and are converted into two probability tables Qe running in parallel;

[0028] The two index values ​​Index0, Index1 and the two high-probability symbols MPS0, high-probability symbol MPS1, as well as the pixel to be decoded SCD and the feedback signal of the decoding unit are jointly output through a multiplexer to a new index value Index and a new high-probability symbol MPS; two probability tables Qe running in parallel, as well as the pixel to be decoded SCD and the feedback signal of the decoding unit are jointly output through another multiplexer to a new probability table Qe; and the context CX of the context CX register is updated at the same time;

[0029] In the step 3), the step S3-2: the decoding unit processing flow includes: the pixel to be decoded SCD, the new high probability symbol MPS and the new probability table Qe are renormalized or arithmetically decoded;

[0030] The precision of the second register C and the second register A in the decoding unit are 24 bits and 16 bits respectively. The second register C is divided into Clow -2 and Chigh -2 Two parts, and Clow -2 Indicates the lower 8 bits of the second register C, Chigh -2 Represents the upper 16 bits of the second register C; and Clow -2 Used only to read the incoming compressed data stream, shifting it to the high bit while doing the renormalization;

[0031] In the arithmetic decoding, the new probability table Qe is shifted left to achieve doubling, and the second register A is shifted left to perform arithmetic and logical operations; when initializing the second register C at the beginning of each stripe, an 8-bit shift is performed, and only Chigh -2 Perform arithmetic and logical operations; finally, restore the original pixel D.

[0032] Further, in the JBIG arithmetic coding and decoding method of the present invention, in the arithmetic decoding unit, the arithmetic operation and the logic operation performed by the second register A and the second register C are as follows:

[0033] A temp =A-Qe (1)

[0034] A<2*Qe (4)

[0035] C high -A temp <0 (7)

[0036] C high_temp =C high -A temp (6)

[0037] Where A is the value assigned to the second register A, C high Chigh -2 .

[0038] Further, in the JBIG arithmetic coding and decoding method of the present invention, the updating index value Index and the output probability value Qe are implemented as follows:

[0039] Based on the input old index value Index, the NLPS-I lookup table, the NMPS-I lookup table, the NLPS-Qe lookup table and the NMPS-Q lookup table are combined and created;

[0040] Output a new index value Index through the NLPS-I lookup table and the NMPS-I lookup table;

[0041] Through the NLPS-Qe lookup table and the NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low-probability symbol LPS and the next high-probability symbol MPS defined in the original table is output, and then the final probability value Qe is selected through two multiplexers.

[0042] In the present invention, the NLPS-I lookup table, NMPS-I lookup table, NLPS-Qe lookup table and NMPS-Qe lookup table can be obtained by combining the NLPS and ST columns, the NMPS and ST columns, the NLPS and LSZ columns, and the NMPS and LSZ columns in the PET table in the standard ITU-TT.82 to obtain the NLPS-I lookup table, the NMPS-I lookup table, the NLPS-Qe lookup table and the NMPS-Qe lookup table.

[0043] Furthermore, in the JBIG arithmetic coding and decoding method described in the present invention, the first context CX memory is configured to be 32 bits wide and 256 bits deep; data is read from the first context CX memory in an asynchronous manner or written in a synchronous manner.

[0044] Furthermore, in the JBIG arithmetic coding and decoding method of the present invention, the encoding unit uses a multiplexer to select the final assignments allocated to the first register A and the first register C.

[0045] Further, in the JBIG arithmetic coding and decoding method of the present invention, in the arithmetic coding, in the carry selection adder, the 16-bit addition Clow+A temp Decision C temp The lower 16 bits of the carry select adder select value Chigh or Chigh+1 as C temp The upper 12 digits.

[0046] On the other hand, the present invention provides a JBIG arithmetic coding and decoding system, the system is a system based on any one of the JBIG arithmetic coding and decoding methods described above, the system comprising: a context CX construction module, a QM encoder, and a decoder, the QM encoder comprising an adaptive coding module and an encoding unit, the decoder comprising an adaptive decoding module and a decoding unit;

[0047] The adaptive encoding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector; the encoding unit is configured with a first register A and a first register C; the adaptive decoding module is configured with a context CX register and 2 multiplexers; and the decoding unit is configured with a second register A and a second register C.

[0048] Further, in the JBIG arithmetic coding and decoding system described in the present invention, the context CX construction module is configured to: tell the QM encoder to perform the INITENC process at the beginning of each stripe; when INITENC is completed, the context CX construction module prepares to generate the context CX and pixel D for the first pixel of the image, and tells the QM encoder to perform the ENCODE process; after encoding all pixels in the stripe, the context CX construction module instructs the QM encoder to perform the FLUSH process; when the FLUSH process ends, the encoding of the stripe is completed, and the compressed pixel SCD is obtained.

[0049] In the present invention, the context CX construction module can be configured to support three-line and two-line templates to generate context CX, and the reused context CX used to encode typical predicted pseudo pixels in different templates is mapped to the same value, thereby improving the flexibility and consistency of encoding.

[0050] Compared with the prior art, the present invention has the following beneficial technical effects:

[0051] (1) The JBIG arithmetic coding and decoding method and system described in the present invention adopts a pipeline architecture to design the QM-Coder Unit, divides the processing of each pixel into multiple stages, improves the throughput of the engine, and achieves the goal of processing nearly 1 pixel per clock cycle. The problem of data dependency conflicts in the pipeline is solved through a data forwarding mechanism, and the reorganization stage is optimized to reduce the impact of pipeline resource conflicts. In the QM-Encoder Unit, according to the characteristics of register A when encoding the high-probability symbol MPS, a 1-bit shift logic is added to reduce the additional cycles required for frequently occurring single-bit shifts without significantly increasing the engine cycle time.

[0052] (2) The JBIG arithmetic coding and decoding method and system described in the present invention can process images at a rate close to 1 pixel per clock cycle, with a fast processing speed. When the typical prediction option is enabled, the performance can be improved by about 40%, which improves the efficiency of image compression and processing. It complies with the JBIG standard, has strong compatibility, and can interact and communicate with other JBIG-compatible devices. It can be applied to a variety of fields such as fax equipment, digital printing and copying equipment, etc., to meet the image processing requirements of different scenarios. Through reasonable hardware resource allocation and algorithm optimization, the resource utilization rate is improved and the cost and power consumption of the system are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a schematic diagram of an arithmetic coding adaptive module in a specific implementation manner of the present invention;

[0054] Figure 2 is a schematic diagram of an arithmetic coding unit in a specific implementation manner of the present invention;

[0055] Figure 3 is a schematic diagram of an arithmetic decoding adaptive module in a specific implementation manner of the present invention;

[0056] Figure 4 is a schematic diagram of an arithmetic decoding unit in a specific implementation manner of the present invention;

[0057] Figure 5 It is a schematic diagram of the processing flow of QM-coder in a specific implementation mode of the present invention;

[0058] Figure 6 is a schematic diagram of updating the index value I and the probability Qe value in a specific embodiment of the present invention;

[0059] Figure 7 It is a schematic diagram of a three-line template of context CX in a specific implementation manner of the present invention;

[0060] Figure 8 It is a schematic diagram of a two-line template of context CX in a specific implementation manner of the present invention;

[0061] Fig. 9 is a schematic diagram of a three-line template of context CX containing virtual pixels in a specific implementation manner of the present invention,

[0062] Fig.10 It is a schematic diagram of a two-row template of context CX containing virtual pixels in a specific implementation manner of the present invention. DETAILED DESCRIPTION

[0063] In order to have a clearer understanding of the technical features, purposes and effects of the present invention, the specific embodiments of the present invention are now described in detail with reference to the accompanying drawings. The specific embodiments described are only part of the specific embodiments of the present invention, not all of the specific embodiments. Based on the specific embodiments of the present invention, all other specific embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. If the specific conditions are not specified in the specific embodiments, they shall be carried out according to conventional conditions or the conditions recommended by the manufacturer.

[0064] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. For example, the probability Qe in the drawings represents the probability Qe value; to distinguish the registers of the decoding and encoding processes, some registers and memories of the encoding process are defined as "first", and some registers and memories of the decoding process are defined as "second". The following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims. The terms used in the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. Specific implementation method one:

[0066] A JBIG arithmetic coding and decoding method of the present invention is implemented based on the architecture of a QM encoder and a decoder, wherein the QM encoder includes an adaptive coding module and an encoding unit, and the decoder includes an adaptive decoding module and a decoding unit;

[0067] The method comprises: step 1) generating context CX, step 2) JBIG arithmetic coding process and step 3) JBIG arithmetic decoding process; the step 2) is composed of step S2-1: the processing flow of the adaptive coding module and step S2-2: the processing flow of the coding unit, and the step 3) is composed of step S3-1: the processing flow of the adaptive decoding module and step S3-2: the processing flow of the decoding unit;

[0068] The above step 1) generates the context CX, including: the context CX construction module reads pixels in the image strip from the memory to generate a 12-bit context CX and a pixel to be encoded D;

[0069] In the above step 2), the above step S2-1: adaptive coding module processing flow includes:

[0070] After receiving the pixel encoding request, the adaptive coding module reads the address from the context CX as a decimal value and stores it in the first context CX memory; then performs simplified reading to generate a 7-bit valid context CX, generates an index value Index with the decimal value corresponding to the valid context CX, and uses the index value Index as the write address to store the context CX, the valid context CX and the index value Index in the first context CX memory;

[0071] In this implementation, the input is a 12-bit context CX. According to the 2^12=4096 possible contexts that may be generated by the template pixel, the corresponding decimal values ​​are used as read addresses to store the 4096 possible contexts CX in the context CX register RAM; by simplifying the 4096 possible situations, the last seven bits are read and effectively stored, that is, &0x7f, to generate a 7-bit valid context CX, and the index value Index is generated by the decimal value corresponding to the valid context CX, and the Index value Index is used as the write address to store Index and CX in ROM.

[0072] The first selector reads the index value Index and the high-probability symbol MPS corresponding to the given context CX from the lookup table of the first context CX memory, and the first selector determines whether to update the index value Index according to the first determination rule, and then outputs the updated or unupdated new index value Index, and selects the new high-probability symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new high-probability symbol MPS and the probability table Qe; and then the second selector determines the index value Index, the high-probability symbol MPS and the probability table Qe to be fed back to the encoding unit for arithmetic encoding;

[0073] The first determination rule is: determine whether the target pixel is a high-probability symbol; if the target pixel is a high-probability symbol, do not update the index value Index, and directly output the index value Index; if the target pixel is not a high-probability symbol, update the index value Index, and output a new index value Index;

[0074] In the above step 2), the above step S2-1: encoding unit processing flow includes:

[0075] The pixel D to be encoded, the high probability symbol MPS, the index value Index and the probability table Qe transmitted by the above adaptive encoding module are arithmetic encoded;

[0076] Secondly, it is determined whether the first register A and the first register C need to perform renormalization. The probability table Qe assigns the value A to the first register A, and the above A corresponds to the low probability symbol LPS; and when A = A << 1, the renormalization stage is executed; in the above renormalization stage, the values of the first register C and the first register A are doubled until A is greater than 0x8000;

[0077] Thirdly, the arithmetic coding is performed. The arithmetic coding includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations, and then are updated to the first register A and the first register C; finally, after encoding all the pixels in the strip, the above QM encoder executes the FLUSH process to output the compressed pixel SCD;

[0078] The precisions of the above first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, and Clow represents the lower 16 bits of the first register C, and Chigh represents the higher 12 bits of the first register C;

[0079] At the end of the arithmetic coding of each strip, the refresh of the first register C executed includes a CLEARBITS process of clearing the trailing bits in the compressed data stream to zero. The above CLEARBITS process is: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0;

[0080] Wherein, A is the assignment of the above first register A, and C is the assignment of the above first register C.

[0081] The above high probability symbol MPS is a 1-bit value representing the more likely color in the pixel, and the above index value Index is a 7-bit value used to index the probability table Qe containing the numerical values required for encoding.

[0082] In the present invention, during the execution of the CLEARBITS process, the selection part in the carry-select adder is reused to select the value of the high bit high. However, the logic for determining how to make the selection is different from the logic used in the encoding process. The encoder uses an in-line 1-bit shifter to process the unit renormalization of the C and A registers without the need for additional clock cycles. This creates many possibilities when assigning the next value to the C and A registers. The possible assignments of the A register are: Clow = 0

[0083] In some embodiments, such as Figure 1As shown, after receiving a request to encode a pixel, the QM encoder first reads the value of the high probability symbol MPS and the index value Index of the probability corresponding to the given context CX from the memory. The high probability symbol MPS is a 1-bit value, which indicates the color of the more likely symbol in the pixel; the index value Index is a 7-bit value used to index the probability table Qe containing the numerical value required for encoding. The high probability symbol MPS and the index value Index together capture the probability table Qe of the adaptive probability estimate associated with the specific context CX. Using the index value Index as an index, the adaptive encoding module and the adaptive decoding module read information such as the value Qe, NMPS, NLPS and SW index value IndexTCH from the internal ROM table. Qe is the size of the LPS subinterval; NLPS indicates that the next probability estimation state is a low-probability symbol, NMPS indicates that the next probability estimation state is a high-probability symbol, and when renormalization is required, the estimated state of the LPS and high-probability symbol MPS observation values; finally, the SW index value IndexTCH indicates whether the value of the high-probability symbol MPS should be reversed when the index value Index given by NLPS changes. After reading from the ROM table, the encoding module and the decoding module perform the arithmetic encoding, arithmetic decoding, and logical operations required to process a specific pixel, and update the value registers and memory as needed. Depending on the results of the arithmetic and logical operations, registers A and C may need to be renormalized. When pixel processing needs to be completed, the JB index value IndexG encoder renormalizes the appropriate registers and updates the values. A multi-stage pipeline is designed to increase the throughput of the JB index value IndexG encoder, so that continuous pixel overlap can be processed.

[0084] The renormalization operation cannot run in parallel with the stage code. Both stages operate on the values ​​in registers A and C, resulting in resource conflicts. The encoding stage processing of the subsequent pixel cannot start immediately before the transformation stage processing of the previous pixel is completed. When entering the renormalization stage, the pipeline process will be temporarily stopped.

[0085] like Figure 1As shown, the adaptive module in the arithmetic coding process, wherein the input is a 12-bit context CX, and according to the 2^12=4096 possible possibilities that may be generated by the template pixel point, the corresponding decimal value is used as the read address to store the 4096 possible context CX. By simplifying the 4096 possible situations, the last seven bits are read and effectively stored, that is, &0x7f, to generate a 7-bit valid context CX, and the index value Index is generated by the decimal value corresponding to the valid context CX, and the index value Index is used as the write address to store the index value Index and CX. The context CX register is configured as a 32-bit wide and 256-bit deep ROM. In other implementation rooms, the same configuration needs to be maintained in the decoder so that four pairs of index values ​​Index and high-probability symbols MPS in the adaptive memory can be accessed at one time. For design consistency, the same configuration is maintained in the encoder. Data is read asynchronously and written to the context CX register synchronously. The adapter reads the CX and D inputs from the context CX construction module and provides the encoder with probability Qe values, high probability symbols MPS and D associated with the same pixel for processing. In addition, the adaptive module updates the context CX register and internal registers using the results of the encoder. The two bits in the context CX corresponding to the two pixels immediately before the target pixel are not generated in time to become part of the memory address. By using only the 7 bits available in the context CX as the address, the adaptive module reads the index value Index and the high probability symbol MPS value for all four possible values ​​of CX. When decoding the last two bits of the context CX, a fast multiplexer can be used to select the appropriate pair.

[0086] In some embodiments, the simple process is: through a selector, which is controlled by the feedback of the encoder core unit, it is decided whether to use the new index value Index, and the value of the current high-probability symbol MPS is selected through the updated index value Index, and output to the probability table Qe, and a selector controlled by the feedback value of the encoder core unit is used to decide whether to send the current index value Index and the high-probability symbol MPS to the encoder core unit for arithmetic coding. The probability Qe value corresponding to the output current index value Index is also controlled by the selector of the feedback value of the encoder core unit, which decides when to send the current Qe to the encoder for arithmetic coding.

[0087] like Figure 1As shown, the feedback value of the encoder core unit also acts on four parts: used to generate the next index value next index value Index and the next high probability symbol NMPS, the next index value Index and NMPS will be used for the pre-stage selection value of data memory A and data memory B, and act on the selector controlled by the feedback of the encoder core unit. For one selector, the value in data memory B and the next index value Index are selected to be written into the context CX memory. For two selectors, one is the pre-stage selection value of data memory A, and the other is the pre-stage selection value of data memory B.

[0088] like Figure 1 In the arithmetic coding process shown, the output Qe of the adaptive module, the index value Index, the high probability symbol MPS, and the unprocessed pixel D to be coded are simultaneously transmitted to the arithmetic coding core unit for arithmetic coding.

[0089] like Figure 2 As shown, the renormalization stage doubles the value of the first register C and the first register A until A is greater than 0x8000. In hardware design, this means left-shifting the first register C and the first register A until the 15th bit of the first register A becomes 1. By implementing a shift-and circuit to detect the number of leading 0s in register A, the renormalization stage can be easily combined with the code stage to eliminate resource conflicts in the pipeline. However, the additional hardware significantly increases the latency of the engine's critical path, thereby slowing down the clock speed. A compromise solution involves realizing that when encoding the high-probability symbol MPS, the first register A only needs to be doubled at most once to make its value greater than 0x8000.

[0090] In some embodiments, Figure 2 As shown, in the arithmetic coding, the arithmetic operation and logic operation performed by the first register C and the first register A are as follows:

[0091] A temp =A-Qe (1)

[0092] C temp =C+A temp (2)

[0093] A temp <Qe (3)

[0094] A<2*Qe (4)

[0095] Wherein, A is the value assigned to the first register A, and C is the value assigned to the first register C; the implementation of the above formula (4) takes precedence over the above formula (3), and the addition operation in the above formula (2) is implemented as a carry selection adder. In the present invention, the hardware implementation of the above formula (4) is better than that of formula (3) because the comparison can be made without waiting for the result of formula (1). Moreover, the implementation of formula (4) does not require more hardware than formula (3) because the doubling of Qe can be achieved by a left shift operation. Due to the difference in precision between the first register C and the above first register A, the addition operation in formula (2) is implemented as a carry selection adder to reduce the delay of the carry ripple.

[0096] In some embodiments, since the assignment of the probability estimate Qe to the first register A corresponds to the encoding of the LPS, this assignment is always followed by renormalization. The assignment A=A<<1 is only used to perform the renormalization phase when multi-bit renormalization is required. The possible assignments of the C register are:

[0097] C=(C+A temp )<<1

[0098] C=C<<1

[0099] C=(temp+0x8000)<<1

[0100] C=temp<<1

[0101] The encoder uses a multiplexer to select the final value assigned to the first register C and the first register A.

[0102] In some embodiments, the high bit and the low bit are selected and assigned respectively because a carry select adder is used when calculating the next value of the assignment C of the first register C. The decision logic in the encoder determines how the encoder selects the correct values ​​for the first register C and the first register A, and whether the adapter needs to update the data in the first context CX register memory.

[0103] In some embodiments, Figure 2 As shown, the pixel D to be encoded and the high probability symbol MPS are determined through an XOR gate whether to perform low probability encoding. The specific rule is: D^MPS=1, low probability encoding; D^MPS=0, high probability encoding. The decision maker is used to decide whether to update the probability Qe value of the context dynamic probability table Qe, and whether to perform high probability encoding. Part of the output of the decision maker is sent to the previous level context probability update adaptive module, and the other part is sent to the current level module, which are used for the renormalization stage and processing all buffer 0xff byte overflows. Register B is used to temporarily store the high-order value of the new register C. Its output is simply spliced ​​to obtain the correct SCD.

[0104] The decision maker in the present invention plays a key decision-making and regulating role in the entire encoding process.

[0105] The decision maker receives a series of data related to the pixel to be encoded D, including the high probability symbol MPS, the probability table Qe after one-bit left shift, etc. Its core function is to accurately compare and analyze these input data.

[0106] By performing operations such as difference calculations, the decision maker can determine the numerical relationship and degree of difference between input data. Based on preset rules and logic, as well as interaction with the adaptive module, the decision maker makes key decisions.

[0107] For example, based on the comparison result between the probability Qe and other values, the decision maker determines whether to send the data to the adaptive module for further processing, or trigger other related operations, such as control instructions for the first register A, the first register C, etc.

[0108] At the same time, the decision maker continuously monitors the stability and rationality of the input data to ensure the accuracy and reliability of the encoding process.

[0109] In some embodiments, in the above step 3), the above step S3-1: the adaptive decoding module processing flow includes: reading the first 8 bits of the context CX from the context CX register as the address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values ​​Index0 and Index1, which correspond to two high-probability symbols MPS0 and high-probability symbols MPS1, respectively, and are converted into two probability tables Qe running in parallel;

[0110] The above two index values ​​Index0, Index1 and two high probability symbols MPS0, high probability symbol MPS1, as well as the pixel to be decoded SCD and the feedback signal of the decoding unit are jointly output through a multiplexer to a new index value Index and a new high probability symbol MPS; two probability tables Qe running in parallel, as well as the pixel to be decoded SCD and the feedback signal of the decoding unit are jointly output through another multiplexer to a new probability table Qe; and the first context CX register CX is updated at the same time;

[0111] In the above step 3), the above step S3-2: the above decoding unit processing flow includes: the pixel to be decoded SCD, the new high probability symbol MPS and the new probability table Qe are renormalized or arithmetically decoded;

[0112] The precision of the second register C and the second register A in the above decoding unit are 24 bits and 16 bits respectively. The second register C is divided into Clow -2 and Chigh -2 Two parts, and Clow-2 Indicates the lower 8 bits of the second register C, Chigh -2 Represents the upper 16 bits of the second register C; and Clow -2 Used only to read the incoming compressed data stream, shifting it to the high bit while doing the renormalization;

[0113] In the arithmetic decoding, the new probability table Qe is shifted left to double, and the second register A is shifted left to perform arithmetic and logical operations; when initializing the second register C at the beginning of each stripe, an 8-bit shift is performed, and only Chigh is in the second register C. -2 Perform arithmetic and logical operations; finally, restore the original pixel D.

[0114] In other embodiments, Figure 3 As shown, the processing flow of the adaptive decoding module of the decoder is the same as the adaptive arithmetic coding flow, except that the selector of the adaptive decoding module is a complex multiplexer, which selects the index value Index and the high probability symbol MPS through the feedback signal of the decoding unit and the pixel to be decoded D. The data of the context CX memory is stored in both data memory 1 and data memory 2.

[0115] In other embodiments, Figure 4 As shown, the second register A in the decoding unit has a 16-bit width like the first register A in the encoding module. The second register C only needs to be 24 bits wide, and all arithmetic operations in the decoding unit are 16-bit arithmetic operations, because the arithmetic operations on the second register C only involve the highest 16 bits of the second register C. The lower 8 bits of the second register C are only used to read the incoming compressed data stream, and then moved to the new second register C high bits when renormalizing.

[0116] In other embodiments, during decoding, the adaptive decoding module performs reading of context CX data by reading data from the context CX register using the first 8 bits of the context CX as an address. At the same time, the decoder decodes the pixel value corresponding to the 9th bit in the context CX. Once the value of the pixel is known, the number of possibilities in the context CX is reduced to two. The adaptive decoding module stores the upper 16 bits or lower 16 bits of the context CX register data in an internal register, depending on whether a 1 bit or a 0 bit is decoded. In the reading context CX data stage, when the last bit of the context CX is decoded, the adapter converts the two stored indexes into a probability table Qe, using two lookup tables running in parallel. Once the decoder decodes the pixel, the final values ​​of the probability table Qe, Index, and the high probability symbol MPS are selected and stored in the register. The adaptive decoding module provides these values ​​to the decoding unit to decode the current pixel in the decoding stage. Like the encoder, the adaptive decoding module updates the context CX second register CX and the internal register when necessary.

[0117] In some embodiments, Figure 4 As shown, in the arithmetic decoding unit, the arithmetic operation and the logic operation performed by the second register A and the second register C are as follows:

[0118] A temp =A-Qe (1)

[0119] A<2*Qe (4)

[0120] C high -A temp <0 (7)

[0121] C high_temp =C high -A temp (6)

[0122] Among them, A is the value assigned to the second register A, C high Chigh -2 .

[0123] In some embodiments, Figure 4 As shown in the figure, decompression is a reversible process of compression. Since it is a binary image compression, its value has only two possibilities: 0 and 1. Therefore, the pixel value is restored by selecting the high probability symbol MPS of the process value and its non-value. The output of the decision maker is used to select the pixel restoration and the value probability Qe of the probability table Qe in the module at this level and the selection output of the relevant register value in the SCD processing process.

[0124] The decision maker receives input data from multiple modules, including the probability Qe value after specific processing (such as left shift, etc.) and various values ​​from other related modules. Its core function is to make accurate comparison and comprehensive analysis of these input data.

[0125] By performing operations such as subtraction, the decision maker can determine the numerical differences and relationships between different data. Based on the preset rules and logic, the decision maker makes key decisions based on these comparisons and calculations.

[0126] For example, if the probability Qe value meets certain conditions after subtraction and comparison with a certain threshold, the decision maker will trigger a series of instructions to pass the data to a specific module (such as an adaptive module) to adjust the subsequent operating mode and parameters of the system.

[0127] In some other embodiments, when combined with an inline 1-bit shifter for renormalization, A is the value assigned to the second register A, and the new value of the second register A may be:

[0128] A=A temp

[0129] A=A temp <<1

[0130] A=Qe<<1

[0131] A=A<<1

[0132] The high bit of the second register C is Chigh -2 The value of is C high , Chigh -2 Possible new values ​​are:

[0133] C high =C high <<1

[0134] C high =C high_temp <<1

[0135] C high =C high <<8

[0136] Thanks to Clow -2 and Chigh -2 represents a different part of the second register C, so when performing a left shift operation, Clow -2 The most significant bit in the Chigh -2The 8-bit shift operation is only used to initialize the second register C at the beginning of each stripe. In addition to determining the appropriate selection of new value assignments in the second register C and the second register A, the decision logic in the decoder also specifies the color of the destination pixel and whether the data in the context CX memory is updated.

[0137] In some implementations, the updating index value Index and the output probability value Qe are implemented as follows: based on the input old index value Index, a NLPS-I lookup table, an NMPS-I lookup table, an NLPS-Qe lookup table, and an NMPS-Q lookup table are combined and created;

[0138] Output a new index value Index through the above NLPS-I lookup table and NMPS-I lookup table;

[0139] Through the above-mentioned NLPS-Qe lookup table and NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low-probability symbol LPS and the next high-probability symbol MPS defined in the original table is output, and then the final probability value Qe is selected through two multiplexers.

[0140] In some implementations, the first context CX memory is configured to be 32 bits wide and 256 bits deep; data is read from or written into the first context CX memory in an asynchronous manner or in a synchronous manner.

[0141] In some embodiments, the context CX construction module allows the use of three-line and two-line templates to generate a context CX.

[0142] In other embodiments, Figure 5 As shown, step 2) the JBIG arithmetic coding process consists of four stages: reading RAM, reading ROM, arithmetic coding, and renormalization. The resources used in the first three stages do not conflict, and the operations can overlap. That is, while the engine is executing the code stage for pixel n, it can also simultaneously execute the ROM reading stage for pixel n+1 and the RAM reading stage for pixel n+2; if the context CX of consecutive pixels is the same, a data dependency conflict may occur because the processing of previous pixels may change the index value Index and the value of the high-probability symbol MPS used to process subsequent pixels. The introduction of a data forwarding mechanism between different stages solves this problem because the engine can replace outdated data in the external memory with updated data inside the engine.

[0143] In other embodiments, Figure 6A method for updating the index value Index and the probability Qe value is shown, which effectively combines NLPS-I, NMPS-I, NLPS-Qe, and NMPS-Qe by creating four new tables. Taking the old index value I as input, the probability Qe value corresponding to the next small probability symbol NLPS and the next large probability symbol NMPS defined in the original table is output. The final value of the probability Qe value can then be selected using the same logic as for selecting the new index value I. The longer delay between the original input old index value I and the final output new probability value Qe and new index value I is eliminated by using a larger area. Each newly defined table returns a 16-bit probability Qe value, so its size is twice the size of the original probability Qe value table. In addition, two additional multiplexers are required to select the final value of the probability Qe value.

[0144] In some embodiments, the NLPS-I lookup table, the NMPS-I lookup table, the NLPS-Qe lookup table, and the NMPS-Qe lookup table are four groups of lookup tables obtained by combining the NLPS and ST columns, the NMPS and ST columns, the NLPS and LSZ columns, and the NMPS and LSZ columns in the PET table in standard ITU-T T.82.

[0145] In some embodiments, the CX construction unit supports context generation by three-line and two-line templates, and the reused contexts used to encode typical predicted pseudo pixels in different templates are mapped to the same value, thereby improving the flexibility and consistency of encoding.

[0146] In some embodiments, Figure 7 As shown, in the context CX construction module, the bits of the context CX in the three-row and two-row templates are assigned, and the numbers in each template box identify the number of bits allocated in the context CX; in order to facilitate the selection of the memory address when accessing the context CX memory, the least significant two bits in the context CX are assigned to the two pixels in the template immediately before the target pixel, and the second bit of the context CX is assigned to the adaptive pixel.

[0147] In some embodiments, Figure 8 As shown, the adaptive pixel is in the default position, but the assignment of the second bit in the context CX follows the movement of the adaptive pixel in the template. The difference between the two templates affects the minimum number of bits in the context CX. When switching between three-line and two-line templates, the unit only changes the assignment of bits 7 to 9 in the context CX.

[0148] In some embodiments, Fig. 9 and Fig.10As shown, the reused context CX used to encode typical predicted pseudo pixels in both templates must be mapped to the same value 0011100101. The context CX construction module implements three buffers for storing pixels; these three buffers represent three rows in the three-row template and only save the active part of the image; since the complete row is not stored, most pixels in the image are read into the module multiple times; to minimize memory access, one of the buffers is inactive when using two-row templates. When encoding stripes, the context CX construction module first reads 16 pixels of each row in the template into the buffer, and then, when the template moves each pixel in the image, it moves the pixels through the buffer; additional pixels are read into the buffer when necessary. To simplify the design, the context CX construction module synchronizes all read requests. The reference row buffer is 19 and 21 bits long. The current row buffer is 22 bits long in the encoder and 128 bits long in the decoder. The current row buffer length in the decoder is necessary for the movement of adaptive pixels. In addition to acting as a template, the current row buffer in the decoder also acts as the output buffer of the engine. The context CX construction module writes data to memory after every 16 pixels are decoded. Two 16-bit counters track the current X and Y position of the strip and are updated after each pixel in the strip is processed.

[0149] In some implementations, the encoding unit uses a multiplexer to select the final assignments to the first register A and the first register C.

[0150] In some embodiments, in the arithmetic coding, in the carry select adder, the 16-bit addition Clow+A temp Decision C temp The lower 16 bits of the carry select adder select value Chigh or Chigh+1 as C temp The upper 12 digits.

[0151] In some other embodiments, the context CX construction link under typical prediction enablement: the reused context for encoding typical prediction pseudo pixels must be mapped to the same value 0011100101; the context CX construction module implements three buffers for storing pixels, which represent three rows in the three-row template and only save the active part of the image; most pixels in the image are read into the module multiple times without storing complete rows; in order to minimize memory access, one of the buffers is inactive when using a two-row template; when encoding a stripe, the context CX construction module first reads 16 pixels of each row in the template into the buffer. Move pixels through the buffer. Additional pixels are read into the buffer when necessary; This unit synchronizes all read requests. The reference line buffer is 19 and 21 bits long. The current line buffer is 22 bits long in the encoder and 128 bits long in the decoder. The current line buffer length in the decoder is necessary for adaptive pixel movement. In addition to acting as a template, the current line buffer in the decoder also acts as the output buffer of the engine. The context CX construction module writes data to memory after every 16 pixels are decoded. Two 16-bit counters track the current X and Y position of the strip and are updated after processing each pixel in the strip. Specific implementation method 2:

[0153] A JBIG arithmetic coding and decoding system of the present invention is a system based on the JBIG arithmetic coding and decoding method of the above-mentioned specific implementation mode 1, and the above-mentioned system comprises: a context CX construction module, a QM encoder, and a decoder, wherein the QM encoder comprises an adaptive coding module and an encoding unit, and the above-mentioned decoder comprises an adaptive decoding module and a decoding unit;

[0154] The above-mentioned adaptive encoding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector. The above-mentioned encoding unit is configured with a first register A and a first register C. The above-mentioned adaptive decoding module is configured with a context CX register and 2 multiplexers. The above-mentioned decoding unit is configured with a second register A and a second register C.

[0155] In some embodiments, the context CX construction module is configured to: tell the QM encoder to perform the INITENC process at the beginning of each strip; when INITENC is completed, the context CX construction module prepares to generate the context CX and pixel D for the first pixel of the image, and tells the QM encoder to perform the ENCODE process; after encoding all pixels in the stripe, the context CX construction module instructs the QM encoder to perform the FLUSH process; when the FLUSH process ends, the encoding of the stripe is completed, and the compressed pixel SCD is obtained.

[0156] The present invention is described by the above-mentioned specific embodiments and specific implementations, and those skilled in the art should understand that various changes and equivalent substitutions can be made to the present invention without departing from the scope of the present invention. The parts not described in detail in the present specification are well-known technologies to those skilled in the art. In addition, various modifications can be made to the present invention for specific situations or specific circumstances without departing from the scope of this new use. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims of the present invention.

Claims

1. A JBIG arithmetic coding and decoding method, characterized in that: The method is implemented based on the architecture of a QM encoder and a decoder, wherein the QM encoder includes an adaptive encoding module and an encoding unit, and the decoder includes an adaptive decoding module and a decoding unit; The method comprises: step 1) generating context CX, step 2) JBIG arithmetic coding process and step 3) JBIG arithmetic decoding process; the step 2) is composed of step S2-1: processing flow of adaptive coding module and step S2-2: processing flow of coding unit, and the step 3) is composed of step S3-1 processing flow of adaptive decoding module and step S3-2 processing flow of decoding unit; The step 1) generates a context CX, including: a context CX construction module reads pixels in an image strip from a memory to generate a 12-bit context CX and a pixel to be encoded D; In the step 2), the step S2-1: adaptive coding module processing flow includes: After receiving the request for pixel encoding, the adaptive coding module reads the address from the context CX with a decimal value and stores it in the first context CX memory; then performs simplified reading to generate a 7-bit valid context CX, generates an index value Index with the decimal value corresponding to the valid context CX, and uses the index value Index as the write address to store the context CX, the valid context CX and the index value Index in the first context CX memory; The first selector reads the index value Index and the high-probability symbol MPS corresponding to the given context CX from the lookup table of the first context CX memory, and the first selector determines whether to update the index value Index according to the first determination rule, and then outputs the updated or unupdated new index value Index, and selects the new high-probability symbol MPS corresponding to the new index value Index, and outputs the new index value Index, the new high-probability symbol MPS and the probability table Qe; and then the second selector determines the index value Index, the high-probability symbol MPS and the probability table Qe to be fed back to the encoding unit for arithmetic encoding; The first determination rule is: determine whether the target pixel is a high-probability symbol; if the target pixel is a high-probability symbol, do not update the index value Index, and directly output the index value Index; if the target pixel is not a high-probability symbol, update the index value Index, and output a new index value Index; In the step 2), the step S2-1: encoding unit processing flow includes: The pixel D to be encoded, the high probability symbol MPS, the index value Index and the probability table Qe transmitted by the adaptive encoding module are arithmetic encoded; Secondly, it is determined whether the first register A and the first register C need to be renormalized. The probability table Qe assigns A to the first register A, and the A corresponds to the low probability symbol LPS; and when A=A<<1, the renormalization stage is executed; the renormalization stage doubles the values ​​of the first register C and the first register A until A is greater than 0x8000; Next, perform the arithmetic coding; the arithmetic coding includes: the probability table Qe is doubled by shifting left through a 1-bit shifter, and the first register A and the first register C perform arithmetic operations and logical operations, and then are updated to the first register A and the first register C; finally, after encoding all the pixels in the strip, the QM encoder executes the FLUSH process to output the compressed pixel SCD; The precisions of the first register C and the first register A are 28 bits and 16 bits respectively. The first register C is divided into two parts, Clow and Chigh, where Clow represents the lower 16 bits of the first register C and Chigh represents the higher 12 bits of the first register C; At the end of each strip arithmetic coding, the flush of the first register C executed includes a CLEARBITS process of clearing the trailing bits in the compressed data stream to zero. The CLEARBITS process is: calculate TEMP = (A - 1 + C) & 0xffff0000 = A - 1 + Clow, compare TEMP < C, and check the carry of the calculation; if the comparison TEMP < C is true, the carry is 0; if the comparison TEMP < C is false, the carry is 1 or Clow = 0; Wherein, A is the assignment of the first register A, and C is the assignment of the first register C.

2. The JBIG arithmetic coding and decoding method according to claim 1, characterized in that: In the arithmetic coding, the arithmetic operations and logical operations performed by the first register C and the first register A are as follows: TO temp =A-Qe (1) C temp =C+A temp (2) A temp <Yes (3) A < 2 * Qe (4) Wherein, A is the assignment of the first register A, and C is the assignment of the first register C; the implementation of the formula (4) takes precedence over the formula (3), and the addition operation in the formula (2) is implemented as a carry-select adder.

3. The JBIG arithmetic coding and decoding method according to any one of claims 1 to 2, characterized in that: In the step 3), the step S3-1: the processing flow of the adaptive decoding module includes: reading the first 8 bits of the context CX from the context CX register as the address, and decoding the pixel value corresponding to the 9th bit in the context CX; when decoding the last bit of the context CX, there are two index values, Index0 and Index1, corresponding to two most-probable symbols, MPS0 and MPS1 respectively, which are converted into two probability tables Qe running in parallel; The two index values Index0, Index1, the two most-probable symbols MPS0, MPS1, the pixel SCD to be decoded, and the decoding unit feedback signal jointly output a new index value Index and a new most-probable symbol MPS through a multiplexer; the two probability tables Qe running in parallel, the pixel SCD to be decoded, and the decoding unit feedback signal jointly output a new probability table Qe through another multiplexer; at the same time, update the context CX of the context CX register; In the step 3), the step S3-2: the processing flow of the decoding unit includes: the pixel SCD to be decoded, the new most-probable symbol MPS, and the new probability table Qe are subjected to renormalization or arithmetic decoding; The precision of the second register C and the second register A in the decoding unit are 24 bits and 16 bits respectively. The second register C is divided into Clow -2 and Chigh -2 Two parts, and Clow -2 Indicates the lower 8 bits of the second register C, Chigh -2 Represents the upper 16 bits of the second register C; and Clow -2 Used only to read the incoming compressed data stream, shifting it to the high bit while doing the renormalization; In the arithmetic decoding, the new probability table Qe is shifted left to achieve doubling, and the second register A is shifted left to perform arithmetic and logical operations; when initializing the second register C at the beginning of each stripe, an 8-bit shift is performed, and only Chigh -2 Perform arithmetic and logical operations; finally, restore the original pixel D.

4. The JBIG arithmetic coding and decoding method according to claim 3, characterized in that: In the arithmetic decoding unit, the arithmetic operations and logical operations performed by the second register A and the second register C are as follows: TO temp =A-Qe (1) A < 2 * Qe (4) C high -A temp <0 (7) C high_temp =C high -A temp (6) Where A is the value assigned to the second register A, C high Chigh -2 .

5. The JBIG arithmetic coding and decoding method according to claim 4, characterized in that: The updating index value Index and the output probability value Qe are implemented as follows: Based on the input old index value Index, the NLPS-I lookup table, the NMPS-I lookup table, the NLPS-Qe lookup table and the NMPS-Q lookup table are combined and created; Output a new index value Index through the NLPS-I lookup table and the NMPS-I lookup table; Through the NLPS-Qe lookup table and the NMPS-Q lookup table, a 16-bit probability value Qe corresponding to the next low-probability symbol LPS and the next high-probability symbol MPS defined in the original table is output, and then the final probability value Qe is selected through two multiplexers.

6. The JBIG arithmetic coding and decoding method according to claim 5, characterized in that: The first context CX memory is configured to be 32 bits wide and 256 bits deep; data is read from the first context CX memory asynchronously or written into the first context CX memory synchronously.

7. The JBIG arithmetic coding and decoding method according to claim 6, characterized in that: The encoding unit uses a multiplexer to select the final assignments to the first register A and the first register C.

8. The JBIG arithmetic coding and decoding method according to claim 7, characterized in that: In the arithmetic coding, in the carry select adder, the 16-bit addition Clow+A temp Decision C temp The lower 16 bits of the carry select adder select value Chigh or Chigh+1 as C temp The upper 12 digits.

9. A JBIG arithmetic coding and decoding system, characterized in that The system is a system based on the JBIG arithmetic coding and decoding method according to any one of claims 1 to 8, the system comprising: a context CX construction module, a QM encoder, and a decoder, the QM encoder comprising an adaptive coding module and an encoding unit, the decoder comprising an adaptive decoding module and a decoding unit; The adaptive encoding module is configured with a first context CX register, a first context CX memory, a first selector, and a second selector; the encoding unit is configured with a first register A and a first register C; the adaptive decoding module is configured with a context CX register and 2 multiplexers; and the decoding unit is configured with a second register A and a second register C.

10. The JBIG arithmetic coding and decoding system according to claim 9, characterized in that: The context CX construction module is configured to: tell the QM encoder to perform the INITENC process at the beginning of each strip; when INITENC is completed, the context CX construction module prepares to generate the context CX and pixel D for the first pixel of the image, and tells the QM encoder to perform the ENCODE process; after encoding all pixels in the stripe, the context CX construction module instructs the QM encoder to perform the FLUSH process; when the FLUSH process ends, the encoding of the stripe is completed, and the compressed pixel SCD is obtained.

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