Preparation method and device of local isolation oxide layer device structure

Abstract

The invention provides a preparation method and device for a local isolation oxide layer device structure, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: determining a target etching reagent for etching a silicon oxynitride layer according to the comparison of the continuous etching workload of phosphoric acid and a preset workload threshold value, according to the target etching reagent, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer and the target loss thickness of the pad oxide layer, phosphoric acid etching time and hydrofluoric acid etching time are calculated respectively, and etching of the device film layer is completed according to the time. The complex change of the etching rate of new and old phosphoric acid to the film layer in the preparation process of the isolation oxide layer device structure is considered, the target loss thickness of the pad oxide film layer in the etching process is combined, the etching time of different acids to the film layer is determined economically and efficiently through the scheme, and accurate control over the thickness of the pad oxide layer is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing process technology, and in particular to a method and apparatus for preparing a local isolation oxide layer device structure. Background Art

[0002] LOCOS (LOCal Oxidation of Silicon) is a commonly used device isolation technology in CMOS (Complementary Metal Oxide Semiconductor) silicon process. It realizes the selective oxidation of silicon by using silicon nitride as a mask. Specifically, in the process of local oxidation of silicon, the area to be isolated is opened by photolithography and etching, and the isolation area is oxidized by a thermal oxidation process to form an isolation structure. Subsequently, high-temperature phosphoric acid is used as a cleaning etchant to remove the silicon nitride of the mask layer to obtain a device structure with isolation function.

[0003] In the process of locally isolating and oxidizing to form a semiconductor device structure, a complex reaction process is involved on the surface of the mask layer silicon nitride, and a new oxide film layer is formed in the process. The film layer structure of the device from top to bottom is a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer, and a silicon substrate. In the process of further forming the isolation structure, in order to effectively remove the mask layer to obtain a locally isolated oxidized device structure, the conventional practice is to use hydrofluoric acid to remove the silicon oxide layer, use hydrofluoric acid or phosphoric acid to remove the silicon oxynitride layer, and use excess phosphoric acid to remove the silicon nitride layer. However, due to the reaction of new and old phosphoric acids with nitrogen oxides, the silicon nitride layer is not completely removed. The etching rate of the silicon film layer varies greatly, and excessive etching of the silicon nitride layer by the phosphoric acid etching agent will cause excessive etching of the remaining silicon oxide film layer (i.e., the pad oxide layer) in the active area, so that the thickness of the remaining pad oxide layer does not meet the requirements, affecting the subsequent process. Therefore, according to the use of phosphoric acid and the etching rate of the silicon oxynitride layer during the current process, it is particularly important to select a suitable target etching agent to etch the silicon oxynitride layer. Selecting a suitable target etching agent to etch the silicon oxynitride layer can ensure that the etching is completed in the shortest time without film residue, while ensuring that the thickness of the remaining pad oxide layer meets the requirements. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide at least a method and apparatus for preparing a local isolation oxide layer device structure, by considering the influence of new and old phosphoric acid on the phosphoric acid etching rate to determine which etching reagent to use to etch the silicon oxynitride layer, and then obtain the etching time of phosphoric acid and hydrofluoric acid reagents, which can improve the production efficiency to the target limit, reduce the excessive etching of the pad oxide layer during the etching process, thereby avoiding affecting the subsequent ion implantation process.

[0005] This application mainly includes the following aspects:

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a local isolation oxide layer device structure, comprising: providing a wafer treated by a thermal oxidation process, wherein an oxide isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate are stacked in sequence from top to bottom in the wafer; measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the thickness of the silicon oxynitride layer; respectively determining a first etching rate of a hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of a hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of a phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, wherein the third etching rate and the fifth etching rate vary with the amount of continuous phosphoric acid etching, and the phosphoric acid continuous etching workload varies. The amount is the product of the cumulative number of wafers etched starting from the phosphoric acid etching and the time required for phosphoric acid etching a single wafer; the target loss thickness of the pad oxide layer in the continuous etching process is obtained; the phosphoric acid continuous etching workload is compared with the preset workload threshold, and the target etching reagent is determined according to the comparison result, the target etching reagent is the reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent; according to the target etching reagent, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness, the target loss thickness, the phosphoric acid continuous etching workload and the etching rate, the phosphoric acid etching time and the hydrofluoric acid etching time are calculated respectively; the phosphoric acid reagent and the hydrofluoric acid reagent are used to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0007] In a possible implementation, the target etching reagent is determined in the following manner: if the phosphoric acid continuous etching workload is less than a preset workload threshold, the phosphoric acid reagent is used as the target etching reagent; if the phosphoric acid continuous etching workload is greater than or equal to the preset workload threshold, the hydrofluoric acid reagent is used as the target etching reagent, and the preset workload threshold is 1500 min.

[0008] In a possible embodiment, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon oxynitride layer, the etching time of the phosphoric acid reagent on the silicon nitride layer, and the etching time of the phosphoric acid reagent on the pad oxide layer, wherein the phosphoric acid etching time and the hydrofluoric acid etching time are determined in the following manner: if the target etching reagent is the phosphoric acid reagent, the etching time of the hydrofluoric acid reagent on the silicon oxide layer is determined according to the thickness of the silicon oxide layer, the first etching rate and the first excess etching coefficient; the etching time of the phosphoric acid reagent on the silicon oxynitride layer is determined according to the thickness of the silicon nitride layer and the third etching rate; the etching time of the phosphoric acid reagent on the silicon nitride layer is determined according to the thickness of the silicon nitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and the second excess etching coefficient; the etching time of the phosphoric acid reagent on the pad oxide layer is determined according to the target loss thickness corresponding to the pad oxide layer and the fifth etching rate.

[0009] In a possible implementation manner, the etching time of the hydrofluoric acid reagent etching the silicon oxide layer is determined by the following formula:

[0010] T(HF1)=(X / E a )×n1

[0011] In the formula, T(HF1) represents the etching time of the hydrofluoric acid reagent etching the silicon oxide layer, X represents the thickness of the silicon oxide layer, Ea represents the first etching rate, and n1 represents the first excess etching coefficient.

[0012] In a possible implementation, the etching time of the phosphoric acid reagent on the silicon oxynitride layer, the etching time of the phosphoric acid reagent on the silicon nitride layer, and the etching time of the phosphoric acid reagent on the pad oxide layer are determined by the following formula:

[0013]

[0014] In this formula, T(HPO1) represents the etching time of phosphoric acid reagent on the silicon oxynitride layer, M represents the thickness of the silicon oxynitride layer, E1 represents the third etching rate of phosphoric acid reagent on the silicon oxynitride layer, T(HPO2) represents the etching time of phosphoric acid reagent on the silicon nitride layer, Y represents the thickness of the silicon nitride layer, and E brepresents the fourth etching rate, n2 represents the second excess etching coefficient, T(HPO3) represents the etching time of the phosphoric acid reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, and E2 represents the fifth etching rate of the phosphoric acid reagent on the pad oxide layer, wherein E1=f1(x), f1(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxynitride layer changing with the continuous phosphoric acid etching workload, the continuous phosphoric acid etching workload x is substituted into f1(x), and the third etching rate E1 of the phosphoric acid reagent on the silicon oxynitride layer is obtained, E2=f2(x), f2(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer changing with the continuous phosphoric acid etching workload, the continuous phosphoric acid etching workload is substituted into f2(x), and the fifth etching rate E2 is obtained.

[0015] In a possible implementation, the phosphoric acid etching time also includes a total phosphoric acid etching time for etching the wafer using a phosphoric acid reagent, wherein the total phosphoric acid etching time T(HPO) is determined by the following formula:

[0016] T(HPO)=T(HPO1)+T(HPO2)+T(HPO3).

[0017] In a possible embodiment, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer and the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon nitride layer and the etching time of the phosphoric acid reagent on the pad oxide layer, wherein the phosphoric acid etching time and the hydrofluoric acid etching time are determined in the following manner: if the target etching reagent is the hydrofluoric acid reagent, the etching time of the hydrofluoric acid reagent on the silicon oxide layer is determined according to the thickness of the silicon oxide layer, the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, and the first excess etching coefficient; the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer is determined according to the thickness of the silicon oxynitride layer and the second etching rate; the etching time of the phosphoric acid reagent on the silicon nitride layer is determined according to the thickness of the silicon nitride layer, the fourth etching rate of the phosphoric acid reagent on the silicon nitride, and the second excess etching coefficient; the etching time of the phosphoric acid reagent on the pad oxide layer is determined according to the target loss thickness corresponding to the pad oxide layer and the fifth etching rate.

[0018] In a possible implementation, the phosphoric acid etching time and the hydrofluoric acid etching time are determined by the following formula:

[0019]

[0020] In the formula, T(HF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, X represents the thickness of the silicon oxide layer, Ea represents the first etching rate, and n1 represents the first excess etching coefficient; T(HF2) represents the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer, M represents the thickness of the silicon oxynitride layer, and Ec represents the second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer; T(HPO2) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, Y represents the thickness of the silicon nitride layer, Eb represents the fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n2 represents the second excess etching coefficient; T(HPO3) represents the etching time of the phosphoric acid reagent on the pad oxide layer. Etching time, S represents the target loss thickness of the pad oxide layer, E2 represents the fifth etching rate of the phosphoric acid reagent on the pad oxide layer, wherein E1=f1(x), f1(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxynitride layer changing with the continuous phosphoric acid etching workload, the continuous phosphoric acid etching workload is substituted into f1(x), and the third etching rate E1 of the phosphoric acid reagent on the silicon oxynitride layer is obtained, E2=f2(x), f2(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer changing with the continuous phosphoric acid etching workload, the continuous phosphoric acid etching workload is substituted into f2(x), and the fifth etching rate E2 is obtained.

[0021] In a possible implementation, the phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent, and the hydrofluoric acid etching time also includes the total hydrofluoric acid etching time for etching the wafer using the hydrofluoric acid reagent.

[0022] The total phosphoric acid etching time T(HPO) and the total hydrofluoric acid etching time T(HF) are determined by the following formula:

[0023]

[0024] In a second aspect, an embodiment of the present application further provides a preparation device for a local isolation oxide layer device structure, the device comprising: a providing module for providing a wafer treated by a thermal oxidation process, wherein an oxide isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom are formed in the wafer; a measuring module for measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the thickness of the silicon oxynitride layer; an etching rate determination module for respectively determining a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, wherein the third etching rate and the fifth etching rate vary with the amount of continuous phosphoric acid etching, and the phosphoric acid continuous etching workload varies. The amount is the product of the cumulative number of wafers etched starting from the phosphoric acid etching and the time required for phosphoric acid etching a single wafer; an acquisition module is used to obtain the target loss thickness of the pad oxide layer during the continuous etching process; a comparison module is used to compare the phosphoric acid continuous etching workload with a preset workload threshold, and determine the target etching reagent according to the comparison result, the target etching reagent is the reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent; a calculation module is used to calculate the phosphoric acid etching time and the hydrofluoric acid etching time according to the target etching reagent, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness, the target loss thickness, the phosphoric acid continuous etching workload and the etching rate; an etching module is used to use the phosphoric acid reagent and the hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0025] The present application provides a method and device for preparing a local isolation oxide layer device structure, including: determining a target etching reagent for etching the oxynitride layer according to the phosphoric acid continuous etching workload, calculating the phosphoric acid etching time and the hydrofluoric acid etching time according to the target etching reagent, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness, target loss thickness, phosphoric acid continuous etching workload and etching rate; using phosphoric acid reagent and hydrofluoric acid reagent, and completing the etching of the silicon oxide layer, silicon oxynitride layer, and silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time. The present application considers the influence of the complex changes of phosphoric acid new and old acid on the film layer etching rate on the wafer etching process during the preparation of the isolation oxide layer device structure, and combines the target loss thickness of the pad oxide layer film layer during the etching process, and economically and efficiently determines the optimal etching time of the etching reagent that makes the pad oxide layer thickness loss within the expected loss range, avoids excessive etching of the pad oxide layer, and realizes precise control of the pad oxide layer thickness, thereby reducing the damage to the wafer due to excessive loss of the pad oxide layer in the subsequent ion implantation process.

[0026] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are specifically cited below and described in detail with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 A schematic diagram of a silicon local oxidation process provided by an embodiment of the present application is shown;

[0029] Figure 2 A schematic diagram of a silicon nitride removal process provided in an embodiment of the present application is shown;

[0030] Figure 3 A flow chart showing a method for preparing a local isolation oxide layer device structure provided by an embodiment of the present application is shown;

[0031] Figure 4 A schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application is shown;

[0032] Figure 5 A trend chart showing the change in etching rate of silicon oxynitride by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid multiplied by the time required for phosphoric acid to etch a single wafer);

[0033] Figure 6 A graph showing a variation trend of the etching rate of silicon oxide by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid multiplied by the time required for phosphoric acid to etch a single wafer);

[0034] Figure 7 A functional module diagram of a device for preparing a local isolation oxide layer device structure provided by an embodiment of the present application is shown;

[0035] Figure 8 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0036] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art, under the guidance of the content of the present application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0037] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0038] Silicon local oxidation is a commonly used device isolation technology in CMOS silicon process. It realizes the selective oxidation of silicon by using silicon nitride as a mask. Figure 1 , Figure 1 FIG. 1 is a schematic diagram of a silicon local oxidation process provided by an embodiment of the present application. Figure 1 As shown in B1 in the figure, a pad oxide layer 105 and a silicon nitride layer 104 are first grown on a silicon substrate 106. As shown in B2, the region to be isolated is opened by photolithography and etching, and the region to be isolated is oxidized by a thermal oxidation process to form an oxidized isolation structure 101. The oxidized isolation structure 101 is composed of silicon oxide. A silicon nitride oxide layer 103 and a silicon oxide layer 102 are formed on the silicon nitride layer 104. Figure 1 Not shown, hydrofluoric acid is then used as an etchant to remove the silicon oxide layer 102, hydrofluoric acid or phosphoric acid is used to remove the silicon oxynitride layer 103, and high-temperature phosphoric acid is used as an etchant to remove the silicon nitride layer 104 to obtain a device structure with isolation function as shown in B4.

[0039] See also Figure 2 , Figure 2 FIG. 1 is a schematic diagram of a silicon nitride removal process provided in an embodiment of the present application. Figure 1 and Figure 2As shown, in the process of forming the oxidation isolation structure 101 shown in B2~B3, in the process of oxidizing the isolation area through a thermal oxidation process, the silicon nitride layer 104 is affected by the thermal oxidation process, and a silicon oxide layer 102 is formed on the upper surface of the silicon nitride layer 104. A very thin silicon oxynitride layer 103 is formed between the silicon oxide layer 102 and the silicon nitride layer 104. Hydrofluoric acid is a conventional reagent for etching silicon oxide, and phosphoric acid is a conventional reagent for etching silicon nitride. Both hydrofluoric acid and phosphoric acid can form an etching effect on silicon oxynitride.

[0040] like Figure 1 In the process of removing the silicon nitride layer 104 shown in B3-B4, the conventional method of removing the silicon nitride layer 104 is to first use hydrofluoric acid to remove the silicon oxide layer 102 formed on the surface of the silicon nitride layer, then rinse off the hydrofluoric acid with water, and then use phosphoric acid to remove the silicon nitride layer 104, and finally rinse off the phosphoric acid with water.

[0041] In the process of using phosphoric acid to etch away the silicon nitride layer 104, the conventional practice is to remove the silicon nitride layer 104 with excessive phosphoric acid. However, facts show that in the process of using excessive (50-100% over-etching) phosphoric acid to etch the silicon nitride layer 104, excessive use of etching reagents will cause etching of the pad oxide layer 105. In the prior art, since it is impossible to control the thickness loss of the pad oxide layer 105, excessive etching of the pad oxide layer 105 often occurs. Since the thickness of the pad oxide layer 105 will directly affect the subsequent ion implantation process of the semiconductor device, once the thickness of the pad oxide layer 105 does not meet the requirements of the ion implantation process, it will further affect the electrical properties of the semiconductor device.

[0042] Based on this, the embodiment of the present application provides a method and device for removing a silicon nitride layer based on a silicon local oxidation process. By considering the cumulative use time of phosphoric acid at the beginning of the process, different etching reagents are used to remove the silicon nitride layer, the overall etching time is reduced to improve the overall etching efficiency, and the excessive etching of the remaining silicon oxide layer is reduced, and the impact of the subsequent ion implantation process on the electrical properties of the device is reduced, as follows:

[0043] See also Figure 3 , Figure 3 A flow chart showing a method for preparing a local isolation oxide layer device structure provided by an embodiment of the present application is shown. Figure 4 , Figure 4 FIG. 1 shows a schematic diagram of a wafer structure obtained after a thermal oxidation process provided by an embodiment of the present application. Figure 3 and Figure 4 As shown, the method provided in the embodiment of the present application comprises the following steps:

[0044] S100, providing a wafer that has been processed by a thermal oxidation process.

[0045] An oxidation isolation structure 101 and a silicon oxide layer 102 , a silicon oxynitride layer 103 , a silicon nitride layer 104 , a pad oxide layer 105 and a silicon substrate 106 stacked in sequence from top to bottom are formed in the wafer.

[0046] S200, measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the thickness of the silicon oxynitride layer.

[0047] The thickness of the silicon oxide layer is the thickness corresponding to the silicon oxide layer 102 , and the thickness of the silicon nitride layer is the thickness corresponding to the silicon nitride layer 104 .

[0048] S300, respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer.

[0049] The third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer.

[0050] S400, obtaining a target loss thickness of the pad oxide layer during continuous etching.

[0051] The phosphoric acid continuous etching workload is the current continuous etching workload of the phosphoric acid reagent.

[0052] S500, comparing the phosphoric acid continuous etching workload with a preset workload threshold, and determining a target etching reagent according to the comparison result.

[0053] The target etching reagent is a reagent selected to remove the silicon oxynitride layer 103 , and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent.

[0054] The target etching reagent is a reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent.

[0055] S600, calculating phosphoric acid etching time and hydrofluoric acid etching time respectively according to target etching reagent, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness, target loss thickness, phosphoric acid continuous etching workload and etching rate.

[0056] S700, using a phosphoric acid reagent and a hydrofluoric acid reagent, and completing the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0057] In the local isolation oxidation technology, the silicon nitride layer 104 on the wafer undergoes the following reactions during the thermal oxidation process:

[0058] Si3 N4(s)+3 / 2O2(g)→3SiO(g)+2N2(g)------A.1

[0059] Si3 N4(s)+3O2(g)→3SiO2(g)+2N2(g)------A.2

[0060] Si3 N4(s)+5O2(g)→3SiO2(g)+4NO(g)------A.3

[0061] 4Si3 N4(s)+3O2(g)→6Si2N2O(g)+2N2(g)------A.4

[0062] It can be seen from the chemical equations A.1 to A.3 that during the process of forming an oxidation isolation structure by the thermal oxidation process of the silicon nitride layer 104, the surface of the silicon nitride layer 104 is affected by the thermal process oxidation of silicon oxide, and a silicon oxide layer 102 is formed on the surface of the silicon nitride layer 104. It can be seen from the chemical equation A.4 that under certain temperature conditions (for example, controlling the temperature between 700°C and 1180°C) on the surface of the silicon nitride layer 104 that is thermally oxidized by oxygen O2 or hydrogen H2, an interface layer, namely a silicon oxynitride layer 103, can be formed between the silicon oxide layer 102 and the silicon nitride layer 104. The silicon oxynitride layer 103 is a conversion layer of the interface of silicon nitride during the oxidation process. In the prior art, phosphoric acid is reused, and its effective components gradually change with use. Therefore, the etching rate of the film layer also changes with use.

[0063] In the prior art solution, in the process of removing the silicon nitride layer 104, hydrofluoric acid is first used to remove the silicon oxide layer 102, and then phosphoric acid is used to remove the silicon nitride layer 104. Considering that the silicon oxynitride layer 103 formed between the silicon nitride layer 104 and the silicon oxide layer 102 can be etched using hydrofluoric acid or phosphoric acid, the etching rates of hydrofluoric acid or phosphoric acid on the silicon oxynitride layer 103 are inconsistent, which will result in different etching times.

[0064] In addition, since the component of the pad oxide layer 105 is silicon oxide, during the process of using a phosphoric acid reagent to over-etch the silicon nitride layer 104, the phosphoric acid will etch the pad oxide layer 105. Since the thickness of the pad oxide layer 105 directly affects the subsequent ion implantation process, and in the prior art, due to the excessive etching of phosphoric acid, the remaining thickness of the pad oxide layer 105 cannot be determined, which easily causes the remaining thickness of the pad oxide layer 105 to fail to meet the requirements of the subsequent ion implantation process, thereby affecting the electrical properties of the semiconductor device.

[0065] Based on this, in steps S100 to S700 of the present application, since the etching effect of the phosphoric acid reagent is affected by the new and old acids of the phosphoric acid, as the continuous phosphoric acid etching workload increases, the corresponding etching effect of the phosphoric acid reagent will gradually decrease. Based on this, the present application compares the continuous phosphoric acid etching workload with the preset workload threshold, based on the etching effect that can be achieved by the phosphoric acid reagent, clarifies the target etching reagent for removing the silicon nitride layer 104, combines the target etching reagent and the thickness of the silicon oxide layer 102, the thickness of the silicon nitride layer 104, the thickness of the silicon oxynitride layer 103, the target loss thickness S, the continuous phosphoric acid etching workload and the etching rate, clarifies the phosphoric acid etching time and the hydrofluoric acid etching time, thereby avoiding excessive etching of the thickness of the pad oxide layer 105, reducing the impact of the subsequent ion implantation process on the electrical properties of the device, and the preset workload threshold is 1500 min (minutes).

[0066] In a preferred embodiment, in step S200, the silicon nitride layer 104, the silicon oxynitride layer 103 and the silicon oxide layer 102 are measured and processed respectively to obtain the silicon oxide layer thickness X, the silicon nitride layer thickness Y and the silicon oxynitride layer thickness M, wherein the value range corresponding to the silicon oxynitride layer thickness M is generally Generally take The unit of length is angstrom.

[0067] In step S300, the analysis of the use of phosphoric acid reagent and hydrofluoric acid reagent shows that the first etching rate Ea of the hydrofluoric acid reagent on the silicon oxide layer 102, the fourth etching rate Eb of the phosphoric acid reagent on the silicon nitride layer 104, and the second etching rate Ec of the hydrofluoric acid reagent on the silicon oxynitride layer 103 are generally conventional and stable, and can be obtained in advance through testing. Generally, the second etching rate (angstroms / minute).

[0068] Specifically, it is also necessary to determine the phosphoric acid continuous etching workload x corresponding to the new phosphoric acid reagent. The phosphoric acid continuous etching workload x is the product of the cumulative number of etched wafers calculated from the start of the new phosphoric acid reagent and the time required for phosphoric acid to etch a single wafer. The phosphoric acid continuous etching workload x reflects the newness of the phosphoric acid. The phosphoric acid continuous etching workload x = the time required for phosphoric acid to etch a single wafer × the cumulative number of etched wafers.

[0069] In a preferred embodiment, in step S400, a target loss thickness S corresponding to the pad oxide layer 105 is also determined, and the target loss thickness S is determined according to actual needs.

[0070] In a preferred embodiment, step S500 includes:

[0071] If the phosphoric acid continuous etching workload is less than the preset workload threshold, the phosphoric acid reagent is used as the target etching reagent; if the phosphoric acid continuous etching workload is greater than or equal to the preset workload threshold, the hydrofluoric acid reagent is used as the target etching reagent.

[0072] In one example, the preset workload threshold can be set to 1500 min, and the phosphoric acid continuous etching workload corresponding to the phosphoric acid reagent is pre-gained and fed back by the host computer.

[0073] In a preferred embodiment, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon oxynitride layer 103, the etching time of the phosphoric acid reagent on the silicon nitride layer 104 and the etching time of the phosphoric acid reagent on the pad oxide layer 105.

[0074] In a preferred embodiment, step S600 includes:

[0075] If the target etching reagent is a phosphoric acid reagent, the etching time of the hydrofluoric acid reagent for etching the silicon oxide layer 102 is determined according to the thickness of the silicon oxide layer 102, the first etching rate Ea and the first excess etching coefficient n1; the etching time of the phosphoric acid reagent for the silicon nitride oxide layer 103 is determined according to the thickness of the silicon oxynitride layer 103 and the third etching rate E1; the etching time of the phosphoric acid reagent for etching the silicon nitride layer 104 is determined according to the thickness of the silicon nitride layer 104, the fourth etching rate Eb of the phosphoric acid reagent for the silicon nitride layer 104 and the second excess etching coefficient n2; the etching time of the phosphoric acid reagent for the pad oxide layer 105 is determined according to the target loss thickness S corresponding to the pad oxide layer 105 and the fifth etching rate E2.

[0076] Preferably, the first over-etching coefficient n1 and the second over-etching coefficient n2 are usually set to 1.2-2, and can be set in advance according to actual needs.

[0077] In a specific embodiment, when the target etching reagent is a phosphoric acid reagent, the etching time T(HF1) for etching the silicon oxide layer 102 by the hydrofluoric acid reagent is determined by the following formula:

[0078] T(HF1)=(X / E a )×n1

[0079] In another specific embodiment, the etching time T(HPO1) of the phosphoric acid reagent on the silicon oxynitride layer 103, the etching time T(HPO2) of the phosphoric acid reagent on the silicon nitride layer 104, and the etching time T(HPO3) of the phosphoric acid reagent on the pad oxide layer 105 are determined by the following formula:

[0080]

[0081] In one example,

[0082] In the formula, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon oxynitride layer, M represents the thickness of the silicon oxynitride layer, and E1 represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer.

[0083] T(HPO2) represents the etching time of the phosphoric acid reagent on the silicon nitride layer, Y represents the thickness of the silicon nitride layer, Eb represents the fourth etching rate, and n2 represents the second excess etching coefficient.

[0084] T(HPO3) represents the etching time of the phosphoric acid reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, and E2 represents the fifth etching rate of the phosphoric acid reagent on the pad oxide layer.

[0085] Wherein, E1=f1(x), f1(x) represents the functional expression of the etching rate of phosphoric acid reagent on the silicon oxynitride layer changing with the continuous etching workload of phosphoric acid. Substituting the continuous etching workload x of phosphoric acid into f1(x), the third etching rate E1 of phosphoric acid reagent on the silicon oxynitride layer is obtained.

[0086] E2=f2(x), where f2(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer as the phosphoric acid continuous etching workload changes. Substituting the phosphoric acid continuous etching workload into f2(x), the fifth etching rate E2 is obtained.

[0087] In one specific embodiment, see Figure 5 , Figure 5 The trend diagram of the change of the etching rate of silicon oxynitride by a phosphoric acid reagent provided in an embodiment of the present application with the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched from the beginning of phosphoric acid and the time required for phosphoric acid to etch a single wafer) is shown. Figure 5 As shown, the horizontal axis is the phosphoric acid continuous etching workload x, the time unit is min (minutes), and the vertical axis represents the phosphoric acid reagent on the silicon oxynitride etching rate, the etching rate unit is (angstroms / minute), L1 represents the first curve of the third etching rate changing with the phosphoric acid continuous etching workload x, and the function expression f1(x)=10 is created from the first curve L1 7 x 2 -0.0013x+2.983, substituting the phosphoric acid continuous etching workload x into f1(x), the third etching rate E1 of the phosphoric acid reagent on the silicon oxynitride layer 103 under the phosphoric acid continuous etching workload x can be obtained.

[0088] Figure 5 The red line in the middle represents the second etching rate Ec of hydrofluoric acid reagent on silicon oxynitride. The second etching rate Ec is constant. Depend on Figure 5It can be seen that when the third etching rate of phosphoric acid on silicon oxynitride is equal to the second etching rate Ec, the corresponding continuous etching workload of phosphoric acid is xa. When the continuous etching workload of phosphoric acid corresponding to the phosphoric acid reagent is less than xa, the etching rate of the phosphoric acid reagent on silicon oxynitride is greater than that of the hydrofluoric acid reagent on silicon oxynitride. When the continuous etching workload of phosphoric acid corresponding to the phosphoric acid reagent is greater than xa, the etching rate of the phosphoric acid reagent on silicon oxynitride is less than that of the hydrofluoric acid reagent on silicon oxynitride.

[0089] See also Figure 6 , Figure 6 The graph shows the change trend of the etching rate of silicon oxide by a phosphoric acid reagent provided in an embodiment of the present application as a function of the cumulative usage of phosphoric acid (the product of the cumulative number of wafers etched starting from phosphoric acid and the time required for phosphoric acid to etch a single wafer). Figure 6 As shown, the horizontal axis is the continuous phosphoric acid etching workload x, that is, the product of the cumulative number of etched wafers and the time required for phosphoric acid etching each wafer unit x since the phosphoric acid was newly acidized, and the vertical axis represents the etching rate of phosphoric acid reagent on silicon oxide, and the unit of etching rate is L2 represents the second curve of the etching rate of phosphoric acid reagent on silicon oxide as the phosphoric acid continuous etching workload changes. The function expression corresponding to the fifth etching rate E2 created by the second curve L2 is f2(x)=9×10 8 x 2 -0.0007x+1.5945, because the composition of the pad oxide layer is silicon oxide, therefore, the phosphoric acid continuous etching workload x is substituted into f2(x)=9×10 8 x 2 -0.0007x+1.5945, the fifth etching rate E2 of the pad oxide layer by the phosphoric acid reagent under the phosphoric acid continuous etching workload x can be obtained.

[0090] In addition, the phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent. When the target etching reagent is the phosphoric acid reagent, the total phosphoric acid etching time T(HPO) is:

[0091] T(HPO)=T(HPO1)+T(HPO2)+T(HPO3).

[0092] In another preferred embodiment, the hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102 and the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer 103, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon nitride layer 104 and the etching time of the phosphoric acid reagent on the pad oxide layer 105.

[0093] In a preferred embodiment, step S500 further includes:

[0094] If the target etching agent is a hydrofluoric acid agent, the etching time T(HF1) for the hydrofluoric acid agent to etch the silicon oxide layer 102 is determined according to the thickness X of the silicon oxide layer 102, the first etching rate Ea of the hydrofluoric acid agent to the silicon oxide layer 102, and the first excess etching coefficient n1.

[0095] The etching time T(HF2) for the hydrofluoric acid reagent to etch the silicon oxynitride layer 103 is determined according to the silicon oxynitride layer thickness M and the second etching rate Ec.

[0096] The etching time T(HPO2) for the phosphoric acid reagent to etch the silicon nitride layer 104 is determined according to the thickness Y of the silicon nitride layer 104, the fourth etching rate Eb of the phosphoric acid reagent on silicon nitride, and the second excess etching coefficient n2.

[0097] According to the target loss thickness S of the pad oxide layer 105 and the fifth etching rate E2, the etching time T(HPO3) of the phosphoric acid reagent on the pad oxide layer 105 is determined.

[0098] Preferably, the etching time of the hydrofluoric acid reagent on the silicon oxide layer 102 and the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer 103 are determined by the following formula, and the phosphoric acid etching time includes the phosphoric acid reagent etching time on the silicon nitride layer 104 and the phosphoric acid reagent etching time on the pad oxide layer 105:

[0099]

[0100] In this formula, the fifth etching rate E2 is determined by f2(x) and the phosphoric acid continuous etching workload x, which will not be elaborated here.

[0101] In addition, the phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent, and the hydrofluoric acid etching time also includes the total hydrofluoric acid etching time for etching the wafer using the hydrofluoric acid reagent.

[0102] The total etching time T(HPO) for phosphoric acid and T(HF) for hydrofluoric acid is determined by the following formula:

[0103]

[0104] In one embodiment, it is assumed that the thickness of the silicon oxide layer 102 formed by oxidation of silicon nitride is determined by measuring The thickness of silicon nitride layer 104 The first etching rate of the hydrofluoric acid reagent on the silicon oxide layer 102 The fourth etching rate of the silicon nitride layer 104 is The first overetching coefficient n1=1.3, the second overetching coefficient n2=1.3, and the target loss thickness of the pad oxide layer 105 Thickness of silicon oxynitride layer 103 Preset workload threshold = 1500min.

[0105] By the method provided in the present application, when the phosphoric acid continuous etching workload x corresponding to the phosphoric acid reagent is 700 min, the third etching rate E1 of the phosphoric acid reagent on the silicon oxynitride layer 103 is greater than the second etching rate Ec of the hydrofluoric acid reagent on the silicon oxynitride layer 103. At this time, the phosphoric acid reagent is used as the target etching reagent to etch the silicon oxynitride layer 103, and finally the total hydrofluoric acid etching time T(HF)=3.99 min and the total phosphoric acid etching time T(HPO)=36.13 min are obtained.

[0106] When the phosphoric acid continuous etching workload x=1800min, at this time, the third etching rate E1 of the phosphoric acid reagent on the silicon oxynitride layer 103 is ≤ the second etching rate Ec of the hydrofluoric acid reagent on the silicon oxynitride layer 103, and the hydrofluoric acid reagent is used as the target etching reagent to etch the silicon oxynitride layer 103, and the total hydrofluoric acid etching time T(HF)=14.30min, and the total phosphoric acid etching time T(HPO)=34min.

[0107] Based on the same application concept, the embodiment of the present application also provides a wafer etching device corresponding to a wafer etching method provided in the above embodiment. Since the principle of solving the problem by the device in the embodiment of the present application is similar to that of a wafer etching method in the above embodiment of the present application, the implementation of the device can refer to the implementation of the method, and the repeated parts will not be repeated.

[0108] See also Figure 7 , Figure 7 The functional module diagram of a device for preparing a local isolation oxide layer device structure provided in an embodiment of the present application is shown. The device includes:

[0109] A module 800 is provided for providing a wafer after a thermal oxidation process, wherein an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate are formed in the wafer.

[0110] The measurement module 810 is used to measure the wafer to determine the thickness of the silicon oxide layer, the silicon nitride layer and the silicon oxynitride layer.

[0111] The etching rate determination module 820 is used to respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, wherein the third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer.

[0112] The acquisition module 830 is used to acquire the target loss thickness of the pad oxide layer during the continuous etching process.

[0113] The comparison module 840 is used to compare the phosphoric acid continuous etching workload with a preset workload threshold, and determine the target etching reagent based on the comparison result. The target etching reagent is the reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent.

[0114] The calculation module 850 is used to calculate the phosphoric acid etching time and the hydrofluoric acid etching time according to the target etching reagent, silicon oxide layer thickness, silicon nitride layer thickness, silicon oxynitride layer thickness, target loss thickness, phosphoric acid continuous etching workload and etching rate.

[0115] The etching module 860 is used to use a phosphoric acid reagent and a hydrofluoric acid reagent to etch the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

[0116] Based on the same application idea, please refer to Figure 8 , Figure 8 The schematic diagram of the structure of an electronic device provided by an embodiment of the present application is shown. The electronic device 900 includes: a processor 910, a memory 920 and a bus 930, the memory 920 stores machine-readable instructions executable by the processor 910, when the electronic device 900 is running, the processor 910 and the memory 920 communicate through the bus 930, and the machine-readable instructions are executed by the processor 910 when running, as in any of the steps of a method for preparing a local isolation oxide layer device structure provided in the above embodiments.

[0117] Based on the same application concept, an embodiment of the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of a method for preparing a local isolation oxide layer device structure provided in any of the above embodiments are executed.

[0118] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0119] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0120] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0121] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, etc., various media that can store program codes.

[0122] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a local isolation oxide layer device structure, characterized in that: The method comprises: Providing a wafer after being processed by a thermal oxidation process, wherein an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom are formed in the wafer; Measuring the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, and the thickness of the silicon oxynitride layer; Respectively determine a first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, a second etching rate of the hydrofluoric acid reagent on the silicon oxynitride layer, a third etching rate of the phosphoric acid reagent on the silicon oxynitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a fifth etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer, wherein the third etching rate and the fifth etching rate vary with the phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of etched wafers calculated from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; Obtaining a target loss thickness of the pad oxide layer during a continuous etching process; Comparing the phosphoric acid continuous etching workload with a preset workload threshold, and determining a target etching reagent according to the comparison result, wherein the target etching reagent is a reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent; According to the target etching reagent, the thickness of the silicon oxide layer, the thickness of the silicon nitride layer, the thickness of the silicon oxynitride layer, the target loss thickness, the phosphoric acid continuous etching workload and the etching rate, respectively calculating the phosphoric acid etching time and the hydrofluoric acid etching time; Phosphoric acid reagent and hydrofluoric acid reagent are used to complete the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

2. The method according to claim 1, characterized in that The target etching reagent is determined by: If the phosphoric acid continuous etching workload is less than the preset workload threshold, the phosphoric acid reagent is used as the target etching reagent; If the phosphoric acid continuous etching workload is greater than or equal to the preset workload threshold, the hydrofluoric acid reagent is used as the target etching reagent; The preset workload threshold is 1500 minutes.

3. The method according to claim 1, characterized in that The hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon oxynitride layer, the etching time of the phosphoric acid reagent on the silicon nitride layer, and the etching time of the phosphoric acid reagent on the pad oxide layer. Wherein, the phosphoric acid etching time and the hydrofluoric acid etching time are determined by the following method: If the target etching reagent is a phosphoric acid reagent, determining the etching time of the hydrofluoric acid reagent to etch the silicon oxide layer according to the thickness of the silicon oxide layer, the first etching rate and the first excess etching coefficient; Determining an etching time of the silicon oxynitride layer by a phosphoric acid reagent according to the thickness of the silicon oxynitride layer and the third etching rate; Determining an etching time for the phosphoric acid reagent to etch the silicon nitride layer according to the thickness of the silicon nitride layer, a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and a second excess etching coefficient; The etching time of the pad oxide layer by the phosphoric acid reagent is determined according to the target loss thickness corresponding to the pad oxide layer and the fifth etching rate.

4. The method according to claim 3, characterized in that The etching time of the hydrofluoric acid reagent etching the silicon oxide layer is determined by the following formula: T(HF1)=(X / E a )×n1 In this formula, T(HF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, X represents the thickness of the silicon oxide layer, and E a represents the first etching rate, and n1 represents the first excess etching coefficient.

5. The method according to claim 3, characterized in that: The etching time of the phosphoric acid reagent on the silicon oxynitride layer, the etching time of the phosphoric acid reagent on the silicon nitride layer, and the etching time of the phosphoric acid reagent on the pad oxide layer are determined by the following formula: In the formula, T(HPO1) represents the etching time of the phosphoric acid reagent on the silicon oxynitride layer, M represents the thickness of the silicon oxynitride layer, and E1 represents the third etching rate of the phosphoric acid reagent on the silicon oxynitride layer. T(HPO2) represents the etching time of the silicon nitride layer by phosphoric acid reagent, Y represents the thickness of the silicon nitride layer, E b represents the fourth etching rate, n2 represents the second excess etching coefficient, T(HPO3) represents the etching time of the phosphoric acid reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, E2 represents the fifth etching rate of the phosphoric acid reagent on the pad oxide layer, Wherein, E1=f1(x), f1(x) represents the functional expression of the etching rate of phosphoric acid reagent on the silicon oxynitride layer changing with the continuous phosphoric acid etching workload. Substituting the phosphoric acid continuous etching workload x into f1(x), the third etching rate E1 of phosphoric acid reagent on the silicon oxynitride layer is obtained. E2=f2(x), where f2(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer as the phosphoric acid continuous etching workload changes. Substituting the phosphoric acid continuous etching workload into f2(x), the fifth etching rate E2 is obtained.

6. The method according to claim 5, characterized in that The phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent. The total phosphoric acid etching time T(HPO) is determined by the following formula: T(HPO)=T(HPO1)+T(HPO2)+T(HPO3).

7. The method according to claim 1, characterized in that The hydrofluoric acid etching time includes the etching time of the hydrofluoric acid reagent on the silicon oxide layer and the etching time of the hydrofluoric acid reagent on the silicon oxynitride layer, and the phosphoric acid etching time includes the etching time of the phosphoric acid reagent on the silicon nitride layer and the etching time of the phosphoric acid reagent on the pad oxide layer. Among them, the phosphoric acid etching time and the hydrofluoric acid etching time are determined by the following method: If the target etching reagent is a hydrofluoric acid reagent, determining the etching time of the hydrofluoric acid reagent etching the silicon oxide layer according to the thickness of the silicon oxide layer, the first etching rate of the hydrofluoric acid reagent on the silicon oxide layer, and the first excess etching coefficient; Determining an etching time for a hydrofluoric acid reagent to etch the silicon oxynitride layer according to the thickness of the silicon oxynitride layer and the second etching rate; Determining an etching time for the phosphoric acid reagent to etch the silicon nitride layer according to the thickness of the silicon nitride layer, a fourth etching rate of the phosphoric acid reagent on silicon nitride, and a second excess etching coefficient; The etching time of the pad oxide layer by the phosphoric acid reagent is determined according to the target loss thickness corresponding to the pad oxide layer and the fifth etching rate.

8. The method according to claim 7, characterized in that The phosphoric acid etching time and the hydrofluoric acid etching time are determined by the following formula: In this formula, T(HF1) represents the etching time of the hydrofluoric acid reagent on the silicon oxide layer, X represents the thickness of the silicon oxide layer, and E a represents the first etching rate, n1 represents the first excess etching coefficient; T(HF2) represents the etching time of the silicon oxynitride layer by the hydrofluoric acid reagent, M represents the thickness of the silicon oxynitride layer, and E c represents a second etching rate of the silicon oxynitride layer by a hydrofluoric acid reagent; T(HPO2) represents the etching time of the silicon nitride layer by phosphoric acid reagent, Y represents the thickness of the silicon nitride layer, E b represents a fourth etching rate of the phosphoric acid reagent on the silicon nitride layer, and n2 represents a second excess etching coefficient; T(HPO3) represents the etching time of the phosphoric acid reagent on the pad oxide layer, S represents the target loss thickness of the pad oxide layer, E2 represents the fifth etching rate of the phosphoric acid reagent on the pad oxide layer, Wherein, E1=f1(x), f1(x) represents the functional expression of the etching rate of phosphoric acid reagent on the silicon oxynitride layer changing with the continuous etching workload of phosphoric acid. Substituting the continuous etching workload of phosphoric acid into f1(x), the third etching rate E1 of phosphoric acid reagent on the silicon oxynitride layer is obtained. E2=f2(x), where f2(x) represents the functional expression of the etching rate of the phosphoric acid reagent on the silicon oxide layer and the pad oxide layer as the phosphoric acid continuous etching workload changes. Substituting the phosphoric acid continuous etching workload into f2(x), the fifth etching rate E2 is obtained.

9. The method according to claim 8, characterized in that The phosphoric acid etching time also includes the total phosphoric acid etching time for etching the wafer using the phosphoric acid reagent, and the hydrofluoric acid etching time also includes the total hydrofluoric acid etching time for etching the wafer using the hydrofluoric acid reagent. The total phosphoric acid etching time T(HPO) and the total hydrofluoric acid etching time T(HF) are determined by the following formula:

10. A device for preparing a local isolation oxide layer device structure, characterized in that: The device comprises: A module is provided for providing a wafer after being processed by a thermal oxidation process, wherein the wafer is formed with an oxidation isolation structure and a silicon oxide layer, a silicon oxynitride layer, a silicon nitride layer, a pad oxide layer and a silicon substrate stacked in sequence from top to bottom; A measurement module, used to measure the wafer to determine the thickness of the silicon oxide layer, the thickness of the silicon nitride layer and the thickness of the silicon oxynitride layer; An etching rate determination module is used to respectively determine a first etching rate of a hydrofluoric acid reagent on a silicon oxide layer, a second etching rate of a hydrofluoric acid reagent on a silicon oxynitride layer, a third etching rate of a phosphoric acid reagent on a silicon oxynitride layer, a fourth etching rate of a phosphoric acid reagent on a silicon nitride layer, and a fifth etching rate of a phosphoric acid reagent on a silicon oxide layer and a pad oxide layer, wherein the third etching rate and the fifth etching rate vary with a phosphoric acid continuous etching workload, and the phosphoric acid continuous etching workload is the product of the cumulative number of wafers etched from the start of phosphoric acid etching and the time required for phosphoric acid etching a single wafer; An acquisition module, used for acquiring a target loss thickness of the pad oxide layer during a continuous etching process; A comparison module, used for comparing the phosphoric acid continuous etching workload with a preset workload threshold, and determining a target etching reagent according to the comparison result, wherein the target etching reagent is a reagent selected to remove the silicon oxynitride layer, and the target etching reagent is a hydrofluoric acid reagent or a phosphoric acid reagent; A calculation module, for respectively calculating the phosphoric acid etching time and the hydrofluoric acid etching time according to the target etching reagent, the silicon oxide layer thickness, the silicon nitride layer thickness, the silicon oxynitride layer thickness, the target loss thickness, the phosphoric acid continuous etching workload and the etching rate; The etching module is used to use a phosphoric acid reagent and a hydrofluoric acid reagent to complete the etching of the silicon oxide layer, the silicon oxynitride layer, and the silicon nitride layer of the wafer according to the phosphoric acid etching time and the hydrofluoric acid etching time.

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