Battery energy supply circuit and method based on RTC clock chip

Abstract

The invention relates to a battery energy supply circuit and method based on an RTC clock chip, and the circuit comprises an oscillator module, a power-on module, a low-voltage detection module and a power switching module, and the power switching module is used for switching between a main power supply and a standby power supply; the low-voltage detection module is used for monitoring the states of the voltage of the power source # imgabs0 # and the voltage of the standby power source # imgabs1 #, and when the voltage of the power source # imgabs2 # is lower than the reference voltage # imgabs3 #, the low-voltage detection module is connected with the power source switching module; the oscillator module is electrically connected with the low-voltage detection module and provides oscillation signals for the RTC clock chip. The circuit is divided into specific functional blocks by adopting a bottom-up method, the optimized modular circuit not only improves the flexibility and maintainability of design and facilitates independent optimization and test of each functional block, but also can be stably switched between a main power supply and a standby battery power supply, has a battery charging function and is convenient to use. And the design efficiency and the power management capability of the RTC clock chip are effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of power management, and in particular to a battery power supply circuit and method based on an RTC clock chip. Background Art

[0002] In the field of power management, especially for the application of real-time clock (RTC) chips, system stability and timing data protection are crucial. To achieve this goal, many single-chip RTC products use a dual power module design, which provides two power supply options to ensure seamless switching to the backup power supply when the main power fails, thereby maintaining continuous operation of the system. This dual power module not only has power failure detection and power switching functions, but also supports trickle charging, which is particularly suitable for battery-driven portable small devices.

[0003] With the development of technology, the operating voltage of MOS devices has been reduced to 2.5V to 1.0V to meet the demand for lower power consumption. However, in order to be compatible with old equipment, many systems still use a power supply voltage of 3.3V to 5.0V. This gap between the external power supply voltage and the internal operating voltage increases the RTC module's reliance on complex power management circuits to ensure voltage conversion and stable power supply. At present, the combination of power management chips with single-chip RTC products or built-in RTC modules has become an indispensable part of system design. For example, TI's ADP3405 power management chip can be used with its GSM processor to provide backup power to the processor's built-in RTC module through the RTC pin.

[0004] The widespread application of the system-on-chip (SoC) design concept has promoted the integration of more and more digital circuits, including RTC, on the same chip. This integration trend means that power management chips based on analog integrated circuit design will no longer be independent of the system architecture, but will be tightly integrated with the RTC module. In the future, the monolithic RTC and power subsystem are expected to be integrated into the same SoC chip, or more complex power management circuits will be used under smaller device processes to solve challenges such as compatibility and power consumption.

[0005] From an engineering perspective, these designs need to comprehensively consider factors such as process difficulty, R&D costs, and market demand. Therefore, when studying RTC design methods, paying attention to related power management systems will help improve the power management capabilities of existing clock chips to find a suitable balance between cost and reliability. In the current application environment, this balance is particularly important because it directly affects the performance and market competitiveness of the device.

[0006] Therefore, a battery power supply method and circuit based on an RTC clock chip are proposed. Summary of the invention

[0007] The present invention provides a battery power supply circuit and method based on an RTC (real-time clock) clock chip. The battery power supply circuit can smoothly switch between a main power supply and a backup battery power supply, and has a battery charging function, thereby improving the power management capability of an existing clock chip, and is suitable for electronic devices that have high requirements for power supply stability.

[0008] The present invention provides a battery power supply circuit based on an RTC clock chip, comprising an oscillator module, a power-on module, a low voltage detection module and a power switching module.

[0009] Power-on module: used to initialize the circuit when the power is turned on;

[0010] A power switching module, used for switching between a main power supply and a backup power supply;

[0011] Low voltage detection module, used to monitor the power supply V CC Voltage and backup power V BACKUP Voltage status, power supply V CC The voltage is lower than the reference voltage V PF When the power supply is switched on, it is connected to the power supply switching module;

[0012] The oscillator module is electrically connected to the low voltage detection module to provide an oscillation signal for the RTC clock chip;

[0013] The oscillator module includes: a crystal oscillator, a capacitor C0, a load capacitor C1, a load capacitor C2, a conductance g1, a conductance g2, a capacitor Cm, an inductance Lm and a resistor Rm, and satisfies g1+g2<(2πf0) 2 C1C2R m In this condition, g1 and g2 are used to represent the conductance values ​​of conductance g1 and conductance g2 respectively, f0 represents the oscillator frequency, C1 and C2 represent the capacitance values ​​of load capacitance C1 and load capacitance C2 respectively, and R m Indicates the resistance value of resistor Rm;

[0014] X1 is the input pin of the crystal oscillator, and X2 is the output pin of the crystal oscillator, which is used to set the resonant frequency;

[0015] Capacitor C0 is a feedback capacitor, and capacitor C0 is connected in parallel between input pin X1 and output pin X2;

[0016] The two load capacitors C1 and C2 are connected to the two ends of the crystal oscillator and then grounded, forming a resonant circuit with the crystal oscillator to form a frequency selection network;

[0017] Conductor g1 and capacitor C1 are connected in parallel to the input pin X1 of the crystal oscillator to form an input network, and the excitation signal of the oscillator module is input from the input pin X1;

[0018] Conductor g2 and capacitor C2 are connected in parallel to output pin X2 of the crystal oscillator to form an output network, and an oscillation signal is taken out from output pin X2;

[0019] The capacitor Cm, the inductor Lm and the resistor Rm are connected in series and connected between the input pin X1 and the output pin X2;

[0020] One end of the capacitor Cm is connected to the input pin X1 , and one end of the resistor Rm is connected to the output pin X2 , serving as an equivalent mechanical oscillation circuit.

[0021] In a further technical solution, the inverter and feedback resistor R F , inverter and feedback resistor R F In the RC circuit equivalent to the oscillator module, the feedback resistor R F It is connected between the input and output of the inverter and forms a feedback mechanism together with the crystal oscillator. The feedback resistor R F Used to ensure the DC bias stability of the inverter.

[0022] In a further technical solution, the two pins X1 and X2 of the crystal oscillator are respectively connected to the input and output of the inverter.

[0023] In a further technical solution, in the oscillator module, a multi-stage frequency division circuit is used to process the high-frequency signal generated by the oscillator step by step. The multi-stage frequency division circuit is connected by a structure composed of a static master-slave D flip-flop and a transmission gate, and the output of the previous stage is used as the input of the next stage; and the frequency division circuit is divided into three stages by segmented power supply, and the first stage frequency division circuit adopts a first working voltage V DD1 The input frequency of the first-stage frequency division circuit is the clock frequency; the second-stage frequency division circuit and the third-stage frequency division circuit use a voltage higher than the first working voltage V DD1 The second working voltage V DD2 , used to reduce the power consumption in the early stage; a buffer and a level conversion circuit are added after the third-stage frequency division circuit, and the buffer and the level conversion circuit adopt a voltage higher than the second working voltage V DD2 The third operating voltage V DD3 , the third working voltage V DD3 The operating voltage is 3.3V, which is used to achieve smooth signal transmission.

[0024] In a further technical solution, the power-on module includes a field effect transistor M1, a capacitor C and a Schmitt trigger, and the field effect transistor M1 and the capacitor C are respectively connected to the input end of the Schmitt trigger;

[0025] Field effect transistor M1 is used to control the power supply. When the power supply V CC When powered on, field effect transistor M1 works to monitor the power supply V CCVoltage;

[0026] Capacitor C is used to store power V CC The charge at power-on, V CC When turned on, capacitor C charges slowly and waits until the power supply V CC After the voltage stabilizes, a reset output signal is generated;

[0027] The Schmitt trigger is used to shape the input signal; when the power supply V CC When the voltage is stable, the reset output signal is pulled high to a high level, and the power-on module completes the initialization circuit and enters a normal working state.

[0028] In a further technical solution, the low voltage detection module includes: a first error amplifier A1 and a second error amplifier A2,

[0029] The positive input terminal of the first error amplifier A1 is connected to the power supply V CC The negative input terminal of the first error amplifier A1 is connected to the reference voltage. The first error amplifier A1 is used to compare the power supply V CC Voltage and reference voltage V PF The voltage difference between the power supply V CC The voltage is higher than the reference voltage V PF When the first error amplifier A1 outputs a high level, the power supply V CC The voltage is lower than the reference voltage V PF When the first error amplifier A1 outputs a low level signal, the low level signal serves as an emergency event indication and triggers the internal protection mechanism;

[0030] The positive input terminal of the second error amplifier A2 is connected to the power supply V CC The negative input terminal of the second error amplifier A2 is connected to the backup power supply V BACKUP The second error amplifier A2 is used to compare the power supply VCC voltage with the backup power supply V BACKUP The voltage difference between the voltage, power supply V CC The voltage is higher than the backup power supply V BACKUP When the voltage is high, the second error amplifier A2 outputs a first control signal, which is used to indicate that the power supply V CC Switch to backup power supply V BACKUP ; Power supply V CC The voltage is lower than the backup power supply V BACKUP When the voltage is high, the second error amplifier A2 outputs a second control signal, which is used to indicate that the power supply V CC Can switch to backup power supply V BACKUP .

[0031] In a further technical solution, the power switching module includes: a Pass tube M1, a Pass tube M2, a Pass tube M3, a Pass tube M4, a PMOS transistor MP and an NMOS transistor NP.

[0032] V DD1 Connect the Pass tube M1 and the Pass tube M2 to supply power to the Pass tube M1 and the Pass tube M2. The Pass tube M1 and the Pass tube M2 are used for power switching;

[0033] V DD2 Connect the Pass tube M3 and the Pass tube M4 to supply power to the Pass tube M3 and the Pass tube M4, and the Pass tube M3 and the Pass tube M4 are used for transmission and driving of control signals;

[0034] The PMOS transistor MP and the NMOS transistor NP form a high-driving force push-pull output structure. By alternately turning on the PMOS transistor MP and the NMOS transistor NP, a larger current output is provided to ensure that the Pass tube M1 and the Pass tube M2 can be turned on smoothly and the power supply can be switched quickly.

[0035] When the low voltage event signal is triggered, the switching control signal triggers the power switching action.

[0036] The present invention also provides a battery power supply method based on an RTC clock chip, which is applied to the battery power supply circuit as described above and includes the following steps:

[0037] S1. When the system is powered on, a reset signal is provided through the power-on module;

[0038] S2. Design an oscillator module to generate a stable oscillation signal;

[0039] S3, monitoring the power supply voltage through the low voltage detection module and outputting a signal when the voltage is lower than a preset threshold;

[0040] S4, switching between the main power supply and the backup power supply through the power switching module;

[0041] S5. Charge the battery.

[0042] In a further technical solution, the design of the oscillator module includes adopting a Pierce oscillator design, and specific capacitance and resistance values ​​satisfy the following formula: L m is the inductance of the inductor Lm, C1 and C2 are the capacitance of the load capacitor C1 and the load capacitor C2 respectively.

[0043] The beneficial effects of the present invention are:

[0044] 1. In the analog circuit design, the present invention adopts a "bottom-up" approach to divide the circuit into specific functional blocks, such as an oscillator module, a power-on module, a low-voltage detection module, and a power switching module. This optimized module circuit design not only improves the flexibility and maintainability of the design, and facilitates the independent optimization and testing of each functional block, but also can smoothly switch between the main power supply and the backup battery power supply, and has a battery charging function, effectively improving the power management capability of the existing RTC clock chip, and providing a basis for the product to find a suitable balance between cost and reliability, so as to ultimately effectively integrate into a complete system and improve design efficiency.

[0045] 2. In the design of the battery power supply circuit and method of the RTC clock chip, the present invention focuses on the dynamic power consumption of the frequency division circuit, and uses a multi-stage frequency division circuit to process the high-frequency signal generated by the oscillator step by step. Then, through the design of multiple frequency division stages and step-by-step changes in the operating frequency, the early power consumption is effectively reduced, and on the basis of meeting the low-power design requirements, the smooth transmission of the signal is effectively achieved. This strategy of the present invention gives priority to energy efficiency in the design process, ensuring that the circuit can significantly improve the overall energy efficiency while meeting the performance requirements, and adapt to the needs of modern low-power devices. Therefore, the present invention can effectively improve the power management capabilities of the RTC clock chip and efficiently achieve an ultra-low power design. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 It is a schematic diagram of AC small signal analysis of the oscillator;

[0047] Figure 2 It is the structure diagram of the power-on reset circuit;

[0048] Figure 3 This is the circuit structure diagram of the low voltage detection module;

[0049] Figure 4 It is a structural diagram of the power switching circuit;

[0050] Figure 5 It is the layout design flow chart of the real-time clock;

[0051] Figure 6 This is the output waveform of the oscillator start-up;

[0052] Figure 7 It is the simulation waveform of the power-on reset circuit;

[0053] Figure 8 It is a real-time clock simulation circuit layout design diagram. DETAILED DESCRIPTION

[0054] The embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0055] Example:

[0056] like Figure 1-Figure 7 As shown, a battery-powered circuit based on an RTC clock chip adopts a "bottom-up" approach. By dividing the circuit into specific functional blocks, the underlying circuits are designed separately. The main designed circuits include an oscillator module, a power-on module, a low-voltage detection module, and a power switching module. Finally, these functional blocks are merged to form a complete system.

[0057] 1. Oscillator module design:

[0058] The Pierce oscillator is used as the crystal resonant circuit. The NMOS tube M1 and PMOS tube M2 in the Pierce oscillator form a typical current source inverter (referred to as inverter). The output end is connected through the feedback resistor R F Connected to the input end, a basic amplification loop is formed. The crystal oscillator and two capacitors constitute a frequency selection network. Under the working conditions of the oscillation circuit, in order to produce an output waveform with a stable frequency, the amplitude balance and phase balance conditions must be met, that is: A(jω)F(jω)=1.

[0059] Where: A(jω) represents the gain of the basic amplifier circuit, and F(jω) represents the gain of the frequency selection network.

[0060] The frequency selection network generates a stable output through the amplification circuit of the sine wave of the specific frequency (32.768kHz in this design) selected by the crystal oscillator, while signals of other frequencies gradually attenuate because they cannot meet the phase balance condition.

[0061] At the same time, the AC small signal of the Pierce oscillator is designed, such as Figure 1 As shown, the two ports X1 and X2 of the oscillator are connected to its resonant branch and parasitic capacitance C0, and the oscillation passes through a transconductance of g M The active components and the two capacitors C1 and C2 are maintained, and the additional parasitic conductances g1 and g2 represent losses and should be minimized.

[0062] Under high frequency stability requirements, a larger and more stable equivalent capacitor C0 is needed, while low power consumption requirements require the circuit to operate within a smaller capacitance value, which creates a trade-off between stability and low power consumption.

[0063] The effect of circuit losses can be represented by g1 and g2. These losses are equivalent to increasing the series resistance R of the crystal. M In order to ensure that these losses have less impact on the overall performance than the losses in the quartz crystal itself, the following relationship must be satisfied: g1+g2<(2πf0) 2 C1C2R m .

[0064] More specifically, the oscillator module of this embodiment includes: a crystal oscillator, a capacitor C0, a load capacitor C1, a load capacitor C2, a conductance g1, a conductance g2, a capacitor Cm, an inductance Lm and a resistor Rm, and satisfies g1+g2<(2πf0) 2 C1C2R m In this condition, g1 and g2 are used to represent the conductance values ​​of conductance g1 and conductance g2 respectively, f0 represents the oscillator frequency, C1 and C2 represent the capacitance values ​​of load capacitance C1 and load capacitance C2 respectively, and R m Indicates the resistance value of resistor Rm;

[0065] X1 is the input pin of the crystal oscillator, and X2 is the output pin of the crystal oscillator, which is used to set the resonant frequency;

[0066] Capacitor C0 is a feedback capacitor, which is connected in parallel between the input pin X1 and the output pin X2 to compensate for frequency stability;

[0067] Two load capacitors C1 and C2 are connected to both ends of the crystal oscillator and then grounded, forming a resonant circuit with the crystal oscillator to form a frequency selection network. Load capacitors C1 and C2 are used to determine the frequency and adjustment stability of the oscillator module.

[0068] Conductor g1 and capacitor C1 are connected in parallel to the input pin X1 of the crystal oscillator to form an input network, and the excitation signal of the oscillator module is input from the input pin X1;

[0069] Conductor g2 and capacitor C2 are connected in parallel to output pin X2 of the crystal oscillator to form an output network, and an oscillation signal is taken out from output pin 2;

[0070] The capacitor Cm, the inductor Lm and the resistor Rm are connected in series and connected between the input pin X1 and the output pin X2 to adjust the quality of the input network and the output network;

[0071] One end of the capacitor Cm is connected to the input pin X1, and one end of the resistor Rm is connected to the output pin X2, as an equivalent mechanical oscillation circuit, which is used to define the resonant frequency and attenuation characteristics of the oscillator module.

[0072] Preferably, the oscillator module further includes an inverter and a feedback resistor R F , inverter and feedback resistor R F It is included in the RC circuit after the oscillator module is equivalent, and belongs to the existing oscillator module. Therefore, it is not marked in Figure 1 The feedback resistor R F It is connected between the input and output of the inverter and forms a feedback mechanism together with the crystal oscillator. The feedback resistor R F Used to ensure the DC bias stability of the inverter.

[0073] It is worth noting that in the oscillator module of this embodiment, a multi-stage frequency division circuit is preferably used to process the high-frequency signal generated by the oscillator step by step. The multi-stage frequency division circuit is connected by a structure composed of a static master-slave D flip-flop and a transmission gate, and the output of the previous stage is used as the input of the next stage; and the frequency division circuit is divided into three stages by segmented power supply, and the first stage frequency division circuit adopts a first working voltage V DD1 The input frequency of the first-stage frequency division circuit is the clock frequency; the second-stage frequency division circuit and the third-stage frequency division circuit use a voltage higher than the first working voltage V DD1 The second working voltage V DD2 , used to reduce the power consumption in the early stage; a buffer and a level conversion circuit are added after the third-stage frequency division circuit, and the buffer and the level conversion circuit adopt a voltage higher than the second working voltage V DD2 The third operating voltage V DD3 , the third working voltage V DD3 is a 3.3V working voltage, which is used to achieve smooth signal transmission. The first working voltage V DD1 and the second operating voltage V DD2 can be adjusted according to actual conditions and requirements. Preferably, the first working voltage V DD1 The working voltage used is about 2V, and the third working voltage V DD3 The standard operating voltage is 3.3V. DD2 The operating voltage used is greater than 2V and less than 3.3V.

[0074] Through such a design, a lower first operating voltage V is first used. DD1 , in order to reduce the power consumption during high-frequency operation, and preferably to raise the signal after 1:8 frequency division to the standard operating voltage level through a level converter until the third operating voltage V DD3 The standard operating voltage (i.e. 3.3V) is used to ensure the stability and reliability of signal processing. Therefore, this embodiment not only realizes the smooth transmission of signals, but also can maintain normal working state when the operating voltage of the first three frequency dividers is as low as about 2V, thus meeting the low power design requirements.

[0075] 2. Power-on module design:

[0076] The power-on module is a typical power-on reset circuit structure, such as Figure 2 As shown in the figure, the PMOS tube is a common MOS device, and its gate is grounded. When the system starts to power on, the drain potential of the PMOS is low, and the PMOS tube is generally in the saturation region; V GS With V CC A linear change occurs, so the PMOS can be regarded as a large resistor;

[0077] In the initial stage of circuit startup, capacitor C is designed to maintain a low potential state. This state is processed by the Schmitt trigger and the subsequent buffer circuit. The initial output is "1". During the power supply process, the capacitor is charged, and the accumulation of its voltage follows the integral relationship between current and time, which is specifically expressed as:

[0078]

[0079] Where: U C is the voltage across the capacitor, C is the capacitance, I C is the current flowing through the capacitor;

[0080] As the system gradually stabilizes, the increase in capacitor voltage causes the drain potential of the PMOS transistor to increase accordingly, causing the PMOS to enter its linear operating region. In this stage, due to the conductive properties of the PMOS, the current gradually decreases, while the voltage continues to rise gently.

[0081] When the voltage on the capacitor reaches the preset flip threshold of the Schmitt trigger, the power-on reset signal flips from "1" to "0". During the flipping process, a pulse signal with a specific duration is generated. The width of the pulse is affected by multiple factors, the most significant of which are the size of the PMOS transistor and the capacitance of the capacitor. The smaller the width-to-length ratio of the PMOS, the weaker its conductivity and the slower the charging process. At the same time, the larger the capacitance value, the longer the time required for charging. In this design, the power-on reset pulse width is set at 15μs.

[0082] 3. Low voltage detection module:

[0083] The low voltage monitoring module uses a dual error amplifier architecture to implement an accurate power status monitoring strategy, such as Figure 3 Specifically, the first error amplifier A1 is designated to monitor V CC Power-off sensitive point V FF The voltage change is used to instantly identify the main power supply V CC A power-down event occurs, once V CC When the voltage drops to the threshold, A1 outputs a low-level signal, which serves as an emergency indication and triggers the internal protection mechanism. The second error amplifier A2 is configured to compare V CC With backup power V BACKUP voltage level to generate a control signal that logically determines the need for a voltage from the main power supply V CC Seamless transition to backup power V BACKUP time, thereby ensuring the continuity and stability of the system power supply;

[0084] The comparator design with hysteresis characteristics is used to optimize the stability of the power monitoring system, especially to prevent false triggering caused by slight fluctuations in the power supply voltage when it is close to the set power-off threshold edge. By introducing a hysteresis threshold window of about 0.1V, it is ensured that when the power supply voltage fluctuates within this range, the low voltage alarm signal and the power switching control signal will not switch frequently, thereby avoiding unnecessary system interference and data loss;

[0085] The bias current source of the hysteresis comparator cleverly uses a bipolar junction transistor (BJT) to generate a current source with a positive temperature coefficient characteristic. The bias current source has the effect of simplifying the circuit structure, improving the adaptive adjustment capability of the current source, and effectively offsetting the impact of temperature changes on the comparator performance.

[0086] 4. Power switching circuit:

[0087] The power switching circuit mainly adopts a switching strategy based on voltage comparison logic, such as Figure 4 Specifically, when the voltage of the backup power supply is lower than the preset threshold value V FF When the backup power supply voltage is higher than the threshold V FF , main power supply voltage V CC Below the threshold V FF , a low-level event signal is needed to trigger the switching mechanism to protect the internal file resources of the system. In the design process of the present invention, V DD1 As the main power supply source for the internal digital circuit and oscillator circuit, the design dimensions of the Pass tubes M1 and M2 both adopt a larger width-to-length ratio to ensure sufficient current supply capacity for the system, while M3 and M4 adopt a smaller size.

[0088] In order to effectively drive the Pass tubes M1 and M2, a high-driving force push-pull output structure (composed of MP and MN transistors) is adopted. This structure optimizes the response speed and efficiency of the switching logic and ensures the speed and reliability of power switching.

[0089] In real-time clock design, a variety of methods are used to control power consumption, especially the dynamic power consumption of CMOS circuits and frequency division circuits. When designing the circuit, it is necessary to give priority to reducing the power consumption of this part, so as to improve the overall energy efficiency.

[0090] As a key component of system clock generation, the oscillation circuit has a low power consumption design which is crucial to improving overall energy efficiency. The circuit mainly consists of a crystal oscillator, load capacitors C1 and C2, an inverter, and a feedback resistor R F The inverter and resistor R F Together they form a feedback mechanism, and an external crystal oscillator is connected to the X1 and X2 pins to achieve oscillation.

[0091] In the process of low-power oscillator design, the first consideration is to reduce the operating voltage, and on this basis optimize the working state of the CMOS device. When the CMOS device works in the saturation region, its voltage and current parameters are as follows:

[0092]

[0093] I D = k′(W / L)(V GS -V T ) 2

[0094] Where: V OV is the voltage margin, that is, the gate-source voltage V GS With the threshold voltage V T The difference between the two, k is the transconductance parameter, which is proportional to the mobility, I D is the leakage current, W / L is the device width-to-length ratio;

[0095] According to the above CMOS transfer characteristic formula, at V OV When the value is small, by increasing the aspect ratio W / L and reducing the leakage current I D , so that the CMOS device can maintain good voltage transmission characteristics at low voltage and meet the operating frequency requirements. In order to utilize the above characteristics and achieve their functions, this embodiment also preferably connects an active resistor in parallel with each NMOS and PMOS tube to achieve the shunting of the working current and further reduce the power consumption.

[0096] That is to say, in the design of the RTC clock chip, this embodiment focuses on the dynamic power consumption of the frequency division circuit and reduces the power consumption through a variety of control methods. This strategy gives priority to energy efficiency in the design process, ensuring that the circuit significantly improves the overall energy efficiency while meeting the performance requirements, and adapts to the needs of modern low-power devices. This will be described in detail later.

[0097] This embodiment also provides a battery power supply method based on an RTC clock chip, which is applied to the battery power supply circuit as described above and includes the following steps:

[0098] S1. When the system is powered on, a reset signal is provided through the power-on module;

[0099] S2. Design an oscillator module to generate a stable oscillation signal;

[0100] S3, monitoring the power supply voltage through the low voltage detection module and outputting a signal when the voltage is lower than a preset threshold;

[0101] S4, switching between the main power supply and the backup power supply through the power switching module;

[0102] S5. Charge the battery.

[0103] The steps to design an oscillator module include taking a Pierce oscillator design and setting specific capacitor and resistor values ​​to meet the frequency stability requirements. The specific capacitor and resistor values ​​satisfy the following formula: L m is the inductance value of the inductor Lm, C1 and C2 are the capacitance values ​​of the load capacitor C1 and the load capacitor C2 respectively; in order to meet the requirements of the clock module for the frequency change of the input signal, a multi-stage frequency division circuit is used to process the high-frequency signal generated by the oscillator step by step. In view of the characteristics of many frequency division stages and gradually reduced operating frequency, the present invention adopts a segmented power supply strategy to optimize power consumption. The segmented power supply divides the frequency division circuit into two parts, a high frequency band and a low frequency band. The first three stages are high frequency bands, and a lower first operating voltage V is used. DD1 To reduce power consumption during high-frequency operation, the signal after 1:8 division is increased to the standard operating voltage level through a level converter. The low-frequency band includes a 12-level division circuit and uses a standard operating voltage (i.e. 3.3V) to ensure the stability and reliability of signal processing.

[0104] In the process of designing circuits in different frequency bands, a structure consisting of a static master-slave D flip-flop and a transmission gate is selected. The output of the previous stage is used as the input of the next stage. At the same time, considering the input-output relationship between each stage, the working voltage of each stage of the frequency division circuit is designed differently. Specifically, the first stage of the frequency division circuit adopts the lowest first working voltage V DD1 The input frequency of the first-stage frequency division circuit is the clock frequency; the second and third stages use a frequency higher than V DD1 The second working voltage V DD2 , effectively reducing the power consumption in the early stage; adding a buffer and level conversion circuit after the third-level frequency division, using a voltage higher than V DD2 The third operating voltage V DD3 (i.e. standard operating voltage) to achieve smooth signal transmission. When the operating voltage of the first three frequency dividers is as low as 2V, this design can still maintain normal working state and meet the low power design requirements.

[0105] Therefore, in the design of the battery power supply circuit and method of the RTC clock chip, this embodiment also focuses on the design of the dynamic power consumption of the frequency division circuit, and uses a multi-level frequency division circuit to process the high-frequency signal generated by the oscillator step by step, and then through the design of multiple frequency division levels and step-by-step changes in the operating frequency, the early power consumption is effectively reduced, and on the basis of meeting the low-power design requirements, the smooth transmission of the signal is also effectively achieved. This strategy of this embodiment gives priority to energy efficiency in the design process, ensuring that the circuit can significantly improve the overall energy efficiency while meeting the performance requirements, and adapt to the needs of modern low-power devices.

[0106] According to the circuit parameter requirements, we can design the layout of analog integrated circuits, design the graphics and size of components under specific process conditions, and through a comprehensive understanding of the circuit working principle and performance requirements, we can reasonably design the shape and size of components to ensure that the layout meets the design standards and improve the performance and reliability of integrated circuits;

[0107] According to the above-mentioned designed oscillator module, power-on module, low voltage detection module and power switching module circuits, it is necessary to reasonably design the layout of the real-time clock, such as Figure 5 As shown, the design process is as follows:

[0108] (1) Familiarity with processes and rules: First, in-depth study of the process technology required for the design, including the number of layout layers, design rules, process parameters (such as block resistance, capacitance, etc.), component graphics and size, and necessary verification files (DRC, LVS);

[0109] (2) Overall circuit planning: Carry out the overall layout of the board according to the front-end module planning, reasonably divide the digital and analog areas, determine the PAD position, sub-module layout and key connection paths (such as power and ground). In particular, for clock chips with strong power management functions, overall planning should be carried out with analog circuits as the core.

[0110] (3) Circuit layout and drawing: Detailed layout of analog circuits is carried out separately. The analog part adopts a full customization method and is completed step by step in the order of unit, module, and chip;

[0111] (4) Layout optimization and verification: Detailed adjustments and optimizations are made to the layout and routing to ensure that the overall layout is reasonable and the performance is optimal. During this process, DRC, LVS and other verifications are continuously performed to ensure that the design complies with process rules and electrical connection requirements until the final layout meets all design indicators and standards.

[0112] According to the above process, the layout design tool Virtuoso was used to design the various sub-modules of the analog part, and the overall picture of the real-time clock layout was obtained by merging them;

[0113] In order to better illustrate the effect of the present invention, a specific embodiment will be used for illustration below;

[0114] In the circuit design process, the parameters of the Pierce oscillator used are: =100pF, =500pF, =80Ω, and the simulation results of the Pierce oscillator are as follows: Figure 6 As shown in the figure, it can be seen that the waveform generated by the Pierce oscillator has a short start-up time and the waveform is stable at a duty cycle of 50%, which meets the design requirements of the real-time clock;

[0115] In this design, the power-on reset pulse width is set to 15μs, and the output voltage waveform of the power-on reset is as follows: Figure 7 As shown in the figure, the voltage of the real-time clock output during power-on reset is proportional to V CC Basically the same, after a period of time, it falls back to a low level. The actual pulse width is calculated to be about 15μs, with an error of 0.3μs from the set value, which meets the power-on reset design requirements of the real-time clock.

[0116] Each circuit with high power consumption is optimized and parameter adjusted one by one to effectively control the power consumption of the high-frequency circuit and ensure that the entire chip meets the goal of low-power design. For comparison, the similar product DS1339 from Maxim was selected and its power consumption was compared with that of this design. The results are shown in Table 1.

[0117] Table 1 Power consumption comparison results

[0118] Maximum dynamic current Quiescent Current Leakage Current DS1339 453.3μA 54.3μA 1.8μA This design 256.2μA 20.6μA 0.6μA

[0119] It can be seen from the table that the maximum dynamic current, static current and leakage current of the designed circuit are all smaller than those of the DS1339 chip, indicating that the designed circuit has lower power consumption.

[0120] like Figure 8 As shown: Finally, the layout design tool Virtuoso was used to design the various sub-modules of the analog part, and the real-time clock layout design was obtained by merging them.

[0121] The above embodiments only express the specific implementation of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A battery powered circuit based on an RTC clock chip, characterized in that: It includes an oscillator module, a power-on module, a low-voltage detection module, and a power switching module; A power-on module, used to initialize the circuit when the power is turned on; A power switching module, used for switching between a main power supply and a backup power supply; Low voltage detection module, used to monitor the power supply V CC Voltage and backup power V BACKUP Voltage status, power supply V CC The voltage is lower than the reference voltage V PF When the power supply is switched on, it is connected to the power supply switching module; The oscillator module is electrically connected to the low voltage detection module to provide an oscillation signal for the RTC clock chip; The oscillator module includes: a crystal oscillator, a capacitor C0, a load capacitor C1, a load capacitor C2, a conductance g1, a conductance g2, a capacitor Cm, an inductance Lm and a resistor Rm, and satisfies g1+g2<(2πf0) 2 C1C2R m In this condition, g1 and g2 are used to represent the conductance values ​​of conductance g1 and conductance g2 respectively, f0 represents the oscillator frequency, C1 and C2 represent the capacitance values ​​of load capacitance C1 and load capacitance C2 respectively, R m Indicates the resistance value of resistor Rm; X1 is the input pin of the crystal oscillator, and X2 is the output pin of the crystal oscillator, which is used to set the resonant frequency; Capacitor C0 is a feedback capacitor, and capacitor C0 is connected in parallel between input pin X1 and output pin X2; The two load capacitors C1 and C2 are connected to the two ends of the crystal oscillator and then grounded, forming a resonant circuit with the crystal oscillator to form a frequency selection network; Conductor g1 and capacitor C1 are connected in parallel to the input pin X1 of the crystal oscillator to form an input network, and the excitation signal of the oscillator module is input from the input pin X1; Conductor g2 and capacitor C2 are connected in parallel to output pin X2 of the crystal oscillator to form an output network, and an oscillation signal is taken out from output pin X2; The capacitor Cm, the inductor Lm and the resistor Rm are connected in series and connected between the input pin X1 and the output pin X2; One end of the capacitor Cm is connected to the input pin X1 , and one end of the resistor Rm is connected to the output pin X2 , serving as an equivalent mechanical oscillation circuit.

2. The battery power supply circuit based on the RTC clock chip according to claim 1, characterized in that: The oscillator module also includes an inverter and a feedback resistor R F , inverter and feedback resistor R F In the RC circuit equivalent to the oscillator module, the feedback resistor R F It is connected between the input and output of the inverter and forms a feedback mechanism together with the crystal oscillator. The feedback resistor R F Used to ensure the DC bias stability of the inverter.

3. The battery power supply circuit based on the RTC clock chip according to claim 2, characterized in that: The two pins X1 and X2 of the crystal oscillator are respectively connected to the input and output of the inverter.

4. The battery power supply circuit based on the RTC clock chip according to claim 1, characterized in that: In the oscillator module, a multi-stage frequency division circuit is used to process the high-frequency signal generated by the oscillator step by step. The multi-stage frequency division circuit is connected by a structure composed of a static master-slave D flip-flop and a transmission gate. The output of the previous stage is used as the input of the next stage. The frequency division circuit is divided into three stages through segmented power supply. The first stage frequency division circuit adopts the first working voltage V DD1 The input frequency of the first-stage frequency division circuit is the clock frequency; the second-stage frequency division circuit and the third-stage frequency division circuit use a voltage higher than the first working voltage V DD1 The second working voltage V DD2 , used to reduce the power consumption in the early stage; a buffer and a level conversion circuit are added after the third-stage frequency division circuit, and the buffer and the level conversion circuit adopt a voltage higher than the second working voltage V DD2 The third operating voltage V DD3 , the third working voltage V DD3 The operating voltage is 3.3V, which is used to achieve smooth signal transmission.

5. The battery power supply circuit based on the RTC clock chip according to claim 1, characterized in that: The power-on module includes a field effect transistor M1, a capacitor C and a Schmitt trigger, and the field effect transistor M1 and the capacitor C are respectively connected to the input end of the Schmitt trigger; Field effect transistor M1 is used to control the power supply. When the power supply V CC When powered on, field effect transistor M1 works to monitor the power supply V CC Voltage; Capacitor C is used to store power V CC The charge at power-on, V CC When turned on, capacitor C charges slowly and waits until the power supply V CC After the voltage stabilizes, a reset output signal is generated; The Schmitt trigger is used to shape the input signal; when the power supply V CC When the voltage is stable, the reset output signal is pulled high to a high level, and the power-on module completes the initialization circuit and enters a normal working state.

6. The battery power supply circuit based on the RTC clock chip according to claim 1, characterized in that: The low voltage detection module includes: a first error amplifier A1 and a second error amplifier A2; The positive input terminal of the first error amplifier A1 is connected to the power supply V CC The negative input terminal of the first error amplifier A1 is connected to the reference voltage. The first error amplifier A1 is used to compare the power supply V CC Voltage and reference voltage V PF The voltage difference between the power supply V CC The voltage is higher than the reference voltage V PF When the first error amplifier A1 outputs a high level, the power supply V CC The voltage is lower than the reference voltage V PF When the first error amplifier A1 outputs a low-level signal, the low-level signal serves as an emergency event indication and triggers the internal protection mechanism; The positive input terminal of the second error amplifier A2 is connected to the power supply V CC The negative input terminal of the second error amplifier A2 is connected to the backup power supply V BACKUP The second error amplifier A2 is used to compare the power supply VCC voltage with the backup power supply V BACKUP The voltage difference between the voltage, power supply V CC The voltage is higher than the backup power supply V BACKUP When the voltage is high, the second error amplifier A2 outputs a first control signal, which is used to indicate that the power supply V CC Switch to backup power supply V BACKUP ; Power supply V CC The voltage is lower than the backup power supply V BACKUP When the voltage is high, the second error amplifier A2 outputs a second control signal, which is used to indicate that the power supply V CC Can switch to backup power supply V BACKUP .

7. The battery power supply circuit based on the RTC clock chip according to claim 1, characterized in that: The power switching module includes: a Pass tube M1, a Pass tube M2, a Pass tube M3, a Pass tube M4, a PMOS transistor MP and an NMOS transistor NP; V DD1 Connect the Pass tube M1 and the Pass tube M2 to supply power to the Pass tube M1 and the Pass tube M2. The Pass tube M1 and the Pass tube M2 are used for power switching; V DD2 Connect the Pass tube M3 and the Pass tube M4 to supply power to the Pass tube M3 and the Pass tube M4, and the Pass tube M3 and the Pass tube M4 are used for transmission and driving of control signals; The PMOS transistor MP and the NMOS transistor NP form a high-driving force push-pull output structure. By alternately turning on the PMOS transistor MP and the NMOS transistor NP, a larger current output is provided to ensure that the Pass tube M1 and the Pass tube M2 can be turned on smoothly and the power supply can be switched quickly. When the low voltage event signal is triggered, the switching control signal triggers the power switching action.

8. A battery power supply method based on an RTC clock chip, characterized in that: The method is applied to a battery power supply circuit as claimed in any one of claims 1 to 7, and comprises the following steps: S1. When the system is powered on, a reset signal is provided through the power-on module; S2. Design an oscillator module to generate a stable oscillation signal; S3, monitoring the power supply voltage through the low voltage detection module and outputting a signal when the voltage is lower than a preset threshold; S4, switching between the main power supply and the backup power supply through the power switching module; S5. Charge the battery.

9. The battery energy supply method according to claim 8, characterized in that: The design of the oscillator module includes adopting a Pierce oscillator design, setting specific capacitance and resistance values ​​to meet the frequency f0 stability requirements, and the specific capacitance and resistance values ​​satisfy the following formula: L m is the inductance of the inductor Lm, C1 and C2 are the capacitance of the load capacitor C1 and the load capacitor C2 respectively.

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