Circuit substrate, processing method of circuit substrate, system-in-package substrate and processing method of system-in-package substrate

Abstract

The invention discloses a circuit substrate and a processing method thereof, and a system-in-package substrate and a processing method thereof. The processing method of the circuit substrate comprises the following steps: providing an insulating base layer and two composite copper layers; the insulating base layer is stacked between the ultrathin copper layers of the two composite copper layers and then pressed into a whole, and the carrier copper layer is removed to obtain a first intermediate plate; performing MSAP process treatment on the first intermediate plate to form a line set comprising an inner-layer line and an impedance prototype on the ultrathin copper layer; the inner-layer lines in the two groups of line sets are communicated, and the impedance rudiment is of a single-line coplanar impedance structure formed by an impedance line lengthening body and a peripheral copper body; after the preset part of the impedance line lengthening body and the inner-layer circuit are subjected to film covering protection, the exposed part of the impedance line lengthening body and the peripheral copper body are etched away to obtain the hypersensitive impedance; and removing the film to obtain the circuit substrate. According to the processing method, the packaging density and precision are improved, large-scale production of the circuit board product with the hypersensitive impedance is realized, and the yield of the hypersensitive impedance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a circuit substrate and a processing method thereof, a system-level packaging substrate and a processing method thereof. Background Art

[0002] With the development of society and science and technology, electronic products are becoming increasingly integrated. By integrating multiple functional components (such as microcontrollers, memory, RF modules, etc.) on the same packaging substrate, not only can close integration be achieved, signal transmission speed can be increased and latency can be reduced, but modules with different functions can also be customized according to different application scenarios, thereby improving the application performance of the packaging substrate while significantly reducing power consumption and saving packaging substrate space.

[0003] In order to make the package substrate meet the above technical requirements, a super-sensitive impedance is usually set on the package substrate. The super-sensitive impedance is a single-line non-coplanar impedance with very high precision requirements, and at least needs to meet the following technical requirements: impedance line width ≤ 40μm, impedance line length ≤ 10μm, impedance tolerance ≤ ±5%, etc. However, due to the current level of circuit board processing technology, it is difficult to achieve mass production of circuit board products with the super-sensitive impedance, and the yield of the super-sensitive impedance is also low, so it cannot meet the production needs well.

[0004] In view of this, the present invention is proposed. Summary of the invention

[0005] In order to overcome the above-mentioned defects, the present invention provides a circuit substrate and a processing method thereof, a system-level packaging substrate and a processing method thereof. The processing method is simple, reasonable and novel. On the one hand, the density and precision of the obtained circuit can be very high, which greatly improves the packaging density and precision. On the other hand, it also effectively solves the problem that the ultra-sensitive impedance is not easy to be supervised during the production and processing process, which not only realizes the large-scale production of circuit board products with ultra-sensitive impedance, but also effectively improves the yield of ultra-sensitive impedance, which well meets the market and production needs.

[0006] The technical solution adopted by the present invention to solve the technical problem is: a method for processing a circuit substrate, comprising:

[0007] Providing an insulating base layer and two composite copper layers, wherein the composite copper layer comprises a carrier copper layer and an ultra-thin copper layer detachably arranged on the carrier copper layer;

[0008] The insulating base layer is stacked between the two ultra-thin copper layers of the composite copper layer and pressed to form a whole, and then the carrier copper layer is completely removed to obtain a first intermediate plate;

[0009] The first intermediate board is subjected to MSAP process to form a circuit set including an inner layer circuit and an impedance prototype on the two ultra-thin copper layers of the first intermediate board respectively; wherein the inner layer circuits in the two groups of the circuit sets are connected, and the impedance prototype is a single-line coplanar impedance structure composed of an impedance line extension body and a peripheral copper body located next to the impedance line extension body;

[0010] After the preset part of the impedance line extension body and the inner layer circuit are coated for protection, the exposed part of the impedance line extension body and the outer copper body are etched away, so that the preset part of the impedance line extension body is formed into a super-sensitive impedance with a single-line non-coplanar impedance structure; the film is then removed to obtain a circuit substrate with the inner layer circuit and the super-sensitive impedance.

[0011] As a further improvement of the present invention, the MSAP process includes laser drilling through holes, copper plating, lamination pretreatment, plating resist photosensitive film, exposure, development, pattern electroplating, film stripping and flash etching on the first intermediate plate in sequence;

[0012] Among them, the vertical electroplating method is adopted when the first intermediate plate is subjected to pattern electroplating processing, and the specific processing conditions of the pattern electroplating are: the current density is not greater than 1.2ASD, and the electroplating efficiency decreases step by step from top to bottom, so that the thickness of the electroplated copper layer on the first intermediate plate is consistent.

[0013] As a further improvement of the present invention, the electroplating efficiency corresponding to the upper part of the first intermediate plate is 110% to 125%, the electroplating efficiency corresponding to the middle part of the first intermediate plate is 100%, and the electroplating efficiency corresponding to the lower part of the first intermediate plate is 85% to 100%, so that the thickness tolerance of the electroplated copper layer on the first intermediate plate is ±2μm.

[0014] As a further improvement of the present invention, the impedance line extension body obtained by the MSAP process has a line length of ≥20mm, a line width of ≤40μm, a line width tolerance of ±2μm, and a thickness of 25-45μm, and the line width of the inner layer circuit is 10-40μm, the line width tolerance is ±2μm, the line spacing is 10-40μm, and the thickness is 25-45μm;

[0015] In addition, the line length of the supersensitive impedance is ≤10 mm, the line width is ≤40 μm, the thickness is 25-45 μm, and the impedance value tolerance is ≤±5%.

[0016] As a further improvement of the present invention, the surface roughness Rz of the side of the ultra-thin copper layer facing the insulating base layer is ≤ 0.8 μm;

[0017] The pressing process adopts electric heating pressing method, and the processing conditions of the pressing process are: heating rate not less than 8°C / min, maximum pressing temperature not less than 230°C, maximum pressing pressure not less than 450psi; so that the dielectric thickness tolerance of the first intermediate plate is ≤±5%.

[0018] As a further improvement of the present invention, after the first intermediate board is subjected to the MSAP process, the circuit set is subjected to an appearance inspection, and the impedance prototype is subjected to an impedance test.

[0019] The present invention also provides a circuit substrate, which is manufactured by using the processing method of the circuit substrate described in the present invention.

[0020] The present invention also provides a method for processing a system-level packaging substrate, comprising:

[0021] A circuit substrate according to the present invention is provided, wherein the circuit substrate is subjected to double-sided lamination, board separation and double-sided circuit production in sequence, so as to form a circuit set A including an outer layer circuit and an impedance prototype A on opposite sides of the circuit substrate; wherein the outer layer circuits in two groups of the circuit sets A are respectively connected to the two groups of the inner layer circuits on the circuit substrate, and the impedance prototype A is a single-line coplanar impedance structure composed of an impedance line extension body A and a peripheral copper body A located next to the impedance line extension body A;

[0022] After the preset part of the impedance line extension body A and the outer layer circuit are coated for protection, the exposed part of the impedance line extension body A and the outer copper body A are etched away, so that the preset part of the impedance line extension body A is formed into a super-sensitive impedance A of a single-line non-coplanar impedance structure; then the film is removed to obtain a semi-finished system-level packaging substrate;

[0023] The obtained semi-finished system-level packaging substrate is subjected to conventional solder masking, surface treatment, molding, finished product testing, finished product inspection, and packaging processing to obtain the system-level packaging substrate.

[0024] As a further improvement of the present invention, the circuit substrate is subjected to double-sided lamination, board separation and double-sided circuit production in sequence, including:

[0025] An insulating build-up layer and a composite copper layer A are sequentially stacked on opposite sides of the circuit substrate and then subjected to a pressing process to obtain a first processed board; wherein the composite copper layer A is provided with a carrier copper layer A and an ultra-thin copper layer A detachably arranged on the carrier copper layer A, and the ultra-thin copper layer A is attached to the insulating build-up layer; the pressing process adopts an electric heating pressing method, and the processing conditions of the pressing process are: a heating rate of not less than 8°C / min, a maximum pressing temperature of not less than 230°C, and a maximum pressing pressure of not less than 450psi;

[0026] The carrier copper layer A on the first processed board is completely removed to obtain a second processed board;

[0027] The second processed board is subjected to MSAP process to form the circuit set A on the two ultra-thin copper layers A of the second processed board respectively; wherein the specific processing method of the second processed board is the same as the specific processing method of the first intermediate board, that is, the line length of the obtained impedance line extension body A is ≥20mm, the line width is ≤40μm, the line width tolerance is ±2μm, and the thickness is 25-45μm, and the line width of the obtained outer layer circuit is 10-40μm, the line width tolerance is ±2μm, the line spacing is 10-40μm, and the thickness is 25-45μm;

[0028] In addition, the line length of the supersensitive impedance A is ≤10mm, the line width is ≤40μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%;

[0029] In addition, after the second processed board is subjected to the MSAP process, the circuit set A is visually inspected, and the impedance prototype A is impedance tested.

[0030] The present invention also provides a system-level packaging substrate, which is manufactured using the processing method of the system-level packaging substrate described in the present invention.

[0031] The beneficial effects of the present invention are as follows: by utilizing the circuit substrate processing method and the system-level packaging substrate processing method described in the present invention, on the one hand, the density and precision of the obtained circuits (such as inner layer circuits and outer layer circuits) can be very high, greatly improving the packaging density and precision; on the other hand, it also effectively solves the problem that the hypersensitive impedance is not easy to be supervised during the production and processing process, thereby achieving large-scale production of circuit substrates / and system-level packaging substrates with hypersensitive impedance, and effectively improving the yield of hypersensitive impedance, which well meets market and production needs. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is a flow chart of the method for processing a circuit substrate according to Embodiment 1 of the present invention;

[0033] Figure 2 is a schematic diagram of the cross-sectional structure of the composite substrate in Example 1 of the present invention;

[0034] Figure 3 is a schematic cross-sectional structural diagram of the first intermediate plate in Embodiment 1 of the present invention;

[0035] Figure 4 Schematic diagram of the cross-sectional structure of the board obtained after completing S34 processing in Example 1 of the present invention;

[0036] Figure 5 is a schematic cross-sectional structural diagram of the second intermediate plate in Embodiment 1 of the present invention;

[0037] Figure 6 It is a schematic cross-sectional structure diagram of the impedance prototype described in Example 1 of the present invention;

[0038] Figure 7 is a schematic cross-sectional structural diagram of the circuit substrate described in Embodiment 1 of the present invention;

[0039] Figure 8 It is a schematic diagram of the cross-sectional structure of the supersensitive impedance described in Example 1 of the present invention;

[0040] Fig. 9 This is a flow chart of a method for processing a system-level packaging substrate according to Embodiment 3 of the present invention;

[0041] Fig.10 is a schematic cross-sectional structural diagram of the first processing plate in Example 3 of the present invention;

[0042] Fig.11 Schematic diagram of the cross-sectional structure of the board obtained after completing step 2 in Example 3 of the present invention;

[0043] Fig.12 Schematic diagram of the cross-sectional structure of the impedance prototype A described in Example 3 of the present invention;

[0044] Fig.13 Schematic diagram of the cross-sectional structure of the semi-finished system-level packaging substrate in Embodiment 3 of the present invention;

[0045] Fig.14 Schematic diagram of the cross-sectional structure of the supersensitive impedance A described in Example 3 of the present invention;

[0046] Fig.15 Schematic diagram of the cross-sectional structure of the system-level packaging substrate described in Example 3 of the present invention.

[0047] Combined with the attached drawings, the following description is given:

[0048] 1. Insulation base layer; 20. Carrier copper layer; 21. Ultra-thin copper layer; 30. Inner layer circuit; 31. Impedance prototype; 310. Impedance line extension body; 311. Outer copper body; 32. Super-sensitive impedance; 4. Insulation enhancement layer; 50. Carrier copper layer A; 51. Ultra-thin copper layer A; 60. Outer layer circuit; 61. Impedance prototype A; 610. Impedance line extension body A; 611. Outer copper body A; 62. Super-sensitive impedance A; 7. Solder mask; 100. Tool hole; 101. Through hole; 102. Film pattern; 103. Electroplated copper layer; 104. Connecting copper body; 105. Connecting copper body A; B1. First intermediate board; B2. Second intermediate board; B3. First processing board. DETAILED DESCRIPTION

[0049] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0050] Embodiment 1:

[0051] Please see attached Figures 1 to 8 As shown, this embodiment 1 provides a method for processing a circuit substrate, which mainly includes the following processing steps:

[0052] S1: providing an insulating base layer 1 and two composite copper layers, wherein the insulating base layer 1 is a prepreg, and the composite copper layer is provided with a carrier copper layer 20 and an ultra-thin copper layer 21 detachably arranged on the carrier copper layer 20 .

[0053] Furthermore, regarding the insulating base layer 1, the present embodiment does not impose any restrictions on the thickness or number of the insulating base layer 1, which can be determined according to product design requirements.

[0054] Regarding the composite copper layer, the ultra-thin copper layer 21 is deposited on the carrier copper layer 20 by an electroplating process, and before the electroplating process, the carrier copper layer 20 needs to be treated with a liquid medicine to ensure that there is a predetermined peeling force between the ultra-thin copper layer 21 and the carrier copper layer 20, so that good separation can be achieved. This is a conventional technical means in the field of circuit boards, so it will not be described in detail here.

[0055] In addition, this embodiment also optimizes the thickness, roughness and other technical parameters of the composite copper layer according to the product design requirements, such as: the thickness of the carrier copper layer 20 is preferably 17μm, the thickness of the ultra-thin copper layer 21 is preferably 2-3μm, and the surface roughness Rz≤0.8μm of the side of the ultra-thin copper layer 21 facing away from the carrier copper layer 20 (that is, the side of the ultra-thin copper layer 21 facing the insulating base layer 1 in the post-process). Compared with the surface roughness Rz≤2μm of the traditional ultra-thin copper layer, the surface roughness Rz of the ultra-thin copper layer 21 in this embodiment is smaller, which can reduce the influence of the skin effect on the one hand, and provide a basic guarantee for the firm combination of the ultra-thin copper layer 21 and the insulating base layer 1 in the post-process. In addition, the ultra-thin thickness of the ultra-thin copper layer 21 also provides a basic guarantee for the overall ultra-thinness of the circuit substrate product and the precision circuit (small line width and line spacing) obtained in the post-process.

[0056] S2: Lay the insulating base layer 1 between the two ultra-thin copper layers 21 of the composite copper layer and perform a pressing process to combine them into one (the integrated structure can be defined as a composite substrate, and its specific structure can be referred to in the attached Figure 2 Then, the carrier copper layer 20 is completely removed to obtain a first intermediate board B1; the structure of the first intermediate board B1 can be found in the attached Figure 3 shown.

[0057] Specifically, after the insulating base layer 1 and the two composite copper layers are stacked, the present embodiment performs an electric heating pressing treatment on the stacked composition, and at the same time optimizes the processing conditions of the electric heating pressing treatment to: a heating rate of not less than 8°C / min, a maximum pressing temperature of not less than 230°C, and a maximum pressing pressure of not less than 450psi. It can be understood that based on the rough surface of the ultra-thin copper layer 21 and the above-mentioned optimized electric heating pressing process, the molten insulating base layer 1 can flow on the rough surface of the ultra-thin copper layer 21 in a wider and more sufficient range, so that the ultra-thin copper layer 21 after solidification can be firmly combined with the insulating base layer 1, and the dielectric thickness tolerance of the composite substrate and the first intermediate plate B1 can be no more than ±5%, that is: the dielectric thickness consistency of the composite substrate and the first intermediate plate B1 is very good, which provides good technical support and guarantee for the subsequent process to obtain precision circuits.

[0058] After the insulating base layer 1 and the two composite copper layers are combined into an integrated structure through an electric heating pressing process, a unique PNL two-dimensional code is printed on the edge of the composite substrate using a two-dimensional code printer according to product design requirements, a tool hole 100 for post-process alignment is drilled on the edge of the composite substrate using a mechanical drill, and the carrier copper layer 20 on the composite substrate is completely removed using a mechanical stripping machine to obtain the first intermediate board B1.

[0059] S3: Perform MSAP process on the first intermediate board B1 to form a circuit set including inner-layer circuits 30 and impedance prototypes 31 on the two ultra-thin copper layers 21 of the first intermediate board B1; wherein the inner-layer circuits 30 in the two groups of the circuit sets are connected, and the impedance prototype 31 is a single-line coplanar impedance structure composed of an impedance line extension body 310 and a peripheral copper body 311 located next to the impedance line extension body 310. Note: In the field of circuit board technology, "single-line coplanar impedance" refers to the impedance tested when the signal line is transmitted between the GND line and the VCC line around it (the spacing between the signal line and the GND line and the VCC line on both sides of it is equal); accordingly, the signal line and the GND line and the VCC line around it together form a single-line coplanar impedance structure.

[0060] Specifically, the specific method of performing the MSAP process on the first intermediate plate B1 in this embodiment is as follows:

[0061] S31: using a CO2 laser to drill a hole at a preset position of the first intermediate plate B1 to obtain an X-shaped through hole 101.

[0062] S32: Desmearing the tool hole 100 and the hole wall of the through hole 101, and coppering the entire first intermediate board B1 (including the tool hole 100 and the hole wall of the through hole 101), which can be understood as roughening the copper surface to increase the bonding strength between the anti-plating photosensitive film and the copper surface in the subsequent process.

[0063] S33: After cleaning and drying the first intermediate board B1 (i.e., pre-lamination treatment), a plating-resistant photosensitive dry film is pasted on the two ultra-thin copper layers 21; then, the plating-resistant photosensitive dry film is exposed and developed according to the operation data to process the plating-resistant photosensitive dry film into a film pattern 102; at that time, part of the ultra-thin copper layer 21 is exposed outside the film pattern 102 and part of it is covered by the film pattern 102.

[0064] S34: The first intermediate board B1 is subjected to pattern electroplating processing by vertical electroplating method, so as to plate an electroplated copper layer 103 at the position where the ultra-thin copper layer 21 is exposed outside the film pattern 102, and plate a connecting copper body 104 in the through hole 101, wherein the connecting copper body 104 can partially connect the electroplated copper layers 103 respectively located on the two ultra-thin copper layers 21. For details, please refer to the attached Figure 4 shown.

[0065] In particular, the present embodiment also optimizes the specific processing conditions during the electroplating of the above-mentioned pattern as follows: the current density is not greater than 1.2ASD; the electroplating efficiency corresponding to the upper part of the first intermediate plate B1 is 110% to 125%, the electroplating efficiency corresponding to the middle part of the first intermediate plate B1 is 100%, and the electroplating efficiency corresponding to the lower part of the first intermediate plate B1 is 85% to 100%, that is, the electroplating efficiency configured during the electroplating of the above-mentioned pattern decreases stepwise from top to bottom; thereby, the thickness tolerance of the electroplated copper layer 103 on the first intermediate plate B1 reaches ±2μm, that is, the thickness of the electroplated copper layer 103 on the first intermediate plate B1 is well achieved to be consistent. Based on the high consistency of the thickness of the electroplated copper layer 103, it can provide very good technical support and guarantee for the subsequent process to obtain precision circuits.

[0066] Supplementary explanation: ① It is well known that the calculation formula for the thickness of the electroplated copper layer in the field of circuit board technology is: electroplated copper layer thickness (μm) = current density (ASF) × electroplating time (min) × electroplating efficiency × electroplating coefficient; where the current density is the number of amperes of current passing through the unit area per square foot; the electroplating time is the duration of the electroplating process; the electroplating efficiency is the actual utilization efficiency of the current during the electroplating process; the electroplating coefficient is a constant of 0.0202. It is understandable that the electroplating efficiency can have a significant impact on the thickness of the electroplated copper layer. ② In order to achieve differentiated control of the electroplating efficiency at various locations of the first intermediate plate B1, this embodiment uses three rectifiers to respectively manage the electroplating efficiency and current density applied to the upper, middle and lower parts of the first intermediate plate.

[0067] S35: firstly remove the film pattern 102 with a strong alkaline solution, and then heat and dry the whole board to achieve lattice reorganization of the electroplated copper layer; then flash-etch the dried first intermediate board B1 to etch away the portion of the ultra-thin copper layer 21 exposed outside the electroplated copper layer 103, and thin the electroplated copper layer 103 as a whole to a predetermined thickness, thereby completing the production of the circuit assembly. It is understandable that based on product design requirements, the circuit set includes the inner circuit 30 and the impedance prototype 31, and combined with the above S31~S35, it can be known that the inner circuit 30 and the impedance prototype 31 are both composed of the thinned electroplated copper layer 103 and the ultra-thin copper layer 21, that is: the thickness of the inner circuit 30 and the impedance prototype 31 are both the sum of the thickness of the thinned electroplated copper layer 103 and the thickness of the ultra-thin copper layer 21; and, the inner circuits 30 in the two groups of the circuit sets are connected through the connecting copper body 104, and the impedance prototype 31 is a single-line coplanar impedance structure composed of an impedance line extension body 310 and a peripheral copper body 311 located next to the impedance line extension body 310. For details, please refer to the attached Figure 5 and attached Figure 6 shown.

[0068] Based on the above-mentioned optimized MSAP process, the circuit set obtained in this embodiment has achieved the following technical indicators: ① The line length of the impedance line extension body 310 in the impedance prototype 31 is ≥20mm, the line width is ≤40μm, the line width tolerance is ±2μm, and the thickness is 25~45μm; ② The line width of the inner layer circuit 30 is 10~40μm, the line width tolerance is ±2μm, the line spacing is 10~40μm, and the thickness is 25~45μm.

[0069] It can be seen from the above that the density and precision of the inner layer circuit 30 manufactured in this embodiment are very high, and the precision of the impedance line extension body 310 is also very high, thereby greatly improving the packaging density and precision.

[0070] S4: After completing the above S3 processing, the circuit set is visually inspected using AOI inspection equipment, and the impedance prototype 31 is impedance tested using an impedance tester, and the obtained appearance inspection information and impedance test information are respectively stored in combination with the PNL two-dimensional code.

[0071] It can be understood that the impedance prototype 31 obtained based on this embodiment is a single-line coplanar impedance structure, and the line length of the impedance line extension body 310 is specially optimized to be not less than 20 mm, which can well meet the technical requirements for monitoring the impedance line during the circuit substrate processing, thereby ensuring the yield of the impedance line and realizing the mass production of the circuit substrate.

[0072] S5: After the preset part of the impedance line extension body 310 and the inner layer circuit 30 are coated for protection, the exposed part of the impedance line extension body 310 and the outer copper body 311 are etched away, so that the preset part of the impedance line extension body 310 is formed into a super-sensitive impedance 32 with a single-line non-coplanar impedance structure; then the film is removed to obtain a circuit substrate with the inner layer circuit 30 and the super-sensitive impedance 32.

[0073] Specifically, the specific processing method of the above S5 is:

[0074] S51: The board obtained after the above S4 processing is defined as the second intermediate board B2; after cleaning and drying the second intermediate board B2, a resist photosensitive dry film is applied to the opposite sides of the second intermediate board B2; then the resist photosensitive dry film is exposed and developed according to the operation data, so that the preset part (i.e., the attached part) of the impedance line extension body 310 is Figure 6 The AB segment shown in FIG. 1 (including the B point) and the inner layer circuit 30 are covered and protected by the anti-etching photosensitive dry film, and the remaining portion of the impedance line extension body 310 (i.e., the attached Figure 6 The BC segment shown in FIG. 2 (excluding the B point) and the peripheral copper body 311 are exposed outside the anti-etching photosensitive dry film.

[0075] S52: The exposed portion of the impedance line extension body 310 (i.e., the portion exposed outside the anti-etching photosensitive dry film, the above-mentioned attachment Figure 6 The BC segment shown in FIG. 1 , excluding the B point position) and the peripheral copper body 311 are etched away, so that the preset portion of the impedance line extension body 310 is formed into a super-sensitive impedance 32 of a single-line non-coplanar impedance structure, which can be seen in the attached Figure 7 and attached Figure 8Note: In the field of circuit board technology, "single-line non-coplanar impedance" refers to the impedance measured by a single signal line, usually when there is no copper around the signal line (GND line and VCC line); accordingly, a single signal line without copper around it constitutes a single-line non-coplanar impedance structure.

[0076] Based on product design requirements and the structural characteristics of the impedance line extension body 310, the super-sensitive impedance 32 meets the following technical indicators: the line length of the super-sensitive impedance 32 is ≤10mm, the line width is ≤40μm, the line width tolerance is ±2μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%; it meets the circuit board product requirements very well.

[0077] S53: The anti-corrosion photosensitive dry film is removed by using a strong alkaline solution, and then dried and inspected for appearance, so as to obtain a circuit substrate with the inner layer circuit 30 and the supersensitive impedance 32. Figure 7 and attached Figure 8 shown.

[0078] From the above, it can be seen that by utilizing the circuit substrate processing method provided in this embodiment 1, on the one hand, the density and precision of the obtained inner layer circuit can be very high, which greatly improves the packaging density and precision. On the other hand, it also effectively solves the problem that the ultra-sensitive impedance is not easy to be supervised during the production and processing process, thereby realizing the large-scale production of circuit substrates with ultra-sensitive impedance and effectively improving the yield of ultra-sensitive impedance.

[0079] Embodiment 2:

[0080] This embodiment 2 provides a circuit substrate, which is manufactured using the processing method of the circuit substrate described in the above embodiment 1.

[0081] Specifically, the specific structure of the circuit substrate described in this embodiment 2 is as follows: Figure 7 and attached Figure 8 As shown, the circuit substrate includes an insulating base layer 1, and circuit sets respectively fixedly arranged on opposite sides of the insulating base layer 1, and the two groups of the circuit sets both include inner-layer circuits 30 and super-sensitive impedances 32, and the inner-layer circuits 30 in the two groups of the circuit sets are connected by connecting copper bodies 104; in addition, in each group of the circuit sets, the line width of the inner-layer circuit 30 is 10-40 μm, the line width tolerance is ±2 μm, the line spacing is 10-40 μm, and the thickness is 25-45 μm, the super-sensitive impedance 32 is a non-coplanar impedance structure, and the line length of the super-sensitive impedance 32 is ≤10 mm, the line width is ≤40 μm, the thickness is 25-45 μm, and the impedance value tolerance is ≤±5%.

[0082] From the above, it can be seen that the density and precision of the inner layer circuit in the circuit substrate obtained in this embodiment 2 are very high, and the precision and yield of the supersensitive impedance are also very high, which well meets the packaging requirements.

[0083] Embodiment 3:

[0084] Please see attached Figures 9 to 15 As shown, this embodiment 3 provides a method for processing a system-level packaging substrate, which mainly includes the following processing steps:

[0085] Step 1: Provide a circuit substrate, which is manufactured by the processing method of the circuit substrate described in the above-mentioned embodiment 1; after the circuit substrate is double-sided laminated, depaneled and double-sided circuit manufactured in sequence, a circuit set A including an outer layer circuit 60 and an impedance prototype A61 is formed on opposite sides of the circuit substrate; wherein the outer layer circuits 60 in the two groups of the circuit sets A are respectively connected to the two groups of the inner layer circuits 30 on the circuit substrate, and the impedance prototype A61 is a single-line coplanar impedance structure composed of an impedance line extension body A610 and a peripheral copper body A611 located next to the impedance line extension body A610.

[0086] Specifically, the specific processing method of the above step 1 is:

[0087] Step 11: stack the insulating build-up layer 4 and the composite copper layer A on opposite sides of the circuit substrate in sequence and then perform a pressing process to obtain a first processed board B3. Fig.10 shown.

[0088] The insulating build-up layer 4 may be a prepreg, and this embodiment 3 does not impose any restrictions on the thickness / number of the insulating build-up layer 4. The composite copper layer A is provided with a carrier copper layer A50 and an ultra-thin copper layer A51 detachably disposed on the carrier copper layer A50, and the ultra-thin copper layer A51 is attached to the insulating build-up layer 4; further, the composite copper layer A may adopt the same implementation structure as the composite copper layer described in embodiment 1, so it is not described here.

[0089] The pressing process adopts an electric heating pressing method, and the processing conditions of the pressing process can be optimized as follows: the heating rate is not less than 8°C / min, the maximum pressing temperature is not less than 230°C, and the maximum pressing pressure is not less than 450psi. Further, the pressing process used in this step 11 can be the same as the pressing process described in S2 in Example 1.

[0090] In addition, after the first processed board B3 is obtained, a PNL QR code is printed on the edge of the first processed board B3 using a QR code printer according to product design requirements, and a tool hole A for post-process alignment is drilled on the edge of the first processed board B3 using a mechanical drill.

[0091] Step 12: The carrier copper layer A50 on the first processed board B3 is completely removed to obtain a second processed board.

[0092] Similar to the first embodiment, in step 12, a mechanical stripper may be used to remove the carrier copper layer A50.

[0093] Step 13: Perform MSAP process on the second processed board to form the circuit set A on the two ultra-thin copper layers A51 of the second processed board respectively. Fig.11 and attached Fig.12 As shown; wherein, the specific processing method of performing MSAP process on the second processed plate is the same as the specific processing method of performing MSAP process on the first intermediate plate B1 in Example 1, so it is not repeated here; but it can be understood that based on the above-mentioned MSAP process, in the circuit set A obtained in this step 13, the line width of the outer layer circuit 60 is 10-40μm, the line width tolerance is ±2μm, the line spacing is 10-40μm, and the thickness is 25-45μm; and the outer layer circuit 60 is connected to the corresponding inner layer circuit 30 through the connecting copper body A105; the impedance prototype A61 is a single-line coplanar impedance structure, and the line length of the impedance line extension body A610 is ≥20mm, the line width is ≤40μm, the line width tolerance is ±2μm, and the thickness is 25-45μm.

[0094] It can be seen from the above that the density and precision of the outer layer circuit 60 manufactured in this embodiment are very high, and the precision of the impedance line extension body A610 is also very high, thereby greatly improving the packaging density and precision.

[0095] Step 2: After completing the processing in the above step 1, use AOI inspection equipment to perform appearance inspection on the line set A, and use an impedance tester to perform impedance test on the impedance prototype A61, and the obtained appearance inspection information and impedance test information are also stored in combination with the PNL QR code.

[0096] It can be understood that the impedance prototype A61 obtained based on this embodiment is a single-line coplanar impedance structure, and the line length of the impedance line extension body A610 is specially optimized to be not less than 20 mm, which can well meet the technical requirements for monitoring the impedance line during the circuit substrate processing, thereby ensuring the yield of the impedance line and realizing the mass production of the circuit substrate.

[0097] Step 3: The preset portion (i.e., the attached Fig.12 After the AB segment (including the B point) and the outer layer line 60 are coated for protection, the exposed portion of the impedance line extension body A610 (i.e. the attached Fig.12 The BC segment shown in the figure, excluding the B point position) and the peripheral copper body A611 are etched away, so that the preset part of the impedance line extension body A610 is formed into a super-sensitive impedance A62 of a non-coplanar impedance structure; then the film is removed, and drying and appearance inspection are performed to obtain a semi-finished system-level packaging substrate, which can be referred to in the attached Fig.13 and attached Fig.14 shown.

[0098] Specifically, the specific processing technology of step 3 can be the same as the specific processing technology of S5 in embodiment 1, so it is not repeated here. However, it can be understood that the supersensitive impedance A62 obtained in step 3 can also meet the following technical indicators: the line length of the supersensitive impedance A62 is ≤10mm, the line width is ≤40μm, the line width tolerance is ±2μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%; it meets the requirements of circuit board products very well.

[0099] Step 4: Perform conventional solder masking (forming a solder mask layer 7), surface treatment, molding, finished product testing, finished product inspection, and packaging processing on the obtained semi-finished system-level packaging substrate to obtain the system-level packaging substrate. Fig.15 shown.

[0100] In combination with Example 1, it can be seen that by utilizing the processing method of the system-level packaging substrate provided in this Example 3, the density and precision of the inner and outer circuits obtained can be very high, and the problem that the hypersensitive impedance is not easy to be supervised during the production and processing can be effectively solved, thereby achieving large-scale production of system-level packaging substrates with hypersensitive impedance and improving the yield, packaging accuracy and density of the hypersensitive impedance.

[0101] Embodiment 4:

[0102] The fourth embodiment provides a system-level packaging substrate, which is manufactured by using the processing method of the system-level packaging substrate described in the third embodiment.

[0103] Specifically, the specific structure of the system-level packaging substrate described in this embodiment 4 is as follows: Fig.15As shown, the system-level packaging substrate includes an insulating base layer 1, a circuit set respectively fixedly arranged on two opposite sides of the insulating base layer 1, an insulating layer 4 respectively fixedly attached to the two circuit sets, a circuit set A respectively fixedly arranged on two opposite sides of the two insulating layers 4, and a solder mask 7, wherein the two groups of circuit sets both include inner-layer circuits 30 and super-sensitive impedances 32, the inner-layer circuits 30 in the two groups of circuit sets are connected by connecting copper bodies 104, the line width of the inner-layer circuits 30 in each group of the circuit sets is 10-40 μm, the line width tolerance is ±2 μm, the line spacing is 10-40 μm, and the thickness is 25-45 μm, the super-sensitive impedance 32 is a non-coplanar impedance structure, and the super-sensitive The line length of the impedance 32 is ≤10mm, the line width is ≤40μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%; the two groups of circuit sets A both include an outer layer circuit 60 and an impedance prototype A61, and the two groups of outer layer circuits 60 are respectively connected to the two groups of inner layer circuits 30 through the connecting copper body A105, the line width of the outer layer circuit 60 in each group of the circuit set A is 10-40μm, the line width tolerance is ±2μm, the line spacing is 10-40μm, and the thickness is 25-45μm, the super-sensitive impedance A62 is a non-coplanar impedance structure, and the line length of the super-sensitive impedance A62 is ≤10mm, the line width is ≤40μm, the line width tolerance is ±2μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%.

[0104] It can be seen from the above that the system-level packaging substrate obtained in this embodiment 4 has high packaging accuracy and density, high product yield, and well meets market and production needs.

[0105] Finally, the prefixes "first", "second", etc. of the component names in this application specification (such as the first intermediate board, the second intermediate board, etc.), and the suffixes "A", etc. of the component names (such as carrier copper layer A, ultra-thin copper layer A, etc.) are only for the convenience of description and are not used to limit the scope of the implementation of the patent of this invention.

[0106] Many specific details are described in the above description to facilitate a full understanding of the present invention. However, the above description is only a preferred embodiment of the present invention. The present invention can be implemented in many other ways different from those described herein, so the present invention is not limited to the specific implementation disclosed above. At the same time, any person familiar with the art can make many possible changes and modifications to the technical solution of the present invention using the methods and technical contents disclosed above without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes. Any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A method for processing a circuit substrate, characterized in that: include: An insulating base layer (1) and two composite copper layers are provided, wherein the composite copper layer is provided with a carrier copper layer (20) and an ultra-thin copper layer (21) detachably arranged on the carrier copper layer (20); The insulating base layer (1) is stacked between the two ultra-thin copper layers (21) of the composite copper layer and pressed to form a whole, and then the carrier copper layer (20) is completely removed to obtain a first intermediate plate; The first intermediate board is subjected to MSAP process to form a circuit set including an inner layer circuit (30) and an impedance prototype (31) on the two ultra-thin copper layers (21) of the first intermediate board respectively; wherein the inner layer circuits (30) in the two groups of the circuit sets are connected, and the impedance prototype (31) is a single-line coplanar impedance structure composed of an impedance line extension body (310) and a peripheral copper body (311) located next to the impedance line extension body (310); After the preset portion of the impedance line extension body (310) and the inner layer circuit (30) are coated for protection, the exposed portion of the impedance line extension body (310) and the outer copper body (311) are etched away, so that the preset portion of the impedance line extension body (310) is formed into a super-sensitive impedance (32) of a single-line non-coplanar impedance structure; the coating is then removed to obtain a circuit substrate with the inner layer circuit (30) and the super-sensitive impedance (32).

2. The method for processing a circuit substrate according to claim 1, wherein: The MSAP process includes laser drilling through holes, copper plating, lamination pretreatment, anti-plating photosensitive film coating, exposure, development, pattern electroplating, film stripping and flash etching on the first intermediate plate in sequence; Among them, the vertical electroplating method is adopted when the first intermediate plate is subjected to pattern electroplating processing, and the specific processing conditions of the pattern electroplating are: the current density is not greater than 1.2ASD, and the electroplating efficiency decreases step by step from top to bottom, so that the thickness of the electroplated copper layer on the first intermediate plate is consistent.

3. The method for processing a circuit substrate according to claim 2, characterized in that: The electroplating efficiency corresponding to the upper part of the first intermediate plate is 110% to 125%, the electroplating efficiency corresponding to the middle part of the first intermediate plate is 100%, and the electroplating efficiency corresponding to the lower part of the first intermediate plate is 85% to 100%, so that the thickness tolerance of the electroplated copper layer on the first intermediate plate is ±2μm.

4. The method for processing a circuit substrate according to claim 2, wherein: The impedance line extension body (310) manufactured by the MSAP process has a line length of ≥20 mm, a line width of ≤40 μm, a line width tolerance of ±2 μm, and a thickness of 25 to 45 μm; the inner layer line (30) has a line width of 10 to 40 μm, a line width tolerance of ±2 μm, a line spacing of 10 to 40 μm, and a thickness of 25 to 45 μm; In addition, the line length of the supersensitive impedance (32) is ≤10 mm, the line width is ≤40 μm, the thickness is 25-45 μm, and the impedance value tolerance is ≤±5%.

5. The method for processing a circuit substrate according to claim 1, wherein: The surface roughness Rz of the ultra-thin copper layer (21) on the side facing the insulating base layer (1) is ≤ 0.8 μm; The pressing process adopts electric heating pressing method, and the processing conditions of the pressing process are: heating rate not less than 8°C / min, maximum pressing temperature not less than 230°C, maximum pressing pressure not less than 450psi; so that the dielectric thickness tolerance of the first intermediate plate is ≤±5%.

6. The method for processing a circuit substrate according to claim 1, wherein: After the first intermediate board is subjected to the MSAP process, the circuit set is subjected to an appearance inspection, and the impedance prototype (31) is subjected to an impedance test.

7. A circuit substrate, characterized in that: The circuit substrate is manufactured by the processing method of any one of claims 1 to 6.

8. A method for processing a system-level packaging substrate, characterized in that: include: A circuit substrate as claimed in claim 7 is provided, wherein the circuit substrate is subjected to double-sided lamination, board separation and double-sided circuit production in sequence, so as to form a circuit set A comprising an outer layer circuit (60) and an impedance prototype A (61) on opposite sides of the circuit substrate; wherein the outer layer circuits (60) in two groups of the circuit sets A are respectively connected to the two groups of the inner layer circuits (30) on the circuit substrate, and the impedance prototype A (61) is a single-line coplanar impedance structure composed of an impedance line extension body A (610) and a peripheral copper body A (611) located next to the impedance line extension body A (610); After coating the preset portion of the impedance line extension body A (610) and the outer layer circuit (60) with a protective film, the exposed portion of the impedance line extension body A (610) and the outer copper body A (611) are etched away, so that the preset portion of the impedance line extension body A (610) is formed into a super-sensitive impedance A (62) of a single-line non-coplanar impedance structure; then the film is removed to obtain a semi-finished system-level packaging substrate; The obtained semi-finished system-level packaging substrate is subjected to conventional solder masking, surface treatment, molding, finished product testing, finished product inspection, and packaging processing to obtain the system-level packaging substrate.

9. The method for processing a system-level packaging substrate according to claim 8, wherein: The circuit substrate is subjected to double-sided lamination, board separation and double-sided circuit production in sequence, including: An insulating build-up layer (4) and a composite copper layer A are sequentially stacked on opposite sides of the circuit substrate and then subjected to a pressing process to obtain a first processed board; wherein the composite copper layer A is provided with a carrier copper layer A (50) and an ultra-thin copper layer A (51) detachably arranged on the carrier copper layer A (50), and the ultra-thin copper layer A (51) is attached to the insulating build-up layer (4); the pressing process adopts an electric heating pressing method, and the processing conditions of the pressing process are: a heating rate of not less than 8°C / min, a maximum pressing temperature of not less than 230°C, and a maximum pressing pressure of not less than 450psi; removing all of the carrier copper layer A (50) on the first processed board to obtain a second processed board; The second processed board is subjected to MSAP process to form the circuit set A on the two ultra-thin copper layers A (51) of the second processed board respectively; wherein the specific processing method of the second processed board is the same as the specific processing method of the first intermediate board, that is, the line length of the obtained impedance line extension body A (610) is ≥20mm, the line width is ≤40μm, the line width tolerance is ±2μm, and the thickness is 25-45μm; the line width of the obtained outer layer circuit (60) is 10-40μm, the line width tolerance is ±2μm, the line spacing is 10-40μm, and the thickness is 25-45μm; In addition, the line length of the supersensitive impedance A (62) is ≤10mm, the line width is ≤40μm, the thickness is 25-45μm, and the impedance value tolerance is ≤±5%; In addition, after the MSAP process is completed on the second processed board, the circuit set A is visually inspected, and the impedance prototype A (61) is impedance tested.

10. A system-level packaging substrate, characterized in that: The system-level packaging substrate is manufactured by the processing method of any one of claims 8 to 9.

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