Critical path length calculation method suitable for high-speed serial interface

Abstract

The invention provides a critical path length calculation method suitable for a high-speed serial interface, which comprises the following steps of: deriving a result of parallel data by virtue of a matrix by utilizing a logic derivation method based on a serial circuit structure, and obtaining a check operator; according to the principle that XOR logic and additive operation are equivalent, a check operator is expressed as a product of data to be coded and a conversion matrix, a common factor of 1 in each row of the conversion matrix is searched and eliminated through a common factor fast searching algorithm, and a new conversion matrix is obtained; and determining the position of the key path based on the number of '1' in each column in the new transformation matrix, and calculating the length of the key path according to the number of newly added variables in the new transformation matrix and the incidence relation. According to the invention, the usage amount of logic units is reduced, and a small-area and low-power-consumption high-speed data coding and decoding circuit is realized; the method is suitable for data with different bit widths, and compared with a traditional logic derivation method, the hardware resource consumption of the data encoding and decoding circuit is reduced by about 40%-60%.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed serial interfaces, and in particular to a critical path length calculation method suitable for high-speed serial interfaces. Background Art

[0002] High-speed serial interface (SerDes) technology is a data transmission technology, which is mainly used for high-speed data transmission between different devices. Compared with another parallel multi-channel data transmission technology, SerDes only transmits a pair of differential data signals, which has the advantages of fewer natural transmission channels, fewer chip pins, and simple wiring, avoiding various problems such as clock synchronization, data crosstalk, and clock offset that appear in parallel multi-channel transmission technology. In addition, with the help of various channel equalization technologies and clock data recovery (CDR) technologies, SerDes can still maintain a fairly high stability and reliability even in high-speed and long-distance application scenarios.

[0003] Because of the above advantages, high-speed serial interfaces represented by JESD204C have been widely used in high-performance computing centers, large switches, and data transmission between chips. However, the manufacturing cost of the interface circuit (positively correlated with the area), power consumption, and data transmission reliability are key factors limiting the development of high-speed serial interface technology. How to reduce the area and power consumption of the circuit while maintaining high data transmission rate is an urgent problem that needs to be solved by academia and industry.

[0004] High-speed serial interfaces often use data encoding and decoding algorithms such as data scrambling, CRC (Cyclic Redundancy Check) and FEC (Forward Error Correction) to improve data transmission reliability and reduce bit error rates. Taking the JESD204C interface as an example, previous studies have found that its data link layer circuit area accounts for about 58% of the entire interface circuit, and the data encoding and decoding module accounts for about 60% of the overall area of ​​the link layer. The power consumption distribution of the data encoding and decoding module in the link layer is similar to the area, and its proportion is also high. Therefore, it is necessary to study the small area and low power consumption design of each data encoding and decoding module to meet the needs of application scenarios such as wireless communications and intelligent driving for miniaturized, low-energy, high-speed data transmission interface circuits.

[0005] Since data is processed in parallel format in the data link layer of the JESD204C interface, if data encoding and decoding algorithms such as data scrambling, CRC, and FEC are implemented in serial mode, the corresponding circuit operating frequency should be 16GHz, while the operating frequency of other circuit modules in the link layer is 485MHz, which will lead to the emergence of asynchronous clock circuits, increase the difficulty of circuit design, and reduce system stability. At the same time, high-speed clocks are also prone to jitter, causing bit errors and bringing higher power consumption. Therefore, the parallel design of data encoding and decoding algorithms is a major direction to reduce hardware resources and energy consumption.

[0006] There are two main types of parallel implementation schemes for data encoding and decoding such as data scrambling, CRC and FEC: lookup table and linear feedback shift register (LFSR). Among them, the lookup table method is to save the encoding result in the storage unit in advance. Its operation speed is fast, but it consumes more hardware resources to store data; LFSR uses basic gate-level units to perform logical operations to implement the algorithm. The LFSR method can be divided into serial circuit parallel method and logic deduction method. The serial circuit parallel method is to connect multiple serial circuits in parallel to process multi-bit width data. Its operation speed is fast, but it has high requirements for system clock consistency and consumes more hardware resources; the logic deduction method is based on the serial circuit structure. The encoding algorithm of multi-bit data is completed through logical operations. Its hardware resource consumption is small, but the operation speed is relatively slow. Summary of the invention

[0007] In view of the technical problems in the prior art that the hardware resources are consumed more and the operation speed is restricted by the critical path length, the present invention proposes a critical path length calculation method suitable for high-speed serial interfaces. Based on the fast search common factor algorithm, the common factors in the combinational logic unit are quickly found and eliminated, and the critical path length in the combinational logic circuit is further located and calculated to obtain the minimum resource requirement that meets the operating frequency.

[0008] In order to achieve the above object, the technical solution of the present invention is implemented as follows: a critical path length calculation method suitable for a high-speed serial interface, the steps of which are as follows:

[0009] Step 1: Based on the serial circuit structure, use the logic deduction method to derive the result of parallel data with the help of the matrix to obtain the check operator;

[0010] Step 2: Based on the principle that XOR logic is equivalent to addition, the check operator is expressed as the product of the data to be encoded and the transformation matrix. The common factor of "1" in each row of the transformation matrix is ​​searched and eliminated using the fast common factor search algorithm to obtain a new transformation matrix.

[0011] Step 3: Determine the location of the critical path based on the number of "1"s in each column of the new transformation matrix, and calculate the length of the critical path based on the number of newly added variables and their associations in the new transformation matrix.

[0012] Preferably, the method for obtaining the check operator in step one is: determining the source polynomial of the serial circuit structure; every other clock cycle, the user data u(x) and the data stored in the register in the serial circuit structure are subjected to an XOR logic operation using the source polynomial, and the data in the final register is the check operator.

[0013] Preferably, the source polynomial is: g(x)=g0+g1x+…+g n-k-1 x n-k-1 +g n-k x n-k ;

[0014] Assume the value of the register at time t is r(t)=[r n-k-1 ( t ),r n-k-2 (t),…,r0(t)]′, the input data is u(t), then the value of the register in the next cycle r(t+1)=A×r(t)+b×u(t), where the state transfer matrix b=[g n-k-1 ,…,g1,g0]';

[0015] Substitute the register value r(t+1) into itself p times to obtain a CRC encoding algorithm for p-bit parallel data:

[0016]

[0017] Among them, x is the data to be encoded, n represents the total number of bits of the register, k represents the order of the original polynomial, t represents time, and the coefficients g0, g1, ...g n-k-1 , g n-k The value is 0 or 1, indicating whether feedback is performed at this position. p represents the p-th power of the state transfer matrix A, B p Represents the input coefficients of the CRC encoding algorithm for p-bit parallel data obtained by inserting itself p times, and the input u p (t) is a column vector.

[0018] Preferably, the method of expressing the check operator as the product of the data to be encoded and the conversion matrix is: in the Galois field, the XOR logic and the addition operation are equivalent, then the check operator finally generated by the source polynomial is simplified to y=H·x, wherein x is the data to be encoded, H is the conversion matrix, and the number of XOR logic gates in the circuit is positively correlated with the "1" in the conversion matrix H; the check operator y finally generated is obtained by substituting the data to be encoded x into the source polynomial to obtain the parameters in the source polynomial to control the opening and closing of the XOR logic gate, the conversion matrix H is obtained by the source polynomial, and the data to be encoded x is sent by the user data.

[0019] Preferably, the implementation method of the fast common factor search algorithm is:

[0020] S1: Count the number of "1" in each row and column of the transformation matrix H;

[0021] S2: Determine two common factors based on the maximum and second largest values ​​of the column;

[0022] S3: Eliminate the "1" in the column where the common factor in the transformation matrix H is located, and use the new variable x k Replace the common factors and equivalently expand the rows and columns of the transformation matrix H;

[0023] S4: The number of rows of the transformation matrix H is k=k+1, and the number of columns is n=n+1. Repeat steps S1-S3 until the number of "1"s in each row of the transformation matrix H is less than or equal to 2, and the new transformation matrix H is obtained. new .

[0024] Preferably, the common factor is x e-1 and x f-1 , where e and f are the numbers corresponding to the maximum and second maximum values ​​of the column, and e is greater than f.

[0025] Preferably, the new variable x k The method of replacing the common factors and equivalently expanding the rows and columns of the transformation matrix H is: the common factor x of each row e-1 and x f-1 The corresponding coefficient "1" becomes "0"; the e and f columns of the k+1th row of the transformation matrix H are 1, the first k numbers of the n+1th column of the transformation matrix H are the results of the logical AND of the corresponding positions of the e and f columns, and the elements of the k+1th row and n+1th column are 0.

[0026] Preferably, the new transformation matrix H new The number of "1"s minus the total number of rows gives the number of XOR logic gates.

[0027] Preferably, the method for calculating the critical path length is as follows: calculating a new conversion matrix H new The number of "1"s in each row is denoted as W i , the new transformation matrix Hnew The number of newly added rows is recorded as M; calculate W i -2 value, when W i -2≥0 is recorded as row W maxi ; Search line W maxi The row with "1" in the last column is recorded as the location of the critical path W cpd ; Determine the critical path of the circuit schematic according to the location of the critical path; Determine the new conversion matrix H new Are there any associations between the newly added rows? If they are all associated, the critical path length is (M+1); otherwise, the critical path length is (M+1) minus the number of unassociated rows.

[0028] Preferably, the variables composed of common factors searched each time are composed of two common factors and are sequentially attached to the last row of the transformation matrix H. The critical path is located at the new transformation matrix H new The row corresponding to the last column contains two "1"s and one "1" is located in the row corresponding to the last column. The row where the critical path is located contains two "1"s, and the row where the critical path is located contains one delay unit. The "1" in the newly added column is obtained by converting two common factors, and each row has a delay unit; if there is no correlation between the newly added rows, the two are in parallel positions on the propagation path, and only one delay unit needs to be calculated.

[0029] The beneficial effects of the present invention are as follows: the present invention proposes a critical path length algorithm suitable for each combinational circuit module in a high-speed serial interface according to the structural characteristics of the high-speed serial interface. The present invention is based on a fast common factor search algorithm to quickly find and eliminate common factors in combinational logic units, further locate and calculate the critical path length in the combinational logic circuit, and obtain the minimum resource requirement to meet the operating frequency. After verification by the FPGA platform and actual test analysis, the present invention realizes a small-area, low-power data link layer, thereby reducing the use of logic units, and further realizing a small-area, low-power high-speed data encoding and decoding circuit.

[0030] The fast calculation algorithm for critical path length based on the fast common factor elimination algorithm proposed in the present invention is applicable to data of different bit widths. Compared with the traditional logic deduction method, the hardware resource consumption of the data encoding and decoding circuit is reduced by about 40% to 60%. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0032] Figure 1It is a flow chart of the present invention.

[0033] Figure 2 It is the principle diagram of the serial CRC encoding circuit of the present invention.

[0034] Figure 3 It is a schematic diagram of the operation process of the fast common factor search algorithm of the present invention.

[0035] Figure 4 The figure is a comparison diagram between the traditional algorithm and the algorithm for quickly searching and eliminating common factors of the present invention, wherein (a) is the circuit schematic diagram before optimization, and (b) is the circuit schematic diagram after the common factors are eliminated.

[0036] Figure 5 It is a schematic diagram of the circuit delay of the present invention.

[0037] Figure 6 Schematic diagram of the critical path in the circuit of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] like Figure 1 As shown, a method for calculating the critical path length suitable for high-speed serial interfaces is provided. The critical path length is quickly calculated based on a fast common factor elimination algorithm, the critical path in the data encoding and decoding module design is found, the minimum resource requirements to meet the operating frequency are obtained, and the area and power consumption of the circuit are reduced. The specific implementation process of the present invention is as follows:

[0040] Step 1: Use the logic deduction method, based on the serial circuit structure, and use the matrix to derive the results of parallel data to obtain the check operator.

[0041] In order to reduce the area and power consumption of the circuit, the present application adopts a logical deduction method to implement various encoding and decoding circuits.

[0042] The traditional logic deduction method is based on the serial circuit structure and uses the matrix to derive the result of parallel data. Assume that the CRC coding source polynomial and the serial structure coding circuit are as follows: Figure 2As shown in the figure, the circuit is mainly composed of a linear feedback shift register LFSR and an XOR logic gate. The parameter g in the source polynomial controls the opening and closing of the XOR logic gate. Every other clock cycle, the user data u(x) performs an XOR logic operation with the data stored in the register in the LFSR. The data in the final register is the syndrome of the CRC. Assume that the value of the register in the LFSR at time t is r(t) = [r n-k-1 ( t ),r n-k-2 (t),…r0(t)]′, where n represents the total number of bits in the register, k represents the order of the feedback polynomial, t represents time, and the input data is u(t). The value of the register in the next cycle can be obtained by equations (2) to (4). Substituting equation (2) into itself p times, a CRC encoding algorithm for p-bit parallel data can be obtained by equation (5).

[0043] g(x)=g0+g1x+…+g n-k-1 x n-k-1 +g n-k x n-k (1)

[0044] r(t+1)=A×r(t)+b×u(t) (2)

[0045]

[0046] b=[g n-k-1 ,…,g1,g0]' (4)

[0047]

[0048] Where x is the independent variable, representing the power term in the polynomial, g(x) represents the feedback polynomial, and the coefficient g i (i.e. g n-k ) is 0 or 1, indicating whether feedback is performed at this position. Matrix A is the state transfer matrix. b is a column vector representing the input coefficient. p represents the number of times equation (2) is introduced into itself. A p represents the pth power of matrix A, B p represents the input coefficient of the CRC encoding algorithm for p-bit parallel data obtained by substituting equation (2) into itself p times, u p (t) is a column vector representing the input.

[0049] If the above traditional logic deduction method is directly used to complete the design of parallel data scrambling, CRC, FEC and other encoding and decoding circuits, the problem of high consumption of combinational logic units will be faced. For example, for the CRC-12 algorithm in JESD204C, its original polynomial is as shown in formula (6). Since the order of the original polynomial is short, when 64-bit user data participates in the operation, the data propagation path experiences more XOR logic gates during the operation, and the corresponding delay is also greater. For example: For the check operator r0 of the CRC-12 algorithm, there are a total of 39 XOR logic gates involved in the operation, as shown in formula (7). The data propagation path contains more XOR logic gate units, which not only occupies more area resources, but also limits the circuit operating frequency, is prone to burrs, and brings burr power consumption.

[0050] g(x)=1+x+x 2 +x 3 +x 8 +x 9 +x 12 (6)

[0051]

[0052] Among them, u0, u3, ... 63 Represents the user data involved in the calculation, r1(t-1)…r 11 (t-1) represents the verification operator at the previous moment.

[0053] Step 2: Based on the principle that XOR logic is equivalent to addition, the check operator represents the product of the data to be encoded and the transformation matrix. The algorithm for quickly searching for common factors is used to search and eliminate the common factors of "1" in each row of the transformation matrix to obtain a new transformation matrix.

[0054] In the Galois domain, XOR logic is equivalent to addition operation, so the above algorithm can be simplified to the form of y=H·x, where y is the final generated check operator, x is the data to be encoded, H is the conversion matrix, and the number of XOR logic gates in the circuit is positively correlated with the "1" in H. Accordingly, the present application is based on an algorithm for quickly searching for common factors, which reduces the number of XOR logic gates by searching and eliminating the common factors of "1" in each row of the conversion matrix H. The algorithm for quickly searching for common factors includes the final generated check y, the conversion matrix H, and the data to be encoded x, wherein the final generated check y is obtained by substituting the data to be encoded into the source polynomial, and the parameter g in the source polynomial controls the opening and closing of the XOR logic gate. Every other clock cycle, the user data u(x) performs an XOR logic operation with the data stored in the register in the LFSR, and the data in the final register is the check y of the CRC, obtained by formula (6) (7). The conversion matrix H is obtained from the original polynomial. Since XOR logic is equivalent to addition operation, y = H x. After multiplying the conversion matrix H by the data to be encoded x, addition is equivalent to XOR operation. For example, for The data to be encoded is sent by user data.

[0055] like Figure 3 As shown, the algorithm is applicable to a variety of data encoding and decoding algorithms and is compatible with data of different bit widths. The steps include:

[0056] S1: Count the number of "1"s in each row and column of the transformation matrix H, denoted by m respectively i With n j ; The number of rows of the transformation matrix H is m, and the number of columns is n.

[0057] S2: Select m respectively i With n j The maximum and second largest positions of the columns are selected as the two common factors x e-1 、x f-1 In terms of obtaining common factors, the results of obtaining common factors for two rows and two columns at the same time are the same as those of obtaining common factors separately (intuitively, the common factor is the overlapping part of two rows and two columns. This setting can minimize the number of XOR logic gates. e and f are the column numbers corresponding to the maximum and second maximum values ​​of the column, and e is greater than f.

[0058] S3: Eliminate the "1" in the column where the common factor in the transformation matrix H is located, that is, replace "1" with "0", and use the variable x n =x e-1 +x f-1 Replace the common factor and append it to the rows and columns of the transformation matrix H. That is, append the coefficients of the corresponding rows of the e-th column and the f-th column to the corresponding row of the last column of the transformation matrix H. Only when the same row of the e-th column and the f-th column are both 1, the number of the row of the n+1th column is 1, otherwise it is 0. And replace the variable x n The corresponding coefficients are attached to the end of the last row of the transformation matrix H, that is, the corresponding values ​​of columns e and f in the m+1th row are 1, and the others are 0, and a new transformation matrix is ​​obtained; see the attached figure Figure 2 , the first column, second column, and nth column of the transformation matrix represent x0, x1, x n-1 , using x new Replacing the common factors is actually similar to merging the largest similar terms. Multiplying the merged transformation matrix by the encoded data x again to get equation (8), we will find that the number of “+” operations is the least, which means that the number of XOR logic gates is reduced.

[0059] S4: Repeat the above three steps until the number of "1" in each row of the transformation matrix H is less than or equal to 2, and the new transformation matrix H is obtained. new ; New transformation matrix H new The number of "1"s minus the total number of rows gives the number of XOR logic gates.

[0060] For example, when y = H·x as in equation (8), the number of rows and columns with the most and second most “1” in the transformation matrix H are m1, m2, n1, and n2 respectively, then x new =x0+x1, that is, x0 and x1 are common factors, which are eliminated in the transformation matrix H, and the variable x new Expand to the rows and columns of the transformation matrix H, search for the values ​​of m and n again according to the above steps and repeat the operation until the number of "1" in each row of the transformation matrix H is less than or equal to 2. The operation process is as follows Figure 2 As shown. By the new transformation matrix H new The number of XOR logic gates used in the circuit can be quickly obtained by adding the number of "1"s in each row and then subtracting the total number of rows (12-8=4). This method reduces 6 basic logic units compared to the traditional implementation scheme. Figure 4 shown.

[0061]

[0062] The fast common factor search algorithm based on the present invention can quickly find the common factors of the combinational logic in data encoding and decoding algorithms such as data scrambling, CRC and FEC and eliminate them. Compared with traditional algorithms, its hardware resource consumption is reduced by about 30%-50%. It is suitable for encoding and decoding operations of user data of different bit widths, and has low computational complexity.

[0063] Step 3: Determine the location of the critical path based on the number of "1"s in each column of the new transformation matrix, and calculate the length of the critical path based on the number of newly added variables and their associations in the new transformation matrix.

[0064] In digital circuits, if the data propagation path contains many combinational logic units, it is necessary to analyze the critical path to evaluate whether the circuit's operating frequency meets expectations. Without considering clock jitter and offset, the circuit's maximum operating frequency is obtained by equation (9), where T is the critical path length between the two triggers, and t clk-q is the delay between the input clock of the trigger and the data output, t comb is the longest propagation delay of the combinational logic circuit between two flip-flops, t setup is the trigger establishment time, such as Figure 5 shown.

[0065]

[0066] When the process is determined, the key factor affecting the circuit operating frequency is the longest transmission delay t comb For more complex combinational logic circuits, there are many data propagation paths, and how to quickly find the critical path is a more difficult problem.

[0067] In this regard, based on the above-mentioned fast common factor search algorithm, this application proposes an algorithm for calculating the critical path length based on matrix transformation: Calculate the new transformation matrix H new The number of "1"s in each row is denoted as W i , and the new transformation matrix H new The number of newly added rows is recorded as M; calculate W i -2, W i -2≥0 is denoted as W maxi ; Search W maxi The last row in the column that contains "1" is W. maxi Which last column is "1", denoted as W cpd , which is the location of the critical path. Figure 6 As shown, the critical path is a line connected by red arrows. The critical path directly determines the maximum delay of the circuit and affects the operating speed of the circuit. Quickly finding the critical path can help designers optimize the part with the longest delay, shorten the critical path, increase the operating frequency, and improve the overall operating speed of the circuit. Determine whether there is a correlation between the newly added rows. x5=x0+x1, x6=x3+x5, x7=x4+x6. In these three formulas, x6 uses x5, so the two are related. Similarly, x7 uses x6, so the two are related. Therefore, these three are related to each other. If they are all related, the critical path length is: M+1, otherwise the critical path length is M+1 minus the number of unrelated numbers.

[0068] In the present invention, since the common factor x is searched each time new They are composed of two items and are attached to the last row of the transformation matrix in sequence. Therefore, the critical path of the circuit is located in the new transformation matrix H new The row corresponding to the last column contains two "1"s and one "1" is located in the row corresponding to the last column. The row where the critical path is located contains two "1s", so the row contains a delay unit, and the "1" in the newly added column is converted from the two common factors in the same row, so each row has a delay unit. If there is no correlation between the newly added rows, the two are in parallel positions on the propagation path, and only one delay unit needs to be calculated. Still taking formula (8) as an example, the new conversion matrix H can be obtained by the algorithm of fast searching for common factors new According to the above algorithm, we know that M = 3, W cpd =1, that is, the critical path is in the first row, such as Figure 6 As shown. The sixth to eighth newly added rows are associated with each other, so the critical path length of this circuit is: M+1=4. This calculation result is consistent with Figure 6 The final result after matrix transformation is shown in formula (10), where three variables x5, x6, and x7 are added, that is, M = 3, and x5, x6, and x7 are related to each other, that is, the critical path is M + 1 = 4, which is the same as Figure 6Corresponding.

[0069]

[0070] Taking formula (8) proposed in the present invention as an example, formula (10) is obtained after transformation. The results show that the number of XOR logic gates used by the traditional method is 10, while the number of XOR logic gates used by the method proposed in the present invention is only 4, thereby reducing the use of logic units, thereby realizing a small-area, low-power, high-speed data encoding and decoding circuit.

[0071] method Number of XOR logic gates Traditional methods 10 The method proposed by the present invention 4

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for calculating the critical path length of a high-speed serial interface, characterized in that: The steps are as follows: Step 1: Based on the serial circuit structure, use the logic deduction method to derive the result of parallel data with the help of the matrix to obtain the check operator; Step 2: Based on the principle that XOR logic is equivalent to addition, the check operator is expressed as the product of the data to be encoded and the transformation matrix. The common factor of "1" in each row of the transformation matrix is ​​searched and eliminated using the fast common factor search algorithm to obtain a new transformation matrix. Step 3: Determine the location of the critical path based on the number of "1"s in each column of the new transformation matrix, and calculate the length of the critical path based on the number of newly added variables and their associations in the new transformation matrix.

2. The critical path length calculation method applicable to a high-speed serial interface according to claim 1, characterized in that: The method for obtaining the check operator in step 1 is: determining the source polynomial of the serial circuit structure; every other clock cycle, the user data u(x) and the data stored in the register in the serial circuit structure are subjected to an XOR logic operation using the source polynomial, and the data in the final register is the check operator.

3. The critical path length calculation method applicable to a high-speed serial interface according to claim 2, characterized in that: The original polynomial is: g(x)=g0+g1x+…+g n-k-1 x n-k-1 +g n-k x n-k ; Assume the register value at time t is r(t)=[r n-k-1 ( t ),r n-k-2 (t),…,r0(t)]′, the input data is u(t), then the value of the register in the next cycle r(t+1)=A×r(t)+b×u(t), where the state transfer matrix b=[g n-k-1 ,…,g1,g0]'; Substitute the register value r(t+1) into itself p times to obtain a CRC encoding algorithm for p-bit parallel data: Among them, x is the data to be encoded, n represents the total number of bits of the register, k represents the order of the original polynomial, t represents time, and the coefficients g0, g1, ...g n-k-1 , g n-k The value is 0 or 1, indicating whether feedback is performed at this position. p represents the p-th power of the state transfer matrix A, B p Represents the input coefficients of the CRC encoding algorithm for p-bit parallel data obtained by inserting it p times. Input u p (t) is a column vector.

4. The critical path length calculation method applicable to a high-speed serial interface according to claim 2 or 3, characterized in that: The method of expressing the check operator as the product of the data to be encoded and the conversion matrix is ​​as follows: in the Galois domain, the XOR logic and the addition operation are equivalent, and the check operator finally generated by the source polynomial is simplified to y=H·x, wherein x is the data to be encoded, H is the conversion matrix, and the number of XOR logic gates in the circuit is positively correlated with the "1" in the conversion matrix H; the check operator y finally generated is obtained by substituting the data to be encoded x into the source polynomial to obtain the parameters in the source polynomial to control the opening and closing of the XOR logic gate, the conversion matrix H is obtained by the source polynomial, and the data to be encoded x is sent by the user data.

5. The critical path length calculation method applicable to a high-speed serial interface according to claim 4, characterized in that: The implementation method of the fast common factor search algorithm is: S1: Count the number of "1" in each row and column of the transformation matrix H; S2: Determine two common factors based on the maximum and second largest values ​​of the column; S3: Eliminate the "1" in the column where the common factor in the transformation matrix H is located, and use the new variable x k Replace the common factors and equivalently expand the rows and columns of the transformation matrix H; S4: The number of rows of the transformation matrix H is k=k+1, and the number of columns is n=n+1. Repeat steps S1-S3 until the number of "1"s in each row of the transformation matrix H is less than or equal to 2, and the new transformation matrix H is obtained. new .

6. The critical path length calculation method applicable to a high-speed serial interface according to claim 5, characterized in that: The common factor is x e-1 and x f-1 , where e and f are the numbers corresponding to the maximum and second maximum values ​​of the column, and e is greater than f.

7. The critical path length calculation method applicable to a high-speed serial interface according to claim 6, characterized in that: The new variable x k The method of replacing the common factors and equivalently expanding the rows and columns of the transformation matrix H is: the common factor x of each row e-1 and x f-1 The corresponding coefficient "1" becomes "0"; the e and f columns of the k+1th row of the transformation matrix H are 1, the first k numbers of the n+1th column of the transformation matrix H are the results of the logical AND of the corresponding positions of the e and f columns, and the elements of the k+1th row and n+1th column are 0.

8. The critical path length calculation method for a high-speed serial interface according to any one of claims 5 to 7, characterized in that: The new transformation matrix H new The number of "1"s minus the total number of rows gives the number of XOR logic gates.

9. The critical path length calculation method applicable to a high-speed serial interface according to claim 8, characterized in that: The method for calculating the critical path length is as follows: Calculate the new conversion matrix H new The number of "1"s in each row is denoted as W i , the new transformation matrix H new The number of newly added rows is recorded as M; calculate W i -2 value, when W i -2≥0 is recorded as row W maxi ; Search line W maxi The row with "1" in the last column is recorded as the location of the critical path W cpd ; Determine the critical path of the circuit schematic according to the location of the critical path; Determine the new conversion matrix H new Are there any associations between the newly added rows? If they are all associated, the critical path length is (M+1); otherwise, the critical path length is (M+1) minus the number of unassociated rows.

10. The critical path length calculation method applicable to a high-speed serial interface according to claim 9, characterized in that: The critical path is located in the new transformation matrix H new The row corresponding to the last column contains two "1"s and one "1" is located in the row where the critical path is located. The row where the critical path is located contains two "1"s, and the "1" in the newly added column is obtained by converting two common factors. Each row has a delay unit; if there is no correlation between the newly added rows, the two rows are in parallel positions on the propagation path, and only one delay unit needs to be calculated.

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