Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a plurality of shift registers which are sequentially cascaded along a first direction; the pixel circuit group comprises at least two pixel circuit units arranged along a first direction; wherein in the first direction, at least part of the pixel circuit units do not comprise shift registers. According to the embodiment of the invention, a plurality of pixel circuit units are continuously prepared in the first direction and are not separated by a shift register, so that the preparation compactness of a circuit structure in the display panel is improved, a space nesting condition is provided during circuit preparation, and the space utilization rate during wiring preparation is improved. The feasibility of reducing the area occupied by the circuit structure for preparing the pixel circuit unit and the shift register circuit is improved, enough avoiding space is reserved at the edge position of the display panel, available space is provided for preparing other types of leads, and the applicability of the display panel in a narrow-frame or frameless display device is improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, the market demand for narrow-border screens and even borderless screens is getting wider and wider. For example, in the preparation of some special-shaped display screens or large display screens, multiple narrow-border or borderless screens can usually be spliced ​​together. When preparing narrow-border or borderless screens, in order to allow the display panel to be spliced ​​with other panels and connect signals, the space near the edge of the display panel can be set with pixel circuits and electrostatic release terminals and other lead wires, multiplexer and other circuit structures. At this time, when preparing pixel circuits and other circuits in the display panel, it is necessary to avoid the wiring around the display panel, such as cascade lines, electrostatic release wiring, pins, wiring in the multiplexer circuit and other line structures, to provide sufficient space for the above wiring to ensure the normal operation of the display panel. Therefore, in the application of some narrow-border and borderless display panels, in the process of preparing pixel circuits and shift register circuits in the display panel, improving the compactness of the circuit structure and the space utilization rate are of great significance to improving the progress of display technology. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including a display area, wherein the display area includes:

[0005] A driving circuit, comprising a plurality of shift registers cascaded in sequence along a first direction;

[0006] A pixel circuit group, comprising at least two pixel circuit units arranged along a first direction;

[0007] Wherein, in the first direction, at least some of the pixel circuit units do not include shift registers.

[0008] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0009] In the embodiment of the present application, in the first direction, at least some of the pixel circuit units do not include a shift register, that is, the pixel circuit units prepared in the pixel circuit group in the display area are continuously arranged adjacent to each other in the first direction, and the plurality of adjacently arranged pixel circuit units do not include a shift register. Figure 1 , Figure 2As shown, two pixel circuit units are prepared adjacently in the first direction, and the two adjacent pixel circuit units can be located between two shift registers of adjacent levels. In combination with the relevant technology, it can be known that in the first direction, a plurality of pixel circuit units are prepared continuously without being separated by a shift register in the middle, which is conducive to improving the compactness of the circuit structure preparation in the display panel. This is because the structures of the plurality of pixel circuit units are similar, and the conditions for spatial nesting are available when the circuit is prepared, and the signal frequencies transmitted on the plurality of pixel circuit units are also similar, which is conducive to reducing the risk of crosstalk. Therefore, after at least part of the pixel circuit units in the display panel are set without including a shift register, it is conducive to better utilizing the space adjacent to the routing in the second direction, and it is unnecessary to arrange the plurality of routings one by one along the first direction, thereby improving the space utilization rate when the routing is prepared. The feasibility of reducing the area occupied by the circuit structure of the pixel circuit unit and the shift register circuit is improved, and sufficient avoidance space is reserved at the edge of the display panel to provide available space for preparing other types of leads, which is conducive to improving the applicability of the display panel in a narrow-frame or borderless display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0012] Figure 2 A schematic plan view of another display panel provided in an embodiment of the present application;

[0013] Figure 3 A method provided in the embodiment of the present application Figure 1 A schematic plan view of the middle area E1;

[0014] Figure 4 A method provided in the embodiment of the present application Figure 1 A schematic plan view of the middle area E2;

[0015] Figure 5 A method provided in the embodiment of the present application Figure 1 A schematic plan view of the middle area E3;

[0016] Figure 6 A method provided in the embodiment of the present application Figure 1 Schematic diagram of the plane of the middle area E1 and area E2;

[0017] Figure 7 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0018] Figure 8 A method provided in the embodiment of the present application Figure 6 A partial schematic diagram of the middle area E4;

[0019] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application;

[0020] Fig.10 A schematic plan view of another display panel provided in an embodiment of the present application;

[0021] Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application;

[0022] Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application;

[0023] Fig.13 A schematic plan view of another display panel provided in an embodiment of the present application;

[0024] Fig.14 A method provided in the embodiment of the present application Fig.13 A partial schematic diagram of the middle area E5;

[0025] Fig.15 A schematic plan view of another display panel provided in an embodiment of the present application;

[0026] Fig.16 A schematic plan view of another display panel provided in an embodiment of the present application;

[0027] Fig.17 A schematic plan view of another display panel provided in an embodiment of the present application;

[0028] Fig.18 A schematic plan view of another display panel provided in an embodiment of the present application;

[0029] Fig.19 A schematic plan view of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0030] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0032] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0033] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0034] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0035] It should be understood that although the terms first, second, etc. may be used to describe directions, routing, sub-areas, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish directions, routing, sub-areas, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first direction may also be referred to as the second direction, and similarly, the second direction may also be referred to as the first direction. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0036] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application, Figure 2 A schematic plan view of another display panel provided in an embodiment of the present application.

[0037] The embodiment of the present application provides a display panel 100, such as Figure 1 , Figure 2As shown, the display panel 100 includes a display area AA, the display area AA includes a driving circuit 10, and the driving circuit 10 includes a plurality of shift registers 101 sequentially cascaded along a first direction X1. The display area AA also includes a pixel circuit group 20, and the pixel circuit group 20 includes at least two pixel circuit units 201 arranged along the first direction X1. In the display area AA, at least part of the shift registers 101 are used to be electrically connected to the pixel circuit unit 201, and are used to drive the pixel circuit unit 201 to work, thereby realizing the display work of the display panel 100.

[0038] Alternatively, if Figure 1 As shown, in the preparation process of some narrow-frame display panels 100, part of the shift register 101 in the driving circuit 10 can be arranged in the frame area, and part of the shift register 102 can be arranged in the display area AA. Figure 2 As shown, in the preparation process of some borderless display panels 100, the shift register 101 in the driving circuit 10 can be set to be located in the display area AA. Of course, in the preparation process of the display panel 100, the preparation position of the shift register 101 in the driving circuit 10 can be determined according to the actual use situation. When the shift register 101 is prepared in the display area AA, it is beneficial to improve the space utilization of the display area AA in the display panel 100, reduce the circuit structure prepared in the frame of the display panel 100, thereby reducing the frame area, increasing the effective screen ratio of the display panel 100, and improving the visual experience of the display panel 100.

[0039] In the display area AA, multiple shift registers 101 are cascaded in the first direction X1. It can be seen that there are also pixel circuit units 20 arranged in the first direction X1 in the display area AA. In the related art, multiple shift registers and pixel circuit units arranged in the first direction are usually arranged alternately to form an arrangement of shift registers, pixel circuit units, shift registers, pixel circuit units, etc. in the first direction. In this arrangement, a shift register and a pixel circuit unit are adjacent in the first direction, and the wiring structure belonging to the pixel circuit unit part and the wiring structure belonging to the shift register part are usually arranged adjacent in the first direction. Such a circuit has a high degree of regularity, but when multiple wirings are arranged adjacent in the first direction, it is easy to make the adjacent positions of the wirings in the second direction vacant and not used, thereby increasing the area occupied by the circuit structure of the pixel circuit unit and the shift register, which is not conducive to improving the compactness of the circuit structure and reserving sufficient avoidance space at the edge of the display panel; the second direction is a direction intersecting the first direction.

[0040] In the embodiment of the present application, at least some of the pixel circuit units 201 are arranged in the first direction X1, and the shift register 101 is not included between them. That is, the pixel circuit units 201 prepared in the pixel circuit group 20 in the display area AA are arranged continuously and adjacently in the first direction X1, and the shift register 101 is not included between the plurality of adjacently arranged pixel circuit units 201. For example, Figure 1 , Figure 2 As shown, two pixel circuit units 201 are prepared adjacently in the first direction X1, and the two adjacently prepared pixel circuit units 201 can be located between two shift registers 101 of adjacent levels. In combination with the relevant technology, it can be known that in the first direction X1, a plurality of pixel circuit units 201 are prepared continuously without being separated by the shift register 101 in the middle, which is conducive to improving the compactness of the circuit structure preparation in the display panel 100. This is because the structures of the plurality of pixel circuit units 201 are similar, and the conditions for spatial nesting are met during circuit preparation, and the signal frequencies transmitted on the plurality of pixel circuit units 201 are also similar, which is conducive to reducing the risk of crosstalk. Therefore, after at least part of the pixel circuit units 201 are set in the display panel 100 without including the shift register 101, it is conducive to better utilizing the space adjacent to the wiring in the second direction X2, and it is unnecessary to arrange the plurality of wirings one by one along the first direction X1, thereby improving the space utilization rate during wiring preparation. The feasibility of reducing the area occupied by the circuit structure of the pixel circuit unit 201 and the shift register circuit 101 is improved, and sufficient avoidance space is reserved at the edge of the display panel 100 to provide available space for preparing other types of leads, which is beneficial to improving the applicability of the display panel 100 in narrow-frame or frameless display devices.

[0041] Figure 3 A method provided in the embodiment of the present application Figure 1 Schematic plan view of the middle area E1.

[0042] In one embodiment of the present application, Figure 1 , Figure 3 As shown, in the display area AA, the pixel circuit unit 201 includes at least two pixel circuits 30, and the multiple pixel circuits 30 included in the pixel circuit unit 201 can respectively drive one of the light-emitting devices in the same pixel to emit light. The pixel circuit 30 includes a pulse width modulation module 301 and a pulse amplitude modulation module 302, the pulse width modulation module 301 is electrically connected to the first signal line SL1, and the pulse amplitude modulation module 302 is electrically connected to the second signal line SL2, and the first signal line SL1 and the second signal line SL2 both extend along the first direction X1.

[0043] The pixel circuit 30 proposed in the embodiment of the present application is a form in which a pulse width modulation module 301 and a pulse amplitude modulation module 302 jointly drive the light-emitting device to emit light. The pulse width modulation module 301 prepared in the pixel circuit 30 can be used to control the light-emitting duration of the light-emitting device driven by the pixel circuit 30. In the pixel circuit 30, the pulse width modulation module 301 is provided to facilitate better brightness control of the light-emitting device. The light-emitting duration of the light-emitting device is adjusted by changing the width of the pulse. Generally, a longer pulse width corresponds to a longer light-emitting duration, so that the light-emitting device produces a higher light-emitting brightness. The pulse width modulation module 301 can achieve more precise brightness control and can be applied to display applications requiring high resolution and high frequency. The pulse width modulation module 301 can receive a pulse width data signal Pwm-data, and the first signal line SL1 here can be used to transmit the pulse width data signal Pwm-data. The first signal line SL1 extends in the first direction X1, and can be electrically connected to a plurality of pixel circuits 30 arranged in the first direction X1. The same first signal line SL1 can transmit corresponding pulse width data signals Pwm-data to different pixel circuits 30 in time division.

[0044] The pulse amplitude modulation module 302 can receive the pulse amplitude data signal Pam-data, so the second signal line SL2 can be used to transmit the pulse amplitude data signal Pam-data. Similarly, the second signal line SL2 extends along the first direction X1, and the second signal line SL2 can be electrically connected to a plurality of pixel circuits 30 arranged along the first direction X1, and the second signal line SL2 can transmit different pulse amplitude data signals Pam-data to different pixel circuits 30 in different time periods. The pulse amplitude modulation module 302 prepared in the pixel circuit 30 can achieve more accurate luminous brightness control by adjusting the pulse amplitude of the pulse amplitude data signal Pam-data. Compared with the traditional method of using only voltage to control the luminous brightness, the use of the pulse width modulation module 301 and the pulse amplitude modulation module 302 to jointly control the light-emitting process of the light-emitting device is conducive to improving the working stability and accuracy of the light-emitting device, and can effectively reduce the influence of noise in the circuit on the working of the light-emitting device, thereby improving the image clarity and stability when the display panel 100 is displayed, and improving the visual effect. Furthermore, the use of the pixel circuit 30 including the pulse width modulation module 301 and the pulse amplitude modulation module 302 is beneficial to improving the technical standards applicable to the embodiments of the present application, improving the compatibility with the existing display technologies, and improving the usability of the embodiments of the present application.

[0045] Further, along the second direction X2, the first signal line SL1 and the second signal line SL2 are respectively arranged on the opposite sides of the pixel circuit unit 201, which is conducive to improving the structural symmetry of the display panel 100, thereby improving the uniformity of the display panel 100 when working. In addition, if the first signal line SL1 and the plurality of second signal lines SL2 are arranged on the same side of the pixel circuit unit 201, it is easy to cause the pixel circuit 30 to cross more signal lines when electrically connected to the signal line, which is easy to increase the coupling degree between the lines, and is not conducive to ensuring the accuracy of the signal transmitted by the first signal line SL1 and the second signal line SL2. Therefore, in the embodiment of the present application, the first signal line SL1 and the second signal line SL2 are respectively arranged on the opposite sides of the pixel circuit unit 201, which is conducive to improving the accuracy of the pulse width data signal Pwm-data and the pulse amplitude data signal Pam-data received by the pixel circuit 30, and is conducive to ensuring the working stability of the pixel circuit 30 when combined with the arrangement of the pixel circuit unit 201 and the shift register 201 proposed in the embodiment of the present application, thereby improving the feasibility of the embodiment of the present application.

[0046] In one embodiment of the present application, continue to refer to Figure 1 , Figure 3 As shown, in the same pixel circuit group 20, in two pixel circuits 30 adjacent to each other in the first direction X1, the pulse width modulation module 301 of one pixel circuit 30 is adjacent to the pulse amplitude modulation module 302 of the other pixel circuit. In the embodiment of the present application, the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the same pixel circuit 30 are electrically connected and prepared adjacently along the first direction X1 as an example for explanation. In combination with the above content, it can be known that the display panel 100 includes at least some pixel circuit units 201 without a shift register 101, then, in the same pixel circuit group 20, the pulse width modulation module 301 of the pixel circuit 30 in one pixel circuit unit 201 can be adjacent to the pulse amplitude modulation module 302 of the pixel circuit 30 in the pixel circuit unit 201 adjacent to each other in the first direction X1.

[0047] Since the pulse width modulation module 301 is electrically connected to the first signal line SL1, the pulse amplitude adjustment module 302 is electrically connected to the second signal line SL2, and the first signal line SL1 and the second signal line SL2 are respectively located on opposite sides of the pixel circuit unit 201 in the second direction X2, the winding direction when the pulse width modulation module 301 is electrically connected to the first signal line SL1 and the winding direction when the pulse amplitude modulation module 302 is electrically connected to the second signal line SL2 may be opposite. Therefore, when the pulse width modulation module 301 of one pixel circuit 30 is adjacent to the pulse amplitude modulation module 302 of the other pixel circuit in two pixel circuits 30 adjacent to each other in the first direction X1, it becomes possible for the first signal line SL1 and the second signal line SL2 electrically connected to the two pixel circuits 30 electrically connected in the first direction X1 to be prepared by utilizing each other in the adjacent space in the second direction X2; this is beneficial for making the circuit structure of the pulse width modulation module 301 of one pixel circuit 30 and the circuit structure of the pulse amplitude modulation module 302 of the other pixel circuit 30 in the two pixel circuits 30 adjacent to each other in the first direction X1 at least partially nested in space, and the multiple pixel circuit units 20 prepared in the first direction X1 have the ability to retract, thereby providing avoidance space for the preparation of other wiring at the edge of the display panel 100.

[0048] In one embodiment of the present application, continue to refer to Figure 1 , Figure 3 As shown, the pulse width modulation module 301 is electrically connected to the first signal line SL1 through the first line L1, and the pulse amplitude modulation module 302 is electrically connected to the second signal line SL2 through the second line L2. It should be noted that the first signal line SL1 and the second signal line SL2 are both lines extending along the first direction X1. When the pixel circuit 30 is electrically connected to the first signal line SL1, the first line L1 can be wound from the pixel circuit 30 toward the side where the first signal line SL1 is located. At least part of the first line L1 is extended along the second direction X2, and the multiple first signal lines SL1 electrically connected to the multiple pixel circuits 30 in the same pixel circuit unit 201 are arranged adjacent to each other on one side of the pixel circuit 30. When the first line L1 is electrically connected to the first signal line SL1 corresponding to it, there is a situation where it is necessary to cross other first signal lines SL1. Therefore, the first line L1 and the first signal line SL1 can be set to be located in different film layers, and the first line SL1 and the first signal line SL1 are electrically connected through punching. Similarly, the second routing line L2 and the second signal line SL2 may be located in different film layers, and the second routing line and the second signal line SL2 may be electrically connected via a perforation.

[0049] It can be imagined that in the same pixel circuit unit 201, the plurality of first wirings L1 are all wound toward the side where the first signal line SL1 is located, and the plurality of pixel circuits 20 can be arranged along the second direction X2. In this case, there are portions parallel to the first direction X1 and portions parallel to the second direction X2 between the plurality of first wirings L1. Similarly, in the same pixel circuit unit 201, there are portions parallel to the first direction X1 and portions parallel to the second direction X2 between the plurality of second wirings L2.

[0050] In the embodiment of the present application, in the same pixel circuit group 20, at least part of the first wiring L1 electrically connected to the pulse width modulation module 301 in one pixel circuit unit 201 overlaps with at least part of the second wiring L2 electrically connected to the pulse amplitude modulation module 302 in another pixel circuit unit 201 in the second direction X2, which is conducive to making full use of the space between two adjacent pixel circuit units 201, so that the wiring prepared in the first direction X1 can use the space of each other, reduce the space occupied when preparing the first wiring L1 and the second wiring L2, and improve the space utilization when preparing the wiring structure in the display area AA. In addition, the overlap mentioned here refers to the corresponding position in the second direction X2, not the contact of the two wirings.

[0051] Figure 4 A method provided in the embodiment of the present application Figure 1 Schematic diagram of the middle area E2, Figure 5 A method provided in the embodiment of the present application Figure 1 Schematic diagram of the middle area E3, Figure 6 A method provided in the embodiment of the present application Figure 1 Schematic plan view of area E1 and area E2.

[0052] In one embodiment of the present application, Figure 4 As shown, the pulse amplitude modulation module 302 in the pixel circuit 30 includes a light-emitting driving current output terminal OUT1, and the light-emitting driving current output terminal OUT1 is electrically connected to the light-emitting device 200. In the structure of the display panel 100, the light-emitting device 200 is usually located on the side of the pixel circuit 30 facing the light-emitting surface of the display panel 100, and the light-emitting driving current terminal OUT1 of the pixel circuit 30 is electrically connected to one electrode of the light-emitting device 200. The circuit structure included in the pixel circuit 30 is relatively complex. In the direction perpendicular to the plane where the display panel 100 is located, the area occupied by the pixel circuit 30 is generally larger than the area occupied by the light-emitting device 200 electrically connected to it. When the light-emitting device 200 and the pixel circuit 30 are prepared one by one in the display panel 100, there is a situation where the light-emitting device 200 and the pixel circuit 30 are not completely aligned, and there is also a situation where the light-emitting driving current terminal OUT of the pixel circuit 30 needs to be electrically connected to the light-emitting device 200 through a certain degree of winding.

[0053] In view of the fact that the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the same pixel circuit 30 are arranged along the first direction X1, in the same pixel circuit 30, the distance between the pulse amplitude modulation module 302 and the light-emitting device 200 driven by it in the first direction X1 is different from the distance between the pulse width modulation module 301 and the light-emitting device 200 driven by it in the first direction X1.

[0054] Take the case where the display panel includes an upper frame and a lower frame in the first direction X1, and the light-emitting device 200 and the pixel circuit 30 are prepared one by one from the upper frame to the lower frame. In the related art, the pulse width modulation module in the pixel circuit is usually prepared at a position close to the upper frame, and the pulse amplitude modulation module is prepared at a position close to the lower frame. Then, in the first direction, the distance between the light-emitting device 200 at least partially close to the upper frame portion and the pulse width modulation module 301 in the pixel circuit 30 electrically connected thereto is greater than the distance between the pulse amplitude modulation module 302 in the pixel circuit 30 electrically connected thereto. And the distance between the light-emitting device 200 at least partially close to the lower frame portion and the pulse amplitude modulation module 302 in the pixel circuit 30 electrically connected thereto is greater than the distance between the pulse width modulation module 301 in the pixel circuit 30 electrically connected thereto.

[0055] In the embodiment of the present application, the arrangement order of the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the first type pixel circuit 30A in the first direction X1 is opposite to the arrangement order of the pulse width modulation module 301 and the pulse amplitude modulation module 302 in the second type pixel circuit 30B in the first direction X1. Figure 4 As shown, the display panel 100 includes a first type pixel circuit 30A; or, alternatively, as Figure 5 As shown, the second type pixel circuit 30B included in the display panel 100 is set. Or, optionally, as Figure 6 As shown, the display panel 100 includes a first type of pixel circuit 30A and a second type of pixel circuit 30B. The first type of pixel circuit 30A is a pixel circuit 30 in which the pulse amplitude modulation module 302 is closer to the upper frame of the display panel 100 than the pulse width modulation module 301, and the second type of pixel circuit 30B is a pixel circuit 30 in which the pulse width modulation module 301 is closer to the upper frame of the display panel 100 than the pulse amplitude modulation module 301. Figure 4As shown, setting the pixel circuit 30 in the display panel 100 as the first type pixel circuit 30A is conducive to making the pulse amplitude modulation module 302 in at least part of the pixel circuits 30 near the upper frame area of ​​the display panel 100 closer to the light-emitting device 200 electrically connected thereto than the pulse width modulation module 301, which is conducive to reducing the degree of winding when the light-emitting driving current terminal OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light-emitting device 200, thereby reducing the amount of wiring in the display panel 100 and providing more space for preparing other leads in the display panel 100. Or, as Figure 5 As shown, the pixel circuit 30 in the display panel 100 is set to be the second type of pixel circuit 30B, which is conducive to making the pulse amplitude modulation module 302 in at least part of the pixel circuit 30 near the lower frame area of ​​the display panel 100 closer to the light-emitting device 200 electrically connected thereto than the pulse width modulation module 301, which is conducive to reducing the degree of winding when the light-emitting driving current terminal OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light-emitting device 200, thereby reducing the amount of wiring in the display panel 100, and providing more space for preparing other leads in the display panel 100. It should be noted that the wiring when the pixel circuit 30 is electrically connected to the light-emitting device 200 can be located in a different film layer from the structures such as each transistor of the pixel circuit 30. The wiring when the pixel circuit 30 is electrically connected to the light-emitting device 200 shown in the schematic diagram will use cross-line and other processes in the actual structure and will not cross other wirings in the pixel circuit 30 and the shift register 101.

[0056] Or, if Figure 6 As shown, the display panel 100 includes a first type pixel circuit 30A and a second type pixel circuit 30B. Optionally, the first type pixel circuit 30A is prepared at a position near the upper frame area of ​​the display panel 100, and the second type pixel circuit 30B is prepared at a position near the lower frame area of ​​the display panel 100. This is conducive to making the pulse amplitude modulation module 302 in the first type pixel circuit 30A near the upper frame area of ​​the display panel 100 closer to the light-emitting device 200 electrically connected thereto than the pulse width modulation module 301, and making the pulse amplitude modulation module 302 in the second type pixel circuit 30B near the lower frame area of ​​the display panel 100 closer to the light-emitting device 200 electrically connected thereto than the pulse width modulation module 301. From the overall view of the display panel 100, it is conducive to further reducing the degree of winding when the light-emitting driving current terminal OUT1 in the pulse amplitude modulation module 302 is electrically connected to the light-emitting device 200, reducing the amount of wiring in the display panel 100, and providing more space for preparing other leads in the display panel 100.

[0057] Figure 7A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 8 A method provided in the embodiment of the present application Figure 6 A partial schematic diagram of the middle area E4.

[0058] In one embodiment of the present application, Figure 7 , Figure 8As shown, illustratively, the embodiment of the present application provides a 17T3C type pixel circuit 30, which can be used to generate a light-emitting driving current to drive a light-emitting device 200 to emit light. Optionally, the light-emitting device 200 is any one of a micro light-emitting diode (Micro-LED), a sub-millimeter light-emitting diode (Min i-LED), and an organic light-emitting diode (OLED). The pixel circuit 30 includes a pulse width modulation module 301 and a pulse amplitude modulation module 302. The pulse width modulation module 301 includes transistors T1 to T7, wherein transistor T1 is used to receive a first power drive signal Pwm-VDD of the pulse width modulation module 301; transistor T2 is used to receive a pulse width data signal Pwm-data and transmit it to transistor T3; transistor T4 is used to compensate for a threshold voltage of transistor T3; transistor T5 is used to receive a pulse width reset signal Pwm-ref; transistor T6 is connected in series between a swept frequency constant voltage signal line SWEEP_GND and a first capacitor C1 (for example, a plate in the first capacitor C1 connected to the swept frequency signal line SWEEP), and transistor T6 is turned on to transmit a swept frequency constant voltage provided by the swept frequency constant voltage signal line SWEEP_GND to the first capacitor C3. The swept frequency constant voltage may be the same as a high level of the swept frequency signal, or the same as a low level of the swept frequency signal. At this time, the sweep frequency constant voltage signal line SWEEP_GND and the sweep frequency signal line SWEEP both provide signals to one plate of the first capacitor C1 (for example, the plate in the first capacitor C3 connected to the sweep frequency signal line SWEEP), which can further ensure the stability of the plate potential of the first capacitor C1 and reduce the signal disturbance caused by peripheral signals; the transistor T7 is used to electrically connect the pulse width modulation module 301 and the pulse amplitude modulation module 302.The pulse amplitude modulation module 302 includes transistors T8 to T14, wherein the transistor T8 is used to receive the second power supply driving signal Pam-VDD of the pulse amplitude modulation module 302; the transistor T9 is used to control the light-emitting driving current to flow to the light-emitting device 200; the transistor T10 is used to receive the pulse amplitude data signal Pam-data and transmit it to the transistor T11; the transistor T12 is used to compensate the threshold voltage of the transistor T11 to the gate of the transistor T11; the transistor T13 is used to receive the pulse amplitude reset signal Pam-REF and transmit it to the gate of the transistor T11; the transistor T14 is used to receive the reset signal transmitted by the reset signal line Pam-INIT, and transmit it to the first electrode of the light-emitting device 200; The transistor T15 is turned on to transmit the voltage provided by the second power drive signal Pam-VDD to the second capacitor C2, so that the voltage on the second power drive signal Pam-VDD is applied to the amplitude adjustment module 302 in the light-emitting stage to provide the light-emitting device 200 with a light-emitting drive current; the transistor T16 is connected in series between the first power drive signal Pwm-VDD and the second capacitor C2, and when the transistor T16 is turned on, the voltage provided by the first power drive signal Pwm-VDD is transmitted to the second capacitor C2; the transistor T17 is also connected in series between the first power drive signal Pwm-VDD and the second capacitor C2, and the transistor T15 is turned on to transmit the voltage provided by the first power drive signal Pwm-VDD to the second capacitor C2. Further, the pulse amplitude modulation module 302 also includes a third capacitor C3, which is connected in series between the reset signal line Pam-INIT and the second capacitor C2, and can be used to stabilize the plate potential of the second capacitor C2.

[0059] In the embodiment of the present application, the circuit structure of the first type pixel circuit 30A is set to be symmetrical with the circuit structure of the second type pixel circuit 30B, which is conducive to improving the convenience of preparing the first type pixel circuit 30A and the second type pixel circuit 30B in the display panel 100, improving the structural regularity of the display panel 100, and is conducive to preparing the display panel 100 by means of symmetrical preparation, thereby improving the preparation efficiency of the display panel 100. In addition, it is conducive to ensuring the uniformity of the first type pixel circuit 30A and the second type pixel circuit 30B when using the first type pixel circuit 30A and the second type pixel circuit 30B, reducing the difference between the two when driving the light-emitting device 200, and improving the uniform display effect of the display panel 100.

[0060] Fig. 9 A schematic plan view of another display panel provided in an embodiment of the present application.

[0061] In one embodiment of the present application, Fig. 9As shown, the display area AA includes a first sub-area AA1, a second sub-area AA2, and a third sub-area AA3 distributed in the first direction X1, and the first sub-area AA1 and the third sub-area AA3 are respectively located at opposite sides of the second sub-area AA2 in the first direction X1. Optionally, in the first direction X1, the first sub-area AA1 is located in an area closer to the upper frame in the display area AA, the third sub-area AA3 is located in an area closer to the lower frame in the display area AA, and the second sub-area AA2 is located in a relatively middle area in the display area AA.

[0062] In the embodiments of the present application, Figure 6 As shown, one of the first sub-area AA1 and the third sub-area AA3 includes the first type of pixel circuit 30A and the other includes the second type of pixel circuit 30B. Optionally, the first sub-area AA1 includes the first type of pixel circuit 30A, and the second type of pixel circuit 30B includes the second type of pixel circuit 30B, which is conducive to reducing the wiring distance of the light emitting drive current output terminal OUT1 in the first sub-area AA1 and the third sub-area AA3 and the light emitting device 200. In addition, in combination Fig. 9 As shown, setting the second sub-area AA2 to include the first type of pixel circuit 30A and / or the second type of pixel circuit 30B is conducive to adaptively preparing the first type of pixel circuit 30A and / or the second type of pixel circuit 30B in the second sub-area AA2 according to actual usage, further improving the compactness of the wiring preparation in the display area AA.

[0063] Fig.10 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.11 A schematic plan view of another display panel provided in an embodiment of the present application.

[0064] In one embodiment of the present application, Figure 9-11 As shown, the first sub-area AA1 and / or the third sub-area AA3 are set to include the pixel circuit group 20, and the second sub-area AA2 does not include the pixel circuit group 20. In combination with the above content, it can be seen that the pixel circuit group 20 includes a plurality of adjacent pixel circuit units 201, and the shift register 101 is not included between the adjacent pixel circuit units 201, which is conducive to realizing the structural shrinkage when preparing the pixel circuit 30, and providing a larger avoidance space for the display panel 100 near the edge area. In the embodiment of the present application, optionally, as Fig. 9 As shown, the first sub-area AA1 includes the pixel circuit group 20, and the second sub-area AA2 does not include the pixel circuit group 20, which is conducive to realizing the space shrinkage of the pixel circuit 30 and the wiring structure prepared in the first sub-area AA1, increasing the space for preparing other leads between the first sub-area AA1 and the upper edge of the display panel 100, and improving the splicing performance of the display panel 100. Or, as Fig.10As shown, the third sub-area AA2 includes the pixel circuit group 20, and the second sub-area AA2 does not include the pixel circuit group 20, which is conducive to realizing the space shrinkage of the pixel circuit 30 and the wiring structure prepared in the third sub-area AA3, increasing the space for preparing other leads between the third sub-area AA3 and the lower edge of the display panel 100, and improving the splicing performance of the display panel 100. Or, as Fig.11 As shown, the first sub-area AA1 and the third sub-area AA3 are provided to include the pixel circuit group 20, and the second sub-area AA2 does not include the pixel circuit group 20, which is conducive to realizing the space shrinkage of the pixel circuit 30 and the wiring structure prepared in the first sub-area AA1 and the third sub-area AA3, and increasing the space for preparing other leads in the upper edge area and the lower edge area of ​​the display panel 100. In addition, the second sub-area AA2 of the display panel 100 is provided to not include the pixel circuit group 20, which is conducive to reducing the number of pixel circuit groups 20 prepared in the display panel 100, balancing the wiring impedance in the display panel 100, reducing the degree of wiring aggregation in the display panel 100, and improving the working stability of the display panel 100.

[0065] Fig.12 A schematic plan view of another display panel provided in an embodiment of the present application.

[0066] In one embodiment of the present application, Fig.12 As shown, the display panel 100 further includes a shift register group 40 , and the shift register group 40 includes at least two shift registers 101 arranged along the first direction X1 .

[0067] The above content mentioned that in the prior art, the shift register and the pixel circuit unit are usually arranged alternately in the first direction X1, and the circuit structures of the shift register and the pixel circuit unit are quite different. Some wiring between the shift register and the pixel circuit unit needs to be prepared in a form arranged in sequence along the first direction, which easily wastes the wiring structure preparation space in the display panel.

[0068] In the embodiment of the present application, similar to the pixel circuit group 20, the shift register group 40 is arranged in the first direction X1 between two adjacent pixel circuit units 20, and at least part of the shift registers 101 do not include the pixel circuit unit 20, which is conducive to utilizing the similar properties of the shift registers 101, setting multiple cascaded shift registers 101 in the same shift register group 40, and not including the pixel circuit unit 20 between them, which is conducive to spatially nesting the circuit structures of the adjacent areas of the two shift registers 101 in the shift register group 40, and reducing the area occupied when preparing the shift register 101. In addition, the shift register group 40 is located between two adjacent pixel circuit units 20, which is conducive to applying the scheme of setting the pixel circuit group 20 of the present application, optimizing the electrical connection method between the shift register 101 and the pixel circuit 30, and reducing the degree of winding of the routing of the electrical connection of the shift register 101.

[0069] Fig.13 A schematic plan view of another display panel provided in an embodiment of the present application.

[0070] In one embodiment of the present application, Fig.13 As shown, the shift register 101 includes an output terminal OUT2, and the output terminal OUT2 of the shift register 101 is electrically connected to the pixel circuit 30 adjacent to it in the first direction X1. The shift register 101 can be used to generate control signals such as scanning signals and light-emitting driving signals for controlling the pixel circuit 30 to perform different operations, and the control signal is output from the output terminal OUT2 of the shift register 101 to the pixel circuit 30.

[0071] In the embodiment of the present application, setting the output terminal OUT2 of the shift register 101 to be electrically connected to the pixel circuit 30 adjacent to the first direction X1 is beneficial to reducing the electrical connection distance between the output terminal OUT2 and the pixel circuit 30, thereby reducing the winding when the output terminal OUT2 is electrically connected to the pixel circuit 30, and further reducing the space occupied by the routing structure.

[0072] Fig.14 A method provided in the embodiment of the present application Fig.13 Schematic diagram of a part of the middle area E5.

[0073] In one embodiment of the present application, Fig.13 , Fig.14 As shown, the output terminal OUT2 of the shift register 101 is also electrically connected to the input terminal IN1 of the shift register 101 of the next stage, and the control signal output by the output terminal OUT2 of the shift register 101 is also transmitted to the input terminal IN1 of the shift register 101 of the next stage as a driving signal of the shift register 101 of the next stage, thereby realizing the cascading of multiple shift registers 101 arranged in the first direction X1. Fig.14 A circuit layout diagram of a shift register 101 provided in an embodiment of the present application is mainly used to compare and show the structural relationship between the first type of shift register 101A and the second type of shift register 101B.

[0074] The at least two shift registers 101 included in the shift register group 40 include a first type shift register 101A and a second type shift register 101B connected in cascade, and the output terminal OUT2 of the first type shift register 101A is electrically connected to the input terminal IN1 of the second type shift register 101B connected in cascade. Fig.13 , Fig.14 As shown, the shift register 101 in which the input terminal IN1 and the output terminal OUT2 are sequentially arranged in the first direction X1, which is the same as the cascade direction of the multiple shift registers 101, is a first type of shift register 101A; the shift register 101 in which the input terminal IN1 and the output terminal OUT2 are sequentially arranged in the first direction X1, which is opposite to the cascade direction of the multiple shift registers 101, is a second type of shift register 101B as an example for explanation.

[0075] In the embodiment of the present application, in the same shift register group 40, the output end OUT2 of the first type of shift register 101A and the output end OUT2 of the second type of shift register 101B are oriented toward opposite sides in the first direction X1, the output end OUT2 of the first type of shift register 101A is oriented toward the pixel circuit 30 adjacent to it in the first direction X1, and the output end OUT2 of the second type of shift register 101B is oriented toward the pixel circuit 30 adjacent to it in the first direction X1, which is conducive to making the setting of the shift register group 40 adapt to the scheme of the pixel circuit group 20 proposed in the embodiment of the present application, and through the relative setting of the output ends OU1 of the first type of shift register 101A and the second type of shift register 101B in the first direction X1, the distance between the multiple shift registers 101 in the same shift register group 40 and the pixel circuit 30 electrically connected thereto is shortened, further reducing the winding between the shift register 101 and the pixel circuit 30.

[0076] In one embodiment of the present application, continue to refer to Fig.13 As shown, the pixel circuit unit 20 is not included between the first type shift register 101A and the second type shift register 101B adjacent to each other in the first direction X1, which is beneficial to further improve the compactness of the circuit structure in the display panel 100 during preparation, maintain the structural uniformity of the display panel 100, and thus improve the uniformity of the display panel 100 during display.

[0077] In one embodiment of the present application, continue to refer to Fig.14As shown, the circuit structure of the first type shift register 101A is symmetrical with the circuit structure of the second type shift register 101B, which is beneficial to realize that the output terminals OUT2 of the first type shift register 101A and the second type shift register 101B are both oriented toward the adjacent pixel circuit 30, and shortening the distance required for winding when the output terminal OUT2 is electrically connected to the adjacent pixel circuit 30.

[0078] Fig.15 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.16 A schematic plan view of another display panel provided in an embodiment of the present application.

[0079] In one embodiment of the present application, Figure 15-16 As shown, in the first direction X1, the distance between at least partially adjacent two first-type shift registers 101A is equal to the distance between at least partially adjacent two second-type shift registers 101B.

[0080] Alternatively, if Fig.15As shown, pixel circuit groups 20 and shift register groups 40 are alternately prepared in the first sub-area AA1 and the third sub-area AA3 of the display area AA, and an example is taken that one pixel circuit group 20 includes two pixel circuit units 201, and one shift register group 40 includes one first-type shift register 101 and one second-type shift register 102. Then, in the first sub-area AA1 and / or the third sub-area AA2, the first second-type shift register 101A and two pixel circuit units 201 are included between two first-type shift registers 101A belonging to two adjacent shift register groups 40; similarly, the first first-type shift register 101A and two pixel circuit units 201 are included between two second-type shift registers 101B belonging to two adjacent shift register groups 40. Assuming that the width occupied by the first type shift register 101A and the second type shift register 101B in the first direction X1 is the same, the distance between two adjacent first type shift registers 101A in the first sub-area AA1 and / or the third sub-area AA2 is equal to the distance between two adjacent second type shift registers 101B. In addition, the display area AA also includes a second sub-area AA2 located between the first sub-area AA1 and the third sub-area AA3 in the first direction X1. Optionally, the pixel circuit units 201 and the shift registers 10 in the second sub-area AA2 are arranged alternately in the first direction X1. Taking the shift register 101 in the second sub-area AA2 as the first type shift register 101A as an example, in the display area AA in the first direction X1, only one pixel circuit unit 201 is included between two adjacent first type shift registers 101A in the second sub-area AA2, and the distance is not equal to the distance between two adjacent second type shift registers 101B in the first sub-area AA2 and / or the third sub-area AA3.

[0081] Alternatively, if Fig.16As shown, the display area AA is provided with a shift register group 40 and a pixel circuit group 20, and the shift register group 40 and the pixel circuit group 20 are alternately arranged in the first direction X1, and an example is taken in which a pixel circuit group 20 includes two pixel circuit units 201, and a shift register group 40 includes a first type shift register 101 and a second type shift register 102. Then, between two adjacent first-type shift registers 101A in the first direction X1, there is a second-type shift register 101B and two pixel circuit units 201, and between two adjacent second-type shift registers 101B in the first direction X1, there is a first-type shift register 101B and two pixel circuit units 201. This is conducive to achieving that in the first direction X1, the distance between two adjacent first-type shift registers 101A is equal to the distance between two adjacent second-type shift registers 101B, which is conducive to further improving the uniformity of the circuit structure preparation of the display panel 100, so that the routing impedance distributed in each area of ​​the display panel 100 is more uniform, thereby improving the uniformity of the display panel 100.

[0082] In one embodiment of the present application, continue to refer to Fig.15 As shown, the distance between at least part of the shift register 101 and its previous stage shift register 101 is not equal to the distance between the shift register 101 and its next stage shift register 101. Fig.14 As shown, in the first sub-area AA1 and / or the third sub-area AA3, the first type shift register 101A and the second type shift register 101B in the same shift register group 40 are adjacent and cascaded, and no other circuits are included between the first type shift register 101A and the second type shift register 101B in the same shift register group 40. In the same shift register group 40, taking the cascade connection of the output terminal OUT2 of the first type of shift register 101A and the input terminal IN1 of the second type of shift register 101B as an example, the first type of shift register 101A and the shift register 101 cascaded at the previous level are the second type of shift register 101B located in different shift register groups 40, and a pixel circuit unit 201 is included between the two cascaded shift registers 101 in different shift register groups 40, so in the display panel, the distance between at least part of the shift register 101 and its previous level shift register 101 is not equal to the distance between it and its next level shift register 101, which is conducive to improving the diversity of circuit structure preparation of the embodiments of the present application, improving the applicability of the embodiments of the present application, and providing a reference for relevant technical personnel.

[0083] Fig.17 A schematic plan view of another display panel provided in an embodiment of the present application is shown in FIG. Fig.18 A schematic plan view of another display panel provided in an embodiment of the present application.

[0084] In one embodiment of the present application, Figure 17-Figure 18 As shown, the display area AA includes a first sub-area AA1, a second sub-area AA2, and a third sub-area AA3 distributed in the first direction X1. The first sub-area AA1 and the third sub-area AA3 are respectively located at two opposite sides of the second sub-area A2 in the first direction X1.

[0085] Alternatively, if Fig.17 As shown, at least the first sub-area AA1 includes a shift register group 40 and a pixel circuit group 20 alternately arranged in the first direction X1. In combination with the content of preparing the pixel circuit group 20 and the shift register group 40 in the display panel 100, it can be known that the provision of the pixel circuit group 20 and the shift register group 40 is conducive to realizing the space shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby facilitating the reduction of the area occupied when preparing the pixel circuit 30 and the shift register 101, at least facilitating the improvement of the avoidable space between the first sub-area AA1 and the upper edge of the display panel 100, and providing a preparable space for other driving circuits and electrical connection leads.

[0086] Alternatively, if Fig.18 As shown, at least the third sub-area AA3 includes a shift register group 40 and a pixel circuit group 20 alternately arranged in the first direction X1. Similarly, the provision of the pixel circuit group 20 and the shift register group 40 is conducive to realizing the spatial shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby facilitating the reduction of the area occupied when preparing the pixel circuit 30 and the shift register 101, at least facilitating the increase of the avoidable space between the third sub-area AA3 and the lower edge of the display panel 100, and providing a fabricable space for other drive circuits and electrical connection leads.

[0087] Alternatively, if Fig.15 As shown, at least the first sub-area AA1 and the third sub-area AA3 include a shift register group 40 and a pixel circuit group 20 alternately arranged in the first direction X1. Similarly, the provision of the pixel circuit group 20 and the shift register group 40 is conducive to realizing the spatial shrinkage of the pixel circuit 30 structure and the shift register 101 circuit structure, thereby facilitating the reduction of the area occupied when preparing the pixel circuit 30 and the shift register 101, facilitating the improvement of the avoidable space between the first sub-area AA1 and the upper edge of the display panel 100, and facilitating the improvement of the avoidable space between the third sub-area AA3 and the lower edge of the display panel 100, providing sufficient space for preparation for other driving circuits and electrical connection leads, facilitating the splicing of the display panel 100, and improving the screen-to-body ratio of the display panel 100.

[0088] In one embodiment of the present application, continue to refer to Figure 15-18As shown, the number of pixel circuits 30 included in the pixel circuit group 20 is the same as the number of shift registers 101 included in the shift register group 40, which is beneficial to adapt the circuits of the pixel circuit group 20 and the shift registers 101 in the electrical connection structure, so that the shift registers 101 in the shift register group 40 and the pixel circuits 30 in the pixel circuit group 20 are compact when they are electrically connected.

[0089] In one embodiment of the present application, continue to refer to Figure 15-18 As shown, the pixel circuit group 20 includes two pixel circuit units 201 adjacent to each other in the first direction X1, and the shift register group 40 includes two shift registers 101 adjacent to each other in the first direction X1, which is conducive to electrically connecting the two shift registers 101 in the shift register group 40 to the adjacent pixel circuits 30, reducing the risk that the shift register 101 in the shift register group 40 needs to cross other shift registers 101 to be electrically connected to the pixel circuit 30, and is conducive to reducing the electrical connection distance between the pixel circuit and the shift register 101, further realizing the structural shrinkage of the pixel circuit 30 and the shift register 101, and providing more available space for the display panel 100.

[0090] Fig.19 A schematic plan view of a display device provided in an embodiment of the present application.

[0091] The present application embodiment provides a display device 300, such as Fig.19 As shown, the display device 300 includes the display panel 100 as proposed in any of the above embodiments. Optionally, the display device 300 can be a device for display such as a large spliced ​​screen, a conference room screen, a mobile phone, a special-shaped display screen, etc.

[0092] In the display device 300, at least some of the pixel circuit units 201 are arranged in the first direction X1, and the shift register 101 is not included between them. That is, the pixel circuit units 201 prepared in the pixel circuit group 20 in the display area AA are continuously arranged adjacent to each other in the first direction X1, and the shift register 101 is not included between the plurality of adjacently arranged pixel circuit units 201. For example, Figure 1 , Figure 2As shown, two pixel circuit units 201 are prepared adjacently in the first direction X1, and the two adjacently prepared pixel circuit units 201 can be located between two shift registers 101 of adjacent levels. In combination with the relevant technology, it can be known that in the first direction X1, a plurality of pixel circuit units 201 are prepared continuously without being separated by the shift register 101 in the middle, which is conducive to improving the compactness of the circuit structure preparation in the display panel 100. This is because the structures of the plurality of pixel circuit units 201 are similar, and the conditions for spatial nesting are met during circuit preparation, and the signal frequencies transmitted on the plurality of pixel circuit units 201 are also similar, which is conducive to reducing the risk of crosstalk. Therefore, after at least part of the pixel circuit units 201 are set in the display panel 100 without including the shift register 101, it is conducive to better utilizing the space adjacent to the wiring in the second direction X2, and it is unnecessary to arrange the plurality of wirings one by one along the first direction X1, thereby improving the space utilization rate during wiring preparation. The feasibility of reducing the area occupied by the circuit structure of the pixel circuit unit 201 and the shift register circuit 101 is improved, and sufficient avoidance space is reserved at the edge of the display panel 100 to provide available space for preparing other types of leads, which is beneficial to improving the applicability of the display panel 100 in narrow-frame or frameless display devices.

[0093] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: Comprising a display area, the display area comprising: A driving circuit, comprising a plurality of shift registers cascaded in sequence along a first direction; A pixel circuit group, comprising at least two pixel circuit units arranged along the first direction; Wherein, in the first direction, at least some of the pixel circuit units do not include shift registers.

2. The display panel according to claim 1, characterized in that: The pixel circuit unit includes at least two pixel circuits, and the pixel circuit includes a pulse width modulation module and a pulse amplitude modulation module. The pulse width modulation module is electrically connected to a first signal line, and the pulse amplitude modulation module is electrically connected to a second signal line. The first signal line and the second signal line both extend along the first direction; along the second direction, the first signal line and the second signal line are respectively located on opposite sides of the pixel circuit unit.

3. The display panel according to claim 2, characterized in that: In the same pixel circuit group, among two pixel circuits adjacent to each other in the first direction, the pulse width modulation module of one pixel circuit is adjacent to the pulse amplitude modulation module of the other pixel circuit.

4. The display panel according to claim 3, characterized in that: The pulse width modulation module is electrically connected to the first signal line via a first wiring, and the pulse amplitude modulation module is electrically connected to the second signal line via a second wiring; In the same pixel circuit group, at least part of the first routing line electrically connected to the pulse width modulation module in one pixel circuit unit overlaps with at least part of the second routing line electrically connected to the pulse amplitude modulation module in another pixel circuit unit in the second direction.

5. The display panel according to claim 2, characterized in that: The pulse amplitude modulation module in the pixel circuit includes a light-emitting driving current output terminal, and the light-emitting driving current output terminal is electrically connected to the light-emitting device; in the same pixel circuit, the distance between the pulse amplitude modulation module and the light-emitting device driven by it in the first direction is different from the distance between the pulse width modulation module and the light-emitting device driven by it in the first direction; In which, the display panel includes a first type of pixel circuit, and / or the display panel includes a second type of pixel circuit; the arrangement order of the pulse width modulation module and the pulse amplitude modulation module in the first type of pixel circuit in the first direction is opposite to the arrangement order of the pulse width modulation module and the pulse amplitude modulation module in the second type of pixel circuit in the first direction.

6. The display panel according to claim 5, characterized in that: The circuit structure of the first type of pixel circuit is symmetrical to the circuit structure of the second type of pixel circuit.

7. The display panel according to claim 6, characterized in that: The display area includes a first sub-area, a second sub-area, and a third sub-area distributed in the first direction, and the first sub-area and the third sub-area are respectively located on opposite sides of the second sub-area in the first direction; one of the first sub-area and the third sub-area includes the first type of pixel circuit and the other includes the second type of pixel circuit, and the second sub-area includes the first type of pixel circuit and / or the second type of pixel circuit.

8. The display panel according to claim 7, characterized in that: The first sub-area and / or the third sub-area includes the pixel circuit group, and the second sub-area does not include the pixel circuit group.

9. The display panel according to claim 1, characterized in that: The display panel further includes a shift register group, wherein the shift register group includes at least two shift registers arranged along a first direction; Wherein, in the first direction, the shift register group is located between two adjacent pixel circuit units, and at least part of the shift registers do not include the pixel circuit unit.

10. The display panel according to claim 9, characterized in that: The shift register comprises an output terminal, and the output terminal of the shift register is electrically connected to the pixel circuit adjacent to the shift register in the first direction.

11. The display panel according to claim 10, characterized in that: The output end of the shift register is also electrically connected to the input end of the shift register of the next stage; the at least two shift registers included in the shift register group include a cascaded first-type shift register and a second-type shift register; the output end of the first-type shift register is electrically connected to the input end of the cascaded second-type shift register; In the same shift register group, the output end of the first type of shift register and the output end of the second type of shift register are oriented toward opposite sides in the first direction, the output end of the first type of shift register is oriented toward the pixel circuit adjacent to it in the first direction, and the output end of the second type of shift register is oriented toward the pixel circuit adjacent to it in the first direction.

12. The display panel according to claim 11, characterized in that: The pixel circuit unit is not included between the first type shift register and the second type shift register adjacent to each other in the first direction.

13. The display panel according to claim 11, characterized in that: The circuit structure of the first type of shift register is symmetrical to the circuit structure of the second type of shift register.

14. The display panel according to claim 11, characterized in that: In the first direction, a distance between at least partially adjacent two shift registers of the first type is equal to a distance between at least partially adjacent two shift registers of the second type.

15. The display panel according to claim 11, characterized in that: The distance between at least part of the shift registers and the shift registers of the previous stage is not equal to the distance between part of the shift registers and the shift registers of the next stage.

16. The display panel according to claim 9, characterized in that: The display area includes a first sub-area, a second sub-area, and a third sub-area distributed in the first direction, and the first sub-area and the third sub-area are respectively located at two opposite sides of the second sub-area in the first direction; At least the first sub-area and / or the third sub-area includes the shift register groups and the pixel circuit groups alternately arranged in the first direction.

17. The display panel according to claim 16, characterized in that: The number of the pixel circuits included in the pixel circuit group is the same as the number of the shift registers included in the shift register group.

18. The display panel according to claim 17, characterized in that: The pixel circuit group includes two pixel circuit units adjacent to each other in the first direction, and the shift register group includes two shift registers adjacent to each other in the first direction.

19. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-18.

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