Electric leakage processing method of storage chip
By conducting leakage and functional tests on the memory chip, the chip to be optimized is determined, and the optimization process of injecting phosphorus elements, the gate-to-drain leakage problem after the memory chip area is reduced, improving the yield and reliability of the product.
Patent Information
- Application Number
- CN202411832081.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-18
AI Technical Summary
When the memory chip area is reduced, the gate-to-drain leakage problem increases, resulting in a decrease in product yield and reliability.
By conducting leakage tests and functional tests on multiple test chips, we determine the chip to be optimized with gate to drain leakage problems, and inject phosphorus elements into the gates of these chips according to different processing processes to be selected. After optimization, the chip is verified to determine the target processing process.
It effectively reduces the gate to drain leakage problem after the memory chip is reduced in area, and improves the product yield and reliability.
Smart Images
Figure CN119650419A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a method for handling leakage of a memory chip. Background Art
[0002] Memory chips, also known as semiconductor memories, refer to semiconductor media devices that use electrical energy to store information. The storage and reading process is reflected in the storage or release of electrons. The memory chip market is huge and is the largest market segment in the semiconductor industry, covering consumer electronics, industry, medical, automotive, aerospace and other fields. At present, all walks of life are paying more and more attention to the area cost of memory chips. Therefore, in order to save costs, the storage bit area of memory chips will continue to be reduced. While reducing the storage bit area, the distance between the gate and the drain will also be reduced, resulting in an increase in the leakage problem from the gate to the drain. It will cause leakage problems.
[0003] Therefore, how to reduce the gate-to-drain leakage while reducing the storage bit area is an urgent problem to be solved. Summary of the invention
[0004] The purpose of the present application is to provide a leakage treatment method for a memory chip in view of the above-mentioned deficiencies in the prior art, so as to reduce the leakage problem from the gate to the drain after the area of the memory chip is reduced.
[0005] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0006] In a first aspect, an embodiment of the present application provides a method for handling leakage of a memory chip, the method comprising:
[0007] According to leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced, multiple chips to be optimized that have gate-to-drain leakage problems are determined, and the chips to be optimized are test chips that have gate-to-drain leakage problems after the storage bit area is reduced;
[0008] Injecting phosphorus into the gate of each chip to be optimized according to a selected processing technology corresponding to each chip to be optimized, so as to obtain an optimized chip corresponding to each chip to be optimized, wherein the selected processing technology is used to indicate an injection sequence, an injection dose, an injection energy, and an injection angle;
[0009] The optimized chips are subjected to tape-out verification to obtain verification results corresponding to the optimized chips, and a target processing technology is determined from a plurality of candidate processing technologies according to the verification results, so as to produce chips using the target processing technology.
[0010] Optionally, the process of determining the processing technology to be selected corresponding to the chip to be optimized includes:
[0011] Determining the implantation sequence as follows: implanting the phosphorus element after implanting the second silicon nitride layer into the gate of the test chip;
[0012] Determine adjustment parameters corresponding to the current chip to be optimized, where the adjustment parameters include one or more of the implantation dose, the implantation energy, and the implantation angle;
[0013] Determine the parameter value of each tuning parameter.
[0014] Optionally, determining a parameter value of each adjustment parameter includes:
[0015] The parameter value of each adjustment parameter is determined according to the parameter value of the adjustment parameter of at least one chip to be optimized before the current chip to be optimized, a preset adjustment direction, and a preset adjustment step.
[0016] Optionally, performing tape-out verification on each of the optimized chips to obtain verification results corresponding to each of the optimized chips includes:
[0017] Conduct leakage test and product function test on each optimized chip respectively, and obtain leakage test data and product function test data corresponding to each optimized chip;
[0018] The leakage test data and product function test data corresponding to each optimized chip are used as the verification results corresponding to each optimized chip.
[0019] Optionally, determining a target processing technology from a plurality of candidate processing technologies according to each of the verification results includes:
[0020] The target processing technology is determined based on the leakage test data corresponding to each optimized chip and the product function test data.
[0021] Optionally, the target processing technology is determined according to the leakage test data and product function test data corresponding to each optimized chip, including:
[0022] Selecting at least one intermediate optimized chip from each of the product function test data, wherein the product function test data of each intermediate optimized chip meets a preset good product condition;
[0023] The intermediate optimized chip with the smallest leakage test data is selected from the leakage test data of each intermediate optimized chip as the target optimized chip, and the to-be-selected processing technology corresponding to the target optimized chip is used as the target processing technology.
[0024] Optionally, the determining of multiple chips to be optimized having gate-to-drain leakage problems according to leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced:
[0025] Determine at least one functional chip to be tested according to the leakage test results of the plurality of test chips before the storage bit area is reduced and the leakage test results of the plurality of test chips after the storage bit area is reduced;
[0026] Performing consistency detection on each of the functional chips to be tested to obtain a functional test result of each of the functional chips to be tested, and determining whether each of the functional chips to be tested meets a preset good product condition according to the functional test result of each of the functional chips to be tested;
[0027] If not, each functional chip to be tested is regarded as a chip to be optimized.
[0028] Optionally, determining at least one functional chip to be tested according to leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced includes:
[0029] Traverse the multiple test chips, and for the current test chip that is traversed, determine whether the current test chip has a gate-to-drain leakage problem based on the leakage test result of the current test chip before the storage bit area is reduced and the leakage test result of the current test chip after the storage bit area is reduced. If so, use the current test chip as the functional chip to be tested. After traversing all the test chips, multiple functional chips to be tested are obtained.
[0030] Optionally, the leakage test result of the current test chip before the storage bit area is reduced and the leakage test result of the current test chip after the storage bit area is reduced include:
[0031] According to the leakage test results of the current test chip before the storage bit area is reduced, the leakage test results of the current test chip after the storage bit area is reduced, and a pre-established leakage analysis model, it is determined whether the current test chip has a gate-to-drain leakage problem.
[0032] Optionally, the good product condition includes: the failure rate of the leakage-related test item is less than a preset threshold and there is no preset graph in the wafer test result graph.
[0033] The beneficial effects of this application are:
[0034] The present application provides a method for processing leakage of a memory chip. First, according to the leakage test results of multiple test chips before the storage bit area is reduced, the leakage test results of multiple test chips after the storage bit area is reduced, and the functional test results of multiple test chips after the storage bit area is reduced, multiple chips to be optimized with gate-to-drain leakage problems are determined, and then phosphorus is injected into the gate of each chip to be optimized according to the selected processing technology corresponding to each chip to be optimized, and the optimized chip corresponding to each chip to be optimized is obtained. The optimized chip is flow-through verified to obtain the verification result corresponding to each optimized chip, and the target processing technology is determined from multiple processing technologies to be selected according to each verification result, so as to use the target processing technology for chip production. By determining the chip to be optimized with gate-to-drain leakage problems according to the leakage data of multiple test chips and the product function data, the determined chip to be optimized can be made more accurate, and different processing technologies to be selected are used to inject phosphorus into each chip to be optimized to obtain the optimized chip, and the optimized chip is flow-through verified to obtain the target processing technology, which can effectively reduce the gate-to-drain leakage problem and ensure the yield and reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.
[0036] Figure 1 A schematic flow chart of a method for handling leakage of a memory chip provided in an embodiment of the present application;
[0037] Figure 2 A flowchart of a method for determining a processing technology to be selected provided in an embodiment of the present application;
[0038] Figure 3 A schematic diagram of a process model provided for this embodiment;
[0039] Figure 4 A flowchart of a method for determining a verification result provided in an embodiment of the present application;
[0040] Figure 5 A flowchart of a method for determining a target processing technology provided in an embodiment of the present application;
[0041] Figure 6 A flowchart of a method for determining product function data provided in an embodiment of the present application;
[0042] Figure 7A schematic diagram of consistency test results of various functional chips to be tested provided in an embodiment of the present application;
[0043] Figure 8 A schematic diagram for comparing leakage test results provided in an embodiment of the present application;
[0044] Fig. 9 A schematic diagram of a leakage analysis model provided in an embodiment of the present application;
[0045] Fig.10 A schematic diagram for comparing leakage test results before and after a process provided in an embodiment of the present application;
[0046] Fig.11 A schematic diagram of functional test results of a wafer product after a process provided in an embodiment of the present application. DETAILED DESCRIPTION
[0047] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.
[0048] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and listed in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.
[0049] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.
[0050] Memory chips are the specific application of the concept of embedded system chips in the storage industry. By embedding software in a single chip, it achieves multi-function and high performance, as well as support for multiple protocols, multiple hardware and different applications. Its working principle mainly relies on the use of transistors made of semiconductor materials to complete data storage and processing. Transistors have three electrodes: source, drain and gate. Under normal working conditions, when a certain voltage is applied to the gate, a conductive channel is formed between the source and the drain, allowing current to flow from the source to the drain. On the contrary, when the voltage on the gate disappears or changes, this conductive channel will be closed or narrowed, causing the current to decrease or stop completely. In this way, the transistor can control the switching state of the current, thereby realizing the representation of binary data (0 and 1).
[0051] Figure 1 A schematic diagram of a flow chart of a method for handling leakage of a memory chip provided in an embodiment of the present application. Figure 1 As shown, the method includes:
[0052] S101. Determine multiple chips to be optimized that have gate-to-drain leakage problems based on leakage test results of multiple test chips before storage bit area reduction, leakage test results of multiple test chips after storage bit area reduction, and functional test results of multiple test chips after storage bit area reduction.
[0053] Among them, the chip to be optimized refers to a test chip whose storage bit area is reduced and has a gate-to-drain leakage problem.
[0054] Optionally, the multiple test chips all belong to the same type of memory chips, and the storage bit area of each test chip is reduced, so that each test chip corresponds to a test chip before the storage bit area is reduced and a test chip after the storage bit area is reduced. For example, if the storage bit area of test chip A is reduced, the test chip before the storage bit area is reduced, that is, test chip A, and the test chip A after the storage bit area is reduced are obtained.
[0055] Optionally, the leakage problem existing in the test chip may include a gate-induced drain leakage problem (GIDL), a channel leakage problem, and a junction leakage problem.
[0056] Optionally, a current test can be performed on a test structure of multiple test chips on a wafer before the storage bit area is reduced to obtain a leakage test result before the area is reduced, and a current test can be performed on a test structure of multiple test chips on a wafer after the storage bit area is reduced to obtain a leakage test result after the area is reduced, and a wafer test can be performed on multiple test chips after the storage bit area is reduced to obtain product function data, and the leakage test results before the area is reduced and the leakage test results after the area is reduced are used as leakage data, and a preset method is used based on the leakage data obtained from the test and the product function data to determine multiple chips to be optimized that have gate-to-drain leakage problems.
[0057] S102 , injecting phosphorus into the gate of each chip to be optimized according to the selected processing technology corresponding to each chip to be optimized, so as to obtain an optimized chip corresponding to each chip to be optimized.
[0058] The selected processing technology is used to indicate the implantation sequence, implantation dosage, implantation energy and implantation angle, and specifically refers to the implantation sequence of phosphorus element, the implantation dosage of phosphorus element, the implantation energy of phosphorus element and the implantation angle of phosphorus element.
[0059] Optionally, different processing techniques to be selected may be determined based on the injection sequence, injection dose, injection energy and injection angle, and then phosphorus may be injected into each chip to be optimized according to the different processing techniques to be selected to obtain an optimized chip corresponding to each chip to be optimized.
[0060] If the determined processing technologies to be selected are processing technology to be selected 1, processing technology to be selected 2 and processing technology to be selected 3, and the chips to be optimized include chip A1 to chip A100, then chips A1 to chip A100 can be injected with phosphorus element according to processing technology to be selected 1 to obtain a group of optimized chips A1 to chip A100; chips A1 to chip A100 can be injected with phosphorus element according to processing technology to be selected 2 to obtain a group of optimized chips A1 to chip A100; chips A1 to chip A100 can be injected with phosphorus element according to processing technology to be selected 3 to obtain a group of optimized chips A1 to chip A100.
[0061] S103, performing tape-out verification on each optimized chip to obtain verification results corresponding to each optimized chip, and determining a target processing technology from a plurality of candidate processing technologies according to each verification result, so as to use the target processing technology for chip production.
[0062] Exemplarily, the optimized chips A1 to A100 obtained by injecting phosphorus according to the processing technology to be selected 1 can be subjected to wafer verification to obtain verification results 1 corresponding to the optimized chips A1 to A100; the optimized chips A1 to A100 obtained by injecting phosphorus according to the processing technology to be selected 2 can be subjected to wafer verification to obtain verification results 2 corresponding to the optimized chips A1 to A100; the optimized chips A1 to A100 obtained by injecting phosphorus according to the processing technology to be selected 3 can be subjected to wafer verification to obtain verification results 3 corresponding to the optimized chips A1 to A100. According to the verification results 1, 2 and 3, a preset method can be used to determine the target processing technology from the processing technology to be selected 1, the processing technology to be selected 2 and the processing technology to be selected 3. For example, if the determined target processing technology is the processing technology to be selected 1, the processing technology to be selected 1 can be used for chip production.
[0063] In this embodiment, leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced are used to determine multiple chips to be optimized that have gate-to-drain leakage problems. Then, phosphorus elements are injected into the gate of each chip to be optimized according to the selected processing technology corresponding to each chip to be optimized to obtain an optimized chip corresponding to each chip to be optimized. Flow verification is performed on each optimized chip to obtain verification results corresponding to each optimized chip, and a target processing technology is determined from multiple selected processing technologies based on each verification result, so that chips are produced using the target processing technology. By determining the chips to be optimized that have gate-to-drain leakage problems based on leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced, the determined chips to be optimized can be made more accurate, and different selected processing techniques are used to inject phosphorus elements into each chip to be optimized to obtain an optimized chip, and the optimized chip is verified by wafer taping to obtain a target processing technique, which can effectively reduce the gate-to-drain leakage problem and ensure the yield and reliability of the product.
[0064] Figure 2 A flowchart of a method for determining a processing technology to be selected is provided in an embodiment of the present application, such as Figure 2 As shown, the process of determining the processing technology to be selected corresponding to the chip to be optimized may include:
[0065] S201 , determining the injection sequence as follows: injecting phosphorus element after injecting the second silicon oxide into the gate of the test chip.
[0066] Optionally, in the manufacturing process of the memory chip, the phosphorus element can be injected to adjust the current of the chip and turn on the current of the chip. The general manufacturing process is to inject the phosphorus element after the first silicon oxide is injected into the gate of the chip. This injection method increases the leakage problem from the gate to the drain after the storage bit area is reduced. In this embodiment, the phosphorus element is no longer injected after the first silicon oxide is injected into the gate, but the phosphorus element is injected after the second silicon oxide is injected into the gate. Therefore, the injection order of the phosphorus element is adjusted in this embodiment. In addition, the phosphorus element is injected after the second silicon oxide is injected into the gate, which can keep the injected phosphorus element away from the gate, reduce the influence of the phosphorus element on the gate, and thus reduce the leakage current of the chip.
[0067] The implantation sequence in each of the selected processing steps in this embodiment is: implanting the phosphorus element after implanting the second silicon oxide into the gate of the test chip.
[0068] Figure 3 A schematic diagram of a process model provided for this embodiment, Figure 3 The first picture is a schematic diagram of a chip in a normal process, that is, phosphorus is injected after SPACER1. Figure 3 The second picture is a schematic diagram of the chip after the process improvement, that is, phosphorus is injected after SPACER2. Figure 3 The control tube and storage tube in the circuit both include a gate. Figure 3 It can be clearly seen that the first silicon oxide SPACER1 is closer to the gate, and the second silicon oxide is farther away from the gate. Injecting phosphorus after the second silicon oxide of the gate can make the injected phosphorus element farther away from the gate, thereby reducing the leakage problem from the gate to the drain.
[0069] S202: Determine adjustment parameters corresponding to the current chip to be optimized.
[0070] The adjustment parameters may include one or more of an implantation dose, an implantation energy and an implantation angle.
[0071] Exemplarily, the selected processing technology 1 may be, for example, adjusting the injection sequence and the injection dose 1; the selected processing technology 2 may be, for example, adjusting the injection sequence and the injection dose 2; the selected processing technology 3 may be, for example, adjusting the injection sequence and the injection dose 3; the selected processing technology 4 may be, for example, adjusting the injection sequence and the injection energy; the selected processing technology 5 may be, for example, adjusting the injection sequence and the injection angle; the selected processing technology 6 may be, for example, adjusting the injection sequence, the injection dose and the injection energy; the selected processing technology 7 may be, for example, adjusting the injection sequence, the injection dose, the injection energy and the injection angle; the selected processing technology 8 may be, for example, adjusting the injection sequence, the injection dose and the injection angle, etc.
[0072] Optionally, since the leakage current can be reduced after changing the injection sequence of phosphorus elements, the normal current flowing out of the gate of the chip will also be reduced. In order to reduce the impact on the normal current flowing out of the gate, the injection dose, injection energy and injection angle of the phosphorus elements can be adjusted so that a part of the injected phosphorus elements can diffuse into the gate, thereby reducing the leakage problem of the chip while increasing the normal current flowing out of the chip gate, thereby achieving a balance.
[0073] S203: Determine the parameter value of each adjustment parameter.
[0074] Specifically, the parameter values of each adjustment parameter can be determined according to actual needs, for example, the dose value of the injection dose, the energy value of the injection energy, and the angle value of the injection angle can be determined.
[0075] Optionally, determining the parameter value of each adjustment parameter in S203 may include:
[0076] Specifically, the parameter value of each adjustment parameter can be determined according to the parameter value of the adjustment parameter of at least one chip to be optimized before the current chip to be optimized, the preset adjustment direction and the preset adjustment step. Among them, the parameter value of the adjustment parameter of at least one chip to be optimized before the current chip to be optimized refers to the parameter value of the adjustment parameter of the chip to be optimized in the last processing technology to be selected. For example, processing technology 2 is after processing technology 1, if the current chip to be optimized is a chip to be optimized that is injected with phosphorus according to processing technology 2, then the adjustment parameter of at least one chip to be optimized before the current chip to be optimized refers to the adjustment parameter of the chip to be optimized that is injected with phosphorus according to processing technology 1.
[0077] The preset adjustment direction may be, for example, an increasing direction or a decreasing direction, and the preset adjustment step may be, for example, a preset adjustment ratio or a preset adjustment variation.
[0078] Specifically, the parameter values of the adjustment parameters of at least one chip to be optimized before the current chip to be optimized can be adjusted according to the preset adjustment direction with the preset adjustment step length, so as to obtain the parameter values of the adjustment parameters corresponding to the current chip to be optimized. For example, if the preset adjustment direction is the increasing direction, the preset adjustment compensation is a ratio of 5%, and the parameter value of the injection dose of at least one chip to be optimized before the current chip to be optimized is 10%, then the parameter value of the injection dose corresponding to the current chip to be optimized is 15%.
[0079] Figure 4 A flowchart of a method for determining a verification result provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, in the above S103, each optimized chip is subjected to tape-out verification to obtain verification results corresponding to each optimized chip, which may include:
[0080] S301 , performing leakage test and product function test on each optimized chip respectively, and obtaining leakage test data and product function test data corresponding to each optimized chip.
[0081] Exemplarily, the optimized chips A1 to A100 obtained by injecting phosphorus element according to the selected processing technology 1 can be subjected to leakage test and product function test respectively to obtain leakage test data 1 and product function test data 1; the optimized chips A1 to A100 obtained by injecting phosphorus element according to the selected processing technology 2 can be subjected to leakage test and product function test respectively to obtain leakage test data 2 and product function test data 2; the optimized chips A1 to A100 obtained by injecting phosphorus element according to the selected processing technology 3 can be subjected to leakage test and product function test respectively to obtain leakage test data 3 and product function test data 3.
[0082] S302: Use the leakage test data and product function test data corresponding to each optimized chip as the verification result corresponding to each optimized chip.
[0083] Exemplarily, leakage test data 1 and product function test data 1 are used as verification result 1 of the optimized chip A1 to chip A100; leakage test data 2 and product function test data 2 are used as verification result 2 of the optimized chip A1 to chip A100; leakage test data 3 and product function test data 3 are used as verification result 3 of the optimized chip A1 to chip A100.
[0084] Optionally, determining the target processing technology from a plurality of candidate processing technologies according to each verification result in S103 may include:
[0085] Optionally, the target processing technology can be determined according to the leakage test data and product function test data corresponding to each optimized chip. Wherein, each optimized chip refers to a plurality of optimized test chips. For example, each optimized chip refers to the optimized chips A1 to A100.
[0086] Figure 5 A flowchart of a method for determining a target processing technology provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the above-mentioned determination of the target processing technology according to the leakage test data corresponding to each optimized chip and the product function test data may include:
[0087] S401. Select at least one intermediate optimized chip from the functional test data of each product.
[0088] If the product function test data of each intermediate optimized chip meets the preset good product condition, each optimized chip that meets the preset good product condition will be used as the intermediate optimized chip.
[0089] Exemplarily, if the product function test data of the optimized chips A1 to A100 obtained by injecting the phosphorus element according to the selected processing technology 1 meets the preset good product conditions, then the chips A1 to A100 optimized according to the selected processing technology 1 will be used as the intermediate optimized chips; if the product function test data of the optimized chips A1 to A100 obtained by injecting the phosphorus element according to the selected processing technology 3 meets the preset good product conditions, then the chips A1 to A100 optimized according to the selected processing technology 3 will be used as the intermediate optimized chips.
[0090] S402 , selecting the intermediate optimized chip with the smallest leakage test data from the leakage test data of each intermediate optimized chip as the target optimized chip, and using the candidate processing technology corresponding to the target optimized chip as the target processing technology.
[0091] Exemplarily, if the leakage test data 1 is smaller than the leakage test data 2, and the leakage test data 1 of the optimized chip A1 to chip A100 obtained by injecting the phosphorus element according to the selected processing technology 1 is smaller than the leakage test data 2 of the chip A1 to chip A100 optimized according to the selected processing technology 1, then the optimized chip A1 to chip A100 obtained by injecting the phosphorus element according to the selected processing technology 1 will be used as the target optimized chip, and the selected processing technology 1 will be used as the target processing technology.
[0092] Figure 6 A flowchart of a method for determining product function data provided in an embodiment of the present application, such as Figure 6 As shown, the above S101 determines multiple chips to be optimized that have gate-to-drain leakage problems according to leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced, which may include:
[0093] S501 , determining at least one functional chip to be tested according to leakage test results of multiple test chips before storage bit area reduction and leakage test results of multiple test chips after storage bit area reduction.
[0094] Specifically, at least one functional chip to be tested can be determined using a preset method based on the leakage test results of each test chip before the storage bit area is reduced and the leakage test results of each test chip after the storage bit area is reduced. The obtained functional chips to be tested refer to the test chips after the storage bit area is reduced.
[0095] S502, performing consistency detection on each functional chip to be tested to obtain a functional test result of each functional chip to be tested, and determining whether each functional chip to be tested meets a preset good product condition according to the functional test result of each functional chip to be tested, and if so, treating each functional chip to be tested as a chip to be optimized.
[0096] Optionally, after consistency detection of each functional chip to be tested, the functional test results of each functional chip to be tested can be identified by a wafer test result diagram. Qualified chips and unqualified chips are identified in the wafer test result diagram, so that the yield rate of the product can be obtained.
[0097] Specifically, the test items in the consistency test may include: voltage test, current test, timing test and functional test, etc. The product function data refers to the test results of each test item of the test chip in the consistency test.
[0098] If the test results of each test item of the functional chip A1 to be tested are good, the functional chip A1 to be tested is marked as qualified at the corresponding position on the wafer test result diagram, for example, it can be marked in green; if the test result of the functional chip A1 to be tested is a failure in the voltage test item, the testing of other test items on the functional chip A1 to be tested is stopped, and the position corresponding to the functional chip A1 to be tested on the wafer test result diagram is marked as unqualified, for example, it can be marked in yellow, indicating that the voltage test item has failed; if the test result of the functional chip A1 to be tested is a failure in the current test item, the testing of other test items on the functional chip A1 to be tested is stopped, and the position corresponding to the functional chip A1 to be tested on the wafer test result diagram is marked as unqualified, for example, it can be marked in blue, indicating that the current test item has failed; if the test result of the functional chip A1 to be tested is a failure in the timing test item, the testing of other test items on the functional chip A1 to be tested is stopped, and the position corresponding to the functional chip A1 to be tested on the wafer test result diagram is marked as unqualified, for example, it can be marked in red, indicating that the timing test item has failed. The product function data of multiple test chips after the storage bit area is reduced can be intuitively seen from the wafer test result diagram.
[0099] Figure 7 A schematic diagram of the consistency test results of each functional chip to be tested provided in an embodiment of the present application, Figure 7 The black ones in the figure represent non-qualified chips. Figure 7 The yield rate of each functional chip to be tested can be obtained.
[0100] It is worth noting that when the optimized chips obtained according to the selected processing technology are subjected to wafer verification, product function testing will also be carried out. The process of conducting product function testing on each optimized chip is the same as the process of conducting consistency testing on the chip after the storage bit area is reduced, and will not be repeated here.
[0101] In this embodiment, after determining the functional chip to be tested based on the leakage data, it is also necessary to perform consistency testing on each functional chip to be tested, and then determine the chip to be optimized based on the product function data of the consistency test, so that the determined chip to be optimized is more accurate, thereby making the results of process improvement based on the chip to be optimized more accurate, and the determined target processing technology is more precise.
[0102] Optionally, determining at least one functional chip to be tested according to leakage test results of multiple test chips before the storage bit area is reduced and leakage test results of multiple test chips after the storage bit area is reduced in S501 may include:
[0103] Specifically, multiple test chips are traversed, and for the current test chip traversed, it is determined whether the current test chip has a gate-to-drain leakage problem based on the leakage test results of the current test chip before the storage bit area is reduced and the leakage test results of the current test chip after the storage bit area is reduced. If so, the current test chip is taken as a functional chip to be tested. After traversing all the test chips, multiple functional chips to be tested are obtained.
[0104] The current test chip refers to any one of the multiple test chips.
[0105] For example, the leakage test result of the current test chip before the storage bit area is reduced and the leakage test result of the current test chip after the storage bit area is reduced are as follows: Figure 8 As shown in Figure 8 A black dot in the figure can represent a leakage test result of a test chip before the storage bit area is reduced. Similarly, a white dot in the white dot represents the leakage test result of the test chip before the storage bit area is reduced. Figure 8 It can be seen that the leakage test results of the white points are greater than those of the black points, that is, the leakage problem of the test chip after the storage bit area is reduced is significantly increased compared with the test chip before the storage bit area is reduced.
[0106] Optionally, determining whether the current test chip has a gate-to-drain leakage problem according to the leakage test result of the current test chip before the storage bit area is reduced and the leakage test result of the current test chip after the storage bit area is reduced may include:
[0107] Optionally, it is possible to determine whether the current test chip has a gate-to-drain leakage problem based on the leakage test result of the current test chip before the storage bit area is reduced, the leakage test result of the current test chip after the storage bit area is reduced, and a pre-established leakage analysis model. The established leakage analysis model is as follows Fig. 9 As shown, the leakage analysis model can analyze the specific leakage problem.
[0108] Specifically, it can be determined whether the leakage test result of the current test chip after the storage bit area is reduced is significantly increased compared to the leakage test result of the current test chip before the storage bit area is reduced. If it is significantly increased, the pre-established leakage analysis model is used to analyze which type of leakage problem the significantly increased leakage data belongs to. If the pre-established leakage analysis model analyzes that the significantly increased leakage problem of the current test chip belongs to the gate-to-drain leakage problem, it can be determined that the current test chip has a gate-to-drain leakage problem, otherwise there is no gate-to-drain leakage problem.
[0109] Optionally, the above-mentioned good product condition may include: the failure rate of the leakage-related test item is less than a preset threshold value and there is no preset graph in the wafer test result graph. The leakage-related test item refers to the test items related to leakage in the consistency test. If the failure rate of these test items is less than a preset threshold value and there is no preset graph in the wafer test result graph, it means that the good product condition is met.
[0110] Fig.10 A schematic diagram for comparing leakage test results before and after a process provided in an embodiment of the present application is provided, where the leakage test results obtained by performing leakage test on each chip to be optimized after process improvement using the process of the present application are compared with the leakage data before process improvement. The leakage data before process improvement refers to the leakage data of the test chip after the storage bit area is reduced in the above-mentioned manner, wherein the blue represents the test results of the chip before process improvement, and the brown represents the test results of the chip after process improvement. Fig.10 It can be clearly seen that after using the method of the present application for improvement, the leakage problem from the gate to the drain is significantly reduced.
[0111] Fig.11 A schematic diagram of a functional test result of a wafer product after a process provided in an embodiment of the present application, from Fig.11 It can be seen from the figure that after optimizing each chip to be optimized using the process in this application, that is, the result of consistency testing of each optimized chip is consistent with Figure 7 Compared with the product function test results in Fig.11 The yield rate in the test is significantly increased. Figure 7 The product function test results in are the consistency test results of each functional chip to be tested with reduced storage bit area before process improvement.
[0112] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.
[0113] In addition, each functional unit in each embodiment of the present application can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, RandomAccess Memory), disk or optical disk and other media that can store program code.
[0114] The above are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be covered by the protection scope of the present application.
Claims
1. A method for handling leakage of a memory chip, characterized in that: The method comprises: According to leakage test results of multiple test chips before the storage bit area is reduced, leakage test results of multiple test chips after the storage bit area is reduced, and functional test results of multiple test chips after the storage bit area is reduced, multiple chips to be optimized that have gate-to-drain leakage problems are determined, and the chips to be optimized are test chips that have gate-to-drain leakage problems after the storage bit area is reduced; Injecting phosphorus into the gate of each chip to be optimized according to a selected processing technology corresponding to each chip to be optimized, so as to obtain an optimized chip corresponding to each chip to be optimized, wherein the selected processing technology is used to indicate an injection sequence, an injection dose, an injection energy, and an injection angle; The optimized chips are subjected to tape-out verification to obtain verification results corresponding to the optimized chips, and a target processing technology is determined from a plurality of candidate processing technologies according to the verification results, so as to produce chips using the target processing technology.
2. The method for processing leakage of a memory chip according to claim 1, characterized in that: The process of determining the processing technology to be selected corresponding to the chip to be optimized includes: Determining the implantation sequence as follows: implanting the phosphorus element after implanting the second silicon nitride layer into the gate of the test chip; Determine adjustment parameters corresponding to the current chip to be optimized, where the adjustment parameters include one or more of the implantation dose, the implantation energy, and the implantation angle; Determine the parameter value of each tuning parameter.
3. The method for processing leakage of a memory chip according to claim 2, characterized in that: The step of determining the parameter value of each adjustment parameter includes: The parameter value of each adjustment parameter is determined according to the parameter value of the adjustment parameter of at least one chip to be optimized before the current chip to be optimized, a preset adjustment direction, and a preset adjustment step.
4. The method for processing leakage of a memory chip according to claim 1, characterized in that: The step of performing tape-out verification on each of the optimized chips to obtain verification results corresponding to each of the optimized chips includes: Conduct leakage test and product function test on each optimized chip respectively, and obtain leakage test data and product function test data corresponding to each optimized chip; The leakage test data and product function test data corresponding to each optimized chip are used as the verification results corresponding to each optimized chip.
5. The method for processing leakage of a memory chip according to claim 1, characterized in that: Determining a target processing technology from a plurality of candidate processing technologies according to each of the verification results includes: The target processing technology is determined based on the leakage test data corresponding to each optimized chip and the product function test data.
6. The method for processing leakage of a memory chip according to claim 5, characterized in that: The target processing technology is determined based on the leakage test data corresponding to each optimized chip and the product function test data, including: Selecting at least one intermediate optimized chip from each of the product function test data, wherein the product function test data of each intermediate optimized chip meets a preset good product condition; The intermediate optimized chip with the smallest leakage test data is selected from the leakage test data of each intermediate optimized chip as the target optimized chip, and the to-be-selected processing technology corresponding to the target optimized chip is used as the target processing technology.
7. The method for processing leakage of a memory chip according to claim 1, characterized in that: According to the leakage test results of the plurality of test chips before the storage bit area is reduced, the leakage test results of the plurality of test chips after the storage bit area is reduced, and the functional test results of the plurality of test chips after the storage bit area is reduced, a plurality of chips to be optimized having gate-to-drain leakage problems are determined: Determine at least one functional chip to be tested according to the leakage test results of the plurality of test chips before the storage bit area is reduced and the leakage test results of the plurality of test chips after the storage bit area is reduced; Performing consistency detection on each of the functional chips to be tested to obtain a functional test result of each of the functional chips to be tested, and determining whether each of the functional chips to be tested meets a preset good product condition according to the functional test result of each of the functional chips to be tested; If not, each functional chip to be tested is regarded as a chip to be optimized.
8. The method for processing leakage of a memory chip according to claim 7, characterized in that: The step of determining at least one functional chip to be tested according to the leakage test results of the plurality of test chips before the storage bit area is reduced and the leakage test results of the plurality of test chips after the storage bit area is reduced comprises: Traverse the multiple test chips, and for the current test chip that is traversed, determine whether the current test chip has a gate-to-drain leakage problem according to the leakage test result of the current test chip before the storage bit area is reduced and the leakage test result of the current test chip after the storage bit area is reduced. If so, use the current test chip as the functional chip to be tested. After traversing all the test chips, multiple functional chips to be tested are obtained.
9. The method for processing leakage of a memory chip according to claim 8, characterized in that: The determining whether the current test chip has a gate-to-drain leakage problem according to a leakage test result of the current test chip before the storage bit area is reduced and a leakage test result of the current test chip after the storage bit area is reduced includes: According to the leakage test results of the current test chip before the storage bit area is reduced, the leakage test results of the current test chip after the storage bit area is reduced, and a pre-established leakage analysis model, it is determined whether the current test chip has a gate-to-drain leakage problem.
10. The method for processing leakage of a memory chip according to claim 8, characterized in that: The good product conditions include: the failure rate of the leakage-related test item is less than a preset threshold and there is no preset graph in the wafer test result graph.