Substrate and preparation method thereof, chip packaging structure and electronic equipment

Abstract

The invention discloses a substrate and a preparation method thereof, a chip packaging structure and electronic equipment, and relates to the technical field of substrate preparation technologies, the substrate preparation method comprises the steps that a substrate is provided, and the surface of one side of the substrate comprises a first area and a second area which are adjacent to each other; a patterned first insulating layer is formed on the surface of the substrate, the first insulating layer comprises a plurality of isolation walls located in the first area, and gaps are formed between the adjacent isolation walls; the retaining wall is positioned in the second area; based on the first insulating layer, a target metal layer is formed on the surface of the substrate through an electroplating process, and the target metal layer comprises a signal line and grounding metal; the signal line is located on the substrate surface exposed by the gap; the grounding metal is located on the substrate surface of the second region; in the electroplating process, electroplating liquid flows to the first area from the second area, and the retaining wall is located on a flowing path of the electroplating liquid.

Description

Technical Field

[0001] The present application relates to the technical field of substrate preparation technology, and in particular to a substrate and a preparation method thereof, a chip packaging structure and an electronic device. Background Art

[0002] With the continuous development of science and technology, more and more electronic devices are widely used in people's daily life and work, which brings great convenience to people's daily life and work and becomes an indispensable tool for people today. The core component of electronic devices to realize various functions is the chip.

[0003] In order to protect the chip, and to ensure electrical connection, enhance heat dissipation, improve reliability, and facilitate installation and transportation, the chip needs to be packaged and protected. An indispensable component for chip packaging protection is the substrate. At present, chip packaging pursues higher performance, smaller size and lower cost design. In the total cost of chip packaging, in addition to the cost of the chip itself, the manufacturing cost of the substrate used for chip packaging accounts for a large proportion, and reducing the number of metal layers stacked in the substrate can greatly reduce the manufacturing cost of the substrate.

[0004] Although reducing the number of metal layers stacked in the substrate can effectively reduce the manufacturing cost of the substrate, the reduction in the number of metal layers will inevitably lead to an increase in the distribution density of signal lines and a decrease in line width in the remaining metal layers. The larger signal line distribution density and smaller line width will make the metal layer where the signal line is located prone to signal line short-circuit problems during the electroplating preparation process, thereby reducing the preparation yield of the substrate. Summary of the invention

[0005] In view of the above problems, the present application provides a substrate and a preparation method thereof, a chip packaging structure and an electronic device to prevent the signal line short circuit problem in the metal layer of the substrate during the electroplating process and improve the preparation yield of the substrate. The specific scheme is as follows:

[0006] The first aspect of the present application provides a method for preparing a substrate, comprising:

[0007] Providing a substrate, wherein one side surface of the substrate includes a first area and a second area adjacent to each other;

[0008] A patterned first insulating layer is formed on the surface of the substrate, wherein the first insulating layer comprises: a plurality of isolation walls located in the first region, with gaps between adjacent isolation walls; and a retaining wall located in the second region;

[0009] Based on the first insulating layer, a target metal layer is formed on the surface of the substrate through an electroplating process, and the target metal layer includes a signal line and a grounding metal; the signal line is located on the surface of the substrate exposed by the gap; the grounding metal is located on the surface of the substrate in the second area; during the electroplating process, the plating solution flows from the second area to the first area, and the retaining wall is located on the flow path of the plating solution.

[0010] Optionally, in the above substrate preparation method, the base comprises a first metal layer and a first intermetallic insulating layer located on the surface of the first metal layer; the first intermetallic insulating layer has a conductive hole electrically connected to the ground metal;

[0011] The method of forming the first insulating layer includes:

[0012] forming a first insulating layer covering the first region and the second region;

[0013] The first insulating layer is etched to form a plurality of sequentially arranged isolation walls in the first region and a retaining wall in the second region. After etching, the first insulating layer exposes the isolation walls and the substrate surface outside the retaining walls.

[0014] Optionally, in the above-mentioned substrate preparation method, the base includes a first metal layer and a first intermetallic insulating layer located on the surface of the first metal layer; the first intermetallic insulating layer has a conductive hole electrically connected to the grounding metal; in the length direction of the retaining wall, the conductive hole and the straight line where the retaining wall is located have an overlapping part; in the direction perpendicular to the plane where the base is located, the retaining wall and the conductive hole have no overlapping part.

[0015] Optionally, in the above substrate preparation method, there is a first distance between the center of the conductive hole and the adjacent isolation wall; there is a second distance between the blocking wall and the adjacent isolation wall; and the second distance is greater than the first distance.

[0016] Optionally, in the above substrate preparation method, a plurality of conductive holes arranged in sequence are provided on the surface of the second region, and an arrangement direction of the conductive holes is parallel to a length direction of the isolation wall;

[0017] The second distance is greater than half of the diameter of the conductive hole, and a retaining wall is provided between two adjacent conductive holes.

[0018] Optionally, in the above substrate preparation method, there is a first distance between the center of the conductive hole and the adjacent isolation wall;

[0019] There is a second distance between the retaining wall and the adjacent isolation wall, and the second distance is smaller than the first distance.

[0020] Optionally, in the above substrate preparation method, a plurality of conductive holes arranged in sequence are provided on the surface of the second region, and an arrangement direction of the conductive holes is parallel to a length direction of the isolation wall;

[0021] A barrier wall is provided between adjacent conductive holes.

[0022] Optionally, in the above substrate preparation method, the distance between the retaining wall and the adjacent isolation wall meets the critical size requirement, so that the target metal layer between the retaining wall and the isolation wall forms a grounding wire, and the grounding wire is electrically connected to the conductive hole.

[0023] A second aspect of the present application provides a substrate, comprising:

[0024] A substrate, wherein one side surface of the substrate includes a first area and a second area adjacent to each other;

[0025] The circuit layer is located on the surface of the substrate, and the circuit layer includes: a plurality of isolation walls arranged in sequence in the first area; a plurality of signal lines located between adjacent isolation walls; a retaining wall located in the second area; and a grounding metal located on the surface of the substrate in the second area;

[0026] The retaining wall is at least used to reduce the impact force of the coating on the isolation wall during the process of forming the signal line by electroplating.

[0027] A third aspect of the present application provides a chip packaging structure, including:

[0028] The substrate comprises: a base, one side surface of the base comprises a first region and a second region adjacent to each other; a circuit layer, the circuit layer comprises: a plurality of isolation walls arranged in sequence in the first region, with gaps between adjacent isolation walls; a retaining wall located in the second region; a signal line located on the surface of the base exposed by the gap; and a grounding metal located on the surface of the base in the second region; wherein the retaining wall is at least used to reduce the impact force of the coating on the isolation wall during the process of electroplating the signal line;

[0029] A chip fixed to a substrate.

[0030] Optionally, in the above-mentioned chip packaging structure, the substrate includes a first metal layer and a first intermetallic insulating layer located on the surface of the first metal layer; the first intermetallic insulating layer has a conductive hole electrically connected to the grounding metal; in the length direction of the retaining wall, the conductive hole and the straight line where the retaining wall is located have an overlapping part; in the direction perpendicular to the plane where the substrate is located, the retaining wall and the conductive hole have no overlapping part.

[0031] Optionally, in the above chip packaging structure, there is a first distance between the center of the conductive hole and the adjacent isolation wall; there is a second distance between the blocking wall and the adjacent isolation wall; there are a plurality of conductive holes arranged in sequence on the surface of the second region, and the arrangement direction of the conductive holes is parallel to the length direction of the isolation wall; wherein,

[0032] The second distance is greater than the first distance; the second distance is greater than half of the diameter of the conductive hole, and a retaining wall is provided between two adjacent conductive holes;

[0033] Alternatively, the second distance is smaller than the first distance, and there is a barrier wall between adjacent conductive holes.

[0034] A fourth aspect of the present application provides an electronic device, comprising the above-mentioned chip packaging structure.

[0035] By means of the above technical solution, in the substrate and its preparation method, chip packaging structure and electronic device provided by the present application, in the process of preparing the substrate, a patterned first insulating layer is formed on the surface of the base, and the first insulating layer includes a plurality of isolation walls located in the first area and a retaining wall located in the second area. The gaps between the isolation walls can form signal lines in the process of electroplating to form the target metal layer, and the retaining walls located on the flow path of the plating solution can buffer the flow impact force of the plating solution, and can reduce the impact of the plating solution on the isolation walls, thereby preventing the short circuit problem of the signal line caused by the isolation wall being collapsed by the impact of the plating solution, and can improve the preparation yield of the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0037] The structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not used to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modification, change in proportion or adjustment of size, without affecting the effects and purposes that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0038] Figure 1 is a cross-sectional view of a substrate;

[0039] Figure 2 A schematic diagram of the preparation principle of a substrate;

[0040] Figure 3 A schematic diagram of the electroplating principle of a metal layer in a substrate;

[0041] Figure 4-Figure 7 A schematic diagram of the product structure of a substrate preparation method in different process steps provided in an embodiment of the present application;

[0042] Figure 8 A top view of a substrate provided in an embodiment of the present application;

[0043] Fig. 9 for Figure 8 A cross-sectional view of the substrate along the BB' direction;

[0044] Fig.10 For preparation Figure 8 A top view of a first insulating layer used in the substrate;

[0045] Fig.11 A top view of another substrate provided in an embodiment of the present application;

[0046] Fig.12 For preparation Fig.11 A top view of a first insulating layer used in the substrate;

[0047] Fig.13 A top view of another substrate provided in an embodiment of the present application;

[0048] Fig.14 A cross-sectional view of a chip packaging structure provided in an embodiment of the present application.

[0049] Reference numerals:

[0050] 11-signal line; 12-grounding metal; 13-insulating dielectric layer; 14-photoresist dry film; 141-graphic structure; 15-substrate; 151-first area; 152-second area; 153-first metal layer; 154-first intermetallic insulating layer; 16-first insulating layer; 161-isolation wall; 162-retaining wall; 171-first gap; 172-second gap; 18-target metal layer; 19-grounding line; 20-conductive hole; 21-substrate; 22-chip; 23-plastic encapsulation layer. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. It is known to those skilled in the art that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0052] When the manufacturing cost of the substrate is reduced by reducing the number of metal layers in the substrate, the signal line density in the single metal layer will increase. Under the premise that the substrate area remains unchanged, the increase in the signal line density in the single metal layer requires limiting the line width of the signal line.

[0053] At the same time, for some signals, due to the need for high transmission rates, low impedance design is required to meet signal integrity requirements, such as the data selection signal (DQ) in the low-power double data rate synchronous dynamic random access memory (LPDDR5X). In order to make the impedance design of the signal line meet the signal integrity requirements, when the stacking conditions in the package substrate remain unchanged, while reducing the line width of the signal line, it is necessary to reduce the spacing between the signal line and the reference ground to increase the capacitance of the surrounding lines, thereby meeting the requirements of impedance design and signal line fan-out line width control at the same time.

[0054] refer to Figure 1 , Figure 1 It is a cross-sectional view of a substrate, and the substrate shown includes: a plurality of metal layers stacked in sequence, and an insulating dielectric layer 13 is provided between adjacent metal layers. Figure 1 Take three metal layers as an example for illustration. The second metal layer includes a signal line 11 and a grounding metal 12 disposed adjacent to the signal line 11. The impedance of the signal line 11 is set to Z, the inductance of the signal line 11 is set to L, the capacitance between the signal line 11 and the adjacent grounding metal 12 is set to C, the distance between the signal line 11 and the adjacent grounding metal 12 is set to d, and the facing area between the signal line 11 and the adjacent grounding metal 12 is set to S. The facing area S between the signal line 11 and the adjacent grounding metal 12 is related to the facing length of the signal line 11 and the grounding metal 12 and the thickness of the metal layer. When the facing length and the thickness of the metal layer remain unchanged, S is equivalent to a constant.

[0055] Then Z and C can be expressed as follows:

[0056] (1)

[0057] (2)

[0058] in, is the dielectric constant of the dielectric material between the signal line and the ground metal in the substrate, and k is the electrostatic force constant.

[0059] If the line width w of the signal line 11 is reduced, L will increase. When L increases, if Z is to remain unchanged, C needs to be increased based on the above formula (1). If C is to be increased based on the above formula (2), d needs to be reduced.

[0060] From the above description, it can be known that in order to ensure that the impedance Z of the signal line 11 in the substrate remains unchanged to maintain signal integrity, when the signal line width w is reduced, the distance d between the signal line 11 and the adjacent grounding metal 12 needs to be reduced.

[0061] Taking the common substrate-supported thin-line manufacturing stacked semi-additive process (SAP) process as an example, substrate line lithography usually uses negative photoresist, and the photoresist solidified area will not be copper plated during the electroplating process to form an insulation gap between different network lines. The preparation principle is as follows: Figure 2 shown.

[0062] refer to Figure 2 , Figure 2 This is a schematic diagram of the principle of substrate preparation. If you want to prepare Figure 2 The substrate shown in the middle left figure can be used to prepare a metal layer having a ground metal 12 and a signal line 11 in a circuit board based on the SAP process. Figure 2 As shown in the middle right figure, a negative photoresist is used to prepare a patterned photoresist dry film 14. The portion of the insulating dielectric layer 13 surface covered by the photoresist dry film 14 will not be copper plated during the electroplating process, and the portion of the insulating dielectric layer 13 not covered by the photoresist dry film 14 will form a grounding metal 12 and a signal line 11 based on the pattern structure 141 of the photoresist dry film 14 during the electroplating process.

[0063] Based on the internal design of the chip and the arrangement of the copper interconnect bumps, some signal lines 11 in the substrate are adjacent to the large area grounding metal 12. During the electroplating process, the electroplating solution will Figure 3 As shown, the electroplated surface is flushed with a certain spray pressure.

[0064] refer to Figure 3 , Figure 3 A schematic diagram of the electroplating principle of a metal layer in a substrate. Figure 3 The dashed arrow in the middle is used to indicate the flow direction of the plating solution, and the plating solution flows from the outside of one edge of the substrate to the inside at a certain spray pressure. As described above, when the line width of the signal line 11 is reduced, the distance d between the signal line 11 and the grounding metal 12 will be reduced, which will in turn reduce the width of the isolation wall formed by the photoresist dry film 14. In the area adjacent to the signal line 11 and the large-area grounding metal 12, due to the low density of the photoresist dry film 14, the photoresist dry film 14 in this area is subjected to a greater impact force of the plating solution than the area with the signal line 11 distribution density. When d is small, the isolation wall formed by the photoresist dry film 14 will collapse, which will cause a short circuit problem in the metal layer, resulting in a reduction in the preparation yield of the substrate.

[0065] exist Figure 3In the figure, four isolation walls in the photoresist dry film 14 are used as an example for illustration. The gap between adjacent isolation walls can form a signal line 11 by electroplating metal. The area exposed on the outside of the isolation wall on the left side of the photoresist dry film 14 can be formed into a large area of ​​grounding metal 12 by electroplating metal. For the isolation wall on the left side, since it is located upstream of the flow direction of the plating solution, there is no other structure on its left side to buffer the impact of the plating solution, so the isolation wall on the left side is prone to collapse, which will cause a short circuit between the signal line 11 and the adjacent grounding metal 12.

[0066] In order to prevent the short circuit problem between the signal line 11 and the adjacent ground metal 12, an easy way to think of is to increase the distance d so that Figure 3 The width of the isolation wall on the left side is increased to improve its ability to withstand the impact of the plating solution. Although this method can prevent the isolation wall from collapsing, it can avoid the short circuit problem between the signal line 11 and the adjacent grounding metal 12. However, based on the above formula (2), increasing the distance d will lead to a decrease in capacitance C. In order to ensure the integrity of the signal transmission of the signal line 11, when the capacitance C is reduced and the impedance Z needs to be kept unchanged, based on the above formula (1), the inductance L needs to be reduced.

[0067] Since the inductance L is negatively correlated with the line width w of the signal line 11, the line width w of the signal line 11 needs to be increased when L is reduced. This method requires increasing the line width w of the signal line 11, which is contrary to the solution of reducing the number of metal layers in the substrate and reducing the line width. It is impossible to keep the impedance Z constant while increasing the line width w.

[0068] Based on the above description, if the isolation wall collapse problem is prevented by increasing the distance d, it is necessary to sacrifice the impedance requirements and relax the requirements for signal integrity. The substrate is prepared based on the design parameters of a larger distance d and a smaller line width w, thereby reducing the number of metal layers in the substrate.

[0069] From the above description, it can be seen that in conventional technology, the purpose of reducing the number of metal layers in the substrate can only be achieved by sacrificing the impedance requirements of the signal line 11 in the substrate and the signal integrity requirements, and designing the layout of the signal line 11 and the grounding metal 12 in the substrate with a larger distance d and a smaller line width w. It is impossible to reduce the number of metal layers in the substrate while taking into account the impedance performance of the signal line 11 and ensuring signal integrity.

[0070] In order to solve the above problems, the present invention provides a method for preparing a substrate, comprising:

[0071] Providing a substrate, wherein one side surface of the substrate includes a first area and a second area adjacent to each other;

[0072] A patterned first insulating layer is formed on the surface of the substrate, wherein the first insulating layer comprises: a plurality of isolation walls located in the first region, with gaps between adjacent isolation walls; and a retaining wall located in the second region;

[0073] Based on the first insulating layer, a target metal layer is formed on the surface of the substrate through an electroplating process, and the target metal layer includes a signal line and a grounding metal; the signal line is located on the surface of the substrate exposed by the gap; the grounding metal is located on the surface of the substrate in the second area; during the electroplating process, the plating solution flows from the second area to the first area, and the retaining wall is located on the flow path of the plating solution.

[0074] In the embodiment of the present application, in the process of preparing the substrate, a patterned first insulating layer is formed on the surface of the substrate, and the first insulating layer includes a plurality of isolation walls located in the first area and a retaining wall located in the second area. The gaps between the isolation walls can form signal lines in the process of forming the target metal layer by electroplating, and the retaining walls located on the flow path of the plating solution can buffer the flow impact force of the plating solution, and can reduce the impact of the plating solution on the isolation walls, thereby preventing the short circuit problem of the signal line caused by the isolation walls being collapsed by the impact of the plating solution, and can improve the preparation yield of the substrate.

[0075] From the above description, it can be seen that since the retaining wall in the second area can buffer the flow impact force of the plating solution, the isolation wall adjacent to the second area in the first area can be prevented from collapsing due to the impact force of the plating solution. Based on this, the layout parameters of the signal line and the grounding metal in the substrate can be designed while maintaining a small distance d and a small line width w. While reducing the number of metal layers through high signal line density and small line width design parameters, the impedance characteristics of the signal line can also be guaranteed to ensure the integrity of the signal.

[0076] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0077] refer to Figure 4-Figure 7 , Figure 4-Figure 7 A schematic diagram of the product structure of a substrate preparation method in different process steps provided in an embodiment of the present application, Figure 4-Figure 6 They can all be cross-sectional views of the substrate along the AA′ direction at the corresponding process steps. Figure 7 A top view of a substrate after forming a target metal layer 18 by electroplating. The substrate preparation method shown includes:

[0078] Step S11: Figure 4 As shown, a substrate 15 is provided, and one side surface of the substrate 15 includes adjacent first areas 151 and second areas 152 .

[0079] In the embodiment of the present application, Figure 41 is a schematic diagram of a partial cross section of the substrate 15. For the entire substrate 15, the second region 152 may surround the first region 151.

[0080] Step S12: Figure 5 As shown, a patterned first insulating layer 16 is formed on the surface of the substrate 15 .

[0081] The first insulating layer 16 includes: a plurality of isolation walls 161 located in the first region 151 , with gaps between adjacent isolation walls 161 ; a retaining wall 162 located in the second region 152 ;

[0082] Optionally, the width of the retaining wall 162 may be greater than the width of the isolation wall 161, so as to better buffer the impact of the electroplating solution and better protect the isolation wall 161. In other embodiments, the width of the retaining wall 162 may be no greater than the width of the isolation wall 161, which also has a certain buffering effect on the impact of the electroplating solution compared to the solution without the retaining wall 162.

[0083] Step S13: Figure 6 and Figure 7 As shown, based on the first insulating layer 16, a target metal layer 18 is formed on the surface of the substrate 15 through an electroplating process. Optionally, in the embodiment of the present application, the material of the metal layer may be copper.

[0084] The target metal layer 18 includes a signal line 11 and a grounding metal 12; the signal line 11 is located on the surface of the substrate 15 exposed by the gap; the grounding metal 12 is located on the surface of the substrate 15 in the second area 152; during the electroplating process, the plating solution flows from the second area 152 to the first area 151, and the retaining wall 162 is located on the flow path of the plating solution. The plating solution flows from the second area 152 to the first area 151, that is, Figure 4-Figure 6 In the direction from left to right.

[0085] The first insulating layer 16 includes at least one group of isolation walls, and one group of isolation walls includes two isolation walls 161 that are spaced apart. In the same group of isolation walls, there is a first gap 171 between two isolation walls 161. When there are multiple groups of isolation walls, there is a second gap 172 between two adjacent groups of isolation walls. After the target metal layer 18 is formed by electroplating, the portion of the target metal layer 18 located in the first gap 171 is the signal line 11, and the portion located in the second gap 172 is the ground line 19 adjacent to the signal line 11. In other embodiments, multiple signal lines 11 may be arranged in sequence, and adjacent signal lines 11 are isolated based on the isolation walls 161, and there is no need to set a ground line 19 between adjacent signal lines 11.

[0086] In the substrate preparation method provided by the embodiment of the present application, since the retaining wall 162 in the second area 152 can buffer the flow impact force of the electroplating solution, the isolation wall 161 adjacent to the second area 152 in the first area 151 can be prevented from collapsing due to the impact force of the electroplating solution. Based on this, the layout parameters of the signal line 11 and the grounding metal 12 in the substrate can be designed while maintaining a small distance d and a small line width w. While reducing the number of metal layers through high signal line density and small line width design parameters, the impedance characteristics of the signal line 11 can be guaranteed, the integrity of the signal can be guaranteed, and the yield rate of substrate preparation can be improved.

[0087] refer to Figure 8 and Fig. 9 , Figure 8 A top view of a substrate provided in an embodiment of the present application, Fig. 9 for Figure 8 The cross-sectional view of the substrate along the BB' direction is shown. Based on the above embodiment, the substrate 15 includes a first metal layer 153 and a first metal interlayer 154 located on the surface of the first metal layer 153; the first metal interlayer 154 has a conductive hole 20 electrically connected to the ground metal 12. The conductive hole 20 is a reference ground return hole for the ground metal 12, which can reduce signal crosstalk.

[0088] based on Figure 8 and Fig. 9 The method shown is also referenced Figures 5 to 7 In the substrate preparation method, the method for forming the first insulating layer 16 includes: first, forming the first insulating layer 16 covering the first area 151 and the second area 152; then, etching the first insulating layer 16 to form a plurality of sequentially arranged isolation walls 161 located in the first area 151 and a retaining wall 162 located in the second area 152, and the first insulating layer 16 after etching exposes the surface of the substrate 15 outside the isolation walls 161 and the retaining wall 162. Optionally, the first insulating layer 16 can be a photoresist dry film, and the first insulating layer 16 of the desired graphic structure can be formed by a photolithography process. The first insulating layer 16 can also be other insulating dielectric materials, not limited to photoresist dry films.

[0089] Based on the conductive via 20 , the grounding metal 12 can be connected to the first metal layer 153 in the substrate 15 , and the first metal layer 153 is a grounding metal layer.

[0090] In one implementation of the present application, Figure 8 and Fig. 9 As shown, the substrate 15 includes a first metal layer 153 and a first intermetallic insulating layer 154 located on the surface of the first metal layer 153; the first intermetallic insulating layer 154 has a conductive hole 20 electrically connected to the ground metal 12; the retaining wall 162 and the isolation wall 161 are parallel and opposite to each other, as shown in FIG. Figure 8 As shown, both extend in the horizontal direction.

[0091] like Figure 8 As shown, in the length direction of the retaining wall 162, the conductive hole 20 and the straight line where the retaining wall 162 is located have an overlapping portion. Based on the overlapping portion, this method can make the retaining wall 162 occupy at least part of the area between the conductive holes 20 as much as possible, reduce the occupation of the grounding metal layer area outside the side of the conductive hole 20 away from the isolation wall 161, improve the utilization rate of the substrate space, and reduce the area of ​​the substrate. In other embodiments, as described below, when the substrate layout space is sufficient, it can also be as follows Fig.13 As shown, the retaining wall 162 is arranged in the length direction, the conductive hole 20 and the retaining wall 162 have no overlapping parts, and the retaining wall 162 is located on the side of the conductive hole 20 away from the isolation wall 161.

[0092] In order to prevent the retaining wall 162 from affecting the electrical connection effect between the grounding metal 12 and the conductive hole 20, a non-overlapping portion between the retaining wall 162 and the conductive hole 20 is set in a direction perpendicular to the plane where the substrate 15 is located, so as to prevent the retaining wall 162 from covering the conductive hole 20 and affecting the electrical connection effect between the grounding metal 12 and the conductive hole 20.

[0093] There is a first distance H1 between the center of the conductive hole 20 and the adjacent isolation wall 161 ; there is a second distance H2 between the blocking wall 162 and the adjacent isolation wall 161 ; and the second distance H2 is greater than the first distance H1 .

[0094] like Figure 8 As shown, when H2>H1, there is a larger area between the retaining wall 162 and the adjacent isolation wall 161 for electroplating the grounding metal 12. At this time, the peripheral signal line 11 is directly arranged adjacent to the large area of ​​the grounding metal 12, and there is no need to arrange a thinner grounding line 19 between the signal line 11 and the grounding metal 12. The peripheral signal line 11 is the signal line 11 adjacent to the second area 152.

[0095] When H2>H1, the surface of the second region 152 has a plurality of conductive holes 20 arranged in sequence, and the arrangement direction of the conductive holes 20 is parallel to the length direction of the isolation wall 161; the second distance H2 is greater than half the aperture of the conductive hole 20, and a retaining wall 162 is respectively arranged between two adjacent conductive holes 20. In this way, the retaining wall 162 can be arranged in the area between the two conductive holes 20, thereby improving the utilization rate of the layout space in the substrate and reducing the substrate area. At this time, a row of conductive holes 20 adjacent to the peripheral isolation wall 161 can be arranged in the second region 152. The peripheral isolation wall 161 is the isolation wall 161 adjacent to the second region 152.

[0096] for Figure 8For the substrate shown, H2>H1, a retaining wall 162 having a larger second distance H2 from the peripheral isolation wall 161 can be manufactured in the second region 152 to buffer the impact force of the electroplating solution on the peripheral isolation wall 161 during the electroplating process.

[0097] This method is suitable for a solution where there is enough space around the peripheral signal line 11 for laying out a larger area of ​​grounding metal 12. In this method, the coverage area ratio of the metal layer in the second area 152 can be optimized by optimizing the design parameters of the retaining wall 162, thereby optimizing the performance and reliability of the substrate. Generally, the metal layer in the substrate is an electroplated copper layer, and by optimizing the design parameters of the retaining wall 162, the copper coverage ratio in the second area 152 can be optimized, thereby optimizing the performance and reliability of the substrate.

[0098] In the embodiment of the present application, when the layout space of the substrate is sufficient, H2 can be set to be greater than or equal to the aperture of the conductive hole 20. In this case, in the length direction of the retaining wall 162, the straight line where the retaining wall 162 is located has no overlapping part with the conductive hole 20, and the conductive hole 20 is located between the length extension straight line of the retaining wall 162 and the isolation wall 161. H2 can also be set to be smaller than the aperture of the conductive hole 20. In this case, in the length direction of the retaining wall 162, the extension line of the retaining wall 162 has an overlapping part with the conductive hole 20, and the retaining wall 162 can be arranged based on the space between adjacent conductive holes 20.

[0099] refer to Fig.10 , Fig.10 For preparation Figure 8 A top view of the first insulating layer used in the substrate shown, Fig.10 The dashed arrow in the middle is used to indicate the flow direction of the electroplating solution. When a retaining wall 162 is respectively provided between two adjacent conductive holes 20, if the number of the conductive holes 20 is greater than 2, a plurality of retaining walls 162 spaced apart on the same straight line can be arranged based on the length direction of the isolation wall 161. By optimizing the width and length of the retaining wall 162, the buffering effect of the retaining wall on the impact force of the electroplating solution can be optimized, which can better assist in resisting the impact force of the electroplating solution, so as to better optimize the electroplating effect of the target metal layer 18.

[0100] On the one hand, it is necessary to set the width of the retaining wall 162 to be larger. For example, the width of the retaining wall 162 can be set to be larger than the width of the isolation wall 161. The width of the retaining wall 162 can be no less than 30μm to prevent the retaining wall 162 from collapsing due to the impact of the plating solution due to its small width. It is also necessary to prevent the width of the retaining wall 162 from being too large and affecting the area of ​​the grounding metal 12 in the second area 152. For example, the width of the retaining wall 162 can be set to not exceed 50μm.

[0101] On the other hand, when the layout area in the substrate is sufficient, a larger H2 is set between the retaining wall 162 and the isolation wall 161, and the larger space between the retaining wall 162 and the isolation wall 161 further buffers the flow rate, and after the plating solution is blocked by the retaining wall, the larger size of H2 can alleviate the uneven distribution of the plating solution area. At this time, the value of H2 can be set to be the same as or approximately the same as the aperture of the conductive hole 20, such as 75 um ~ 100 um. In another case, if the space of the substrate is limited and H2 with the same or approximately the same aperture as the conductive hole 20 cannot be laid out, H2 can be set according to the key size requirements required by the grounding wire 19. At this time, when H2 does not exceed 25 um, the reliability risk of the substrate is relatively small.

[0102] As described above, the retaining wall 162 cannot cover the position of the conductive via 20 to avoid affecting the electrical contact area between the formed grounding metal 12 and the conductive via 20 and increasing the resistance.

[0103] In addition, the distance between the retaining wall 162 and the adjacent isolation wall 161 cannot be too far, that is, H2 cannot be too large, so as to avoid the problem of insufficient buffering effect on the impact force of the electroplating solution caused by H2 being too large.

[0104] for Figure 8 In the solution shown, the peripheral signal line 11 is directly adjacent to the large area grounding metal 12, and a small isolation distance d is required between the signal line 11 and the grounding metal 12. Fig.10 As shown in the second region 152, due to the lower line density in the second region 152, the peripheral isolation wall 161 adjacent to the second region 152 is at a higher risk of being washed down by the plating solution during the electroplating process, and the target metal layer 18 will be electroplated at the washed down position, which will cause the signal line 11 and the ground metal 12 to short-circuit and fail at this position. Fig.10 The retaining wall 162 in the second area 152 can buffer the impact force of the electroplating solution and prevent the outer isolation wall 161 from collapsing during the electroplating process, thereby preventing the signal line 11 and the ground metal 12 from short-circuiting and failing.

[0105] refer to Fig.11 , Fig.11 A top view of another substrate provided in an embodiment of the present application, Figure 8 The difference between the methods shown is that Fig.11In the substrate shown, the second distance H2 is smaller than the first distance H1. This method is suitable for scenarios where the layout space in the substrate is limited. The aperture of the conductive hole 20 is determined, and the minimum value of H1 is equal to the radius of the conductive hole 20. When H2 < H1, a grounding line 19 with a line width smaller than the signal line 11 can be formed by using the smaller second distance H2 and the space between the retaining wall 162 and the adjacent isolation wall 161. The grounding line 19 is connected to the grounding metal 12 and is connected to the grounding metal layer below through the conductive hole 20.

[0106] exist Fig.11 In the illustrated embodiment, the surface of the second region 152 has a plurality of conductive holes 20 arranged in sequence, and the arrangement direction of the conductive holes 20 is parallel to the length direction of the isolation wall 161; there is a retaining wall 162 between adjacent conductive holes 20. In this embodiment, a grounding wire 19 with a smaller line width can be formed between two adjacent conductive holes 20. The grounding wire and the grounding metal 12 are an integrated structure formed by electroplating, and can be connected to the grounding metal layer below through the conductive hole 20 to ensure the integrity of the grounding plane in the substrate.

[0107] for Fig.11 In the substrate shown, the distance H2 between the retaining wall 162 and the adjacent isolation wall 161 is small, and a ground line can be formed during the electroplating process based on the distance H2. In this way, since the width of the retaining wall 162 can be compressed within the aperture interval of the conductive hole 20 perpendicular to the isolation wall 161, the width of the retaining wall 162 can be reduced.

[0108] refer to Fig.12 , Fig.12 For preparation Fig.11 A top view of the first insulating layer used in the substrate shown, Fig.12 The dashed arrow in the middle is used to indicate the flow direction of the electroplating solution. In this method, the buffering effect of the retaining wall on the impact force of the electroplating solution can also be optimized by optimizing the width and length of the retaining wall 162, which can better help resist the impact force of the electroplating solution and better optimize the electroplating effect of the target metal layer 18.

[0109] In the embodiment of the present application, the distance between the retaining wall 162 and the adjacent isolation wall 161 meets the critical dimension requirement, so that the target metal layer 18 located between the retaining wall 162 and the isolation wall 161 forms a grounding line 19, and the grounding line 19 is electrically connected to the conductive hole 20. Optionally, the critical dimension is not greater than 25 μm. In this way, the distance between the retaining wall 162 and the adjacent isolation wall 161 can be controlled by controlling the second distance H2 between the retaining wall 162 and the adjacent isolation wall 161 so that the distance between the retaining wall 162 and the adjacent isolation wall 161 meets the critical dimension requirement.

[0110] Optionally, in the embodiment of the present application, the width of the retaining wall 162 may be in the range of 30 μm to 50 μm, such as 35 μm, 40 μm, or 45 μm. Optionally, the length of the retaining wall 162 may be set to be smaller than the distance between two adjacent conductive holes 20. In this case, the retaining wall 162 may be arranged in the space between the conductive holes 20. As described below, it is also possible to Fig.13 The length of the retaining wall 162 is set to be greater than the distance between two adjacent conductive holes 20 .

[0111] It can be seen from the above description that the substrate prepared by the substrate preparation method provided in the embodiment of the present application can control the signal line 11 in the substrate to meet the impedance design requirements of fine lines and fine spacing, while reducing the risk of collapse of the isolation wall 161 during the substrate preparation process, which can improve the preparation yield of the substrate and reduce the manufacturing cost. Therefore, the technical solution of the embodiment of the present application can prevent the short circuit problem caused by the collapse of the isolation wall 161 while ensuring the impedance stability and signal integrity of the signal line 11, and is thus suitable for the layout design requirements of high signal line density and small line width when reducing the number of metal layers in the substrate.

[0112] Based on the substrate preparation method provided in the above embodiment, another embodiment of the present application further provides a substrate, which can be prepared based on any implementation of the above embodiment. Referring to the drawings of the above embodiment, the substrate includes:

[0113] A substrate 15, wherein one side surface of the substrate 15 includes a first region 151 and a second region 152 adjacent to each other;

[0114] The circuit layer is located on the surface of the substrate 15, and the circuit layer includes: a plurality of isolation walls 161 arranged in sequence in the first area 151; a plurality of signal lines 11 located between adjacent isolation walls 161; a retaining wall 162 located in the second area 152; and a grounding metal 12 located on the surface of the substrate 15 in the second area 152;

[0115] The retaining wall 162 is at least used to reduce the impact force of the coating on the isolation wall 161 during the process of forming the signal line by electroplating.

[0116] In the embodiment of the present application, the retaining wall 162 and the isolation wall 161 in the substrate can be the unremoved portion of the first insulating layer 16 in the embodiment of the substrate preparation method. After the signal line 11 and the grounding metal 12 are formed by electroplating, the surface of the target metal layer 18 on the side away from the substrate 15 can be thinned to remove the target metal layer 18 covering the upper surface of the first insulating layer 16 during the electroplating process. In this way, the signal line 11 and the grounding metal 12 of the substrate are directly insulated and isolated based on the first insulating layer 16. The upper surface of the first insulating layer 16 is the surface of the pseudo first insulating layer 16 on the side away from the substrate 15.

[0117] In another method, after the signal line 11 and the grounding metal 12 are formed by electroplating, the surface of the target metal layer 18 facing away from the substrate 15 is thinned, the target metal layer 18 covering the upper surface of the first insulating layer 16 during the electroplating process is removed, and then the first insulating layer 16 at the position of the isolation wall 161 and the retaining wall 162 is peeled off, and the insulating dielectric material is filled in the groove formed by peeling off the first insulating layer 16 to form a new isolation wall 161 and retaining wall 162.

[0118] refer to Fig.13 , Fig.13 This is a top view of another substrate provided in an embodiment of the present application. Based on the above embodiment, in the substrate, a retaining wall 162 may be provided on the side of the conductive hole 20 away from the isolation wall 161. In this case, H2 may be larger than the aperture of the conductive hole 20. This method is suitable for a substrate with sufficient space to lay out a retaining wall 162 with a larger H2.

[0119] like Fig.13 As shown, since H2 is larger than the aperture of the conductive hole 20, in this method, the length of the retaining wall 162 can be set to be larger than the distance between two adjacent conductive holes 20. At this time, since the retaining wall 162 has no overlapping portion with the conductive hole 20 in the length extension direction, the length of the retaining wall 162 can be set according to demand, and the length of the retaining wall 162 can also be smaller than the distance between two adjacent conductive holes 20.

[0120] The substrate provided in the embodiment of the present application can be prepared using the substrate preparation method provided in the above-mentioned embodiment. The retaining wall 162 can be used to buffer the impact force of the plating solution during the electroplating process to avoid the short circuit problem caused by the isolation wall 161 being knocked down. While ensuring the impedance stability and signal integrity of the signal line 11, the short circuit problem caused by the collapse of the isolation wall 161 can be prevented. Therefore, it is suitable for reducing the number of metal layers in the substrate and meeting the layout design requirements of high signal line density and small line width.

[0121] refer to Fig.14 , Fig.14 This is a cross-sectional view of a chip packaging structure provided in an embodiment of the present application, and the chip packaging structure shown includes: a substrate 21 provided in any implementation manner of the above embodiments; and a chip 22 fixed on the substrate 21.

[0122] The attached drawings of the substrate 21 can be described as in the above embodiment, including: a base 15, one side surface of the base 15 includes adjacent first areas 151 and second areas 152; a circuit layer, the circuit layer includes: a plurality of isolation walls 161 arranged in sequence in the first area 151, with gaps between adjacent isolation walls 161; a retaining wall 162 located in the second area 152; a signal line 11, located on the surface of the base 15 exposed by the gap; a grounding metal 12, located on the surface of the base 15 in the second area 152; wherein the retaining wall 162 is at least used to reduce the coating impact force borne by the isolation wall 161 during the process of electroplating to form the signal line;

[0123] Optionally, a plastic packaging layer 23 surrounding the chip 22 may be provided on the substrate 21 to improve the plastic packaging reliability and stability of the chip 22 .

[0124] In the chip packaging structure, a substrate 15 can be provided including a first metal layer 153 and a first metal interlayer insulating layer 154 located on the surface of the first metal layer 153; the first metal interlayer insulating layer 154 has a conductive hole 20 electrically connected to the grounding metal 12; in the length direction of the retaining wall 162, the conductive hole 20 and the retaining wall 162 have an overlapping portion.

[0125] In one embodiment, a first distance H1 may be provided between the center of the conductive hole 20 and the adjacent isolation wall 161; a second distance H2 may be provided between the retaining wall 162 and the adjacent isolation wall 161, and a plurality of conductive holes 20 may be arranged in sequence on the surface of the second region 152, and the arrangement direction of the conductive holes 20 may be parallel to the length direction of the isolation wall 161; wherein the second distance H2 is greater than the first distance H1; the second distance H2 is greater than half the aperture of the conductive hole 20, and a retaining wall 162 is provided between two adjacent conductive holes 20 respectively; or, the second distance H2 is less than the first distance H1, and a retaining wall 162 is provided between adjacent conductive holes 20.

[0126] The chip packaging structure provided in the embodiment of the present application adopts the substrate 21 mentioned in the above embodiment, which can reduce the number of metal layers in the substrate 21 to reduce the volume of the chip packaging structure. In addition, while reducing the number of metal layers in the substrate 21, the electroplating impact force on the isolation wall 161 during the electroplating process can be reduced by the retaining wall 162 to prevent short circuit problems, and at the same time, the impedance and signal integrity of the signal line 11 can be guaranteed.

[0127] Based on the above embodiment, another embodiment of the present application further provides an electronic device, and the electronic device includes the above chip packaging structure.

[0128] In the embodiment of the present application, the electronic device may be a mobile phone, a laptop computer, a tablet computer, a wearable device, etc. The electronic device adopts the above chip packaging structure, and the substrate used can reduce the number of metal layers while ensuring signal integrity and signal line impedance performance, and reduce the thickness of the device while reducing the manufacturing cost.

[0129] In the specification of this application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0130] It should be noted that in the description of the present application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structure. In addition, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially refer to positioning on the upper side of another element according to the direction of gravity.

[0131] The terms "upper", "lower", "top", "bottom", "inner", "outer", etc. indicate positions or positional relationships based on the positions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally arranged component at the same time.

[0132] It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such article or device. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the existence of other identical elements in the article or device including the above elements.

[0133] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a substrate, comprising: Providing a substrate, wherein a surface of one side of the substrate includes a first area and a second area adjacent to each other; A patterned first insulating layer is formed on the surface of the substrate, wherein the first insulating layer comprises: a plurality of isolation walls located in the first region, with gaps between adjacent isolation walls; and a retaining wall located in the second region; Based on the first insulating layer, a target metal layer is formed on the surface of the substrate through an electroplating process, and the target metal layer includes a signal line and a grounding metal; the signal line is located on the surface of the substrate exposed by the gap; the grounding metal is located on the surface of the substrate in the second area; during the electroplating process, the plating solution flows from the second area to the first area, and the retaining wall is located on the flow path of the plating solution.

2. The method for preparing a substrate according to claim 1, wherein the base comprises a first metal layer and a first intermetallic insulating layer located on a surface of the first metal layer; The first intermetallic insulating layer has a conductive hole electrically connected to the grounding metal; The method of forming the first insulating layer includes: forming the first insulating layer covering the first region and the second region; The first insulating layer is etched to form a plurality of sequentially arranged isolation walls located in the first region and the retaining wall located in the second region, and the first insulating layer after etching exposes the isolation walls and the substrate surface outside the retaining walls.

3. According to the substrate preparation method according to claim 1, the base includes a first metal layer and a first metal interlayer insulating layer located on the surface of the first metal layer; the first metal interlayer insulating layer has a conductive hole electrically connected to the grounding metal; in the length direction of the retaining wall, the conductive hole has an overlapping part with the straight line where the retaining wall is located; in the direction perpendicular to the plane where the base is located, the retaining wall has no overlapping part with the conductive hole.

4. According to the substrate preparation method of claim 3, there is a first distance between the center of the conductive hole and the adjacent isolation wall; there is a second distance between the blocking wall and the adjacent isolation wall; and the second distance is greater than the first distance.

5. The method for preparing a substrate according to claim 4, wherein a plurality of the conductive holes are arranged in sequence on the surface of the second region, and an arrangement direction of the conductive holes is parallel to a length direction of the isolation wall; The second distance is greater than half of the diameter of the conductive hole, and the retaining wall is respectively arranged between two adjacent conductive holes.

6. The method for preparing a substrate according to claim 3, wherein a first distance exists between the center of the conductive hole and the adjacent isolation wall; There is a second distance between the retaining wall and the adjacent isolation wall, and the second distance is smaller than the first distance.

7. The method for preparing a substrate according to claim 6, wherein a plurality of the conductive holes are arranged in sequence on the surface of the second region, and an arrangement direction of the conductive holes is parallel to a length direction of the isolation wall; There is a blocking wall between adjacent conductive holes.

8. According to the substrate preparation method of claim 3, the distance between the retaining wall and the adjacent isolation wall meets the critical size requirement, so that the target metal layer located between the retaining wall and the isolation wall forms a grounding wire, and the grounding wire is electrically connected to the conductive hole.

9. A substrate, comprising: A substrate, wherein one side surface of the substrate includes a first area and a second area adjacent to each other; A circuit layer, located on the surface of the substrate, the circuit layer comprising: a plurality of isolation walls arranged in sequence in the first area; a plurality of signal lines located between adjacent isolation walls; a retaining wall located in the second area; and a grounding metal located on the surface of the substrate in the second area; The retaining wall is at least used to reduce the impact force of the coating on the isolation wall during the process of forming the signal line by electroplating.

10. A chip packaging structure, comprising: A substrate, the substrate comprising: a base, one side surface of the base comprising a first region and a second region adjacent to each other; a circuit layer, the circuit layer comprising: a plurality of isolation walls arranged in sequence in the first region, with gaps between adjacent isolation walls; a retaining wall located in the second region; a signal line located on the surface of the base exposed by the gap; and a grounding metal located on the surface of the base in the second region; wherein the retaining wall is at least used to reduce the impact force of the coating on the isolation wall during the process of electroplating the signal line; A chip is fixed on the substrate.

11. According to the chip packaging structure of claim 10, the substrate includes a first metal layer and a first metal interlayer insulating layer located on the surface of the first metal layer; the first metal interlayer insulating layer has a conductive hole electrically connected to the grounding metal; in the length direction of the retaining wall, the conductive hole has an overlapping portion with the straight line where the retaining wall is located; in the direction perpendicular to the plane where the substrate is located, the retaining wall has no overlapping portion with the conductive hole.

12. The chip packaging structure according to claim 11, wherein there is a first distance between the center of the conductive hole and the adjacent isolation wall; there is a second distance between the blocking wall and the adjacent isolation wall; a plurality of the conductive holes are arranged in sequence on the surface of the second region, and the arrangement direction of the conductive holes is parallel to the length direction of the isolation wall; wherein, The second distance is greater than the first distance; the second distance is greater than half of the diameter of the conductive hole, and the retaining wall is respectively arranged between two adjacent conductive holes; Alternatively, the second distance is smaller than the first distance, and there is a blocking wall between adjacent conductive holes.

13. An electronic device comprising the chip packaging structure according to any one of claims 10 to 12.

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