Package substrate and manufacturing method thereof

Abstract

The invention provides a package substrate and a manufacturing method thereof. The package substrate includes a circuit structure formed on a core layer having a plurality of conductive posts, and a support structure formed in the core layer and in the circuit structure and disposed corresponding to a peripheral region of the core layer, so that the support structure can effectively suppress layering of the circuit structure.

Description

Technical Field

[0001] The present invention relates to a semiconductor packaging technology, and in particular to a packaging substrate capable of improving reliability and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor packaging technology, semiconductor devices have developed different packaging types. The semiconductor device mainly arranges a semiconductor chip on a package substrate, electrically connects the semiconductor chip to the package substrate, and then encapsulates the semiconductor chip with a packaging colloid.

[0003] Figures 1A to 1C It is a cross-sectional schematic diagram of a method for manufacturing a conventional packaging substrate 1 .

[0004] like Figure 1A As shown, a plurality of through holes 100 are formed on a core layer 10 .

[0005] like Figure 1B As shown, a wiring layer 12 is formed on the upper and lower sides of the core layer 10 by a patterning process, and a plurality of conductive pillars 11 electrically connected to the wiring layer 12 are formed in each of the through holes 100 .

[0006] like Figure 1C As shown, a circuit structure 14 is formed on the upper and lower sides of the core layer 10, and a metal sheet 15 is formed at the edge of the circuit structure 14. The circuit structure 14 includes at least one dielectric layer 140, a circuit layer 141 formed on the dielectric layer 140, and a plurality of conductive blind vias 142 formed in the dielectric layer 140 and electrically connecting the circuit layer 141 and the wiring layer 12.

[0007] In the subsequent process, a solder mask layer such as green paint may be formed on the circuit structure 14 (not shown).

[0008] However, in the conventional method of manufacturing the package substrate 1, the metal sheet 15 is too thin. In the process of full-page specifications, the stress between the dielectric layers 140 is too large, and it is difficult to suppress the delamination between the dielectric layers 140, resulting in moisture infiltration and damage to electrical functions or poor reliability.

[0009] On the other hand, the bonding strength between the dielectric layer 140 and the core layer 10 is also poor, and delamination is likely to occur at high temperatures during the process. In addition, the metal sheet 15 is too thin to effectively prevent delamination. Figure 1C-1 The edge C shown may cause moisture to penetrate and damage the electrical function or cause poor reliability.

[0010] Therefore, how to avoid the various defects of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0011] In view of the various defects of the above-mentioned prior art, the present invention provides a packaging substrate, including: a core layer, which is defined with a wiring area and a peripheral area surrounding the wiring area; a plurality of conductive pillars, which are formed in the wiring area of ​​the core layer and connect the opposite sides of the core layer; a wiring layer, which is formed on the opposite sides of the core layer and electrically connects the plurality of conductive pillars; a circuit structure, which is formed on the wiring area and the peripheral area of ​​at least one side of the core layer and electrically connects the wiring layer; and a supporting structure, which is formed in the core layer and in the circuit structure and is arranged corresponding to the peripheral area.

[0012] The present invention also provides a method for manufacturing a packaging substrate, including: providing a core layer defining a wiring area and a peripheral area surrounding the wiring area; forming a plurality of conductive pillars in the wiring area of ​​the core layer and connecting the opposite sides of the core layer, and forming a wiring layer on the opposite sides of the core layer and electrically connecting the plurality of conductive pillars; forming a circuit structure on the wiring area and the peripheral area of ​​at least one side of the core layer, and electrically connecting the circuit structure to the wiring layer; and forming a supporting structure in the core layer and the circuit structure, and configuring the supporting structure to correspond to the peripheral area.

[0013] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the circuit structure is formed on two opposite sides of the core layer, so that the packaging substrate is symmetrical.

[0014] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the circuit structure is only formed on one side of the core layer, so that the packaging substrate is asymmetric.

[0015] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the support structure is not electrically connected to the circuit structure.

[0016] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the support structure includes at least one support column formed in the core layer and at least one support block formed in the circuit structure. For example, the support block is connected to the support column, so that the support structure is stacked. Alternatively, the support block is not connected to the support column, so that the support structure is fault-type. Further, the support block can be rivet-shaped, grid-shaped or frame-shaped.

[0017] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, the support structure may include a plurality of support blocks, and the support structure further includes a connection pad for overlapping the upper and lower adjacent support blocks.

[0018] In a specific embodiment of the aforementioned packaging substrate and the manufacturing method thereof, when the support structure is in a stacked type, a connection pad may be formed between the support block and the support column to connect the support block and the support column.

[0019] In a specific embodiment of the aforementioned packaging substrate and its manufacturing method, the material of the core layer is organic material, glass, ceramic, silicon carbide (SiC), AlO2 or a composite material with a modulus of 50 to 100 GPa.

[0020] As can be seen from the above, in the packaging substrate and the manufacturing method thereof of the present invention, the support structure is mainly formed in the core layer and the circuit structure and is designed to correspond to the peripheral area to enhance the adhesion between the dielectric layers and between the dielectric layer and the core layer. Therefore, compared with the prior art, when delamination occurs between the dielectric layers (or between the dielectric layer and the core layer) at high temperature during the process, the support structure (especially the support block) can effectively suppress the occurrence of delamination to avoid moisture infiltration and damage to electrical functions or poor reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1C It is a cross-sectional schematic diagram of a conventional method for manufacturing a packaging substrate.

[0022] Figure 1C-1 for Figure 1C A partially enlarged cross-sectional schematic diagram of .

[0023] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing a packaging substrate of the present invention.

[0024] Figure 3A and Figure 3B It is a top view schematic diagram of different specifications of the packaging substrate of the present invention.

[0025] FIG. 4A to FIG. 4C for Figure 2C Schematic cross-sectional views of other different embodiments.

[0026] Figure 5A and Figure 5B for Figure 3A and Figure 3B Schematic top views of other different embodiments.

[0027] Fig. 6A and Figure 6B for Figure 5A and Figure 5B Schematic top views of other different embodiments.

[0028] The reference numerals are as follows: 1,2~6 Package substrate 10,20 Core Layer 100,200 Perforation 11,21 Conductive column 12,22 wiring layers 14,24 Line structure 140,240 Dielectric layer 141,241 Line Layer 142,242 Conductive blind vias 15 Metal Sheet 2a,4a,4b,4c,5a,5b,6a,6b Support structure 201 Groove 23 Support Column 25,45,55,65 support blocks 250,450 Connection pads 3a Strip A. Wiring area B Outer area C Edge D1,D2,R diameters. DETAILED DESCRIPTION

[0029] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0030] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effects and purposes that can be produced by the present invention, should still fall within the scope of the technical contents disclosed in the present invention. At the same time, the terms such as "on", "first", "second", "one", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of their relative relationship should also be regarded as the scope of the implementation of the present invention without substantially changing the technical contents.

[0031] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing a package substrate 2 of the present invention.

[0032] like Figure 2A As shown, a core layer 20 is provided, which defines a wiring area A and a peripheral area B surrounding the wiring area A, and at least one through-hole 200 is formed on the wiring area A of the core layer 20 and at least one through-groove 201 is formed on the peripheral area B of the core layer 20 by laser, machine drilling or other means.

[0033] In this embodiment, the material of the core layer 20 can be organic material, glass, ceramic, silicon carbide (SiC), AlO 2 or a composite material with a high rigidity and a modulus of 50 to 100 GPa.

[0034] like Figure 2B As shown, a wiring layer 22 is formed on opposite sides of the core layer 20 by electroplating and patterning processes, a conductive column 21 electrically connected to the wiring layer 22 is formed in each of the through holes 200, and a supporting column 23 not electrically connected to the wiring layer 22 is formed in each of the grooves 201.

[0035] In this embodiment, the wiring layer 22 , the conductive pillars 21 and the support pillars 23 may be formed by electroplating metal (such as copper) or other methods.

[0036] Furthermore, the plurality of conductive pillars 21 are solid metal pillars, such as copper pillars. Alternatively, in other embodiments, the plurality of conductive pillars 21 may also be hollow copper pillars, which may be filled with a plug material such as an insulating material or a conductive material (not shown) in the hollow part, without any particular limitation.

[0037] like Figure 2C As shown, a circuit structure 24 electrically connected to the wiring layer 22 and a support block 25 stacked and connected to the support column 23 are respectively formed on opposite sides of the core layer 20 to form a symmetrical package substrate 2, and a support structure 2a is formed in the peripheral area B of the package substrate 2. In the subsequent process, a solder mask such as green paint can be formed on the circuit structure 24 (not shown).

[0038] The circuit structure 24 includes at least one dielectric layer 240, a circuit layer 241 formed on the dielectric layer 240, and a plurality of conductive blind vias 242 formed in the dielectric layer 240 and electrically connecting the circuit layer 241 and the wiring layer 22. At the same time, when the circuit layer 241 is formed, a connection pad 250 for connecting the upper and lower adjacent support blocks 25 and a connection pad 250 for connecting the support column 23 and the support block 25 can be formed accordingly.

[0039] In this embodiment, the dielectric layer 240 may include Bismaleimidetriazine (BT), prepreg (PP), ABF film (Ajinomoto build-up film), polybenzoxazole (PBO), polyimide (PI) or other dielectric materials.

[0040] The support block 25 is combined with the dielectric layer 240 but is not electrically connected to the circuit layer 241 and the wiring layer 22 .

[0041] In this embodiment, the manufacturing of the support block 25 is the same as that of the circuit layer 241 and the conductive blind via 242. For example, the support block 25 is in the shape of a rivet, and the diameter D1 of the connection pad 250 as the cap is larger than the diameter D2 of the support block 25 as the nail and the diameter R of the support column 23. It should be understood that the support structure 2a is made of any material suitable for combining the core layer 20 and the dielectric layer 240.

[0042] Furthermore, the end surface of the support structure 2a (or the outer end of the support block 25) is in a circular pad shape, such as Figure 3A or Figure 3B As shown, a plurality of supporting structures 2a are arranged around the peripheral area B of the package substrate 2. For example, the package substrate 2 is a full-page specification including a plurality of strips, such as Figure 3A As shown, the plurality of support structures 2a surround the wiring area A of each of the strips 3a. Alternatively, as Figure 3B As shown, the package substrate 3 is a single substrate specification, such as Figure 3B As shown, the plurality of support structures 2 a surround the wiring area A of the packaging substrate 3 .

[0043] In addition, the supporting structure 2a has many embodiments and can be designed according to the requirements. Figure 4A In the symmetrical package substrate 4 shown, the support block 45 is not connected to the support column 23, so that the support structure 4a is formed in a fault type, but the ends of the support column 23 and the support block 45 can form a connection pad 450 as needed to strengthen the interlayer adhesion. Alternatively, the support structures 4b, 4c are changed according to the shape of the package substrates 5, 6, such as Figure 4B or Figure 4C As shown, the circuit structure 24 and the support blocks 25, 45 are formed only on one side of the core layer 20 to form an asymmetric packaging substrate 5, 6, so that the support structure 4b is an asymmetric stacking type, or the support structure 4c is an asymmetric fault type.

[0044] In addition, the occupied area of ​​the support structure 2a can also be designed according to the needs. Figure 5A The full page size shown or Figure 5B In the single substrate specification shown, the support block 55 may be in the form of a hedge, with its end surface (or the outer end of the support block 55) being rectangular. Fig. 6A The full page size shown or Figure 6B In the single substrate specification shown, the support block 65 forms a frame, and its end surface (or the outer end of the support block 65) is annular.

[0045] It should be understandable that Figure 5A and Figure 5B and Fig. 6A and Figure 6BIn the embodiment, a connection pad (not shown) may be formed between the upper and lower adjacent support blocks 55, 65. A connection pad (not shown) may also be formed between the support blocks 55, 65 and the support column 23. In addition, regardless of the full-page specification or the single-substrate specification, the package substrates 2-6 may be divided into 12 embodiments according to the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b, as shown in Table 1: Table 1: 12 embodiments of support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b

[0046] Therefore, the package substrates 2-6 of the present invention mainly form rivet-shaped, grid-shaped or frame-shaped support blocks 25, 45, 55, 65 in the peripheral area B by the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b to enhance the adhesion between the dielectric layer 240 and the core layer 20, and also enhance the adhesion between the dielectric layers 240 and the dielectric layers 240. Therefore, compared with the prior art, when delamination occurs between the dielectric layers 240 (or between the dielectric layers 240 and the core layer 20) at high temperatures during the process, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b (especially the support blocks 25, 45, 55, 65) can effectively suppress the occurrence of delamination, especially at the edges of the package substrates 2-6, so as to avoid moisture penetration and damage to electrical functions or poor reliability.

[0047] Furthermore, the stacked support structures 2 a and 4 b can simultaneously suppress delamination between the dielectric layer 240 and the core layer 20 and between the dielectric layers 240 , while the faulted support structures 4 a and 4 c are used to suppress delamination between the dielectric layers 240 .

[0048] Furthermore, regardless of whether the packaging substrates 2~6 are of full-page specifications (strip 3a specifications) or single-substrate specifications, the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b can be easily configured on the peripheral area B for easy layout, so that the packaging substrates 2~6 can effectively reduce the occurrence of delamination problems regardless of the distribution area (or quantity) of the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b during the production or reliability testing stage. Therefore, the packaging substrates 2~6 can configure the support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b in areas with high delamination risks as required to avoid delamination problems.

[0049] The present invention also provides a package substrate 2-6, including: a core layer 20, a plurality of conductive pillars 21, a wiring layer 22, a circuit structure 24 and support structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b.

[0050] The core layer 20 is defined as a wiring area A and a peripheral area B surrounding the wiring area A.

[0051] The plurality of conductive pillars 21 are formed in the wiring region A of the core layer 20 and connect two opposite sides of the core layer 20 .

[0052] The wiring layer 22 is formed on the opposite side of the core layer 20 and electrically connects the plurality of conductive pillars 21 .

[0053] The circuit structure 24 is formed on the wiring region A and the peripheral region B on at least one side of the core layer 20 and is electrically connected to the wiring layer 22 .

[0054] The supporting structures 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b are formed in the core layer 20 and the circuit structure 24 and are arranged corresponding to the peripheral area B.

[0055] In one embodiment, the circuit structure 24 is formed on two opposite sides of the core layer 20 , so that the package substrate 2 is symmetrical.

[0056] In one embodiment, the circuit structure 24 is formed on only one side of the core layer 20 , so that the package substrates 4 , 6 are asymmetrical.

[0057] In one embodiment, the support structures 2 a , 4 a , 4 b , 4 c , 5 a , 5 b , 6 a , 6 b are not electrically connected to the circuit structure 24 .

[0058] In a specific embodiment, the support structure 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b includes at least one support column 23 formed in the core layer 20 and at least one support block 25, 45, 55, 65 formed in the circuit structure 24. For example, the support block 25 is connected to the support column 23, so that the support structure 2a, 4b is stacked. Alternatively, the support block 45 is not connected to the support column 23, so that the support structure 4a, 4c is faulted.

[0059] In a specific embodiment, the support structure 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b may include a plurality of support blocks 25, 45, 55, 65, and the support structure 2a, 4a, 4b, 4c, 5a, 5b, 6a, 6b further includes connection pads 250, 450 for overlapping the upper and lower adjacent support blocks 25, 45, 55, 65.

[0060] In a specific embodiment, the connection pad 250 , 450 may be further formed between the support block 25 , 45 , 55 , 65 and the support column 23 to connect the support block 25 , 45 , 55 , 65 and the support column 23 .

[0061] In one embodiment, the support blocks 25, 45 are rivet-shaped, or the support block 55 is grid-shaped, or even the support block 65 is a frame.

[0062] In summary, the packaging substrate and the manufacturing method thereof of the present invention, by means of the design that the support structure is formed in the core layer and the circuit structure and is arranged corresponding to the peripheral area, so as to enhance the adhesion between the dielectric layers and between the dielectric layer and the core layer. Therefore, compared with the prior art, when delamination occurs between the dielectric layers (or between the dielectric layer and the core layer) at a high temperature during the process, the support structure (especially the support block) can effectively suppress the occurrence of delamination to avoid moisture infiltration and damage to electrical functions or poor reliability.

[0063] The above embodiments are used to illustrate the principles and effects of the present invention, but are not used to limit the present invention. Those skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. A packaging substrate, characterized in that: include: A core layer, which is defined with a wiring area and a peripheral area surrounding the wiring area; A plurality of conductive pillars are formed in a wiring region of the core layer and connect two opposite sides of the core layer; a wiring layer formed on opposite sides of the core layer and electrically connecting the plurality of conductive pillars; A circuit structure formed on the wiring area and the peripheral area of ​​at least one side of the core layer and electrically connected to the wiring layer; as well as The support structure is formed in the core layer and the circuit structure and is arranged corresponding to the peripheral area, and the support structure is not electrically connected to the circuit structure.

2. The packaging substrate according to claim 1, wherein: The support structure includes at least one support column formed in the core layer and at least one support block formed in the circuit structure.

3. The packaging substrate according to claim 2, wherein: The support block is connected to the support column so that the support structure is stacked, or the support block is not connected to the support column.

4. The packaging substrate according to claim 3, characterized in that: The support structure includes a plurality of support blocks, and the support structure also includes a connection pad, and the connection pad is used to overlap the upper and lower adjacent support blocks, and when the support structure is in a stacked type, the connection pad connects the support block and the support column.

5. The packaging substrate according to claim 2, wherein: The support block is in the shape of a rivet, a grid or a frame.

6. The packaging substrate according to claim 1, wherein: The core layer is made of organic material, glass, ceramic, silicon carbide, AlO2 or a composite material with a modulus of 50 to 100 GPa.

7. A method for manufacturing a packaging substrate, characterized in that: include: Providing a core layer defining a wiring area and a peripheral area surrounding the wiring area; Forming a plurality of conductive pillars in the wiring region of the core layer and connecting two opposite sides of the core layer, and forming a wiring layer on two opposite sides of the core layer and electrically connecting the plurality of conductive pillars; Forming a circuit structure on the wiring area and the peripheral area of ​​at least one side of the core layer, and electrically connecting the circuit structure to the wiring layer; as well as A support structure is formed in the core layer and the circuit structure, and the support structure is arranged corresponding to the peripheral area, and the support structure is not electrically connected to the circuit structure.

8. The method for manufacturing a packaging substrate according to claim 7, wherein: The support structure includes at least one support column formed in the core layer and at least one support block formed in the circuit structure.

9. The method for manufacturing a packaging substrate according to claim 8, wherein: The support block is connected to the support column so that the support structure is stacked, or the support block is not connected to the support column.

10. The method for manufacturing a packaging substrate according to claim 8, wherein: The support structure includes a plurality of support blocks, and the support structure also includes a connection pad, and the connection pad is used to overlap the upper and lower adjacent support blocks, and when the support structure is in a stacked type, the connection pad connects the support block and the support column.

11. The method for manufacturing a packaging substrate according to claim 8, wherein: The support block is in the shape of a rivet, a grid or a frame.

12. The method for manufacturing a packaging substrate according to claim 7, wherein: The core layer is made of organic material, glass, ceramic, silicon carbide, AlO2 or a composite material with a modulus of 50 to 100 GPa.

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