Network bypass circuit and bypass method based on wired transmission

Abstract

The invention provides a network bypass circuit and method based on wired transmission in the technical field of wired transmission. The network bypass circuit comprises a CPU, a relay control circuit, a relay set, a first network port, a second network port, a first network card and a second network card. The relay group comprises a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay; the first network port, the third relay, the fourth relay and the first network card are sequentially connected in series; the second network port, the fifth relay, the sixth relay and the second network card are sequentially connected in series; after the first relay and the second relay are connected in parallel, one end is connected with the first network port, and the other end is connected with the second network port; the CPU is connected with the relay control circuit, the first network card, the second network card, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay. The network bypass circuit has the advantage that the operation reliability of the network bypass circuit is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of wired transmission, and in particular to a network bypass circuit and a bypass method based on wired transmission. Background Art

[0002] Network bypass (NET BYPASS) is a very common network application requirement in the field of network security technology. Figure 5 As shown, under normal working conditions, network device A and network device B filter and process data streams through the network security device, that is, wired transmission is performed through the normal path of the network security device. Network device A communicates with network device B through network port 1, network card 1, CPU, network card 2, and network port 2 in sequence. When the network security device fails or is abnormal, the fault path (bypass) of network port 1 and network port 2 is turned on for wired transmission to ensure uninterrupted communication between network device A and network device B. For example, the Chinese utility model patent with application number CN201420379794.2 and classification number H04B discloses a fast fault recovery optical communication base station fault automatic bypass device, which can quickly short-circuit (shake off) the device when it is abnormal, and ensure the normal transmission of optical signals through the relay circuit module; the Chinese invention patent with application number CN200880102566.8 and classification number H04B discloses providing a bypass switch to bypass a failed node, which provides a bypass switch to bypass one or more failed network nodes.

[0003] However, any network security device is subject to failure, that is, the fault path is also subject to failure. If both the normal path and the fault path fail at the same time, communication will be interrupted. In special application scenarios such as rail transit, the reliability of the network bypass function is the key point that affects the response of the entire fault system.

[0004] Therefore, how to provide a network bypass circuit and bypass method based on wired transmission to improve the reliability of the operation of the network bypass circuit has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a network bypass circuit and bypass method based on wired transmission, so as to improve the reliability of the operation of the network bypass circuit.

[0006] In a first aspect, the present invention provides a network bypass circuit based on wired transmission, comprising a CPU, a relay control circuit, a relay group, a first network port, a second network port, a first network card and a second network card; the relay group comprises a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay; The first network port, the third relay, the fourth relay and the first network card are connected in series in sequence; the second network port, the fifth relay, the sixth relay and the second network card are connected in series in sequence; after the first relay and the second relay are connected in parallel, one end is connected to the first network port and the other end is connected to the second network port to form a wired fault path; The CPU is connected to the relay control circuit, the first network card, the second network card, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay respectively; the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port form a normal wired path; The first relay and the second relay are both in a normally closed state when power is off, and the third relay, the fourth relay, the fifth relay and the sixth relay are all in a normally open state when power is off; The relay control circuit includes a CPLD, a MOS tube Q1, a fuse F1, a power module, a transformer T1, a diode D1, a capacitor C1, a voltage stabilizing chip U1, an overvoltage chip U2, an overvoltage optocoupler OC1, an undervoltage optocoupler OC2, a wiring terminal J1 and a wiring terminal J2; The gate of the MOS tube Q1 is connected to the CPLD, the source is connected to the negative electrode of the power module and grounded, and the drain is connected to the pin 2 of the primary side of the transformer T1; one end of the fuse F1 is connected to the positive electrode of the power module, and the other end is connected to the pin 1 of the primary side of the transformer T1; the input end of the overvoltage optocoupler OC1 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the input end of the undervoltage optocoupler OC2 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the CPLD is connected to the CPU; The input end of the diode D1 is connected to the pin 4 of the secondary side of the transformer T1, and the output end is connected to the voltage regulator chip U1 and one end of the capacitor C1; the other end of the capacitor C1 is connected to the pin 3 of the secondary side of the transformer T1, the voltage regulator chip U1 and the terminal J2 and is grounded; the voltage regulator chip U1 is connected to the overvoltage chip U2 and the terminal J1; The wiring terminal J1 and the wiring terminal J2 are connected to the control end of the relay group.

[0007] Furthermore, the MOS tube Q1 is an NMOS tube.

[0008] Furthermore, the diode D1 is a Schottky diode.

[0009] Further, the turns ratio of the primary side of the transformer T1 is smaller than the turns ratio of the secondary side; The supply voltage of the power module is lower than the working voltage of the relay group.

[0010] Furthermore, the CPLD is provided with a register group including an enable register, a pulse width register, a timeout register and a fault register.

[0011] Furthermore, the CPLD is connected to the CPU via a GPIO bus and an I2C bus.

[0012] Furthermore, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay are all electromagnetic relays.

[0013] In a second aspect, the present invention provides a bypass method for a network bypass circuit based on wired transmission, comprising the following steps: Step S1, the CPU performs a power-on operation on the relay group through the relay control circuit to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay; Step S2: after the relay group is powered on, the links of the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port are turned on, so that the first network device and the second network device connected to the network bypass circuit communicate normally; Step S3: When the CPU detects a network fault or a relay control circuit fault, the relay group is powered off to close the first relay and the second relay, and to disconnect the third relay, the fourth relay, the fifth relay, and the sixth relay; Step S4: After the relay group is powered off, a link between the first network port, the first relay, and the second network port is connected, or a link between the first network port, the second relay, and the second network port is connected.

[0014] Furthermore, the step S1 is specifically as follows: The pulse width register of the CPLD stores the pulse width range in advance, and the timeout register stores the timeout period in advance; the CPLD dynamically adjusts the pulse width range stored in the pulse width register with a period of 2 seconds based on a preset transformation rule; The CPU controls the enable register of the CPLD to be set, reads the pulse width range from the pulse width register, and the CPU sends a bypass closing pulse control signal to the CPLD based on the pulse width range; When the CPLD determines that the enable register is set, the bypass closing pulse control signal is checked through the pulse width range and the timeout period. If the check passes, a PWM pulse is sent to the MOS tube Q1 to turn on the MOS tube Q1. If the check fails, the PWM pulse is turned off. The power module supplies power to the relay group through the fuse F1, transformer T1, diode D1 and voltage regulator chip U1 in sequence, and then performs a power-on operation on the relay group to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay.

[0015] Furthermore, the step S3 is specifically as follows: When the CPU detects a network failure, it powers off the relay group through the relay control circuit; The CPLD of the relay control circuit performs overvoltage detection and undervoltage detection through the voltage stabilizing chip U1 and the overvoltage chip U2, generates overvoltage and undervoltage detection results and stores them in the fault register; when the enable register is set, and the overvoltage and undervoltage detection results stored in the fault register are overvoltage or undervoltage, stops sending PWM pulses to the MOS tube Q1 to disconnect the MOS tube Q1, and then performs a power-off operation on the relay group; When the transformer T1 is short-circuited, the relay group will be powered off because the power supply voltage of the power module is lower than the working voltage of the relay group; when the transformer T1 is open-circuited, the relay group will be powered off; When the MOS tube Q1 is open-circuited, the relay group will be powered off; when the MOS tube Q1 is short-circuited, the fuse F1 provides overcurrent protection, the relay group has no voltage, and the relay group is powered off; When the power module, diode D1 or voltage regulator chip U1 fails, the relay group will be powered off; When the relay group performs a power-off operation, the first relay and the second relay are closed, and the third relay, the fourth relay, the fifth relay, and the sixth relay are opened.

[0016] The advantages of the present invention are: 1. After the first relay and the second relay are connected in parallel, one end is connected to the first network port, and the other end is connected to the second network port; the first network port, the third relay, the fourth relay and the first network card are connected in series in sequence; the second network port, the fifth relay, the sixth relay and the second network card are connected in series in sequence; and the first relay and the second relay are both in a normally closed state when the power is off, and the third relay, the fourth relay, the fifth relay and the sixth relay are all in a normally open state when the power is off, that is, the normal path is in a conducting state in the power-on state, and the fault path is in a disconnected state; the normal path is in a disconnected state in the power-off state, and the fault path is in a conducting state, and each path is switched on and off by two relays to improve safety redundancy; when the network bypass circuit fails, even if the first relay or the second relay fails, the first network port and the second network port can be interconnected; when the relay group loses power, even if any one of the third relay and the fourth relay fails, or any one of the fifth relay and the sixth relay fails, the network port and the network card can be disconnected, thereby greatly improving the reliability of the network bypass circuit operation.

[0017] 2. By setting up a relay control circuit including CPLD, MOS tube Q1, fuse F1, power module, transformer T1, diode D1, capacitor C1, voltage regulator chip U1, overvoltage chip U2, overvoltage optocoupler OC1, undervoltage optocoupler OC2, terminal J1 and terminal J2; the primary side of transformer T1 is sequentially connected through fuse F1, power module, and MOS tube Q1 to form a loop; the secondary side of transformer T1 is sequentially connected through diode D1 and capacitor C1 to form a loop; the voltage regulator chip U1 is connected in parallel to both ends of capacitor C1; the CPLD is respectively connected to MOS tube Q1 , overvoltage optocoupler OC1, undervoltage optocoupler OC2, and CPU; one end of the overvoltage chip U2 is connected to the voltage regulator chip U1, and the other end is connected to the overvoltage optocoupler OC1 and the undervoltage optocoupler OC2; when any component of the MOS tube Q1, transformer T1, diode D1 or voltage regulator chip U1 fails, or the CPLD detects overvoltage / undervoltage, the power supply circuit of the power module will be cut off, and then the relay group will be powered off to perform path switching (normal path switches faulty path), further improving the reliability of the network bypass circuit operation.

[0018] 3. By setting the supply voltage of the power module to be lower than the working voltage of the relay group, the turns ratio of the primary side of the transformer T1 is smaller than the turns ratio of the secondary side, that is, the power module alone cannot drive the relay group to work, and the power module must drive the relay group to work through the voltage boost of the transformer T1. When the transformer T1 is short-circuited, since the supply voltage of the power module is lower than the working voltage of the relay group, the relay group will be powered off to perform path switching, thereby further improving the reliability of the network bypass circuit operation.

[0019] 4. By setting the voltage regulator chip U1, overvoltage chip U2, overvoltage optocoupler OC1 and undervoltage optocoupler OC2 to perform real-time monitoring of overvoltage and undervoltage, the user can grasp the operating status of the network bypass circuit in real time, further improving the reliability of the network bypass circuit operation.

[0020] 5. The pulse width range is stored by setting the pulse width register, and the pulse width range is dynamically adjusted based on the preset transformation law and period. The CPU sends a bypass closing pulse control signal to the CPLD based on the read pulse width range. When the CPLD determines that the pulse width of the bypass closing pulse control signal does not meet the pulse width range, the enable register is not set; that is, the pulse width range is automatically refreshed every 2 seconds, and the CPU needs to send the bypass closing pulse control signal within 2 seconds, otherwise it will not meet the requirements; through this design, it can effectively identify the situation where the CPU main program runs away, while the CPU timing interrupt program is still running, and the bypass closing pulse control signal with a fixed width is output, which further improves the reliability of the network bypass circuit operation.

[0021] 6. By setting a register group including an enable register, a pulse width register, a timeout register and a fault register, the PWM pulse is output only when the enable register is set and the pulse width range stored in the pulse width register passes the bypass shutdown pulse control signal verification; when the bypass shutdown pulse control signal does not meet the required duration and exceeds the timeout period stored in the timeout register, the PWM pulse is turned off; when the over-voltage or under-voltage detection result stored in the fault register is overvoltage or undervoltage, the PWM pulse is turned off, that is, the PWM pulse is strictly controlled by the register group, which further improves the reliability of the network bypass circuit operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0023] Figure 1 The invention discloses a circuit principle block diagram of a network bypass circuit based on wired transmission.

[0024] Figure 2 It is a circuit principle block diagram of the relay group of the present invention.

[0025] Figure 3 1 is a circuit diagram of a relay control circuit of the present invention.

[0026] Figure 4 The invention discloses a flow chart of a bypass method of a network bypass circuit based on wired transmission.

[0027] Figure 5 It is the circuit principle block diagram of the traditional network bypass circuit. DETAILED DESCRIPTION

[0028] The technical solution in the embodiment of the present application has the following overall idea: by setting the normally open and normally closed states of the relay group, when the relay group loses power, the first network port and the second network port can remain interconnected, and each path is switched on and off by two relays to improve safety redundancy; by setting the circuit structure of the relay control circuit, when any component fails, or when the CPLD detects overvoltage / undervoltage, the relay group will be powered off; by setting the boost circuit structure, when the transformer T1 is short-circuited, the power module cannot support the work of the relay group, so that the relay group is powered off; by real-time monitoring of the overvoltage / undervoltage state, the user can grasp the operating state of the network bypass circuit in real time; by setting a dynamic pulse width range, the situation in which the CPU main program runs away while the CPU timing interrupt program is still running can be effectively identified; by setting the register group to strictly control the PWM pulse, thereby improving the reliability of the operation of the network bypass circuit.

[0029] Please refer to Figures 1 to 5 As shown, a preferred embodiment of a network bypass circuit based on wired transmission of the present invention comprises a CPU, a relay control circuit, a relay group, a first network port, a second network port, a first network card and a second network card; the relay group comprises a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay; the relay control circuit is used to ensure that when any component fails, the relay group is in a power-off state to achieve reliable operation of the entire circuit; The first network port, the third relay, the fourth relay and the first network card are connected in series in sequence; the second network port, the fifth relay, the sixth relay and the second network card are connected in series in sequence; after the first relay is connected in parallel with the second relay, one end is connected to the first network port, and the other end is connected to the second network port to form a wired fault path; that is, the third relay and the fourth relay are a group of relays; the fifth relay and the sixth relay are a group of relays; the first relay and the second relay are a group of relays; when any one of the groups of relays fails, it will not affect the switching of the network path to improve safety redundancy; in actual application scenarios, the 1000M network has four pairs of signals, that is, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay are each composed of four sub-relays to realize the connection of four pairs of signals.

[0030] The CPU is connected to the relay control circuit, the first network card, the second network card, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay respectively; the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port form a normal wired path; The first relay and the second relay are both in a normally closed state when the power is off, and the third relay, the fourth relay, the fifth relay and the sixth relay are all in a normally open state when the power is off; that is, in the power-on state, the normal path is connected and the fault path is disconnected; in the power-off state, the fault path is connected and the normal path is disconnected, and the network bypass function is performed; The relay control circuit includes a CPLD, a MOS tube Q1, a fuse F1, a power module, a transformer T1, a diode D1, a capacitor C1, a voltage regulator chip (LDO chip) U1, an overvoltage chip U2, an overvoltage optocoupler OC1, an undervoltage optocoupler OC2, a wiring terminal J1 and a wiring terminal J2; the voltage regulator chip U1 is used for undervoltage detection; the overvoltage chip U2 is used for overvoltage detection; the overvoltage optocoupler OC1 is used to transmit overvoltage signals; the undervoltage optocoupler OC2 is used to transmit undervoltage signals; The gate of the MOS tube Q1 is connected to the CPLD, the source is connected to the negative electrode of the power module and grounded, and the drain is connected to the pin 2 of the primary side of the transformer T1; one end of the fuse F1 is connected to the positive electrode of the power module, and the other end is connected to the pin 1 of the primary side of the transformer T1; the input end of the overvoltage optocoupler OC1 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the input end of the undervoltage optocoupler OC2 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the CPLD is connected to the CPU; The input end of the diode D1 is connected to the pin 4 of the secondary side of the transformer T1, and the output end is connected to the voltage regulator chip U1 and one end of the capacitor C1; the other end of the capacitor C1 is connected to the pin 3 of the secondary side of the transformer T1, the voltage regulator chip U1 and the terminal J2 and is grounded; the voltage regulator chip U1 is connected to the overvoltage chip U2 and the terminal J1; The wiring terminal J1 and the wiring terminal J2 are connected to the control end of the relay group.

[0031] The MOS tube Q1 is an NMOS tube.

[0032] The diode D1 is a Schottky diode.

[0033] The turns ratio of the primary side of the transformer T1 is smaller than the turns ratio of the secondary side; The power supply voltage of the power module is lower than the working voltage of the relay group. That is, the power module alone cannot drive the relay group to work, and the power module must be boosted by the transformer T1 to drive the relay group to work. When the transformer T1 is short-circuited, since the power supply voltage of the power module is lower than the working voltage of the relay group, the relay group will be powered off to perform path switching.

[0034] The CPLD is provided with a register group including an enable register, a pulse width register, a timeout register and a fault register, which are used to control the output or shutdown of the PWM pulse.

[0035] The CPLD is connected to the CPU via a GPIO bus and an I2C bus.

[0036] The first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay are all electromagnetic relays, which have the advantages of high conduction bandwidth, strong anti-interference ability and small size.

[0037] A preferred embodiment of a bypass method of a network bypass circuit based on wired transmission of the present invention comprises the following steps: Step S1, the CPU performs a power-on operation on the relay group through the relay control circuit to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay; Step S2: after the relay group is powered on, the link (normal path) of the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port is turned on, so that the first network device connected to the network bypass circuit and the second network device communicate normally; Step S3: When the CPU detects a network fault or a relay control circuit fault, the relay group is powered off to close the first relay and the second relay, and to disconnect the third relay, the fourth relay, the fifth relay, and the sixth relay; Step S4: after the relay group is powered off, the link (fault path) of the first network port, the first relay and the second network port is turned on, or the link (fault path) of the first network port, the second relay and the second network port is turned on.

[0038] The step S1 is specifically as follows: The pulse width register of the CPLD stores the pulse width range in advance, and the timeout register stores the timeout period in advance; the CPLD dynamically adjusts the pulse width range stored in the pulse width register with a period of 2 seconds based on a preset transformation rule; in specific implementation, the pulse width range is dynamically refreshed only when the enable register is set; the CPU needs to access the pulse width register within 2 seconds to obtain the effective pulse width range, so as to adjust the pulse width of the bypass closing pulse control signal to meet the requirements.

[0039] The CPU controls the enable register of the CPLD to be set, reads the pulse width range from the pulse width register, and the CPU sends a bypass closing pulse control signal to the CPLD based on the pulse width range; When the CPLD determines that the enable register is set, the bypass closing pulse control signal is checked through the pulse width range and the timeout period. If the check passes, a PWM pulse is sent to the MOS tube Q1 to turn on the MOS tube Q1. If the check fails, the PWM pulse is turned off. That is, the pulse width of the bypass closing pulse control signal must meet the requirements of the pulse width range before the PWM pulse is output. When the bypass closing pulse control signal does not meet the requirements for a period of time exceeding the timeout period, the PWM pulse is stopped from being output. The power module supplies power to the relay group through the fuse F1, transformer T1, diode D1 and voltage regulator chip U1 in sequence, and then performs a power-on operation on the relay group to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay.

[0040] The step S3 is specifically as follows: When the CPU detects a network failure, it powers off the relay group through the relay control circuit; The CPLD of the relay control circuit performs overvoltage detection and undervoltage detection through the voltage stabilizing chip U1 and the overvoltage chip U2, generates overvoltage and undervoltage detection results and stores them in the fault register; when the enable register is set, and the overvoltage and undervoltage detection results stored in the fault register are overvoltage or undervoltage, stops sending PWM pulses to the MOS tube Q1 to disconnect the MOS tube Q1, and then performs a power-off operation on the relay group; When the transformer T1 is short-circuited, the relay group will be powered off because the power supply voltage of the power module is lower than the working voltage of the relay group; when the transformer T1 is open-circuited, the relay group will be powered off; When the MOS tube Q1 is open-circuited, the relay group will be powered off; when the MOS tube Q1 is short-circuited, the fuse F1 provides overcurrent protection, the relay group has no voltage, and the relay group is powered off; When the power module, diode D1 or voltage regulator chip U1 fails, the relay group will be powered off; When the relay group performs a power-off operation, the first relay and the second relay are closed, and the third relay, the fourth relay, the fifth relay, and the sixth relay are opened.

[0041] During overvoltage detection and undervoltage detection, the overvoltage optocoupler OC1 outputs a high level to indicate that there is no overvoltage, and a low level to indicate overvoltage; the undervoltage optocoupler OC2 outputs a high level to indicate undervoltage, and a low level to indicate that there is no undervoltage. Therefore, when there is no voltage on the load (relay group), the overvoltage optocoupler OC1 is disconnected and outputs a high level, indicating that there is no overvoltage; the undervoltage optocoupler is disconnected and outputs a high level, indicating that there is undervoltage. When the load is working normally, the undervoltage optocoupler OC2 is turned on and outputs a low level to inform the CPLD that there is no undervoltage.

[0042] If the transformer T1 turns are short-circuited, the voltage regulator chip U1 input and output are short-circuited, and the voltage rises, the overvoltage optocoupler OC1 will output a low level, thus turning off the PWM pulse. If other faults cause undervoltage, the undervoltage optocoupler OC2 will output a high level, thus turning off the PWM pulse.

[0043] In summary, the advantages of the present invention are: 1. After the first relay and the second relay are connected in parallel, one end is connected to the first network port, and the other end is connected to the second network port; the first network port, the third relay, the fourth relay and the first network card are connected in series in sequence; the second network port, the fifth relay, the sixth relay and the second network card are connected in series in sequence; and the first relay and the second relay are both in a normally closed state when the power is off, and the third relay, the fourth relay, the fifth relay and the sixth relay are all in a normally open state when the power is off, that is, the normal path is in a conducting state in the power-on state, and the fault path is in a disconnected state; the normal path is in a disconnected state in the power-off state, and the fault path is in a conducting state, and each path is switched on and off by two relays to improve safety redundancy; when the network bypass circuit fails, even if the first relay or the second relay fails, the first network port and the second network port can be interconnected; when the relay group loses power, even if any one of the third relay and the fourth relay fails, or any one of the fifth relay and the sixth relay fails, the network port and the network card can be disconnected, thereby greatly improving the reliability of the network bypass circuit operation.

[0044] 2. By setting up a relay control circuit including CPLD, MOS tube Q1, fuse F1, power module, transformer T1, diode D1, capacitor C1, voltage regulator chip U1, overvoltage chip U2, overvoltage optocoupler OC1, undervoltage optocoupler OC2, terminal J1 and terminal J2; the primary side of transformer T1 is sequentially connected through fuse F1, power module, and MOS tube Q1 to form a loop; the secondary side of transformer T1 is sequentially connected through diode D1 and capacitor C1 to form a loop; the voltage regulator chip U1 is connected in parallel to both ends of capacitor C1; the CPLD is respectively connected to MOS tube Q1 , overvoltage optocoupler OC1, undervoltage optocoupler OC2, and CPU; one end of the overvoltage chip U2 is connected to the voltage regulator chip U1, and the other end is connected to the overvoltage optocoupler OC1 and the undervoltage optocoupler OC2; when any component of the MOS tube Q1, transformer T1, diode D1 or voltage regulator chip U1 fails, or the CPLD detects overvoltage / undervoltage, the power supply circuit of the power module will be cut off, and then the relay group will be powered off to perform path switching (normal path switches faulty path), further improving the reliability of the network bypass circuit operation.

[0045] 3. By setting the supply voltage of the power module to be lower than the working voltage of the relay group, the turns ratio of the primary side of the transformer T1 is smaller than the turns ratio of the secondary side, that is, the power module alone cannot drive the relay group to work, and the power module must drive the relay group to work through the voltage boost of the transformer T1. When the transformer T1 is short-circuited, since the supply voltage of the power module is lower than the working voltage of the relay group, the relay group will be powered off to perform path switching, thereby further improving the reliability of the network bypass circuit operation.

[0046] 4. By setting the voltage regulator chip U1, overvoltage chip U2, overvoltage optocoupler OC1 and undervoltage optocoupler OC2 to perform real-time monitoring of overvoltage and undervoltage, the user can grasp the operating status of the network bypass circuit in real time, further improving the reliability of the network bypass circuit operation.

[0047] 5. The pulse width range is stored by setting the pulse width register, and the pulse width range is dynamically adjusted based on the preset transformation law and period. The CPU sends a bypass closing pulse control signal to the CPLD based on the read pulse width range. When the CPLD determines that the pulse width of the bypass closing pulse control signal does not meet the pulse width range, the enable register is not set; that is, the pulse width range is automatically refreshed every 2 seconds, and the CPU needs to send the bypass closing pulse control signal within 2 seconds, otherwise it will not meet the requirements; through this design, it can effectively identify the situation where the CPU main program runs away, while the CPU timing interrupt program is still running, and the bypass closing pulse control signal with a fixed width is output, which further improves the reliability of the network bypass circuit operation.

[0048] 6. By setting a register group including an enable register, a pulse width register, a timeout register and a fault register, the PWM pulse is output only when the enable register is set and the pulse width range stored in the pulse width register passes the bypass shutdown pulse control signal verification; when the bypass shutdown pulse control signal does not meet the required duration and exceeds the timeout period stored in the timeout register, the PWM pulse is turned off; when the over-voltage or under-voltage detection result stored in the fault register is overvoltage or undervoltage, the PWM pulse is turned off, that is, the PWM pulse is strictly controlled by the register group, which further improves the reliability of the network bypass circuit operation.

[0049] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A network bypass circuit based on wired transmission, characterized in that: It includes a CPU, a relay control circuit, a relay group, a first network port, a second network port, a first network card and a second network card; the relay group includes a first relay, a second relay, a third relay, a fourth relay, a fifth relay and a sixth relay; The first network port, the third relay, the fourth relay and the first network card are connected in series in sequence; the second network port, the fifth relay, the sixth relay and the second network card are connected in series in sequence; after the first relay and the second relay are connected in parallel, one end is connected to the first network port and the other end is connected to the second network port to form a wired fault path; The CPU is connected to the relay control circuit, the first network card, the second network card, the first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay respectively; the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port form a normal wired path; The first relay and the second relay are both in a normally closed state when power is off, and the third relay, the fourth relay, the fifth relay and the sixth relay are all in a normally open state when power is off; The relay control circuit includes a CPLD, a MOS tube Q1, a fuse F1, a power module, a transformer T1, a diode D1, a capacitor C1, a voltage stabilizing chip U1, an overvoltage chip U2, an overvoltage optocoupler OC1, an undervoltage optocoupler OC2, a wiring terminal J1 and a wiring terminal J2; The gate of the MOS tube Q1 is connected to the CPLD, the source is connected to the negative electrode of the power module and grounded, and the drain is connected to the pin 2 of the primary side of the transformer T1; one end of the fuse F1 is connected to the positive electrode of the power module, and the other end is connected to the pin 1 of the primary side of the transformer T1; the input end of the overvoltage optocoupler OC1 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the input end of the undervoltage optocoupler OC2 is connected to the overvoltage chip U2, and the output end is connected to the CPLD; the CPLD is connected to the CPU; The input end of the diode D1 is connected to the pin 4 of the secondary side of the transformer T1, and the output end is connected to the voltage regulator chip U1 and one end of the capacitor C1; the other end of the capacitor C1 is connected to the pin 3 of the secondary side of the transformer T1, the voltage regulator chip U1 and the terminal J2 and is grounded; the voltage regulator chip U1 is connected to the overvoltage chip U2 and the terminal J1; The wiring terminal J1 and the wiring terminal J2 are connected to the control end of the relay group.

2. A network bypass circuit based on wired transmission as claimed in claim 1, characterized in that: The MOS tube Q1 is an NMOS tube.

3. A network bypass circuit based on wired transmission as claimed in claim 1, characterized in that: The diode D1 is a Schottky diode.

4. A network bypass circuit based on wired transmission as claimed in claim 1, characterized in that: The turns ratio of the primary side of the transformer T1 is smaller than the turns ratio of the secondary side; The supply voltage of the power module is lower than the working voltage of the relay group.

5. The network bypass circuit based on wired transmission according to claim 1, characterized in that: The CPLD is provided with a register group including an enable register, a pulse width register, a timeout register and a fault register.

6. A network bypass circuit based on wired transmission as claimed in claim 1, characterized in that: The CPLD is connected to the CPU via a GPIO bus and an I2C bus.

7. A network bypass circuit based on wired transmission as claimed in claim 1, characterized in that: The first relay, the second relay, the third relay, the fourth relay, the fifth relay and the sixth relay are all electromagnetic relays.

8. A bypass method for a network bypass circuit based on wired transmission, characterized in that: The method requires using the network bypass circuit according to any one of claims 1 to 7, comprising the following steps: Step S1, the CPU performs a power-on operation on the relay group through the relay control circuit to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay; Step S2: after the relay group is powered on, the links of the first network port, the third relay, the fourth relay, the first network card, the CPU, the second network card, the sixth relay, the fifth relay and the second network port are turned on, so that the first network device and the second network device connected to the network bypass circuit communicate normally; Step S3: When the CPU detects a network fault or a relay control circuit fault, the relay group is powered off to close the first relay and the second relay, and to disconnect the third relay, the fourth relay, the fifth relay, and the sixth relay; Step S4: After the relay group is powered off, a link between the first network port, the first relay, and the second network port is connected, or a link between the first network port, the second relay, and the second network port is connected.

9. A bypass method for a network bypass circuit based on wired transmission as claimed in claim 8, characterized in that: The step S1 is specifically as follows: The pulse width register of the CPLD stores the pulse width range in advance, and the timeout register stores the timeout period in advance; the CPLD dynamically adjusts the pulse width range stored in the pulse width register with a period of 2 seconds based on a preset transformation rule; The CPU controls the enable register of the CPLD to be set, reads the pulse width range from the pulse width register, and the CPU sends a bypass closing pulse control signal to the CPLD based on the pulse width range; When the CPLD determines that the enable register is set, the bypass closing pulse control signal is checked through the pulse width range and the timeout period. If the check passes, a PWM pulse is sent to the MOS tube Q1 to turn on the MOS tube Q1. If the check fails, the PWM pulse is turned off. The power module supplies power to the relay group through the fuse F1, transformer T1, diode D1 and voltage regulator chip U1 in sequence, and then performs a power-on operation on the relay group to disconnect the first relay and the second relay, and close the third relay, the fourth relay, the fifth relay and the sixth relay.

10. The bypass method of a network bypass circuit based on wired transmission according to claim 8, characterized in that: The step S3 is specifically as follows: When the CPU detects a network failure, it powers off the relay group through the relay control circuit; The CPLD of the relay control circuit performs overvoltage detection and undervoltage detection through the voltage stabilizing chip U1 and the overvoltage chip U2, generates overvoltage and undervoltage detection results and stores them in the fault register; when the enable register is set, and the overvoltage and undervoltage detection results stored in the fault register are overvoltage or undervoltage, stops sending PWM pulses to the MOS tube Q1 to disconnect the MOS tube Q1, and then performs a power-off operation on the relay group; When the transformer T1 is short-circuited, the relay group will be powered off because the power supply voltage of the power module is lower than the working voltage of the relay group; when the transformer T1 is open-circuited, the relay group will be powered off; When the MOS tube Q1 is open-circuited, the relay group will be powered off; when the MOS tube Q1 is short-circuited, the fuse F1 provides overcurrent protection, the relay group has no voltage, and the relay group is powered off; When the power module, diode D1 or voltage regulator chip U1 fails, the relay group will be powered off; When the relay group performs a power-off operation, the first relay and the second relay are closed, and the third relay, the fourth relay, the fifth relay, and the sixth relay are opened.

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