Reinforcement device for single event effect

Abstract

The invention relates to a reinforcing device for a single event effect, which is characterized in that a corresponding well is inserted into a central region of a source electrode of a transistor device on the layout design of an integrated circuit, the well is seamlessly connected with the source electrode, and the pulse width of SET (Single Event Transistor) of an NMOS (N-channel Metal Oxide Semiconductor) tube and the pulse width of SET of a PMOS (P-channel Metal Oxide Semiconductor) tube are inhibited by enhancing the controllability of well point positions; therefore, the structure layout of the source-level center insertion well technology is adopted on the integrated circuit layout, so that the WSET of the PMOS transistor and the WSET of the NMOS transistor in different PVT working environments are remarkably reduced: when the linear energy transfer (LET) is 37 mev.cm < 2 > / mg, compared with an unreinforced layout, the WSET of the PMOS transistor can be reduced by about 80%, and the WSET of the NMOS transistor is reduced by about 50%.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuit design and relates to a reinforcement device for single particle effects. Background Art

[0002] With the rapid development of aerospace technology, SET (single-particle transient) in integrated circuits has become one of the key threats to system reliability, and the efficiency of reinforcement against single-particle effects depends largely on the randomness of the impact position when ions are injected and the changes in process-voltage-temperature (PVT). At advanced technology nodes, the reliability problems caused by SET in the field of space and avionics are particularly prominent. SET caused by high-energy particles may cause voltage disturbances or transient current latching in combinational logic, which further leads to soft error responses in CMOS (complementary metal oxide semiconductor) integrated circuit design. As the size of transistors decreases and the node capacitance decreases, this transient phenomenon becomes more obvious.

[0003] The reinforcement technology for SET is basically to strengthen the device structure, layout reinforcement, and layout optimization. When heavy particles hit the sensitive area of ​​the transistor, the parasitic transient current generated may cause glitches or signal flips, so most reinforcement technologies start from this. However, traditional reinforcement technology still has the technical problem of being difficult to effectively suppress the SET effect under different PVT working environments. Summary of the invention

[0004] In view of the problems existing in the above-mentioned conventional technologies, the present invention proposes a reinforcement device for single particle effect, which can effectively suppress the SET effect under different PVT working environments.

[0005] In order to achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: A reinforcement device for single particle effect is provided, including a target transistor in an integrated circuit layout, wherein a well is inserted into the central region of the source of the target transistor; wherein the target transistor includes a PMOS tube and an NMOS tube, wherein the N well is inserted into the central region of the source of the PMOS tube, and the P well is inserted into the central region of the source of the NMOS tube.

[0006] One of the above technical solutions has the following advantages and beneficial effects: The above-mentioned reinforced device for single-particle effect, by inserting a corresponding well in the central region of the source of the transistor device in the integrated circuit layout design and making the well and the source seamlessly connected, suppresses the pulse width of the SET of the NMOS tube and the PMOS tube by enhancing the controllability of the well point position. In this way, the structure layout of the source-level central well insertion technology is adopted in the integrated circuit layout, so that the PMOS tube and the NMOS tube are W under different PVT working environments. SET The W of the PMOS tube is significantly reduced when the linear energy transfer (LET) is 37mev·cm2 / mg compared with the unreinforced layout. SET It can reduce the W of NMOS tube by about 80%. SET The reduction is about 50%. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0008] Figure 1 A schematic diagram of implementing a source-level central insertion well technology used in a hardened device for single event effects in one embodiment; Figure 2 The substrate embedded N is used in a reinforced device for single event effects in one embodiment. WELL Schematic diagram of the technology implementation. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and Examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0010] It should be noted that the reference to "embodiment" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase at various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be appreciated by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in the specification and appended claims of the present invention refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0011] The following will describe the implementation of the present invention in detail with reference to the accompanying drawings in the embodiment diagram of the present invention.

[0012] With the development of aerospace technology, spacecraft have put forward higher performance requirements and radiation resistance requirements for their core components and circuits. At more advanced technology nodes, with the continuous reduction of process size and operating voltage, the circuit's resistance to single particle effect and total dose effect is also facing challenges. What is more serious is that the mutual influence between the two is enhanced, and new radiation effect mechanisms need to be broken through. Therefore, based on the development trend of CMOS integrated circuits and the current status of research on radiation-resistant integrated circuits at the nanoscale, aiming at the design needs of GHz-level high-frequency integrated circuits, this paper studies the reinforcement methods for single particle effects.

[0013] In order to enable the chip to work under all possible conditions, the important factor of process-voltage-temperature (PVT) variation needs to be considered in this specification. Due to changes in the manufacturing process, such as doping distribution, oxide thickness and channel length, parameters such as the threshold voltage (Vth) of the transistor will deviate from the expected value. The Vth of the transistor plays a vital role in the power consumption of the circuit and should be given more attention in the SET evaluation. One reason for the voltage variation is the reduction of infrared in the distribution network, which reduces the supply voltage (Vdd) relative to the required value. Another reason for the voltage variation is the power supply noise caused by parasitic inductance, resistance and capacitance. For technologies with Vdd close to 1V, these potential changes may lead to unexpected fragility of the SET response; both in critical and extreme space environments and inside the chip, the temperature variation range is large, which may cause large delay differences. Therefore, the combined effects of process, voltage and temperature will change the operating margin of the circuit and even cause unexpected failure of the entire system.

[0014] Traditional SET reinforcement technology is basically to strengthen the device structure, layout reinforcement, and layout and wiring optimization. When heavy particles hit the sensitive area of ​​the transistor, the parasitic transient current generated may cause glitches or signal flips, so most reinforcement technologies start from this. Based on the input dependence of the logic gate SET sensitivity, a traditional reliability-driven pin allocation optimization method is introduced below: For a NAND gate, when the two input signals are different, a symmetrical input relationship can be observed, that is, as long as one output is at a low level, the output signal can be determined, and this symmetrical output can be observed in all two-input basic standard unit gates.

[0015] Given a register transfer level (RTL) circuit description, the symmetrical input relationship of each standard cell is determined, and the SET cross-section of the mutually changing input combination is calculated. On this basis, a set of pin assignment rules are formulated so that each standard cell is connected to a network with the lowest probability of signal occurrence, so that the probability of the most sensitive interchangeable input combination occurring is minimized. Based on the Boolean function of each gate, the signal probability of the signal being at a logical value of 1 is calculated. Then, through the pin assignment rules and signal probability, the optimization algorithm can determine which pins need to be swapped to reduce the occurrence of interchangeable input combinations with higher SET cross-sections. After the pins are swapped, the optimized netlist is used for the standard design process. Depending on the circuit structure, the overall reduction in SET cross-section ranges from 8% to 28%. This traditional optimization technique has no area overhead and can be used together with other reinforcement techniques. In addition, it does not affect the cell layout, and the network wiring is minimally affected.

[0016] Although the above traditional reinforcement techniques reduce the impact of SET on standard cells, these results mainly reflect the average level and do not take into account other factors such as power supply noise and process-voltage-temperature (PVT) changes. In fact, due to periodic parameter fluctuations and changes in operating conditions, changes in single-particle response always exist. Whether layout reinforcement design can reduce changes caused by SET requires further research.

[0017] Since the traditional reinforcement technology does not consider the impact of process-voltage-temperature (PVT) on device characteristics and circuit performance, the reduction range is reduced to varying degrees under different process-voltage-temperature (PVT), so a reinforcement solution is needed that can have a good effect of reducing the SET effect under different working conditions. This specification will aim to use a combination of source-level central insertion well and substrate embedded N WELL The two technologies optimize the internal electrical structure of transistor devices, thereby effectively suppressing the SET effect under different PVT working environments.

[0018] In one embodiment, Figure 1 As shown, a reinforcement device for single particle effects (on the layout) is provided, including a target transistor in the integrated circuit layout, and a well is inserted into the central region of the source of the target transistor; wherein the target transistor includes a PMOS tube and an NMOS tube, the central region of the source of the PMOS tube is inserted into the N well, and the central region of the source of the NMOS tube is inserted into the P well.

[0019] It can be understood that in order to improve the SET (single event transient) robustness of digital circuits, layout-based radiation hardening technology is often used. The technology used in this embodiment is the source-level central insertion well technology. The source-level central insertion well technology can be as follows: Figure 1 As shown, a well is inserted into the central region of the source (S) and the well is seamlessly connected to the source S to enhance the controllability of the well point position. In the PMOS (P-type metal oxide semiconductor) tube, an N well (such as Figure 1 In NMOS (N-type metal oxide semiconductor) tubes, a P well can be inserted (such as Figure 1 Specifically, for a PMOS transistor, when heavy ions enter the source-drain (SD) of the transistor, under the action of negative bias, the N well collects the electrons generated by ionization, which reduces the potential, forward biases the emitter junction, and reverse biases the collector junction, leading to conduction. Inserting a well in the central region of the source can suppress the SET effect by reducing the base resistance of the parasitic bipolar, and the same is true for NMOS transistors. Figure 1 Vss represents the ground potential.

[0020] Specifically, in a transistor, the P-well and N-well are specific areas formed on a silicon substrate by ion implantation or diffusion during semiconductor manufacturing. For example, the P-well is a P-type semiconductor region formed by doping acceptor impurities on an N-type silicon substrate, and the N-well is an N-type semiconductor region formed by doping donor impurities on a P-type silicon substrate. This allows the insertion of the above-mentioned wells. When inserting the well, reverse doping technology can be used, such as first implanting high-energy, high-dose ions, and then significantly reducing the implantation energy and dose, accurately controlling the implantation depth and doping profile, making the transition of the doping concentration between the well and the source smoother, reducing the sudden change in impurity concentration at the interface, thereby reducing contact resistance and achieving better electrical connection, thereby achieving seamless connection between the well and the source S.

[0021] Alternatively, high-precision lithography technology can be used to ensure accurate alignment of the well and source during the lithography process, so that the physical positions of the two are more matched and the connection problems caused by misalignment are reduced. Advanced lithography technologies such as electron beam lithography can achieve smaller line widths and higher alignment accuracy, ensure the effective connection area between the well and the source, and reduce contact resistance, thereby achieving seamless connection between the well and the source S. Alternatively, appropriate annealing treatment can be performed after the well is inserted and the source is formed, which can eliminate lattice damage and stress caused by processes such as ion implantation and lithography, repair the semiconductor lattice structure, and make the crystal structure of the well and source more complete, thereby improving the electrical performance and connection stability between the two, thereby achieving seamless connection between the well and the source S.

[0022] The above-mentioned reinforced device for single-particle effect, by inserting a corresponding well in the central region of the source of the transistor device in the integrated circuit layout design and making the well and the source seamlessly connected, suppresses the pulse width of the SET of the NMOS tube and the PMOS tube by enhancing the controllability of the well point position. In this way, the structure layout of the source-level central well insertion technology is adopted in the integrated circuit layout, so that the PMOS tube and the NMOS tube are W under different PVT working environments. SET (i.e., SET cross section) are significantly reduced: when the linear energy transfer (LET) is 37mev·cm2 / mg, the W of the PMOS tube is compared with the unreinforced layout. SET It can reduce the W of NMOS tube by about 80%. SET The reduction is about 50%.

[0023] In one embodiment, Figure 2 As shown, an N+ layer is added to the bottom of the N well inserted in the central region of the source of the PMOS tube.

[0024] It can be understood that the N+ layer represents a high concentration N-type doped layer. WELL Technology can be Figure 2 As shown in the figure, a layer of N+ layer with high doping concentration is added to the substrate under the N well inserted in the PMOS tube. The SET of the PMOS tube is more serious than that of the NMOS tube. This is because in the nano CMOS device, the parasitic bipolar effect of the PMOS tube becomes an important SET charge collection mechanism. Therefore, adding a layer of N+ layer with high doping concentration to the substrate under the N well inserted in the PMOS tube can effectively reduce the amount of substrate hole collection, increase the potential of its N well, suppress the parasitic bipolar effect, and thus reduce the SET pulse width.

[0025] In this embodiment, in order to obtain a matching driving current, the width of the PMOS tube is usually designed to be larger than that of the NMOS tube, thereby increasing the sensitive area of ​​the PMOS tube. WELLThe SET effect is further weakened by introducing substrate embedded N WELL The technology further optimizes the layout design of the PMOS tube, thereby further significantly improving the integrated circuit's resistance to single-particle effects.

[0026] In one embodiment, the PMOS transistor includes an LVT device or a SVT device.

[0027] In one embodiment, the NMOS transistor includes an LVT device or an SVT device, wherein the LVT device refers to a low threshold voltage device, and the SVT device refers to a standard threshold voltage device.

[0028] It is understandable that different technical options target different device types and Vth values. Combining reinforcement constraints to optimize the circuit's radiation resistance can help guide both high-performance circuits and the design and optimization of low-power circuits in radiation environments. The above-mentioned source-level central insertion well technology suppresses the SET effect of NMOS and PMOS tubes by enhancing the controllability of the well point. The coupling effect of the source-level central insertion well technology can significantly reduce the pulse width of the SET, and the substrate embedded N WELL The introduction of technology can further reduce the W of PMOS tubes under all Vth options SET , especially for LVT devices and SVT devices; in NMOS tubes, for HVT devices, its W SET There was also a significant decrease.

[0029] The focus of this manual is to reduce SET from the perspective of transistor structure and layout. For PMOS tubes, the doping concentration of the N-type substrate has a significant impact on the SET effect. However, in actual processes, the adjustment of the N-well doping concentration will be adjusted by many factors. Therefore, adding a layer of highly doped well under the N-well of the PMOS tube will not affect its original function, but can also more effectively reduce the SET effect. The source seamless connection technology reduces the SET effect by adjusting the layout from the perspective of the layout.

[0030] In traditional logic synthesis, the method of using the functional equivalence of logic gate input pins to improve power consumption and performance indicators in VLSI circuit (very large scale integrated circuit) design is more focused on optimizing the synthesis method, and does not consider the changes related to the hit position to quantify the impact of SET on pulse width, or does not consider the impact of PVT, so in terms of results, it is not as effective as the above-mentioned solution in this specification.

[0031] In one embodiment, the size and doping concentration of the well are respectively the designed target size and target doping concentration. The doping concentration and thickness of the N+ layer are respectively the designed optimal doping concentration and target thickness.

[0032] It can be understood that by combining the source level central insertion well and substrate embedded N WELL Two technologies optimize the internal electrical structure of the transistor, thereby achieving more effective suppression of the SET effect under different PVT working environments. In the integrated circuit layout design, a corresponding well is inserted in the center of the source to ensure seamless connection between the well and the source to improve the controllability of the well point. The base resistance of the parasitic bipolar transistor can be optimized by adjusting the size and doping concentration of the well, thereby reducing the probability of the SET effect. At the same time, by adjusting the doping concentration and thickness of the N+ layer under the substrate, the SET effect can be further weakened. For example, in a 22nm device, the target size and target doping concentration of the well can be, for example, respectively: the thickness is about 6nm, the depth is about 2nm, and the doping concentration is one order of magnitude lower than the concentration around the well. The optimal doping concentration and target thickness of the N+ layer can be designed as follows: the doping concentration of the N+ layer is one order of magnitude higher than the doping concentration of the N well. The specific size and doping concentration will vary according to the specific process node and design requirements, as long as the required reinforcement performance can be achieved.

[0033] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0034] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of protection of the invention. It should be pointed out that, for those of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the attached claims.

Claims

1. A device for strengthening against single event effects, characterized in that: It includes a target transistor in an integrated circuit layout, wherein the central region of the source of the target transistor is inserted into a well; wherein the target transistor includes a PMOS tube and an NMOS tube, the central region of the source of the PMOS tube is inserted into an N well, and the central region of the source of the NMOS tube is inserted into a P well.

2. The device for strengthening against single event effects according to claim 1, characterized in that: An N+ layer is added to the bottom of the N well inserted in the central region of the source of the PMOS tube.

3. The device for strengthening against single event effects according to claim 1 or 2, characterized in that: The PMOS tube includes an LVT device or a SVT device.

4. The device for strengthening against single event effects according to claim 1 or 2, characterized in that: The NMOS transistor includes an LVT device or a SVT device.

5. The device for strengthening against single event effects according to claim 2, characterized in that: The size and doping concentration of the well are respectively the designed target size and target doping concentration, and the doping concentration and thickness of the N+ layer are respectively the designed optimal doping concentration and target thickness.

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