Display device and driving method thereof

Abstract

The present invention provides a display device and a driving method thereof. The display device has a first operating mode and includes a display panel and a driving circuit board electrically connected to the display panel. In the first operating mode, the driving circuit board is used to activate the overcurrent protection of the display panel when the current of the signal line in the display panel is greater than a preset current for at least two consecutive frames, thereby avoiding the interruption of the electrostatic discharge capability test caused by accidental activation of the overcurrent protection during the electrostatic discharge capability test.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to display devices and their driving methods. Background Technology

[0002] Tri-gate driving technology, as an advanced display driving technology, can be used to reduce the number of display driver circuit boards, thereby reducing chip costs.

[0003] However, in the three-gate driving technology, each pixel unit needs to be controlled by three different gate signals to be turned on in sequence, resulting in a shorter scanning time for each row of sub-pixels. During electrostatic discharge testing, the large current in the clock signal line connected to the gate driving circuit cannot be released quickly, which can easily trigger the overcurrent protection of the display device and cause a black screen phenomenon, making it impossible to complete the electrostatic discharge test. Summary of the Invention

[0004] The purpose of this invention is to provide a display device and its driving method to improve the problem that existing display devices are prone to accidentally triggering overcurrent protection and interrupting electrostatic discharge tests during electrostatic discharge testing.

[0005] The present invention provides a display device having a first operating mode, including:

[0006] Display panel, including signal cables;

[0007] A drive circuit board is electrically connected to the display panel;

[0008] In the first operating mode, the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than a preset current for at least two consecutive frames.

[0009] In some embodiments, a second operating mode is also provided;

[0010] In the second operating mode, the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line exceeds the preset current within one frame.

[0011] In some embodiments, the driving circuit board includes a register, which is used to provide overcurrent protection for the display panel based on information stored in the register and the current of the signal line;

[0012] In the second operating mode, the information stored in the register includes first information, and the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than the preset current within one frame.

[0013] In the first operating mode, the information stored in the register includes second information, and the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than the preset current for at least two consecutive frames.

[0014] In some embodiments, when the information stored in the register includes the second information, the driving circuit board is used to provide overcurrent protection to the display panel when the current of the signal line is greater than the preset current in two consecutive frames.

[0015] In some embodiments, the second information is at least a first sub-information or a second sub-information;

[0016] Wherein, when the information stored in the register includes the first sub-information, the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than the preset current in two consecutive frames;

[0017] When the information stored in the register includes the second information, the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than the preset current for at least three consecutive frames.

[0018] In some embodiments, the driving circuit board is configured to determine whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the current of the signal line is greater than the preset current in two time intervals within a frame; and / or,

[0019] The driving circuit board is used to determine whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the current of the signal line is greater than the preset current for at least a preset duration within a frame.

[0020] In some embodiments, the signal line includes a clock signal line, and the driving circuit board is at least used to control the display panel to provide overcurrent protection when the current of at least one of the clock signal lines is greater than the preset current for at least two consecutive frames.

[0021] The display panel includes:

[0022] Multiple sub-pixels;

[0023] Multiple gate lines;

[0024] A gate driving circuit is electrically connected to multiple gate lines, and the gate driving circuit is used to transmit corresponding gate signals to the corresponding multiple sub-pixels through the gate lines;

[0025] Multiple clock signal lines are electrically connected to the gate driving circuit and are used to transmit multiple clock signals. The multiple clock signals are used by the gate driving circuit to generate multiple gate signals.

[0026] In some embodiments, the amplitude of the clock signal alternates between a first potential and a second potential within a frame, and the current signal corresponding to the current of the clock signal line includes a first sub-current signal corresponding to the first potential and a second sub-current signal corresponding to the second potential.

[0027] The driving circuit board is used to determine whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the potential when at least one first sub-current signal is stable and / or the absolute value of the potential when at least one second sub-current signal is stable is greater than the preset current.

[0028] In some embodiments, the signal line includes a power signal line, and the driving circuit board is at least used to control the display panel to perform overcurrent protection when the current of at least one of the power signal lines is greater than the preset current for at least two consecutive frames.

[0029] The display panel includes:

[0030] Multiple sub-pixels;

[0031] Multiple pixel circuits, each of which is electrically connected to a corresponding sub-pixel;

[0032] A gate driving circuit is electrically connected to the plurality of pixel circuits;

[0033] The power signal lines are electrically connected to at least one of the gate drive circuit and the pixel circuit.

[0034] The present invention also provides a driving method for a display device, comprising:

[0035] The driver circuit board obtains the current from the signal lines in the display panel;

[0036] In the first working mode, the driving circuit board determines whether the current of the signal line is greater than a preset current for at least two consecutive frames.

[0037] If so, the driver circuit board provides overcurrent protection for the display panel.

[0038] The present invention provides a display device and a driving method thereof. The display device includes a display panel and a driving circuit board electrically connected to each other. The display panel includes signal lines. By configuring the driving circuit board to provide overcurrent protection for the display panel when the current in the signal lines is greater than a preset current for at least two consecutive frames, the overcurrent protection is not accidentally triggered during the electrostatic discharge capability test, thus interrupting the electrostatic discharge capability test and improving the reliability of the electrostatic discharge capability test. Attached Figure Description

[0039] Figure 1 This is an architectural diagram of a display device provided in an embodiment of the present invention.

[0040] Figure 2 A block diagram of a display device provided in an embodiment of the present invention.

[0041] Figure 3 The waveform diagram shows some signals in the display device provided in the embodiment of the present invention.

[0042] Figure 4 This is a top view of the display panel provided in an embodiment of the present invention.

[0043] Figure 5 A flowchart of a driving method for a display device provided in an embodiment of the present invention. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0045] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first" or "second" may explicitly or implicitly include one or more of the stated features. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the accompanying drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0046] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0047] The present invention provides a display device, which includes, but is not limited to, the following embodiments and combinations thereof.

[0048] In some embodiments, such as Figure 1 As shown, the display device 100 has a first operating mode and includes: a display panel 10 including a signal line 20; and a driving circuit board 30 electrically connected to the display panel 10. In the first operating mode, the driving circuit board 30 is used to provide overcurrent protection to the display panel 10 when the current of the signal line 20 is greater than a preset current for at least two consecutive frames.

[0049] The display device 100 is, but is not limited to, an organic self-emissive display device, an inorganic self-emissive direct-view display device, or a liquid crystal display device. For example... Figure 1 As shown, this example illustrates the arrangement of multiple sub-pixels P in display area A of display panel 10 as n rows, m columns, where n and m are positive integers. Correspondingly, display panel 10 may also include multiple data lines (DL1 to DLm), multiple gate lines (GL1 to GLn), multiple pixel circuits 40 corresponding to the multiple sub-pixels P, source drivers 301 electrically connected to the multiple data lines, and gate drivers 50 electrically connected to the multiple gate lines. The gate driver 50 can be a gate driving circuit located on the substrate of display panel 10 or a chip independently of the substrate. Figure 1 (This is just one example of the first case).

[0050] Specifically, each sub-pixel P is electrically connected to the corresponding pixel circuit 40, and each gate line (each of GL1 to GLn) is electrically connected to the multiple pixel circuits 40 corresponding to the multiple sub-pixels P in the corresponding row to output the corresponding gate signal gate. In each frame, the gate signal gate includes a gate pulse for controlling the multiple pixel circuits 40 to turn on. The multiple row pixel circuits 40 are turned on sequentially under the control of the multiple gate pulses in the multiple gate signals. Each data line (each of DL1 to DLm) is connected to the multiple pixel circuits 40 corresponding to the multiple sub-pixels P in the corresponding column to output the corresponding data signal data. The multiple data signals corresponding to the multiple columns of sub-pixels P are set so that when each row of pixel circuits 40 is turned on, the multiple data signals data also transmit multiple valid data voltages corresponding to the sub-pixels P in that row. Thus, when each row of pixel circuits 40 is turned on, the multiple valid data voltages corresponding to the multiple sub-pixels P in that row are driven to emit light. In this way, all the multiple rows of sub-pixels P emit light to display the image of that frame.

[0051] Furthermore, in addition to the source driver 301 described above, the driving circuit board 30 of this embodiment may also include a timing controller 302 electrically connected to the source driver 301 and the gate driver 50, and a power manager 303 electrically connected to the source driver 301, the gate driver 50, the timing controller 302, and multiple pixel circuits 40. The multiple pixel circuits 40 are electrically connected to the power manager 303 through multiple power signal lines 201. The power manager 303 can supply power to the driving circuit board 30 and the display panel 10. The timing controller 302 can generate a grayscale signal and a corresponding first control signal acting on the source driver 301, and can also generate a corresponding second control signal acting on the gate driver 50. The source driver 301 generates the multiple data signals (data) based on the grayscale signal and the first control signal, and the gate driver 50 generates the multiple gate signals (gate) based on the second control signal.

[0052] Based on the above discussion, the signal lines 20 within the display panel 10 may include at least one of multiple gate lines (GL1 to GLn), multiple data lines (DL1 to DLm), and multiple power signal lines 201.

[0053] It should be noted that, in order to avoid damage to the display device 100 caused by excessive current in the signal line 20 within the display panel 10 due to faults such as short circuits, the overcurrent protection of the display panel 10 can generally be controlled by detecting whether the current in the signal line 20 exceeds a preset current within one frame, thereby cutting off or limiting the current supply to the display panel 10. However, when testing the electrostatic discharge capability of the display device 100, due to charge accumulation, the current in the signal line 20 within the display panel 10 will also be large, causing the existing overcurrent protection to be falsely triggered, resulting in the display panel 10 going black and failing to complete the electrostatic discharge capability test.

[0054] Understandably, since the charge accumulated during the electrostatic discharge capability test can be released during the initial period of each frame to reduce the current (unlike the charge accumulation caused by short circuits or other faults on signal line 20, which has no release path and causes the current to remain excessive), the risk of excessive current caused by the electrostatic discharge capability test is generally concentrated between the start of the current frame and the start of the next frame. In this embodiment, the driving circuit board 30 is configured to "in the first working mode, activate the overcurrent protection of the display panel 10 when the current of signal line 20 is greater than a preset current for at least two consecutive frames". That is, the overcurrent protection will only be activated when the current of signal line 20 is detected to be greater than the preset current for at least two consecutive frames. This avoids activating the overcurrent protection only when a large current is detected in signal line 20 within one frame, avoids accidentally triggering the overcurrent protection during the electrostatic discharge capability test and interrupting the electrostatic discharge capability test, and improves the reliability of the electrostatic discharge capability test.

[0055] In some embodiments, combined with Figure 1 , Figure 2 As shown in Table 1, the display device 100 also has a second operating mode; wherein, in the second operating mode, the driving circuit board 30 is used to provide overcurrent protection to the display panel 10 when the current of the signal line 20 exceeds the preset current within one frame. Specifically, the driving circuit board 30 includes a register 304, and the driving circuit board 30 is used to provide overcurrent protection to the display panel 10 based on the information stored in the register 304 and the current of the signal line 20; wherein, in the second operating mode, the information stored in the register 304 includes first information, and the driving circuit board 30 is used to provide overcurrent protection to the display panel 10 when the current of the signal line 20 exceeds the preset current within one frame; wherein, in the first operating mode, the information stored in the register 304 includes second information, and the driving circuit board 30 is used to provide overcurrent protection to the display panel 10 when the current of the signal line 20 exceeds the preset current for at least two consecutive frames.

[0056] As discussed above, the information stored in register 304 includes either first information (e.g., "000" in Table 1) or second information (e.g., one of the seven types of information, "001"..."111" in Table 1). When register 304 stores the first information, the driving circuit board 30 is used to activate the overcurrent protection of the display panel 10 when the current of the signal line 20 exceeds the preset current within one frame. When register 304 stores the second information, the driving circuit board 30 is used to activate the overcurrent protection of the display panel 10 when the current of the signal line 20 exceeds the preset current for at least two consecutive frames.

[0057] As discussed above, if the signal line 20 experiences excessive current due to faults such as short circuits during the testing of the electrostatic discharge capability of the display device 100, it is generally necessary to detect whether the current of the signal line 20 exceeds the preset current within one frame to control whether to activate the overcurrent protection.

[0058] Understandably, this embodiment sets the information stored in the register 304 of the driver circuit board 30 to include either first information or second information, so that the driver circuit board 30 determines the "detection frame number" required for the current overcurrent protection based on the information stored in the register 304. Then, when the current of the signal line 20 is detected to be greater than the preset current within the corresponding "detection frame number", the overcurrent protection is activated. This allows different overcurrent protection mechanisms to be set in different scenarios, taking into account both reducing the risk of damage to the display device 100 caused by overcurrent due to faults such as short circuits in the signal line 20 of the display panel 10 and reducing the risk of interrupting the electrostatic discharge capability test due to accidental activation of the overcurrent protection caused by electrostatic accumulation in the signal line 20.

[0059] As shown in Table 1, for example, the information stored in register 304 can include at least three bits of data from low to high: Bit0, Bit1, and Bit2. Each bit can be 0 or 1. Different values ​​can be obtained from the three bits of data to form eight kinds of information: "000", "001"... "111". If each bit of data corresponds to a binary number, then when the value corresponding to the information is decimal i, the corresponding "detection frame number" can be (i+1) detect, where i is any integer from 0 to 7.

[0060] Specifically, based on the definitions of "first information" and "second information" above, we can see that: "first information" is "000", corresponding to a "detection frame number" of 1 frame. That is, overcurrent protection is activated when the current of signal line 20 is detected to be greater than the preset current within 1 frame. The application scenario in this case can be the testing of non-electrostatic discharge capability, that is, it is used to detect whether the signal line 20 is overcurrent due to faults such as short circuits; "second information" is one of the 7 types of information, "001"... "111", corresponding to a "detection frame number" greater than or equal to 2 frames. That is, overcurrent protection is activated only when the current of signal line 20 is detected to be greater than the preset current for at least 2 consecutive frames. The application scenario in this case can be the testing of electrostatic discharge capability.

[0061] Table 1

[0062] Bit2 Bit1 Bit0 Detection frame count 0 0 0 1 frame 0 0 1 2 frames 0 1 0 3 frames 0 1 1 4 frames 1 0 0 5 frames 1 0 1 6 frames 1 1 0 7 frames 1 1 1 8 frames

[0063] Referring to the discussion of Table 1 above, the second information is at least the first sub-information (e.g., "001" in Table 1) or the second sub-information (e.g., "010" in Table 1); wherein, when the information stored in the register 304 includes the first sub-information, the driving circuit board 30 is used to activate the overcurrent protection of the display panel 10 when the current of the signal line 20 is greater than the preset current for two consecutive frames; wherein, when the information stored in the register 304 includes the second information, the driving circuit board 30 is used to activate the overcurrent protection of the display panel 10 when the current of the signal line 20 is greater than the preset current for at least three consecutive frames.

[0064] Understandably, when the application scenario is the electrostatic discharge capability test, this embodiment further refines it into multiple sub-scenarios for testing electrostatic discharge capability. The difference between each sub-scenarios is that the amount of electrostatic charge accumulated in the signal line 20 is different. It can be considered that the more the amount of electrostatic charge accumulated, the more frames are required to release the signal line 20 and no longer be an overcurrent. In other words, the overcurrent in the signal line 20 will last for more frames. At this time, in order to avoid interrupting the electrostatic discharge capability test by enabling overcurrent protection, it is necessary to set the "detection frame number" of overcurrent required to enable overcurrent protection to be larger, that is, the second information is the sub-information corresponding to the larger decimal value.

[0065] Therefore, this embodiment, by setting the second information to be multiple sub-informations, enables the drive circuit board 30 to control the signal line 20 to activate overcurrent protection when the current is greater than the preset current in different consecutive frames, thus making it suitable for testing electrostatic discharge capability under different amounts of electrostatic charge accumulation, and further improving the reliability of electrostatic discharge capability testing.

[0066] Of course, in other embodiments, combined with Figure 1 , Figure 2 As shown in Table 1, when the information stored in the register 304 includes the second information, the drive circuit board 30 is used to activate the overcurrent protection of the display panel 10 when the current of the signal line 20 is greater than the preset current in two consecutive frames.

[0067] Comparing with the discussion of Table 1 above, in this case, when the application scenario is the electrostatic discharge capability test, this embodiment can be considered that regardless of whether the second information corresponds to only one decimal value or to multiple decimal values ​​as mentioned above, the driving circuit board 30 is set to include the second information in the information stored in register 304, and the corresponding "detection frame number" is 2 frames. That is, in the application scenario of the electrostatic discharge capability test, overcurrent protection is activated only when the current of signal line 20 is detected to be greater than the preset current in two consecutive frames.

[0068] Therefore, compared with the embodiments in Table 1, this embodiment can be considered that the large current of the signal line 20 can be reduced to a small current within one frame during the electrostatic discharge capability test. This embodiment avoids the need to activate overcurrent protection only when the current of the signal line 20 is detected to be greater than the preset current for at least three consecutive frames. That is, overcurrent protection is activated only when the current of the signal line 20 is detected to be greater than the preset current for two consecutive frames. This can reduce the risk of damage to the display device 100 caused by overcurrent due to faults such as short circuits in the signal line 20 during the electrostatic discharge capability test.

[0069] In some embodiments, combined with Figures 1 to 3 As shown, the driving circuit board 30 is used to determine the current of the signal line 20 (e.g., the corresponding signal is...). Figure 3 Current signal I in ck The absolute value of ) within two time intervals within a frame (e.g., ) Figure 3 The driving circuit board 30 determines whether the current of the signal line 20 is greater than the preset current I0 within the frame based on whether the absolute value of the current of the signal line 20 is greater than the preset current I0 within a frame and continues for at least a preset duration.

[0070] Understandably, this embodiment further illustrates that within a frame, it is necessary to determine whether the current of the signal line 20 is greater than the preset current I0 within the frame based on whether the absolute value of the current of the signal line 20 is greater than the preset current I0 in both time intervals and / or whether it is greater than the preset current for a continuous preset duration. This improves the reliability of determining whether the current of the signal line 20 is greater than the preset current I0 within a frame and avoids false triggering of overcurrent protection due to the absolute value of the current of the signal line 20 being greater than the preset current I0 at an instant.

[0071] In some embodiments, combined with Figures 1 to 3 As shown, the display panel 10 includes: the aforementioned plurality of sub-pixels P; the aforementioned plurality of gate lines (GL1 to GLn); the aforementioned gate driving circuit (which may be a gate driver 50), electrically connected to the plurality of gate lines, the gate driving circuit being used to transmit the corresponding gate signal gate to the corresponding plurality of sub-pixels P through the gate lines; and a plurality of clock signal lines 202, electrically connected to the gate driving circuit, respectively used to transmit a plurality of clock signals (e.g., CK1, CK2 to CK12), the plurality of clock signals being used to generate a plurality of gate signals gate by the gate driving circuit; wherein, the signal line 20 includes at least one clock signal line 202, and the driving circuit board 30 is at least used to control the current of at least one clock signal line 202 to be greater than the preset current I0 for at least two consecutive frames to activate the overcurrent protection of the display panel 10.

[0072] The driving circuit board 30 includes: the timing controller 302 described above, used to generate clock source signals (including but not limited to the first clock source signal CLK1 and the second clock source signal CLK1) and to drive the display panel 10 to display images (through the source driver 301 and the gate driver 50); and a level converter 306 (e.g., included in the power manager 303), electrically connected to the timing controller 302 and the multiple clock signal lines 202, used to generate multiple clock signals according to the clock source signals.

[0073] Specifically, in combination Figure 1 and Figure 2As shown, the voltage generator 305 in the power manager 303 can provide a high-voltage signal VGH and a low-voltage signal VGL with different amplitudes to the level converter 306. The timing controller 302 can provide a first clock source signal CLK1 and a second clock source signal CLK1 (both clock signals) with a phase difference to the level converter 306. The level converter 306 can generate multiple clock signals (e.g., CK1, CK2 to CK12) based on the phase of the first clock source signal CLK1 and the second clock source signal CLK1, and the amplitude of the high-voltage signal VGH and the low-voltage signal VGL, respectively, to be transmitted to the gate drive circuit through multiple clock signal lines 202. Each gate drive unit in the gate drive circuit generates a corresponding gate signal gate based on at least two of the clock signals.

[0074] Register 304 may be included in level shifter 306, and the execution entity for "activating overcurrent protection of display panel 10 when the current of clock signal line 202 is greater than the preset current I0 for at least two consecutive frames" may be level shifter 306. Level shifter 306 may also be set independently of power manager 303.

[0075] Understandably, this embodiment takes into account that the current of the clock signal line 202 is easily too large, which may lead to overcurrent. Therefore, the current detected by the drive circuit board 30 can be the current of the clock signal line 202, which can greatly reduce the risk of the display device 100 being damaged due to overcurrent.

[0076] When the signal line 20 for the current to be detected includes at least one clock signal line 202, enabling overcurrent protection may include controlling the level converter 306 to stop outputting the corresponding clock signal, so that the corresponding clock signal line 202 is in a high impedance state, thereby reducing the corresponding current.

[0077] As discussed above, since both the first clock source signal CLK1 and the second clock source signal CLK2 are clock signals, such as Figure 3 As shown, the amplitude of the clock signal (a voltage signal, CK1 is used as an example here) generated accordingly alternates between the first potential Vp1 and the second potential Vp2 within one frame, and the current signal I corresponding to the current of the clock signal line... ckThis includes a first sub-current signal I1 / I1' corresponding to the first potential Vp1 and a second sub-current signal I2 / I2' corresponding to the second potential Vp2; wherein, the level converter 306 in the driving circuit board 30 is used to determine whether the current of the signal line 20 is greater than the preset current I0 within a frame based on whether the absolute value of the potential when at least one of the first sub-current signals I1 / I1' is stable and / or the absolute value of the potential when at least one of the second sub-current signals I2 / I2' is stable is greater than the preset current I0.

[0078] Specifically, such as Figure 3 As shown, after the high-voltage signal VGH reaches a certain percentage (e.g., 80%) of its maximum value and remains stable for a first duration T1 (e.g., 130ms), it is considered to have reached stability. Afterwards, the first frame start pulse sp1 of the frame start signal STV appears, indicating the start of the first frame F1. Subsequently, the amplitude of the clock signal CK1 alternates between the first potential Vp1 and the second potential Vp2 to provide the corresponding gate drive unit with the corresponding gate signal gate. The corresponding current signal I is transmitted in the clock signal line 202. ck The amplitude drops sharply at the rising edge and rises sharply at the falling edge of the clock signal CK1.

[0079] Among them, the current signal I at the rising edge of the clock signal CK1 ck After a second duration T2 (e.g., 4μs), the absolute value of the current signal I1 (i.e., the potential when the first sub-current signal I1 / I1' stabilizes) may be greater than, less than, or equal to the preset current I0 for a duration of, for example, 2μs (i.e., within the corresponding time period t1). Similarly, at the falling edge of the clock signal CK1, the current signal I... ck If the absolute value of the amplitude (i.e., the potential when the second sub-current signal I2 / I2' is stable) continues for, for example, 2μs (i.e. within the corresponding time period t2), it may be greater than, less than or equal to the preset current I0.

[0080] Specifically, in this embodiment, the current of the signal line 20 is determined to be greater than or equal to the preset current I0 within a frame by judging whether at least one of the absolute values ​​of the potentials of the first sub-current signal I1 / I1' and the second sub-current signal I2 / I2' when they are stable is greater than the preset current I0. Since the number of first sub-current signals I1 / I1' and second sub-current signals I2 / I2' is the same within a frame, it can actually be determined whether the absolute values ​​of the potentials of j consecutive first sub-current signals I1 / I1' and / or j consecutive second sub-current signals I2 / I2' when they are stable are greater than the preset current I0, where j is a positive integer.

[0081] For example, when j=4, it indicates that the current signal I is being judged. ck Whether the absolute values ​​of the potentials when the four consecutive first sub-current signals I1 / I1' and / or the second sub-current signal I2 / I2' stabilize are all greater than the preset current I0. Figure 3 For example, current signal I ck Including four consecutive first sub-current signals I1 and four consecutive second sub-current signals I2, since the absolute value of the potential of all eight when they are stable is less than the preset current I0, the current signal I is considered to be... ck Within this frame, the current is less than the preset current I0; for example, the current signal I... ck Including four consecutive first sub-current signals I1' and four consecutive second sub-current signals I2', since the absolute value of the potential of all eight when they are stable is greater than the preset current I0, the current signal I is considered to be... ck Within this frame, the current is less than the preset current I0.

[0082] Therefore, it can be seen that in this embodiment, the current signal I of the clock signal line 202 is determined. ck Assuming that the amplitude is greater than the preset current I0 for at least two consecutive frames, and considering that the clock signal CK1 is a clock signal, the current signal I is determined based on its corresponding current signal. ck The relationship between the absolute value of the potential of the first sub-current signal I1 / I1' and the second sub-current signal I2 / I2' when they are stable and the magnitude of the preset current I0 is determined, which further improves the reliability of "whether the current of the signal line 20 is greater than or equal to the preset current I0 within the frame".

[0083] in, Figure 3 The illustration only shows that when the clock signal line 202 used to transmit the clock signal CK1 is greater than the preset current I0 for k consecutive frames (e.g., from the first frame F1 to the kth frame Fk), the overcurrent protection of the display panel 10 is activated. k is a positive integer greater than 1. In actual applications, the values ​​of k, j, the duration of time period t1, the duration of time period t2, etc. are not limited.

[0084] In some embodiments, combined with Figure 1 and Figure 4As shown, the plurality of sub-pixels P includes a plurality of first sub-pixels P1, a plurality of second sub-pixels P2, and a plurality of third sub-pixels P3, wherein the first sub-pixels P1, the second sub-pixels P2, and the third sub-pixels P3 correspond to different colors; wherein each of the gate lines (each of GL1 to GLn) is connected to the corresponding plurality of first sub-pixels P1, the plurality of second sub-pixels P2, or the plurality of third sub-pixels P3. That is, the display panel 10 of this embodiment is a three-gate structure, specifically, each gate line is connected to a plurality of sub-pixels P of the same color. At this time, the three sub-pixels P in the pixel unit (including one first sub-pixel P1, one second sub-pixel P2, and one third sub-pixel P3) that were originally connected to the same gate line need to be electrically connected to three gate lines respectively. This can save the number of output terminals of the source driver 301, or in other words, save the number of source drivers 301, but will cause the number of gate lines to become three times the original, resulting in the time for the gate driver 50 to scan each row of sub-pixels P being shortened to one-third of the original.

[0085] It is understood that this embodiment further limits the application scenario of the above-mentioned overcurrent protection mechanism to a three-gate architecture. Since the gate signal in a three-gate architecture is located after the gate pulse for a short time in a frame, the accumulated charge cannot be fully released during the electrostatic discharge capability test. As a result, the risk of large current in the signal line 20 in that frame is greater. Therefore, the above-mentioned overcurrent protection mechanism is more beneficial to improving the reliability of the electrostatic discharge capability test.

[0086] In some embodiments, combined with Figure 1 and Figure 2 As shown, the display panel 10 includes: the aforementioned plurality of sub-pixels P; the aforementioned plurality of pixel circuits 40, each of the pixel circuits 40 being electrically connected to the corresponding sub-pixel P; a gate driving circuit (i.e., the aforementioned gate driver 50), electrically connected to the plurality of pixel circuits 40; and the aforementioned plurality of power signal lines 201, electrically connected to at least one of the gate driving circuit and the plurality of pixel circuits 40; wherein, the signal line 20 includes at least one power signal line 201, and the driving circuit board 30 is at least used to control the overcurrent protection of the display panel 10 when the current of at least one power signal line 201 is greater than the preset current for at least two consecutive frames.

[0087] As discussed above, multiple pixel circuits 40 are electrically connected to the power manager 303 via multiple power signal lines 201. Similarly, the gate drive circuit within the display panel 10 is also electrically connected to the power manager 303 via multiple power signal lines 201. Considering the risk of overcurrent in the power signal lines 201 during short circuit or electrostatic discharge capability testing, this embodiment further configures the drive circuit board 30 to control whether to activate the overcurrent protection of the display panel 10 based on whether the current of the power signal lines 201 is greater than a preset current for at least two consecutive frames. This further balances reducing the risk of damage to the display device 100 caused by overcurrent and reducing the risk of interrupting the electrostatic discharge capability test.

[0088] To better illustrate the above-described display device, the present invention also provides a driving method for the display device, such as... Figure 5 As shown, the steps may include, but are not limited to, the following steps and combinations thereof:

[0089] S1, the driver circuit board obtains the current of the signal lines in the display panel;

[0090] S2, In the first working mode, the driving circuit board determines whether the current of the signal line is greater than a preset current for at least two consecutive frames.

[0091] If so, then execute:

[0092] S3, the driving circuit board provides overcurrent protection for the display panel.

[0093] As can be seen from the above discussion, when the signal line 20 for the current to be detected includes a clock signal line 202, the execution entity in step S1 may specifically include a level converter 306 in the driver circuit board 30. Of course, when the signal line 20 for the current to be detected includes a power signal line 201, the execution entity in step S1 may specifically include a voltage generator 305 or a timing controller 302 in the driver circuit board 30.

[0094] For details on how to determine whether the current of signal line 20 is greater than the preset current in at least two consecutive frames, please refer to the relevant discussion above.

[0095] The display device and its driving method provided in the embodiments of the present invention have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of the present invention. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display device, characterized in that, Having a first operating mode, the test applied to the electrostatic discharge capability of the display device includes: The display panel has a three-gate structure and includes signal lines, at least one of which is a clock signal line. A driving circuit board is electrically connected to the display panel. The driving circuit board includes a timing controller and a level shifter. A register is included in the level shifter. The timing controller is used to generate a clock source signal and drive the display panel to display an image. The level shifter is electrically connected to the timing controller and the clock signal line, and is used to generate multiple clock signals according to the clock source signal. The driving circuit board is used to perform overcurrent protection on the display panel according to the information stored in the register and the current of the signal line. The overcurrent protection includes controlling the level shifter to stop outputting the corresponding clock signal to reduce the corresponding current. The driving circuit board also determines whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the current of the signal line is greater than the preset current in two time intervals within a frame. Furthermore, the driving circuit board determines whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the current of the signal line is greater than the preset current within a frame and remains greater for at least a preset duration. In the first working mode, the information stored in the register includes second information, which is at least the first sub-information or the second sub-information; When the information stored in the register includes the first sub-information, the driving circuit board is used to provide overcurrent protection to the display panel when the current of the signal line is greater than the preset current in two consecutive frames. When the information stored in the register includes the second sub-information, the driving circuit board is used to provide overcurrent protection to the display panel when the current of the signal line is greater than the preset current for at least three consecutive frames.

2. The display device as claimed in claim 1, characterized in that, It also has a second working mode; In the second operating mode, the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line exceeds the preset current within one frame.

3. The display device as claimed in claim 2, characterized in that, In the second operating mode, the information stored in the register includes first information, and the driving circuit board is used to provide overcurrent protection for the display panel when the current of the signal line is greater than the preset current within one frame.

4. The display device according to any one of claims 1 to 3, characterized in that, The display panel includes: Multiple sub-pixels; Multiple gate lines; A gate driving circuit is electrically connected to multiple gate lines, and the gate driving circuit is used to transmit corresponding gate signals to the corresponding multiple sub-pixels through the gate lines; Multiple clock signal lines are electrically connected to the gate driving circuit and are used to transmit multiple clock signals. The multiple clock signals are used by the gate driving circuit to generate multiple gate signals.

5. The display device as claimed in claim 4, characterized in that, The amplitude of the clock signal alternates between a first potential and a second potential within one frame, and the current signal corresponding to the current of the clock signal line includes a first sub-current signal corresponding to the first potential and a second sub-current signal corresponding to the second potential. The driving circuit board is used to determine whether the current of the signal line is greater than the preset current within a frame based on whether the absolute value of the potential when at least one first sub-current signal is stable and / or the absolute value of the potential when at least one second sub-current signal is stable is greater than the preset current.

6. A driving method for a display device, characterized in that, The display device applied to any one of claims 1-5 comprises: The driver circuit board obtains the current from the signal lines in the display panel; The display panel is protected from overcurrent based on the information stored in the register and the current of the signal line. In the first working mode, the driving circuit board determines whether the current of the signal line is greater than a preset current for at least two consecutive frames. If so, the driver circuit board provides overcurrent protection for the display panel.

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