Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a chip packaging structure, a preparation method thereof and electronic equipment, and is suitable for the technical field of semiconductors, and the chip packaging structure comprises a first wafer, a first dielectric layer, a second dielectric layer, a second wafer and a second conductive structure. The first dielectric layer is disposed on the first wafer. The second dielectric layer is arranged on the side, away from the first wafer, of the first dielectric layer, a first conductive layer and a first conductive structure are arranged in the second dielectric layer, the first conductive structure is arranged on the side, away from the first wafer, of the first conductive layer, and the second dielectric layer comprises a first surface away from the side of the first wafer; the first conductive structure extends into the second dielectric layer from the first surface and is electrically connected with the first conductive layer. The second wafer is disposed on a side of the second dielectric layer away from the first wafer. The second conductive structure penetrates through the second wafer and is electrically connected with the first conductive structure. According to the technical scheme, the overall yield of the chip packaging structure is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] At present, advanced packaging processes all require the use of Through Silicon Via (TSV) to achieve electrical interconnection between stacked chips, so TSV is a key structure in advanced packaging.

[0003] However, TSV has a high aspect ratio and a small process window, which increases the difficulty of etching (ETCH), barrier and seed layer deposition (Barrier & Seed, B&S), electrochemical Plating (Electrochemical Plating, ECP), chemical mechanical polishing (CMP) and other processes in the process of preparing chip packaging structure. There are problems such as the trumpet-mouth morphology at the TSV through-hole on the top of the wafer and the lateral notching (Notching) caused by silicon over-etching at the bottom of the wafer. These problems have an adverse impact on the overall yield of the chip packaging structure. Summary of the invention

[0004] The present application provides a chip packaging structure and a preparation method thereof, and an electronic device, aiming to improve the overall yield of the chip packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions: On the one hand, a chip packaging structure is provided, which includes a first wafer, a first dielectric layer, a second dielectric layer, a second wafer and a second conductive structure. The first dielectric layer is arranged on the first wafer. The second dielectric layer is arranged on a side of the first dielectric layer away from the first wafer, a first conductive layer and a first conductive structure are arranged in the second dielectric layer, the first conductive structure is arranged on a side of the first conductive layer away from the first wafer, the second dielectric layer includes a first surface away from the side of the first wafer, the first conductive structure extends from the first surface into the second dielectric layer, and is electrically connected to the first conductive layer. The second wafer is arranged on a side of the second dielectric layer away from the first wafer. The second conductive structure runs through the second wafer and is electrically connected to the first conductive structure.

[0006] The chip packaging structure provided in the embodiment of the present application includes a first wafer, a first dielectric layer, a second dielectric layer, a second wafer, and a second conductive structure. The first conductive layer and the first conductive structure are arranged in the second dielectric layer, and the second conductive structure electrically connected to the first conductive structure is arranged in the second wafer, thereby realizing electrical connection between the first wafer and the second wafer. By setting the first conductive structure in advance, the film layer through which the second conductive structure is etched is reduced, the side-excavation defect morphology inside the second wafer is avoided, and the trumpet-mouth morphology on the top of the second wafer is avoided, thereby improving the overall yield of the chip packaging structure.

[0007] In some embodiments, a second conductive layer is further disposed in the second dielectric layer, and the second conductive layer is disposed on a side of the first conductive layer away from the first wafer and is directly connected to the first conductive layer. The first conductive structure is directly connected to the first conductive layer.

[0008] In some embodiments, a second conductive layer is further disposed in the second dielectric layer, and the second conductive layer is disposed between the first conductive layer and the first conductive structure. The first conductive structure is electrically connected to the first conductive layer through the second conductive layer.

[0009] In some embodiments, an orthographic projection of the second conductive structure on the first surface at least partially overlaps with an orthographic projection of the first conductive structure on the first surface.

[0010] In some embodiments, the chip packaging structure further includes a third dielectric layer, the third dielectric layer is disposed between the second conductive structure and the second wafer, and the first conductive structure is in direct contact with the second dielectric layer.

[0011] On the other hand, a method for preparing a chip packaging structure is also provided, the method for preparing the chip packaging structure comprising: forming a first dielectric layer on a first wafer to obtain a first bonding structure. Forming a second dielectric layer on a second wafer to obtain a second bonding structure, wherein a first conductive layer and a first conductive structure are provided in the second dielectric layer, the first conductive layer is provided on a side of the first conductive structure away from the second wafer, the second dielectric layer comprises a first surface close to a side of the second wafer, the first conductive structure extends from the first surface into the second dielectric layer, and is electrically connected to the first conductive layer. The first bonding structure is bonded to the second bonding structure, and the surface of the first dielectric layer away from the first wafer is connected to the surface of the second dielectric layer away from the second wafer. A second conductive structure is formed, the second conductive structure passes through the second wafer, and is electrically connected to the first conductive structure.

[0012] The preparation method provided in the embodiment of the present application is to pre-set the first conductive layer and the first conductive structure in the second dielectric layer, form the first dielectric layer on the first wafer, obtain the first bonding structure, bond the first bonding structure to the second bonding structure, and then form a penetrating second conductive structure in the second wafer, and the first conductive structure is electrically connected to the second conductive structure to form a chip packaging structure. Since the first conductive structure is pre-set in the second dielectric layer, the film layer etched to form the second conductive structure is reduced, the side-excavation defect morphology inside the second wafer is avoided, and the trumpet-mouth morphology on the top of the second wafer is avoided, thereby improving the overall yield of the chip packaging structure.

[0013] In some embodiments, forming the second dielectric layer includes forming a first conductive structure and a second conductive layer on the second wafer. The first conductive layer is formed, the first conductive layer is located on a side of the first conductive structure and the second conductive layer away from the second wafer, and the first conductive layer is directly connected to the first conductive structure and the second conductive layer.

[0014] In some embodiments, forming the second dielectric layer includes forming a first conductive structure on a second wafer, forming a second conductive layer, the second conductive layer is located on a side of the first conductive structure away from the second wafer, and is electrically connected to the first conductive structure, and forming a first conductive layer, the first conductive layer is located on a side of the second conductive layer away from the second wafer, and is electrically connected to the second conductive layer.

[0015] In some embodiments, forming the second conductive structure includes etching the second wafer using a photolithography process to form a via hole penetrating the second wafer, wherein the via hole exposes at least a portion of the first conductive structure. Forming a third dielectric layer on a sidewall of the via hole. Forming a second conductive structure on an inner side of the third dielectric layer, wherein the second conductive structure is electrically connected to the first conductive structure.

[0016] On the other hand, an electronic device is provided. The electronic device includes the above-mentioned and a circuit board, wherein the chip packaging structure is arranged on the circuit board and is electrically connected to the circuit board.

[0017] The electronic device provided by the embodiment of the present application has an improved overall performance of the chip packaging structure, so that the preparation accuracy and overall performance of the chip packaging structure are improved, thereby improving the reliability of the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 2 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 3 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 4 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 5 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 6 A flowchart of the chip packaging structure provided in the embodiment of the present application; Figure 7 to Figure 14 for Figure 6 A diagram of each step of the preparation process; Fig.15 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0020] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0021] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0022] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0023] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0024] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0025] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0026] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0027] In the common through silicon via loop technology (TSV Loop), during the etching process, not only does the aspect ratio of TSV ETCH become large, but the film layers to be etched are also very complex. According to the process before and after, the film layers to be etched are the top dielectric layer, silicon, the bottom dielectric layer, the insulating oxide layer (there may also be a residual dielectric layer at this time), and finally stop at the metal conductive structure set in the dielectric layer, and then electrical connection can be achieved. The above problems make the TSV ETCH process more difficult, which reduces the precision of the TSV formed, and then reduces the overall performance of the chip packaging structure.

[0028] On the one hand, after the TSV silicon through hole is completed, the TSV bottom oxide nitride etching (Bottom ONOETCH) needs to be performed. Before the TSV bottom ONO ETCH, it is necessary to ensure that the Si is just etched open. However, in the actual preparation process, due to the difference in the thickness of the Si to be etched and the difference in the wafer temperature at different positions during the low-temperature etching of the stacked wafers, the position of the Si through hole is not completely etched or is over-etched.

[0029] When Si is not completely etched, the subsequent ONO ETCH has a slow etching rate on Si. After ONO ETCH has completed Si etching, when ONO ETCH is performed again, the etching depth of ONO ETCH is insufficient, and ultimately the overall TSVETCH does not stop on the metal, resulting in a short circuit in the chip.

[0030] When Si is over-etched, since the overall etching process parameters (recipe) have almost no etching rate for the dielectric layer, only the lateral Si can be etched, resulting in a Notching bottom side morphology, affecting the overall performance of the chip.

[0031] On the other hand, after TSV Si ETCH etching is completed, the bottom dielectric layer and Liner Oxide (insulating oxide layer) need to be etched in sequence. In the process of etching silicon with the hard mask as a barrier, the surface of the hard mask will have an uneven morphology, especially the raised position at the edge of the TSV hole is easy to attract charges and be etched away first. At the same time, the top hard mask layer and the bottom dielectric layer and Liner Oxide are similar in material, all of which are mainly silicon oxide (SiO2), so the etching rate is similar. While the bottom material is being etched, a large part of the top hard mask layer will also be etched, and finally a trumpet-shaped etching morphology will appear.

[0032] When a trumpet-shaped morphology appears on the top of the wafer, the overall morphology of the TSV will change, and the distance between the TSVs will be shortened, and the electrical performance will be different from the original design. When the TSV distance is close enough to the design and the trumpet-shaped morphology is expanded to a certain extent, the two hole interfaces will contact each other, and eventually the TSV short circuit will occur, which will affect the performance of the subsequently prepared chips.

[0033] Moreover, due to the inclined morphology of the trumpet mouth, the linear insulating oxide layer located on the side wall of the cavity is subsequently etched away during the etching process, so that most of the side wall is not protected by the insulating layer, causing the copper in the TSV to diffuse in the silicon, affecting the electrical performance of the wafer and even causing a short circuit in the TSV.

[0034] To solve at least one of the above problems, the embodiments of the present application provide the following technical solutions: Figure 1 A schematic diagram of a chip packaging structure provided in an embodiment of the present application; Figure 2 A schematic diagram of another chip packaging structure provided in an embodiment of the present application.

[0035] On the one hand, the embodiments of the present application provide a chip packaging structure, such as Figure 1 and Figure 2As shown, the chip packaging structure 1 includes a first wafer 10, a first dielectric layer 11, a second dielectric layer 12, a second wafer 13, and a second conductive structure 14. The first dielectric layer 11 is disposed on the first wafer 10. The second dielectric layer 12 is disposed on a side of the first dielectric layer 11 away from the first wafer 10. The second dielectric layer 12 is provided with a first conductive layer 121 and a first conductive structure 122. For example, the first conductive layer 121 is one of conductive metals such as aluminum (Al), and the first conductive structure 122 is disposed on the first conductive layer 121. Figure 1 The conductive structure in the TSV is shown in FIG. Figure 2 For the contact hole (Contact, CT).

[0036] The first conductive structure 122 is disposed on a side of the first conductive layer 121 away from the first wafer 10, the second dielectric layer 12 includes a first surface 120 away from the first wafer 10, the first conductive structure 122 extends from the first surface 120 into the second dielectric layer 12, and is electrically connected to the first conductive layer 121. The second wafer 13 is disposed on a side of the second dielectric layer 12 away from the first wafer 10. The second conductive structure 14 penetrates the second wafer 13 and is electrically connected to the first conductive structure 122. It can be understood that the first wafer 10 is electrically connected to the second conductive structure 14 through the first conductive layer 121 and the first conductive structure 122 to achieve electrical communication between the first wafer 10 and the second wafer 13.

[0037] For example, Figure 1 As shown, during the back-end process of manufacturing the second wafer 13, the design of a mask of a certain mask Via layer is changed, and a Via pattern is exposed by photolithography at the position where the subsequent TSV is about to land. Subsequently, conventional Damascus processes, namely ETCH, B&S, ECP and CMP processes, are followed to complete the manufacturing of the first conductive structure 122 in advance.

[0038] For example, Figure 2 As shown, in the CT mask, the original design is changed, and in addition to the conventional intermediate structure for interconnecting the device and the metal wire, the first conductive structure (CT) 122 is fabricated in advance at the location of the subsequent TSV Landing. The process of this embodiment can be implemented by following the conventional process without adding additional steps, and the fabrication of the first conductive structure 122 is completed in advance.

[0039] In some embodiments, Figure 1 and Figure 2As shown, the chip packaging structure 1 further includes a third dielectric layer 15, which is disposed between the second conductive structure 14 and the second wafer 13, and the first conductive structure 122 is in direct contact with the second dielectric layer 12. Exemplarily, the third dielectric layer 15 is an insulating oxide layer, which is used to isolate the second conductive structure 14 from the second wafer 13, to prevent over-etching due to different wafer thicknesses during etching of the second wafer 13, thereby avoiding side-digging defects in the second wafer 13.

[0040] The chip packaging structure 1 provided in the embodiment of the present application includes a first wafer 10, a first dielectric layer 11, a second dielectric layer 12, a second wafer 13, and a second conductive structure 14. A first conductive layer 121 and a first conductive structure 122 are provided in the second dielectric layer 12, and a second conductive structure 14 electrically connected to the first conductive structure 122 is provided in the second wafer 13, thereby realizing electrical connection between the first wafer 10 and the second wafer 13. By providing the first conductive structure 122 in advance, the film layer etched to form the second conductive structure 14 is reduced, the side-excavation defect morphology inside the second wafer 13 is avoided, and the trumpet-mouth morphology on the top of the second wafer 13 is avoided, thereby improving the overall yield of the chip packaging structure 1.

[0041] In some embodiments, Figure 1 As shown, a second conductive layer 123 is also provided in the second dielectric layer 12. The second conductive layer 123 is provided on a side of the first conductive layer 121 away from the first wafer 10 and is directly connected to the first conductive layer 121. Exemplarily, the second conductive layer 123 is a metal conductor. The first conductive structure 122 is directly connected to the first conductive layer 121. It can be understood that the first conductive structure 122 and the second conductive layer 123 are electrically connected through the first conductive layer 121 to achieve electrical communication between the three.

[0042] In some embodiments, Figure 2 As shown, the second dielectric layer 12 is further provided with a second conductive layer 123, and the second conductive layer 123 is provided between the first conductive layer 121 and the first conductive structure 122. The first conductive structure 122 is electrically connected to the first conductive layer 121 through the second conductive layer 123. It can be understood that the first conductive structure 122 is directly connected to the second conductive layer 123, and the first conductive structure 122, the second conductive layer 123 and the first conductive layer 121 are vertically stacked in the second dielectric layer 12, and electrical communication is achieved among the three.

[0043] Figure 3 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 4 A schematic diagram of another chip packaging structure provided in an embodiment of the present application; Figure 5A schematic diagram of another chip packaging structure provided in an embodiment of the present application.

[0044] like Figure 1~Figure 5 As shown, there is a clear boundary between the first conductive structure 122 and the second conductive structure 14 , which is a two-stage structure. A third dielectric layer (Liner Oxide) 15 is disposed between the second conductive structure 14 and the second wafer 13 , and no Liner Oxide structure is disposed between the first conductive structure 122 and the second dielectric layer 12 .

[0045] For example, Figure 2~Figure 5 In the chip packaging structure 1 shown, a mask layer 16 is further provided on the side of the second wafer 13 away from the first wafer 10 . The mask layer 16 is a hard mask, which protects the surface of the second wafer 13 away from the first wafer 10 from being etched during the formation of the second conductive structure 14 .

[0046] In some embodiments, Figure 1~Figure 5 As shown, the orthographic projection of the second conductive structure 14 on the first surface 120 at least partially overlaps with the orthographic projection of the first conductive structure 122 on the first surface 120, that is, along the direction Z, the second conductive structure 14 is at least partially located above the first conductive structure 122, and because the etching selectivity ratios of the second conductive structure 14 and the mask layer 16 to the second wafer 13 are different, the second conductive structure 14 and the mask layer 16 will not be etched during the process of etching the second wafer 13 to form the TSV structure, thereby ensuring the product accuracy of the chip packaging structure 1.

[0047] For example, Figure 1 and Figure 2 As shown, the orthographic projection of the second conductive structure 14 on the first surface 120 is completely within the orthographic projection of the first conductive structure 122 on the first surface 120 , and the outer contour of the orthographic projection of the insulating oxide layer 15 on the first surface 120 coincides with the outer contour of the orthographic projection of the first conductive structure 122 on the first surface 120 .

[0048] For example, Figure 3 As shown, the orthographic projections of the second conductive structure 14 and the insulating oxide layer 15 on the first surface 120 are completely located within the orthographic projection of the first conductive structure 122 on the first surface 120; or Figure 4 As shown, the orthographic projection of the second conductive structure 14 on the first surface 120 coincides with the orthographic projection of the first conductive structure 122 on the first surface 120; or Figure 5 As shown, one side contour of the orthographic projection of the second conductive structure 14 on the first surface 120 is located within the orthographic projection of the first conductive structure 122 on the first surface 120 , and the other side contour coincides with the orthographic projection of the first conductive structure 122 on the first surface 120 .

[0049] On the other hand, a method for preparing a chip packaging structure is also provided. Figure 6 A flowchart of the chip packaging structure provided in the embodiment of the present application; Figure 7 to Figure 14 for Figure 6 The steps of the preparation process are shown in Figure 2. Figure 6 As shown, the method for preparing the chip packaging structure includes the following steps S1 to S4: Step S1: Figure 7 As shown, a first dielectric layer 11 is formed on a first wafer 10 to obtain a first bonding structure A.

[0050] Step S2: Figure 8 As shown, a second dielectric layer 12 is formed on the second wafer 13 to obtain a second bonding structure B, and a first conductive layer 121 and a first conductive structure 122 are provided in the second dielectric layer 12. The first conductive layer 121 is provided on a side of the first conductive structure 122 away from the second wafer 13. The second dielectric layer 12 includes a first surface 120 close to a side of the second wafer 13. The first conductive structure 122 extends from the first surface 120 into the second dielectric layer 12 and is electrically connected to the first conductive layer 121.

[0051] In some embodiments, forming Figure 8 The specific steps of forming the second dielectric layer 12 in the method include first forming a first conductive structure 122 and a second conductive layer 123 on the second wafer 12, wherein the second conductive layer 123 is disposed on a side of the first conductive layer 121 away from the first wafer 10 and is directly connected to the first conductive layer 121. Exemplarily, the second conductive layer 123 is a metal conductor. Then, the first conductive layer 121 is formed, wherein the first conductive layer 121 is disposed on a side of the first conductive structure 122 and the second conductive layer 123 away from the second wafer 13, and the first conductive layer 121 is directly connected to the first conductive structure 122 and the second conductive layer 123 to achieve electrical connection between the three.

[0052] In the related process, TSV needs to pass through the top hard mask layer, top dielectric layer, silicon, bottom dielectric layer and liner oxide at one time. In particular, the thickness of silicon reaches tens of microns, so it is more difficult to control the etching of silicon, bottom dielectric layer, liner oxide, etc.

[0053] In the embodiment provided by the present application, during the back-end process of manufacturing the second wafer 13, the design of a mask of a certain mask Via layer is changed, and a Via pattern is exposed by photolithography at the position where the subsequent TSV is about to land. Subsequently, conventional Damascus processes, i.e., ETCH, B&S, ECP, CMP and other processes are followed to complete the manufacturing of the first conductive structure 122 in advance without changing the process flow, thereby reducing the process difficulty and improving the process feasibility.

[0054] Step S3: Fig. 9 As shown, the first bonding structure A is bonded to the second bonding structure B, and the surface of the first dielectric layer 11 away from the first wafer 10 is connected to the surface of the second dielectric layer 12 away from the second wafer 13 .

[0055] Step S4: Fig.10 and Fig.11 As shown, a second conductive structure 14 is formed. The second conductive structure 14 penetrates the second wafer 13 and is electrically connected to the first conductive structure 122 .

[0056] In some embodiments, the specific steps of forming the second conductive structure in step S4 include: Fig.10 As shown, a photolithography process is used to form a photoresist layer (PR) 17 with an opening on the surface of the second wafer 13 away from the first wafer 10 to etch the second wafer 13 to form a via 170 that penetrates the second wafer 13, and the via 170 exposes at least a portion of the first conductive structure 122. In the embodiment provided by the present application, after the Si in the second wafer 13 is etched to the first surface 120, it will touch the first conductive structure (Metal Via) 122. At this time, the plasma will be guided along the metal, so the bottom Notching morphology caused by over-etching will not appear. In addition, since there is no dielectric film layer on the top and no dielectric film layer on the bottom during the TSV etching process, the problem of a trumpet-shaped morphology on the top of the second wafer 13 caused by similar etching rates due to similar materials will not occur, which solves the problem of defective morphology at the top and bottom after TSV ETCH in related processes.

[0057] Then as Fig.11 As shown in FIG. 1 , a third dielectric layer 15 is formed on the sidewall of the via hole 170. The third dielectric layer 15 located on the surface of the second wafer away from the first wafer 10 is removed, and the third dielectric layer 15 in the via hole 170 is retained. Then, a second conductive structure 14 is formed inside the third dielectric layer 15 to form a Figure 1 The chip packaging structure 1 shown in FIG.

[0058] The preparation method provided in the embodiment of the present application is to pre-set the first conductive layer 121 and the first conductive structure 122 in the second dielectric layer 12, form the first dielectric layer 11 on the first wafer 10, obtain the first bonding structure A, bond the first bonding structure A to the second bonding structure B, and then form a penetrating second conductive structure 14 in the second wafer 13, and the first conductive structure 122 is electrically connected to the second conductive structure 14 to form a chip packaging structure 1. Since the first conductive structure 122 is pre-set in the second dielectric layer 12, the film layer etched to form the second conductive structure 14 is reduced, the side-excavation defect morphology inside the second wafer 13 is avoided, and the trumpet-mouth morphology on the top of the second wafer 13 is avoided, thereby improving the overall yield of the chip packaging structure 1.

[0059] In some embodiments, in the above step S2, Fig.12 As shown, the specific steps of forming the second dielectric layer 12 may also include first forming a first conductive structure 122 on the second wafer 13, and then forming a second conductive layer 123, the second conductive layer 123 is located on the side of the first conductive structure 122 away from the second wafer 13, and is electrically connected to the first conductive structure 122. Then, a first conductive layer 121 is formed, the first conductive layer 121 is located on the side of the second conductive layer 123 away from the second wafer 13, and is electrically connected to the second conductive layer 123, so as to form the second dielectric layer 12. The first conductive structure 122, the second conductive layer 123 and the first conductive layer 121 are vertically stacked in the second dielectric layer 12 to achieve electrical connection between the three.

[0060] For example, Fig.12 As shown, in the CT mask, the original design is changed, and in addition to the conventional intermediate structure for interconnecting the device and the metal wire, the first conductive structure (CT) 122 is fabricated in advance at the location of the subsequent TSV Landing. The process of this embodiment can be implemented by following the conventional process without adding additional steps, and the fabrication of the first conductive structure 122 is completed in advance.

[0061] After forming the second dielectric layer 12, Fig.13 As shown, the first bonding structure A is bonded to the second bonding structure B, and the surface of the first dielectric layer 11 away from the first wafer 10 is connected to the surface of the second dielectric layer 12 away from the second wafer 13. Fig.14 As shown, a mask layer 16 having an opening is formed on a surface of the second wafer 13 away from the first wafer 10 to etch the second wafer 13 to form a via hole 160 penetrating the second wafer 13. The via hole 160 exposes at least a portion of the first conductive structure 122. For example, the mask layer 16 is a hard mask. Finally, the second conductive structure 14 is formed to form a Figure 2 The chip packaging structure 1 is shown.

[0062] For example, whether it is CT or Metal Via, the etched through hole needs to stop on the silicon of the second wafer 13, or on the second dielectric layer 12 that is closer to the silicon. A Metal Via mask can be added separately to stop on the silicon of the second wafer 13 or the second dielectric layer 12 that is closer to the silicon, so as to realize the preparation method provided in the embodiment of the present application. In addition, since the thickness of the mask layer 16 in the embodiment of the present application is reduced (or even disappears), the final TSV is almost only as thick as silicon, and the aspect ratio is reduced, which is more conducive to the subsequent Wet Clean, B&S, ECP, Cu CMP and other processes.

[0063] On the other hand, the present application also provides an electronic device, Fig.15 A schematic diagram of an electronic device provided in an embodiment of the present application, such as Fig.15 As shown, the electronic device 2 includes the chip packaging structure 1 and the circuit board 21 mentioned above. Figure 1 The chip packaging structure 1 shown is used as an example for explanation. The chip packaging structure 1 is arranged on a circuit board 21 and is electrically connected to the circuit board 21. Exemplarily, the chip packaging structure 1 is electrically connected to the circuit board 21 via solder balls 20. In the electronic device 2 provided in the embodiment of the present application, the preparation accuracy and overall yield of the chip packaging structure 1 are improved, thereby improving the reliability of the electronic device 2.

[0064] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: include: First Wafer; A first dielectric layer is disposed on the first wafer; A second dielectric layer is disposed on a side of the first dielectric layer away from the first wafer; The second dielectric layer is provided with a first conductive layer and a first conductive structure, wherein the first conductive structure is provided on a side of the first conductive layer away from the first wafer; the second dielectric layer includes a first surface away from the first wafer, and the first conductive structure extends from the first surface into the second dielectric layer and is electrically connected to the first conductive layer; A second wafer is disposed on a side of the second dielectric layer away from the first wafer; The second conductive structure penetrates the second wafer and is electrically connected to the first conductive structure.

2. The chip packaging structure according to claim 1, characterized in that: A second conductive layer is also disposed in the second dielectric layer, and the second conductive layer is disposed on a side of the first conductive layer away from the first wafer and is directly connected to the first conductive layer; The first conductive structure is directly connected to the first conductive layer.

3. The chip packaging structure according to claim 1, characterized in that: A second conductive layer is further disposed in the second dielectric layer, and the second conductive layer is disposed between the first conductive layer and the first conductive structure; The first conductive structure is electrically connected to the first conductive layer through the second conductive layer.

4. The chip packaging structure according to claim 1, characterized in that: The orthographic projection of the second conductive structure on the first surface at least partially overlaps with the orthographic projection of the first conductive structure on the first surface.

5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes a third dielectric layer, wherein the third dielectric layer is disposed between the second conductive structure and the second wafer; The first conductive structure is in direct contact with the second dielectric layer.

6. A method for preparing a chip packaging structure, characterized in that: include: forming a first dielectric layer on a first wafer to obtain a first bonding structure; A second dielectric layer is formed on the second wafer to obtain a second bonding structure; a first conductive layer and a first conductive structure are provided in the second dielectric layer, the first conductive layer is provided on a side of the first conductive structure away from the second wafer; the second dielectric layer includes a first surface close to a side of the second wafer, the first conductive structure extends from the first surface into the second dielectric layer, and is electrically connected to the first conductive layer; Bonding the first bonding structure to the second bonding structure, so that a surface of the first dielectric layer away from the first wafer is connected to a surface of the second dielectric layer away from the second wafer; A second conductive structure is formed, wherein the second conductive structure penetrates the second wafer and is electrically connected to the first conductive structure.

7. The preparation method according to claim 6, characterized in that: Forming the second dielectric layer includes: forming the first conductive structure and the second conductive layer on the second wafer; A first conductive layer is formed, where the first conductive layer is located on a side of the first conductive structure and the second conductive layer away from the second wafer; the first conductive layer is directly connected to the first conductive structure and the second conductive layer.

8. The preparation method according to claim 6, characterized in that: Forming the second dielectric layer includes: forming the first conductive structure on the second wafer; forming a second conductive layer, wherein the second conductive layer is located on a side of the first conductive structure away from the second wafer and is electrically connected to the first conductive structure; A first conductive layer is formed, where the first conductive layer is located on a side of the second conductive layer away from the second wafer and is electrically connected to the second conductive layer.

9. The preparation method according to claim 6, characterized in that: Forming the second conductive structure includes: Using a photolithography process, etching the second wafer to form a via hole penetrating the second wafer, wherein the via hole exposes at least a portion of the first conductive structure; forming a third dielectric layer on the sidewall of the via hole; The second conductive structure is formed inside the third dielectric layer, and the second conductive structure is electrically connected to the first conductive structure.

10. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 5; A circuit board, the chip packaging structure is arranged on the circuit board and is electrically connected to the circuit board.

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