Semiconductor wafer and method for manufacturing same
By designing semiconductor chips with different types of electrical defects, the problems of unstable detection capabilities of electron beam equipment and poor consistency of traditional detection samples are solved, and an efficient and low-cost defect detection method is achieved.
Patent Information
- Application Number
- CN202311237086.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-21
- Publication Date
- 2025-03-21
AI Technical Summary
When the prior art detects electrical defects in integrated circuits, the detection capability of the electron beam device is unstable, the repetition and consistency of traditional detection samples are poor, and the preparation cost is high.
A semiconductor wafer is designed, including a new structure with different types of electrical defects, and provides a low-cost defect detection method by building repeatable and consistent detection sample wafers.
It realizes efficient and low-cost quantification and evaluation of the defect detection capabilities of electron beam detection equipment, and provides reliable defect detection methods, suitable for electrical defect detection at different process nodes.
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Figure CN119673917A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuits, and in particular, to a semiconductor wafer for defect detection and a preparation method thereof. Background Art
[0002] Defect detection methods in integrated circuit production processes are usually based on traditional optical imaging inspections such as bright and dark fields. However, as the integrated circuit industry moves towards more advanced process nodes, the key dimensions of integrated circuits continue to shrink, which places higher requirements on the detection of electrical defects. In some cases, electron beams can be used to scan semiconductor wafers to produce voltage contrast (VC) images to detect electrical defects at the bottom layer of semiconductor devices. Different electron beam inspection equipment has different detection capabilities for electrical defects, and even the detection capabilities of the same electron beam inspection equipment will deteriorate over time. This results in unstable detection capabilities of electron beam equipment for electrical defects.
[0003] Currently, the detection capability of electron beam inspection equipment for wafer defects is calibrated by using samples used for defect detection. However, conventional inspection samples introduce defects only by controlling process parameters of conventional device structures, which results in large scale or size of defects. In addition, the repeatability and consistency of inspection samples are poor and the preparation cost is high due to the special process. Summary of the invention
[0004] In view of the above problems, the embodiments of the present disclosure are intended to provide a semiconductor wafer for defect detection. For example, a test sample with electrical defect distribution can be constructed at low cost, and the detection capability of an electron beam inspection device for electrical defects can be quantified and evaluated.
[0005] According to the first aspect of the present disclosure, a semiconductor wafer is provided, comprising: a first type of semiconductor device, wherein the semiconductor device in the first type of semiconductor device comprises: a first active region; a first insulating layer, located on the first active region; and a first via, located on the first insulating layer, the first insulating layer insulates the first active region from the first via; and a second type of semiconductor device, wherein the semiconductor device in the second type of semiconductor device comprises: a second active region, including a first doping type region and a second doping type region; a first conductive layer, located on the second active region and electrically connected to the first doping type region and the second doping type region; and a second via, located on the first conductive layer and electrically connected to the first conductive layer. In this way, a sample wafer for detecting electrical defects that is repeatable and highly consistent can be formed by using a semiconductor wafer with a new structure having different types of electrical defects.
[0006] In some embodiments of the first aspect, the semiconductor wafer further includes: a third type of semiconductor device, wherein the semiconductor device in the third type of semiconductor device includes: a third active region, including a first doping type region and a second doping type region; a second conductive layer, located on the third active region and electrically connected to one of the first doping type region and the second doping type region; and a third via, located on the second conductive layer and electrically connected to the second conductive layer. In this way, by constructing a device with normal electrical connection corresponding to a device with electrical defects, a low-cost and high-precision comparison sample structure is formed. By providing the defect structure and the comparison structure together in the same wafer, reliable defect detection can be provided in a simple, intuitive and low-cost manner.
[0007] In some embodiments of the first aspect, the first type of semiconductor devices includes a first group of devices and a second group of devices, and the device size of the first group of devices is different from the device size of the second group of devices. In this way, by designing devices of different sizes, the test sample can support the detection of electrical defects for different process nodes.
[0008] In some embodiments of the first aspect, the second type of semiconductor devices includes a third group of devices and a fourth group of devices, and the device size of the third group of devices is different from the device size of the fourth group of devices. In this way, by designing devices of different sizes, the test sample can support the detection of electrical defects for different process nodes.
[0009] In some embodiments of the first aspect, the first type of semiconductor device and the second type of semiconductor device are located in the first bare die area of the semiconductor wafer. In this way, by reasonably planning the distribution of devices with electrical defects and devices with normal electrical connections, the defect distribution law of the actual production line can be reflected as accurately as possible.
[0010] In some embodiments of the first aspect, the semiconductor wafer further includes: a second die region, the second die region has the same device distribution as the first die region, and a third type of semiconductor device is arranged at a position in the second die region corresponding to the first type of semiconductor device and the second type of semiconductor device in the first die region. In this way, by reasonably planning the distribution of devices with electrical defects and devices with normal electrical connections, the defect distribution law of the actual production line can be reflected as accurately as possible.
[0011] In some embodiments of the first aspect, the first active region includes: a first doping type well; and a second doping type region located in the first doping type well, and the first insulating layer covers the surfaces of the first doping type well and the second doping type region. In this way, an electrical defect with a disconnected connection is constructed through a simplified design to realize a detection sample with controllable position and size.
[0012] In some embodiments of the first aspect, the semiconductor device in the first type of semiconductor device further includes: a trench located outside the first doping type well and extending from the first insulating layer toward the substrate.
[0013] In some embodiments of the first aspect, the semiconductor device in the second type of semiconductor device further includes: a second insulating layer located in the same layer as the first conductive layer and covering at least a portion of the first doping type region and the second doping type region. In this way, an electrical defect with a short circuit connection is constructed through a simplified design to realize a detection sample with controllable position and size.
[0014] In some embodiments of the first aspect, the first conductive layer includes a titanium nitride (TiN) layer; and the first insulating layer includes a silicon nitride (Si3N4) layer.
[0015] According to a second aspect of the present disclosure, an electron beam inspection system is provided, comprising: a semiconductor wafer according to the first aspect of the present disclosure; and an electron beam inspection device configured to perform electron beam inspection on the semiconductor wafer to generate an inspection pattern. In this way, by using semiconductor wafers with different types of electrical defects that are repeatable and highly consistent as sample wafers for defect inspection, the defect detection capability of the electron beam inspection device over time or of different electron beam inspection devices can be quantified or evaluated efficiently and at low cost.
[0016] In some embodiments of the second aspect, the inspection pattern includes a reference pattern representing a distribution of defect-free devices and a defect pattern representing a distribution of defective devices. In this way, by providing the defect structure and the reference structure together on the same wafer for defect inspection, the defect inspection capability of the electron beam inspection device can be quantitatively evaluated in a simple, intuitive and low-cost manner.
[0017] In some embodiments of the second aspect, the electron beam inspection system further comprises: a processor configured to generate analysis data representing the inspection performance of the electron beam inspection device based on the inspection pattern. In this way, the defect detection capability of the electron beam inspection device can be quantified or evaluated efficiently and in real time through image processing.
[0018] According to a third aspect of the present disclosure, a method for manufacturing a semiconductor wafer is provided, comprising: generating a first type of semiconductor device, comprising: forming a first active region in a semiconductor substrate; depositing a first insulating layer on the first active region; and forming a first via layer on the first insulating layer, the first via layer comprising a first via located in an insulating material; and generating a second type of semiconductor device, comprising: forming a second active region in a semiconductor substrate, the second active region comprising a first doping type region and a second doping type region; forming a first conductive layer on the second active region, the first conductive layer being electrically connected to the first doping type region and the second doping type region; and forming a second via layer on the first conductive layer, the second via layer comprising a second via electrically connected to the first conductive layer. In this way, by changing the relative positional relationship between the conductive layer and the active region, different types of electrical defect structures can be constructed simply and randomly as desired.
[0019] In some embodiments of the third aspect, the method further includes: generating a third type of semiconductor device, including: forming a third active region in a semiconductor substrate, the third active region including a first doping type region and a second doping type region; forming a second conductive layer on the third active region, the second conductive layer being electrically connected to one of the first doping type region and the second doping type region; and forming a third via layer on the second conductive layer, the third via layer including a third via electrically connected to the second conductive layer. In this way, by providing the defect structure and the contrast structure together in the same wafer, reliable defect detection can be provided in a simple, intuitive and low-cost manner. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] The above and other features, advantages and other aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:
[0021] Figure 1 A schematic diagram of an electron beam inspection system for defect detection according to an embodiment of the present disclosure is shown;
[0022] Figure 2 shows a cross-sectional view of a semiconductor wafer for defect detection according to an embodiment of the present disclosure;
[0023] Figure 3 A schematic plan view of a minimum repeating unit of a semiconductor wafer for defect detection according to an embodiment of the present disclosure is shown;
[0024] Figure 4 A schematic diagram showing the distribution of test patterns on a semiconductor wafer for defect detection according to an embodiment of the present disclosure is shown;
[0025] Figure 5A schematic diagram showing the distribution of test patterns on a semiconductor wafer for defect detection according to another embodiment of the present disclosure is shown;
[0026] Figure 6 A schematic diagram showing distribution of test patterns on a semiconductor wafer for defect detection according to yet another embodiment of the present disclosure is shown;
[0027] Figure 7 A flow chart of preparing a semiconductor wafer for defect detection according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0028] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, which are instead provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.
[0029] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or identical objects. Other explicit and implicit definitions may also be included below. The term "and / or" means at least one of the two items associated with it. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below. In addition, even in the case of describing a specific numerical example, in addition to being obviously limited to a numerical value in theory, it can be a numerical value exceeding a specific numerical value, or it can be a numerical value less than a specific numerical value.
[0030] It should be understood that in the technical solutions provided by the embodiments of the present application, some repetitions may not be repeated in the introduction of the following specific embodiments, but these specific embodiments should be regarded as having been referenced to each other and can be combined with each other.
[0031] As mentioned above, with the continuous reduction of the critical dimensions of integrated circuits, higher requirements are placed on the detection of electrical defects in terms of accuracy and efficiency. In some cases, for example, an electron beam detection system is used to detect defects in semiconductor wafers, such as unexpected open circuits or short circuit defects. However, as the process nodes are reduced, some electron beam detection systems may not be able to detect defects at smaller scales. In addition, the performance of the electron beam detection system may also gradually decrease with use. In order to evaluate and quantify the defect detection performance of the electron beam detection system, some sample test wafers with known sample defect distributions can be used to measure the performance of the electron beam detection system. In order to manufacture such sample test wafers, in some related technologies, defects are introduced by controlling the process parameters of conventional device structures. This will result in large defects in size and scale, and cannot reflect the defect distribution in the actual production line as the process nodes are reduced.
[0032] The embodiment of the present disclosure provides a semiconductor wafer for defect detection. The semiconductor wafer includes: a first type of semiconductor device, the semiconductor device in the first type of semiconductor device includes: a first active area; a first insulating layer, located on the first active area; and a first via, located on the first insulating layer, the first insulating layer insulates the first active area from the first via; and a second type of semiconductor device, the semiconductor device in the second type of semiconductor device includes: a second active area, including a first doping type area and a second doping type area; a first conductive layer, located on the second active area and electrically connected to the first doping type area and the second doping type area; and a second via, located on the first conductive layer and electrically connected to the first conductive layer. By using a semiconductor wafer with a new structure having different types of electrical defects, a repeatable and highly consistent sample wafer for detecting electrical defects can be formed.
[0033] Figure 1 A schematic diagram of an electron beam inspection system 100 for defect detection according to an embodiment of the present disclosure is shown. The electron beam inspection system 100 includes a semiconductor wafer 10 to be inspected and an electron beam inspection device (not shown in full). In some embodiments, the electron beam inspection device includes an electron beam gun 20 and an electron detector 40. The electron beam gun 20 is configured to emit an electron beam 30 for bombarding the surface of the semiconductor wafer 10. The electron beam 30 is incident on and scans a specific area of the semiconductor wafer 10, so that the incident electrons interact with the wafer surface to excite secondary electrons for imaging. The electron detector 40 is used to capture the generated secondary electrons and generate a scanning electron microscope (SEM) image.
[0034] The SEM image has a voltage contrast of light and dark, depending on the amount of secondary electrons captured at different locations on the wafer. The voltage contrast map can be used as a detection pattern that provides information about defective devices. In some embodiments, the detection pattern includes a reference pattern representing the distribution of defect-free devices and a defect pattern representing the distribution of defective devices. Figures 2 to 5 A test pattern corresponding to the detection pattern on the semiconductor wafer 10 for defect detection is described. In some embodiments, the electron beam inspection system 100 further includes a processor (not shown). The processor is configured to generate analysis data representing the detection performance of the electron beam inspection device based on the detection pattern (see Table 1).
[0035] The electron beam gun 20 can emit an electron beam 30 for detection in a high energy mode and a low energy mode. In some embodiments, in the high energy mode operation, the electron beam 30 generally has an energy greater than 2KV, bombarding the wafer surface to make it negatively charged. Therefore, this mode is also called a negative mode. In some embodiments, in the low energy mode operation, the electron beam 30 generally has an energy less than 1KV, bombarding the wafer surface to make it positively charged, therefore, this mode is also called a positive mode. It should be understood that in other embodiments, the energy of the electron beam 30 can be other values or ranges, and the present disclosure is not limited thereto.
[0036] Specifically, in the positive mode, the more positive charges accumulate on the surface of the wafer, the fewer secondary electrons the electron detector can capture, that is, the darker it appears in the SEM image, and vice versa. In the negative mode, the more negative charges accumulate on the surface of the wafer, the brighter it appears in the SEM image, and vice versa. In this way, a light and dark contrast corresponding to the operating mode for different electrical defects will appear in the SEM image. In some embodiments, the voltage contrast of the same electrical defect in different operating modes will be reversed. In this case, the semiconductor wafer 10 can be inspected by alternating scanning in the positive mode and the negative mode, so that the electrical defects can be located quickly and accurately. The following will be combined with Figure 2 To describe the voltage contrast of different electrical defects in different modes.
[0037] Figure 2A cross-sectional view of a semiconductor wafer 200 for defect detection according to an embodiment of the present disclosure is shown. The semiconductor wafer 200 includes a semiconductor substrate 201 and a trench STI located in the semiconductor substrate 201. The trench STI extends to the surface of the semiconductor substrate 201 along the thickness direction of the semiconductor substrate 201 and is configured to electrically isolate the semiconductor devices 210, 220 and 230 from each other. In some embodiments, the semiconductor substrate 201 may be a Si-based semiconductor substrate having an N conductive type. In other embodiments, the semiconductor substrate 201 may be a Si-based semiconductor substrate having a P conductive type. The present disclosure does not limit the material and doping type of the semiconductor substrate.
[0038] The semiconductor devices 210, 220 and 230 each include an active region 240 disposed in the semiconductor substrate 201. The active region 240 is a region having carriers (electrons or holes) that participate in conduction. In some embodiments, in a MOS semiconductor device, the active region 240 refers to a source region or a drain region of a transistor. In other embodiments, in a bipolar transistor, the active region 240 refers to a base region between an emitter junction and a collector junction. N-type or P-type doped active regions are achieved by injecting different impurity atoms into the semiconductor substrate 201. The active region 240 of each semiconductor device in the semiconductor devices 210, 220 and 230 may be of the same conductivity type or of different conductivity types.
[0039] In some embodiments, the active region 240 includes a first doping type region 206 and a second doping type region 207 located in the first doping type region 206. The first doping type may be N-type or P-type, and correspondingly, the second doping type may be P-type or N-type. The present disclosure does not limit the doping type in the active region 240.
[0040] like Figure 2 As shown, the semiconductor device 210 also includes a conductive layer 205 and a via structure 204 that contacts and is electrically connected to the conductive layer 205 above the conductive layer 205. The conductive layer 205 is disposed above the second doping type region 207 of the active region 240 and is electrically connected to the second doping type region 207. The conductive layer 205 is formed by etching a position corresponding to the active region 240 of the connection layer 202 formed above the semiconductor body substrate 201 to form an opening, and filling the opening with a conductive material to form the conductive layer 205. In some embodiments, the connection layer 202 may include one or more of SiO2 and Si3N4. In other embodiments, the connection layer 202 may also include other isolation materials, which are not limited in the present disclosure. In some embodiments, the conductive material may include an alloy material such as TiN or TiW. In other embodiments, the conductive material may also be other materials having adhesion and diffusion barrier effects, which are not limited in the present disclosure.
[0041] In some embodiments, the via structure 204 is formed by etching the corresponding position of the contact layer 203 located above the connection layer 202 to form a via, and filling the via with a metal column. The metal column includes, but is not limited to, metal materials such as copper, silver, tungsten, and titanium. In some embodiments, the via structure 204 can also be composed of other non-metallic conductive materials, which is not limited by the present disclosure. In some embodiments, the contact layer 203 includes one or more of SiO2 and Si3N4. In other embodiments, the contact layer 203 can also include other isolation materials, which is not limited by the present disclosure.
[0042] In the semiconductor device 210, the first doping type region 206 and the second doping type region 207 form a PN junction, and the via structure 204 is coupled to the first doping type region 206 via both the conductive layer 205 and the second doping type region 207. In this case, the semiconductor device 210 represents a device with normal electrical connection. In some embodiments, when the first doping type region 206 has a P-type conductivity type and the second doping type region 207 has an N-type conductivity type, when the electron beam 30 with low energy is incident on the surface of the semiconductor device 210, the PN junction formed by the two is reverse biased to the positive charge, so that the positive charge is accumulated on the surface of the via structure 204 of the semiconductor device 210. At this time, as described above, the via structure 204 of the semiconductor device 210 appears as normal dark in the SEM image.
[0043] In other embodiments, when the first doping type region 206 has an N-type conductivity type and the second doping type region 207 has a P-type conductivity type, when the electron beam 30 with low energy is incident on the surface of the semiconductor device 210, the PN junction formed by the two is positively biased to positive charges, so that the positive charges leak through the conductive path formed by the conductive layer 205 and the via structure 204, so that the positive charges cannot be accumulated on the surface of the via structure 204 of the semiconductor device 210. At this time, as described above, the via structure 204 of the semiconductor device 210 appears normally bright in the SEM image.
[0044] In the semiconductor device 220, its active area 240 and the via structure 204 have the same or similar structure / material / component as the active area and the via structure of the semiconductor device 210, so they are not repeated here. The semiconductor device 220 also includes an insulating layer 208 located above the active area and electrically isolating it from the via structure 204. In some embodiments, the insulating layer 208 includes one or more of SiO2 and Si3N4. It should be understood that in other embodiments, the insulating layer 208 may also include other insulating materials, which is not limited by the present disclosure. In some embodiments, the insulating layer 208 has the same or similar components or structures as the connecting layer 202.
[0045] In this case, the via structure 204 is not electrically connected to the active area 240, that is, an open circuit is achieved. The semiconductor device 220 represents a device with an open circuit defect. Due to the presence of the insulating layer 208, the positive charges formed by the low-energy electron beam 30 incident on the surface of the semiconductor device 220 have no leakage path, so they are accumulated in large quantities on the surface of the via structure 204 of the semiconductor device 220. At this time, compared with the semiconductor device 210, the via structure 204 of the semiconductor device 220 is displayed as darker in the SEM image, which is abnormally dark and is called a dark voltage contrast (DVC) defect.
[0046] Similarly, in the negative operation mode, due to the presence of the insulating layer 208, the negative charges formed by the high energy electron beam 30 incident on the surface of the semiconductor device 220 have no leakage path, and thus are largely accumulated on the surface of the via structure 204 of the semiconductor device 220. At this time, as described above, the via structure 204 of the semiconductor device 220 appears bright in the SEM image. Therefore, in some embodiments, the electron beam 30 can be emitted alternately in the positive mode and the negative mode to avoid defect detection errors caused by too low contrast.
[0047] In the semiconductor device 230, its active region 240, via structure 204 and conductive layer 205 have the same or similar structure / material / component as the active region, via structure and conductive layer 205 of the semiconductor device 210, so they are not described here. The difference between the semiconductor device 230 and the semiconductor device 210 is that the position of the conductive layer 205 is offset relative to the active region 240, so that the conductive layer 205 is electrically connected to both the first doping type region 206 and the second doping type region 207. The semiconductor device 230 represents a device with a short circuit. In this case, the charges accumulated on the surface of the via structure 204 of the semiconductor device 230 flow to the active region 240 through the conductive path formed by the conductive layer 205 and the via structure 204.
[0048] In some embodiments, when the first doping type region 206 has a P-type conductivity type and the second doping type region 207 has an N-type conductivity type, when the electron beam 30 with low energy is incident on the surface of the semiconductor device 230, the positive charge at the surface leaks through the conductive path, so that the positive charge accumulated on the surface becomes less. At this time, compared with the semiconductor device 210, the via structure 204 of the semiconductor device 230 appears bright in the SEM image, which is abnormally bright and is called a bright voltage contrast (BVC) defect. Similarly, in the negative operation mode, the negative charge formed by the high energy electron beam 30 incident on the surface of the semiconductor device 220 leaks through the conductive path, so that the negative charge accumulated on the surface becomes less. At this time, compared with the semiconductor device 210, the via structure 204 of the semiconductor device 230 appears dark in the SEM image.
[0049] Thus, for the semiconductor devices 210, 220, and 230 described above, by selecting the materials and / or positions of the active regions 240, the via structures 204, and the connection layer 202 therebetween, electrical defects including short circuit defects and open circuit defects can be controlled and designed randomly as desired. Compared to conventional device structures that construct large-scale and large-sized wafers by controlling process parameters such as doping or etching, in some embodiments of the present disclosure, the method of constructing open circuit and short circuit defect structures of different sizes according to the desired distribution (e.g., random) is more flexible and convenient to detect the defect detection performance of the electron beam detection device, and can be more suitable for the defect detection of the electron beam detection device for miniaturized wafer defect detection moving towards the nanometer size.
[0050] Figure 3 FIG. 3 is a schematic plan view of a minimum repeating unit 300 and 300 ′ of a semiconductor wafer for defect detection according to an embodiment of the present disclosure. Figure 3 As shown, the minimum repeating units 300 and 300' respectively include an active region 302 located in a semiconductor substrate, a via structure 306 located in a contact layer at the top layer of the semiconductor device, and a connection layer 304 between the active region 302 and the via structure 306. The difference between the minimum repeating units 300 and 300' is the shape of the via structure 306 in a plan view. The via structure 306 can be formed into a circular, elliptical, square or any other shape in a plan view. The present disclosure is not limited to this.
[0051] As mentioned above about Figure 2As described above, by selecting the material of the connection layer 304 and the position relative to the active area 303, a semiconductor device 210 with normal electrical connection, a semiconductor device 220 with an open circuit defect, and a semiconductor device 230 with a short circuit defect are constructed. The semiconductor devices with electrical defects are randomly distributed on the semiconductor crystal through a random algorithm to form a test pattern, as shown below. Figure 4 to describe.
[0052] Figure 4 FIG. 4 shows a schematic diagram of the distribution of test patterns 400 on a semiconductor wafer according to an embodiment of the present disclosure. Figure 4 In FIG. 4 , only a portion of the test pattern on the semiconductor wafer is shown. The portion shown includes a first die area 410 and a second die area 420. In the first die area 410, only the semiconductor device 210 ( Figure 2 The black dots and white dots in the area 410 are arranged in rows and alternately, and schematically represent the Figure 2 The via structure 204 of the semiconductor device 210 described above appears in a SEM image with contrast, that is, black represents darkness and white represents light.
[0053] In the second die region 420, randomly distributed electrical defects are arranged at positions corresponding to the first die region 410. Figure 4 As shown, the BVC defect and the DVC defect circled in circles are schematically shown. In this way, the first die area 410 and the second die area 420 are scanned by an electron beam detection device to form a SEM scan image. The SEM scan image is processed to obtain a detection pattern corresponding to the test pattern 400. The detection pattern includes a voltage contrast pattern representing the distribution of defect-free devices and a voltage contrast pattern representing the distribution of defective devices, thereby providing defect distribution information and quickly locating the defect position.
[0054] Figure 5 FIG. 5 shows a schematic diagram of the distribution of test patterns 500 on a semiconductor wafer according to another embodiment of the present disclosure. Figure 5 In FIG. 5 , only a portion of the test pattern on the semiconductor wafer is shown. The portion shown includes a bare die area 510, in which a semiconductor device 210 with normal electrical connection (left) and a semiconductor device with electrical defects (right) are arranged. Figure 5 FIG. 1 schematically shows the BVC defect and the DVC defect circled in FIG. Figure 4 The difference is, Figure 5 The via structure of the semiconductor device is designed to have an elliptical shape.
[0055] Figure 6FIG. 4 shows a schematic diagram of the distribution of test patterns 600 on a semiconductor wafer according to another embodiment of the present disclosure. Figure 6 , a semiconductor wafer 610 and semiconductor device sets M0-M5 on the semiconductor wafer 610 are shown. The semiconductor device sets M0 to M5 may each include the aforementioned test pattern 400 and / or test pattern 500. In some embodiments, the minimum repeating unit size of the semiconductor device sets M0 to M5 may be 50nm, 100nm, 150nm, 200nm, 300nm and 400nm, respectively. By designing semiconductor devices of different sizes for defect detection on the same semiconductor wafer, the detection wafer can support the detection of electrical defects for different process nodes.
[0056] Figure 6 The sizes and relative positions of the semiconductor body device sets M0-M5 in the drawings are not necessarily drawn to scale. For example, the shapes and angles of the various sets are not drawn to scale, and some of the sets are enlarged and positioned to improve the readability of the drawing. In addition, the specific shapes of the depicted sets are not necessarily intended to convey any information about the actual shape of the specific sets, but are selected only for ease of identification in the drawings.
[0057] The following describes the quantification and evaluation of the detection capabilities and limits of BVC defects and DVC defects for different electron beam inspection devices (shown as devices A, B and C) in conjunction with Table 1. It should be understood that devices A, B and C can also refer to different batches of the same model of equipment, which is not limited herein.
[0058] Table 1
[0059]
[0060] Using a semiconductor wafer with a detection pattern 600 as a detection sample, the defect detection capabilities of devices A, B, and C can be quantified. As shown in Table 1, device A has a high defect detection rate for each size of device set, so device A has the highest total defect detection rate. In addition, device A also has the highest detection limit (50nm), can detect more than 50% of M0 (50nm) VC defects, and has a good defect capture rate (98%), but there are some false detections (50%). Device C has the lowest detection limit (200nm), can only detect 70% of M3 (200nm) VC defects, but has the lowest false grasp rate. The defect capture rate (86%) of device B is lower than that of device A but higher than that of device C. Its false grasp rate is also lower than that of device A but higher than that of device C. From the perspective of false grasp rate, device C is the best.
[0061] In some embodiments, the above semiconductor wafer 610 can also be used to evaluate the degradation of the detection capability of the same electron beam detection device over time. Therefore, by controllably designing the size, location and number of defects, standard samples for quantifying and evaluating the detection capability of the electron beam detection device are prepared on a large scale, thereby performing quality control and regular calibration of the electron beam detection device.
[0062] Figure 7 A flow chart 700 of a method for preparing a semiconductor wafer according to an embodiment of the present disclosure is shown. Figure 2 The method 700 is described as follows. In block 702, a first type of semiconductor device 220 is generated, including: forming a first active region 240 in a semiconductor substrate 201; depositing a first insulating layer 208 on the first active region 240; and forming a first via layer 203 on the first insulating layer 208, the first via layer 203 including a first via 204 located in an insulating material.
[0063] In frame 704, a second type semiconductor device 230 is generated, including: forming a second active region 240 in the semiconductor substrate 201, the second active region including a first doping type region 206 and a second doping type region 207; forming a first conductive layer 205 on the second active region 240, the first conductive layer 205 being electrically connected to the first doping type region 206 and the second doping type region 207; and forming a second via layer 203 on the first conductive layer 205, the second via layer 203 including a second via 204 electrically connected to the first conductive layer 205.
[0064] In frame 706, a third type semiconductor device 210 is generated, including: forming a third active region 240 in the semiconductor substrate 201, the third active region 240 including a first doping type region 206 and a second doping type region 207; forming a second conductive layer 205 on the third active region 240, the second conductive layer being electrically connected to one of the first doping type region 206 and the second doping type region 207; and forming a third via layer 203 on the second conductive layer 205, the third via layer 203 including a third via 204 electrically connected to the second conductive layer 205.
[0065] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.
[0066] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.
Claims
1. A semiconductor wafer, comprising: The first type of semiconductor devices, wherein the semiconductor devices in the first type of semiconductor devices include: a first active region; a first insulating layer, located on the first active region; and a first via hole located on the first insulating layer, wherein the first insulating layer insulates the first active area from the first via hole; and The second type of semiconductor devices, wherein the semiconductor devices in the second type of semiconductor devices include: A second active region, comprising a first doping type region and a second doping type region; a first conductive layer located on the second active region and electrically connected to the first doping type region and the second doping type region; and The second via hole is located on the first conductive layer and is electrically connected to the first conductive layer.
2. The semiconductor wafer according to claim 1, further comprising: The third type of semiconductor device, the semiconductor device in the third type of semiconductor device includes: A third active region, comprising a first doping type region and a second doping type region; a second conductive layer located on the third active region and electrically connected to one of the first doping type region and the second doping type region; and The third via hole is located on the second conductive layer and is electrically connected to the second conductive layer. 3 . The semiconductor wafer according to claim 1 , wherein the first type of semiconductor devices comprises a first group of devices and a second group of devices, a device size of the first group of devices being different from a device size of the second group of devices. 4 . The semiconductor wafer according to claim 1 , wherein the second type of semiconductor devices comprises a third group of devices and a fourth group of devices, and a device size of the third group of devices is different from a device size of the fourth group of devices. 5 . The semiconductor wafer according to claim 2 , wherein the first type of semiconductor devices and the second type of semiconductor devices are located in a first die region of the semiconductor wafer. 6 .
6. The semiconductor wafer according to claim 5, further comprising: A second die region, wherein the second die region has the same device distribution as the first die region, and a third type of semiconductor device is arranged at a position in the second die region corresponding to the first type of semiconductor device and the second type of semiconductor device in the first die region.
7. The semiconductor wafer according to any one of claims 1 to 6, wherein the first active area comprises: a first doping type well; as well as The second doping type region is located in the first doping type well, and the first insulating layer covers surfaces of the first doping type well and the second doping type region.
8. The semiconductor wafer according to claim 7, wherein the semiconductor devices in the first type of semiconductor devices further include: A trench is located outside the first doping type well and extends from the first insulating layer to the substrate.
9. The semiconductor wafer according to any one of claims 1 to 8, wherein the semiconductor devices in the second type of semiconductor devices further include: The second insulating layer is located at the same layer as the first conductive layer and covers at least a portion of the first doping type region and the second doping type region.
10. The semiconductor wafer according to any one of claims 1 to 9, wherein The first conductive layer includes a titanium nitride (TiN) layer; and The first insulating layer includes a silicon nitride (Si3N4) layer.
11. An electron beam detection system comprising: A semiconductor wafer according to any one of claims 1 to 10; as well as The electron beam testing device is configured to perform electron beam testing on the semiconductor wafer to generate a testing pattern.
12. The electron beam inspection system of claim 11, wherein the inspection pattern comprises a reference pattern representing a distribution of non-defective devices and a defect pattern representing a distribution of defective devices.
13. The electron beam detection system according to claim 11 or 12, further comprising: A processor is configured to generate analysis data representing detection performance of the electron beam detection device based on the detection pattern.
14. A method for manufacturing a semiconductor wafer, comprising: Generate the first class of semiconductor devices, including: forming a first active region in a semiconductor substrate; depositing a first insulating layer on the first active region; and forming a first via layer on the first insulating layer, the first via layer comprising a first via located in an insulating material; and Generate the second type of semiconductor devices, including: forming a second active region in the semiconductor substrate, the second active region comprising a first doping type region and a second doping type region; forming a first conductive layer on the second active region, the first conductive layer being electrically connected to the first doping type region and the second doping type region; and A second via layer is formed on the first conductive layer, wherein the second via layer includes a second via electrically connected to the first conductive layer.
15. The method according to claim 14, further comprising: Generates the third class of semiconductor devices, including: forming a third active region in the semiconductor substrate, the third active region comprising a first doping type region and a second doping type region; forming a second conductive layer on the third active region, the second conductive layer being electrically connected to one of the first doping type region and the second doping type region; and A third via layer is formed on the second conductive layer, wherein the third via layer includes a third via electrically connected to the second conductive layer.