Silicon carbide-based metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention provides a silicon carbide-based metal oxide semiconductor field effect transistor and a method. The silicon carbide-based metal oxide semiconductor field effect transistor comprises a substrate; the first n-type epitaxial layer and the second n-type epitaxial layer are sequentially stacked on the first surface of the substrate, and through grooves are formed in the middles of the first n-type epitaxial layer and the second n-type epitaxial layer; a first p-type protection layer disposed in the trench; the second p-type protection layer is arranged in a first region on the two sides of the groove in the second n-type epitaxial layer, and the first region and the groove are spaced by a preset distance; when the silicon carbide-based metal oxide semiconductor field effect transistor is under the pressure applying condition, depletion regions are formed among the first n-type epitaxial layer, the second n-type epitaxial layer, the first p-type protection layer and the second p-type protection layer, so that voltage is blocked. By introducing the first P-type protection layer and the second P-type protection layer, the double P-type protection layers and the column-type shielding layer are formed, the drift region of the device realizes a more sufficient depletion effect, and the voltage endurance capability and the blocking efficiency are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a silicon carbide-based metal oxide semiconductor field effect transistor and a preparation method thereof. Background Art

[0002] Silicon carbide (SiC)-based metal oxide semiconductor field effect transistors (MOSFETs) have gradually become important devices in high-efficiency power converters due to their advantages such as high voltage resistance and low conduction loss. The traditional planar gate power MOSFET structure is widely used in current SiC devices due to its simple driving, fast switching speed and mature process. However, this traditional design often faces the limitations of a single longitudinal voltage-resistant layer in the drift region and a lack of diversity in the shielding protection structure, which makes it difficult to optimize both the conduction performance and the voltage resistance. In addition, during the operation of the device, the uneven distribution of the electric field can easily cause the local electric field concentration on the chip surface, limiting the further application and performance improvement of the device.

[0003] In addition, although the high-speed switching performance of traditional SiC-based MOSFET devices can reduce switching losses, it also causes overshoot during shutdown. This overshoot current not only affects the safety of the circuit, but also increases the shutdown loss of the device. Moreover, the dielectric constant of the traditional oxide gate layer is relatively low, which makes the electric field of the device too concentrated in the blocking state, which easily leads to premature breakdown and limits the voltage resistance of the device. Summary of the invention

[0004] In view of the above problems, the present invention provides a silicon carbide-based metal oxide semiconductor field effect transistor and a method for preparing the same, which are used to at least partially solve the above technical problems.

[0005] According to a first aspect of an embodiment of the present invention, a silicon carbide-based metal oxide semiconductor field effect transistor is provided, comprising: a substrate; a first n-type epitaxial layer and a second n-type epitaxial layer, which are sequentially stacked on a first surface of the substrate, a through groove is formed in the middle of the first n-type epitaxial layer and the second n-type epitaxial layer; a first p-type protective layer is arranged in the groove; a second p-type protective layer is arranged in a first region on both sides of the groove in the second n-type epitaxial layer, and the first region is spaced from the groove by a preset distance; wherein, when pressure is applied to the silicon carbide-based metal oxide semiconductor field effect transistor, a depletion region is formed between the first n-type epitaxial layer, the second n-type epitaxial layer and the first p-type protective layer, the second p-type protective layer to block the voltage.

[0006] According to an embodiment of the present invention, it also includes: an n-type highly doped layer, which is arranged on the surface of the first p-type protective layer and the n-type highly doped layer is not farther away from the surface of the first p-type protective layer than the groove; an n+ source region, a p-type channel layer and a p+ base region, which are respectively arranged in the second region, the third region and the fourth region on both sides of the groove in the second n-type epitaxial layer; wherein, along the direction from the first n-type epitaxial layer to the second n-type epitaxial layer, the second region and the third region are located above the first region and in contact with the first region, the second region is in contact with the third region and the third region is close to the groove; a gate oxide layer, which is arranged on a part of the n+ source region, the n-type highly doped layer, the p-type channel layer and the surface of the second n-type epitaxial layer; two gate electrode contacts, which are arranged in different regions on the surface of the gate oxide layer to form a split gate electrode; a passivation layer, which covers the two split gate electrode contacts; a source electrode contact, which is arranged on the gate oxide layer and the passivation layer; a drain electrode contact, which is arranged on the second surface of the substrate, and the first surface is opposite to the second surface.

[0007] According to an embodiment of the present invention, the doping concentration of the first p-type protective layer is 1×10 16 cm -3 ~5×10 17 cm -3 .

[0008] According to an embodiment of the present invention, the doping concentration of the n-type high-doping layer is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer to the second n-type epitaxial layer, the longitudinal depth of the n-type highly doped layer is 0.3 μm-2 μm.

[0009] According to a second aspect of an embodiment of the present invention, a method for preparing a silicon carbide-based metal oxide semiconductor field effect transistor is provided, comprising: preparing a stacked first n-type epitaxial layer and a second n-type epitaxial layer on a first surface of a substrate; performing groove etching on the first n-type epitaxial layer and the second n-type epitaxial layer, wherein the etching depth reaches the junction between the first n-type epitaxial layer and the substrate to form a groove; preparing a first p-type protective layer in the groove; performing ion implantation on a first region on both sides of the groove in the second n-type epitaxial layer to form a second p-type protective layer, wherein the first region is spaced a preset distance from the groove.

[0010] According to an embodiment of the present invention, it also includes: preparing an n-type highly doped layer on the surface of the first p-type protective layer, the n-type highly doped layer is not farther away from the surface of the first p-type protective layer than the groove; performing ion implantation on the second region, the third region and the fourth region on both sides of the groove in the second n-type epitaxial layer to form an n+ source region, a p-type channel layer and a p+ base region respectively, wherein, along the direction from the first n-type epitaxial layer to the second n-type epitaxial layer, the second region and the third region are located above the first region and in contact with the first region, the second region is in contact with the third region and the third region is close to the groove; preparing a gate oxide layer on a part of the n+ source region, the n-type highly doped layer, the p-type channel layer and the surface of the second n-type epitaxial layer; making gate electrode contacts at two different regions on the surface of the gate oxide layer to form a split gate electrode; covering the two split gate electrode contacts with a passivation layer, and etching a source window; preparing a source electrode contact on the source window and the passivation layer; preparing a drain electrode contact on the second surface of the substrate to form an ohmic contact, with the first surface facing the second surface; and performing metal interconnection.

[0011] According to an embodiment of the present invention, dry etching is used to perform trench etching on the first n-type epitaxial layer and the second n-type epitaxial layer.

[0012] According to an embodiment of the present invention, multiple epitaxy is performed in the trench to grow a first p-type protective layer; an n-type highly doped layer is prepared on the surface of the first p-type protective layer by ion implantation or etching + epitaxy; wherein the doping concentration of the n-type highly doped layer is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer to the second n-type epitaxial layer, the longitudinal depth of the n-type highly doped layer is 0.3 μm-2 μm.

[0013] According to an embodiment of the present invention, ion implantation is performed on the second region, the third region and the fourth region on both sides of the groove in the second n-type epitaxial layer to form an n+ source region, a p-type channel layer and a p+ base region respectively, including: performing surface patterning on the mask layer by photolithography and electron beam exposure to obtain an ion implantation window; performing multiple ion implantations based on the ion implantation window to form an n+ source region, a p-type channel layer, a p+ base region and a second p-type protective layer; wherein the size of the ion implantation window is 0.5μm-5μm, and the p-type channel layer 07 can be formed from top to bottom simultaneously with the second p-type protective layer 09.

[0014] According to an embodiment of the present invention, gate electrodes are in contact at two different regions on the surface of a gate oxide layer to form a split gate electrode, including: depositing polysilicon on the surface of the gate oxide layer; patterning the polysilicon to form an etching window; etching the polysilicon based on the etching window to obtain a split gate electrode; wherein the size of the etching window is 1 μm-5 μm.

[0015] The silicon carbide-based metal oxide semiconductor field effect transistor and the preparation method thereof provided by the present invention have at least the following technical effects:

[0016] By introducing the first p-type protection layer and the second p-type protection layer to form a double p-type protection layer and a "pillar" type shielding layer, the drift region of the device achieves a more complete depletion effect, improving the withstand voltage and blocking efficiency. Different from the traditional single-direction depletion, the present invention introduces a lateral depletion mechanism to evenly distribute the electric field, reduce the concentration of local high electric fields, and avoid breakdown caused by excessive electric fields.

[0017] The "pillar" shielding layer used can effectively distribute the voltage and limit the electric field concentration area to the lower part of the device, thereby reducing the electric field strength near the gate oxide layer and reducing the risk of thermal electric breakdown. The presence of the dual P-type protection layer also makes the electric field more evenly distributed inside the device, further enhancing the device's voltage resistance.

[0018] The design of the first P-type protection layer effectively suppresses the overshoot current generated during high-frequency shutdown. Since the depletion region formed by the "pillar" type shielding layer can prevent excessive accumulation of induced carriers, the overshoot current at the moment of shutdown is significantly reduced, improving the safety of the circuit and the high-frequency working characteristics of the device.

[0019] The second P-type protection layer can also effectively inhibit the turn-on of the parasitic bipolar transistor, avoiding premature breakdown caused by parasitic effects. This structure not only improves the blocking ability of the device, but also further enhances the reliability of the device, especially the stability under high voltage and high field conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0021] Figure 1 A schematic diagram shows the structure of a silicon carbide-based metal oxide semiconductor field effect transistor according to an embodiment of the present invention;

[0022] Figure 2A-2K The device structure diagram corresponding to each step in the method for preparing a silicon carbide-based metal oxide semiconductor field effect transistor according to an embodiment of the present invention is schematically shown.

[0023] Reference numerals:

[0024] 01-source electrode contact, 02-gate electrode contact, 03-gate oxide layer, 04-passivation layer, 05-n+ source region, 06-n-type high doping layer, 07-p-type channel layer, 08-p+ base region, 09-second p-type protective layer, 10-second n-type epitaxial layer, 11-first P-type protective layer, 12-first n-type epitaxial layer, 13-SiC substrate, 14-drain electrode contact. DETAILED DESCRIPTION

[0025] Below, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of embodiments of the present invention. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of concepts of the present invention.

[0026] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0027] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0028] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0029] Figure 1 The structure of a silicon carbide-based metal oxide semiconductor field effect transistor according to an embodiment of the present invention is schematically shown.

[0030] like Figure 1 As shown, the silicon carbide-based metal oxide semiconductor field effect transistor may include:

[0031] Substrate 13. The surface buffer structure of this substrate is omitted.

[0032] The first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 are sequentially stacked on the first surface of the substrate 13 , and a through trench is formed in the middle of the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 .

[0033] The first p-type protection layer 11 is disposed in the trench.

[0034] The second p-type protection layer 09 is disposed in the first region on both sides of the trench in the second n-type epitaxial layer 10 , and the first region is spaced apart from the trench by a preset distance.

[0035] Wherein, when pressure is applied to the silicon carbide-based metal oxide semiconductor field effect transistor, a depletion region is formed between the first n-type epitaxial layer 12, the second n-type epitaxial layer 10 and the first p-type protective layer 11, the second p-type protective layer 09 to block the voltage.

[0036] Based on the above embodiment, the silicon carbide-based metal oxide semiconductor field effect transistor may further include:

[0037] The n-type highly doped layer 06 is disposed on the surface of the first p-type protective layer 11 and the n-type highly doped layer 06 is not farther away from the surface of the first p-type protective layer 11 than the groove.

[0038] The n+ source region 05, the p-type channel layer 07 and the p+ base region 08 are respectively arranged in the second region, the third region and the fourth region on both sides of the trench in the second n-type epitaxial layer 10; wherein, along the direction from the first n-type epitaxial layer 12 to the second n-type epitaxial layer 10, the second region and the third region are located above the first region and in contact with the first region, the second region is in contact with the third region and the third region is close to the trench.

[0039] The gate oxide layer 03 is disposed on a portion of the n+ source region 05 , the n-type highly doped layer 06 , the p-type channel layer 07 and the surface of the second n-type epitaxial layer 10 .

[0040] Two gate electrode contacts 02 are provided at different regions on the surface of the gate oxide layer 03 to form a split gate electrode.

[0041] The passivation layer 04 covers the two split gate electrode contacts 02 .

[0042] The source electrode contact 01 is provided on the gate oxide layer 03 and the passivation layer 04 .

[0043] The drain electrode contact 14 is disposed on the second surface of the substrate 13 , and the first surface is opposite to the second surface.

[0044] According to an embodiment of the present disclosure, when the device is in the on state, a forward bias is applied to the gate electrode contact 02, and a reverse charge is formed in the p-type channel layer 07. At this time, when the voltage applied by the drain electrode contact 14 exceeds the threshold voltage, a conduction path is formed and the device starts to work. In the blocking state, the gate voltage is reduced to 0V or lower, resulting in the carriers in the channel being cut off. At the same time, by applying a high voltage to the drain, the depletion region formed between the first and second n-type epitaxy and the first and second p-type protective layers bears the blocking voltage.

[0045] The working process of silicon carbide-based metal oxide semiconductor field effect transistor can be specifically described as follows:

[0046] On state: When the gate electrode contact 02 applies a turn-on voltage, the p-type channel layer 07 under the gate generates an inversion channel, and the n+ source region 05 is connected to the n-type epitaxial layer through the channel. During the growth of the second n-type epitaxial layer 10, its doping concentration can be flexibly adjusted to form a lower on-resistance in the JFET region. This design reduces the conduction loss of the device and improves the conduction capability. In addition, the "pillar" type first P-type protective layer 11, which is similar to the superjunction structure, enables the JFET region and the first n-type epitaxial layer 12 to be laterally depleted, thereby increasing the carrier transport speed and free path, and further reducing the on-resistance.

[0047] Switching state: When the voltage on the gate electrode contact 02 changes from the turn-on voltage to the turn-off voltage, the inversion channel disappears rapidly. However, the conductive carriers in the drift region are still injected, which easily accumulates parasitic inductance in the MOSFET, thereby causing overshoot current during high-frequency shutdown. In some cases, excessive overshoot current may cause circuit damage and reduce circuit reliability. The present invention utilizes the depletion region formed between the "pillar" type first P-type protective layer 11 passing through the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 at the moment of shutdown to compound the injected carriers, thereby reducing the carrier injection during shutdown overshoot and forming a structure similar to a "barrier layer", which effectively suppresses the overshoot current and enhances the high-frequency performance and circuit stability of the device.

[0048] Blocking state: When the voltage of the drain electrode contact 14 continues to increase, the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 are gradually depleted to form a withstand voltage. Due to the existence of the "pillar" type first P-type protection layer 11, the depletion region changes from one-dimensional depletion to two-dimensional depletion, the electric field distribution is more uniform, and the depletion is more sufficient, thereby improving the utilization efficiency of the n-type epitaxial layer. This design avoids excessive concentration of the electric field and reduces the risk of device breakdown caused by excessive electric field.

[0049] Electric field distribution control: Through the action of the "pillar" type first P-type protective layer 11, the depletion of the lateral drift region is enhanced, thereby achieving a lateral voltage division effect. In addition, the protective layer disperses the electric field to the lower part of the device, reducing the electric field strength at the corners of the gate oxide layer 03 and the second p-type protective layer 09, thereby avoiding the problem of high electric field concentration and effectively preventing premature breakdown of the device.

[0050] Based on the above embodiment, the doping concentration of the first p-type protective layer 11 is 1×10 16 cm -3 ~5×10 17 cm -3 .

[0051] Based on the above embodiment, the doping concentration of the n-type high-doping layer 06 is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer 12 to the second n-type epitaxial layer 10 , the longitudinal depth of the n-type highly doped layer 06 is 0.3 μm-2 μm.

[0052] An embodiment of the present invention further provides a preparation method for preparing the above-mentioned silicon carbide-based metal oxide semiconductor field effect transistor.

[0053] The preparation method may include:

[0054] A stacked first n-type epitaxial layer 12 and a second n-type epitaxial layer 10 are prepared on a first surface of a substrate 13 .

[0055] The first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 are subjected to trench etching, and the etching depth reaches the junction between the first n-type epitaxial layer 12 and the substrate 13 to form a trench.

[0056] A first p-type protective layer 11 is formed in the trench.

[0057] Ions are implanted into the first regions on both sides of the trench in the second n-type epitaxial layer 10 to form a second p-type protective layer 09 , wherein the first region is spaced apart from the trench by a preset distance.

[0058] Based on the above embodiment, the preparation method may further include:

[0059] An n-type highly doped layer 06 is formed on the surface of the first p-type protective layer 11 , and the n-type highly doped layer 06 is not further away from the surface of the first p-type protective layer 11 than the groove.

[0060] Ion implantation is performed on the second region, the third region and the fourth region on both sides of the trench in the second n-type epitaxial layer 10 to form an n+ source region 05, a p-type channel layer 07 and a p+ base region 08, respectively. The p-type channel layer 07 and the second p-type protective layer 09 can be formed from top to bottom simultaneously, wherein, along the direction from the first n-type epitaxial layer 12 to the second n-type epitaxial layer 10, the second region and the third region are located above the first region and in contact with the first region, and the second region is in contact with the third region and the third region is close to the trench.

[0061] A gate oxide layer 03 is formed on a part of the n+ source region 05 , the n-type highly doped layer 06 , the p-type channel layer 07 and the surface of the second n-type epitaxial layer 10 .

[0062] The gate electrode contacts 02 at two different regions on the surface of the gate oxide layer 03 to form a split gate electrode.

[0063] A passivation layer 04 is formed on the two split gate electrode contacts 02, and a source window is etched out.

[0064] A source electrode contact 01 is prepared on the source window and the passivation layer 04 .

[0065] A drain electrode contact 14 is prepared on the second surface of the substrate 13 to form an ohmic contact, with the first surface facing the second surface.

[0066] Make metal interconnects.

[0067] Based on the above embodiment, dry etching may be used to perform trench etching on the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 .

[0068] On the basis of the above embodiment, multiple epitaxy operations are performed in the trench to grow the first p-type protection layer 11 .

[0069] The n-type highly doped layer 06 is prepared on the surface of the first p-type protective layer 11 by ion implantation or etching+epitaxial method.

[0070] The doping concentration of the n-type high-doped layer 06 is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer 12 to the second n-type epitaxial layer 10 , the longitudinal depth of the n-type highly doped layer 06 is 0.3 μm-2 μm.

[0071] On the basis of the above embodiment, ion implantation is performed on the second region, the third region and the fourth region on both sides of the trench in the second n-type epitaxial layer 10 to form an n+ source region 05, a p-type channel layer 07 and a p+ base region 08, respectively. The p-type channel layer 07 and the second p-type protective layer 09 can be formed simultaneously from top to bottom, including:

[0072] The mask layer is subjected to surface patterning by photolithography and electron beam exposure to obtain an ion implantation window.

[0073] Based on multiple ion implantation in the ion implantation window, an n+ source region 05, a p-type channel layer 07, a p+ base region 08 and a second p-type protective layer 09 are formed. The p-type channel layer 07 and the second p-type protective layer 09 can be formed simultaneously from top to bottom.

[0074] The size of the ion implantation window is 0.5 μm-5 μm.

[0075] On the basis of the above embodiment, gate electrode contacts 02 are formed at two different regions on the surface of the gate oxide layer 03 to form a split gate electrode, including:

[0076] Polysilicon is deposited on the surface of the gate oxide layer 03.

[0077] The polysilicon is patterned to form an etching window.

[0078] The polysilicon is etched based on the etching window to obtain a split gate electrode.

[0079] The size of the etching window is 1 μm-5 μm.

[0080] In order to more clearly illustrate the above preparation method, a specific example is given below for illustration.

[0081] Figure 2A-2K The device structure diagram corresponding to each step in the method for preparing a silicon carbide-based metal oxide semiconductor field effect transistor according to an embodiment of the present invention is schematically shown.

[0082] like Figure 2A As shown, the SiC substrate is prepared and subjected to RCA standard definition to remove organic and inorganic contaminants on the surface.

[0083] In a possible implementation, the cleaning process may be:

[0084] a. Ultrasonic clean with acetone and ethanol three times in sequence, and then rinse with deionized water.

[0085] b. The organic ultrasonic n++ type SiC substrate 10 is placed in a concentrated sulfuric acid and hydrogen peroxide solution and boiled for at least 10 minutes.

[0086] c. Boil the n++ type SiC substrate 10 boiled in concentrated sulfuric acid in liquid No. 1 and liquid No. 2 for 15 minutes, rinse with deionized water, and blow dry with nitrogen for later use. Liquid No. 1 is a mixture of ammonia water, hydrogen peroxide and deionized water, with a volume ratio of ammonia water: hydrogen peroxide: deionized water = 1:2:5, and liquid No. 2 is a mixture of hydrochloric acid, hydrogen peroxide and deionized water, with a volume ratio of hydrochloric acid: hydrogen peroxide: deionized water = 1:2:5.

[0087] d. Soak the rinsed n++ type SiC substrate 10 in diluted hydrofluoric acid (hydrogen fluoride: deionized water = 1:3 by volume) for 1 min to remove the oxide on the surface, and then wash it with deionized water and dry it.

[0088] like Figure 2B As shown, a first n-type epitaxial layer 12 is grown thereon by chemical vapor deposition (CVD) or molecular beam epitaxy (MBE) method, the thickness of which is controlled between 20 μm and 100 μm according to the withstand voltage requirement of the device, and the doping concentration is 1×10 14 cm -3 ~5×10 16 cm -3 .

[0089] like Figure 2C As shown, the second epitaxial growth is continued on the SiC surface to grow the second n-type epitaxial layer 10. The growth thickness is controlled between 20 μm and 100 μm according to the design requirements, and the doping concentration is 1×10 14 cm -3 ~5×10 16 cm -3。

[0090] like Figure 2D As shown, the SiC substrate is dry-etched by physical or chemical etching methods, such as reactive ion etching (RIE) or inductively coupled plasma (ICP), and the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 are dry-etched. The depth of the etching groove reaches the bottom of the first n-type epitaxial layer 12. The etching gas can be SF 6 / O 2 NF 3 / Ar、CF 4 , HBr, CHF 3 / O 2 , C 4 F 8 / O 2 The etching conditions are: ICP power 600W~1000W, bias power 100W~300W, temperature 17℃~70℃.

[0091] like Figure 2EAs shown, multiple epitaxy is performed at the etched groove to grow a first P-type protective layer 11. The first P-type protective layer 11 penetrates the first n-type epitaxial layer 12 and the second n-type epitaxial layer 10 to form a "pillar" type shielding layer. The doping concentration of the first P-type protective layer 11 is 1×10 16 cm -3 ~5×10 17 cm -3 Then, an n-type highly doped layer 06 is formed on the SiC surface by ion implantation or etching + epitaxy. The doping concentration of the n-type highly doped layer 06 is 1×10 16 cm -3 ~5×10 17 cm -3 , the longitudinal depth is 0.3-2μm.

[0092] like Figure 2F As shown, a mask layer is grown on the epitaxial layer by chemical vapor deposition (CVD) and other methods. The mask material can be SiO 2 The specific thickness is adjusted according to the type and energy of ion implantation. Subsequently, the mask layer is patterned on the surface by precision processing methods such as photolithography and electron beam exposure, and the window size is usually controlled within the range of 0.5 to 5 microns. Through multiple ion implantation and other methods, ion implantation of n+ source region 05, p-type channel layer 07, p+ base region 08 and second p-type protective layer 09 is performed. The ion implantation depth is usually controlled between 0.3 and 2 μm. The p-type channel layer 07 and the second p-type protective layer 09 can be formed from top to bottom at the same time. The n+ source region 05 can be 5×10 18 cm -3 ~1×10 19 cm -3 The doping concentration of the second p-type protective layer 09 can be 1×10 16 cm -3 ~5×10 17 cm -3 The doping concentration of the p-type channel layer 07 can be designed to be 1×10 16 cm -3 ~8×10 17 cm -3 The doping concentration of the p+ base region 08 can be 5×10 18 cm -3 ~1×10 19 cm -3Within. The p-type injection source can be trivalent ions such as Al, and the n-type injection source can be pentavalent elements such as N. Finally, the active area of ​​the device is selectively injected with doping regions to form a first p-type protective layer 11 and a second P-type protective layer 09, forming a double P-type protective layer and a "pillar" type shielding layer. Based on the above-prepared device, a carbon film is covered and high-temperature annealing is performed at 1300 to 1800°C to activate the injected impurities. The annealing atmosphere can select protective gases such as nitrogen or argon, and the rapid annealing time is 5-30 minutes.

[0093] like Figure 2G As shown, the gate oxide layer 03 is grown by dry oxygen oxidation or low pressure vapor deposition at 1100-1500°C, the thickness of the gate oxide layer 03 is controlled to be 50 to 100 nanometers, and annealed at a temperature of 1100°C to 1300°C in an N-containing or N-containing atmosphere for 0.5 to 3 hours, and the annealing atmosphere is not only N 2 , NO, or POCl 3 , H 2 , N 2 O, P 2 O 5 , Sb+NO, etc.

[0094] like Figure 2H As shown, a polysilicon deposition process is performed. The polysilicon is patterned by photolithography to form a split gate electrode to determine its window size, which is usually between 1 and 5 μm. Then, the polysilicon is deposited by chemical vapor deposition and magnetron sputtering, and the thickness is controlled to be between about 0.2 and 1 μm. This step finally completes the preparation of the split gate electrode metal contact 02.

[0095] like Fig.2I As shown, a passivation layer SiO is grown by chemical vapor deposition or physical vapor deposition process. 2 The thickness is adjusted according to the thickness of polysilicon and specific process requirements, and is generally controlled between 2 and 5μm. The passivation layer is used to cover the gate electrode contact 02 area and the gate oxide layer 03, and plays a protective and shielding role above the n-type high-doped layer 06. Subsequently, the passivation layer 04 of the source window is etched by using techniques such as photolithography patterning or electron beam exposure, combined with wet or dry etching processes, until the source contact hole is formed. The size of the contact hole is controlled according to the width of the source electrode, usually between 0.1 and 5μm.

[0096] like Figure 2JAs shown, the source metal is deposited by electron beam evaporation or magnetron sputtering, and the selected metal material may include nickel (Ni), titanium (Ti), aluminum (Al) or a combination of titanium / aluminum alloys. After the metal deposition is completed, a rapid thermal annealing (RTA) process is used, with the temperature range controlled at 800 to 1300°C and carried out in a protective gas environment such as nitrogen or argon. A laser annealing process may also be used to form a good source electrode contact 01.

[0097] like Figure 2K As shown, the front side of the device is protected by coating or growing a protective layer, and metal is evaporated on the back side of the SiC epitaxial wafer by electron beam evaporation or magnetron sputtering technology. Optional metal materials include nickel (Ni), aluminum (Al) or nickel / gold (Ni / Au) alloy. After the metal deposition is completed, a rapid thermal annealing (RTA) process is used, the temperature range is controlled at 800 to 1300°C, and it is processed in a protective gas environment such as nitrogen or argon, or by laser annealing technology, and finally a good ohmic contact is formed to complete the drain electrode contact 14. The pad metal is interconnected, and then the device is packaged to complete the entire device preparation process.

[0098] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems and methods according to various embodiments of the present invention. In this regard, each box in the flowchart or block diagram may represent a module, a program segment or a part of a code, and the above-mentioned module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0099] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways, even if such combinations and / or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention may be combined and / or combined in various ways without departing from the spirit and teachings of the present invention. All of these combinations and / or combinations fall within the scope of the present invention.

[0100] The embodiments of the present invention are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present invention. Although each embodiment is described above, it does not mean that the measures in each embodiment cannot be used in combination. The scope of the present invention is defined by the attached claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A silicon carbide-based metal oxide semiconductor field effect transistor, characterized in that: include: Substrate (13); A first n-type epitaxial layer (12) and a second n-type epitaxial layer (10) are sequentially stacked on a first surface of the substrate (13), wherein a through groove is formed in the middle of the first n-type epitaxial layer (12) and the second n-type epitaxial layer (10); A first p-type protective layer (11) is disposed in the groove; A second p-type protective layer (09) is provided in a first region on both sides of the groove in the second n-type epitaxial layer (10), the first region being spaced apart from the groove by a preset distance; Wherein, when pressure is applied to the silicon carbide-based metal oxide semiconductor field effect transistor, a depletion region is formed between the first n-type epitaxial layer (12), the second n-type epitaxial layer (10) and the first p-type protective layer (11), the second p-type protective layer (09) to block the voltage.

2. The silicon carbide-based metal oxide semiconductor field effect transistor according to claim 1, characterized in that: Also includes: An n-type highly doped layer (06) is provided on the surface of the first p-type protective layer (11), and the distance between the n-type highly doped layer (06) and the surface of the first p-type protective layer (11) does not exceed the groove; An n+ source region (05), a p-type channel layer (07) and a p+ base region (08), which are respectively arranged in a second region, a third region and a fourth region on both sides of the groove in the second n-type epitaxial layer (10); wherein, along a direction from the first n-type epitaxial layer (12) to the second n-type epitaxial layer (10), the second region and the third region are located above the first region and in contact with the first region, and the second region is in contact with the third region and the third region is close to the groove; A gate oxide layer (03) is provided on a partial region of the n+ source region (05), the n-type highly doped layer (06), the p-type channel layer (07) and the surface of the second n-type epitaxial layer (10); Two gate electrode contacts (02) are arranged at different areas on the surface of the gate oxide layer (03) to form a split gate electrode; A passivation layer (04), covering the two split gate electrode contacts (02); A source electrode contact (01) is provided on the gate oxide layer (03) and the passivation layer (04); A drain electrode contact (14) is provided on a second surface of the substrate (13), the first surface being opposite to the second surface.

3. The silicon carbide-based metal oxide semiconductor field effect transistor according to claim 1 or 2, characterized in that: The doping concentration of the first p-type protective layer (11) is 1×10 16 cm -3 ~5×10 17 cm -3 .

4. The silicon carbide-based metal oxide semiconductor field effect transistor according to claim 2, characterized in that: The doping concentration of the n-type high-doping layer (06) is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer (12) to the second n-type epitaxial layer (10), the longitudinal depth of the n-type highly doped layer (06) is 0.3 μm-2 μm.

5. A method for preparing a silicon carbide-based metal oxide semiconductor field effect transistor, characterized in that: include: Preparing a stacked first n-type epitaxial layer (12) and a second n-type epitaxial layer (10) on a first surface of a substrate (13); Performing trench etching on the first n-type epitaxial layer (12) and the second n-type epitaxial layer (10), wherein the etching depth reaches the boundary between the first n-type epitaxial layer (12) and the substrate (13), thereby forming a trench; Preparing a first p-type protective layer (11) in the groove; Ion implantation is performed on a first region on both sides of the trench in the second n-type epitaxial layer (10) to form a second p-type protective layer (09), wherein the first region is spaced a preset distance from the trench.

6. The preparation method according to claim 5, characterized in that: Also includes: An n-type highly doped layer (06) is prepared on the surface of the first p-type protective layer (11), wherein the n-type highly doped layer (06) is not farther away from the surface of the first p-type protective layer (11) than the groove; Ion implantation is performed on the second region, the third region and the fourth region on both sides of the groove in the second n-type epitaxial layer (10) to form an n+ source region (05), a p-type channel layer (07) and a p+ base region (08), respectively, wherein, along a direction from the first n-type epitaxial layer (12) to the second n-type epitaxial layer (10), the second region and the third region are located above the first region and in contact with the first region, the second region is in contact with the third region and the third region is close to the groove; Preparing a gate oxide layer (03) on a partial area of ​​the n+ source region (05), the n-type highly doped layer (06), the p-type channel layer (07) and the surface of the second n-type epitaxial layer (10); Gate electrodes contact (02) at two different regions on the surface of the gate oxide layer (03) to form a split gate electrode; Covering the two split gate electrode contacts (02) with a passivation layer (04), and etching a source window; Preparing a source electrode contact (01) on the source window and the passivation layer (04); Preparing a drain electrode contact (14) on the second surface of the substrate (13) to form an ohmic contact, wherein the first surface is opposite to the second surface; Make metal interconnects.

7. The preparation method according to claim 5, characterized in that: Dry etching is used to perform trench etching on the first n-type epitaxial layer (12) and the second n-type epitaxial layer (10).

8. The preparation method according to claim 6, characterized in that: Performing multiple epitaxy operations in the trench to grow the first p-type protective layer (11); Preparing an n-type highly doped layer (06) on the surface of the first p-type protective layer (11) by ion implantation or etching+epitaxial method; The doping concentration of the n-type high-doping layer (06) is 1×10 16 cm -3 ~5×10 17 cm -3 , along the direction from the first n-type epitaxial layer (12) to the second n-type epitaxial layer (10), the longitudinal depth of the n-type highly doped layer (06) is 0.3 μm-2 μm.

9. The preparation method according to claim 6, characterized in that: The step of implanting ions into the second region, the third region and the fourth region on both sides of the trench in the second n-type epitaxial layer (10) to form an n+ source region (05), a p-type channel layer (07) and a p+ base region (08), respectively, comprises: The mask layer is subjected to surface patterning by photolithography and electron beam exposure to obtain an ion implantation window; Based on the ion implantation window, multiple ion implantations are performed to form an n+ source region (05), a p-type channel layer (07), a p+ base region (08) and a second p-type protective layer (09), wherein the p-type channel layer 07 and the second p-type protective layer 09 are formed simultaneously from top to bottom; Wherein, the size of the ion implantation window is 0.5 μm-5 μm.

10. The method according to claim 6, characterized in that The gate electrode contacts (02) at two different regions on the surface of the gate oxide layer (03) to form a split gate electrode include: Depositing polysilicon on the surface of the gate oxide layer (03); Patterning the polysilicon to form an etching window; Etching the polysilicon based on the etching window to obtain a split gate electrode; Wherein, the size of the etching window is 1 μm-5 μm.

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