Shift register

Abstract

A novel signal output circuit is provided. The present invention is a shift register including a signal output circuit having a vertical channel type transistor. A signal output circuit with a small occupied area is realized by using one of a stray capacitor between a gate and a source and a stray capacitor between a gate and a drain of a vertical channel type transistor, which has a larger capacitance value, as a bootstrap capacitor. The oxide semiconductor is used for the semiconductor layer of the vertical channel type transistor, so that the insulation voltage resistance between the source electrode and the drain electrode is improved, and the channel length can be shortened. In addition, stable work can be realized in a high-temperature environment.

Description

Technical Field

[0001] One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. In addition, one embodiment of the invention disclosed in this specification and the like relates to a process, a machine, a product, or a composition of matter.

[0002] One embodiment of the present invention is not limited to the above-mentioned technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification, etc. include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, electronic devices, lighting devices, input devices (e.g., touch sensors, etc.), input-output devices (e.g., touch panels, etc.), driving methods of these devices, or manufacturing methods of these devices.

[0003] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (transistor, diode, photodiode, etc.), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits, chips with integrated circuits, and electronic components that contain chips in packages. In addition, storage devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and sometimes all include semiconductor devices. Background Art

[0004] In recent years, as electronic devices have become smaller and lighter, there has been an increasing demand for integrated circuits in which transistors and the like are densely integrated. As one method of densely integrating transistors, miniaturization of transistors and reduction of occupied area have been developed.

[0005] As a semiconductor material that can be used for transistors, oxide semiconductors using metal oxides have attracted attention. For example, Patent Document 1 discloses a semiconductor device in which a plurality of oxide semiconductor layers are stacked, in which an oxide semiconductor layer used as a channel contains indium and gallium, and the ratio of indium is higher than that of gallium, thereby improving field effect mobility (sometimes referred to as mobility or μFE).

[0006] [Prior technical literature]

[0007] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2014-7399 Summary of the invention

[0009] Technical problem to be solved by the invention

[0010] One of the purposes of one embodiment of the present invention is to provide a semiconductor device with a small footprint. Another purpose of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another purpose of one embodiment of the present invention is to provide a novel semiconductor device.

[0011] Note that the description of these purposes does not prevent the existence of other purposes. Note that one embodiment of the present invention does not necessarily achieve all of the above purposes. Note that purposes other than the above can be known and extracted from the description of the specification, drawings, claims, etc.

[0012] Solutions to technical problems

[0013] One embodiment of the present invention is a shift register, which includes a plurality of signal output circuits, at least one of which includes a first transistor, and at least one of which has a function of outputting a first signal through the first transistor. The shift register includes a first conductive layer having a region serving as one of a source electrode and a drain electrode of the first transistor, a first insulating layer having a region configured on the first conductive layer, a second conductive layer having a region serving as the other of a source electrode and a drain electrode of the first transistor and a region configured on the first insulating layer, a first opening penetrating the first insulating layer and the second conductive layer and overlapping the first conductive layer, a first semiconductor layer having a region in contact with the first insulating layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer, a third conductive layer having a region serving as a gate electrode of the first transistor, and a second insulating layer having a region serving as a gate insulating film of the first transistor and a region sandwiched between the first semiconductor layer and the third conductive layer in the first opening, wherein the first signal is input to one of the source electrode and the drain electrode of the first transistor.

[0014] For example, the third conductive layer has a region overlapping with the first conductive layer in the first opening and a region overlapping with the second conductive layer on the first insulating layer.

[0015] At least one of the plurality of signal output circuits may also include a second transistor. For example, the shift register may also include a fourth conductive layer having an area serving as one of the source electrode and the drain electrode of the second transistor, a first insulating layer having an area configured on the fourth conductive layer, a fifth conductive layer having an area serving as the other of the source electrode and the drain electrode of the first transistor and an area configured on the first insulating layer, a second opening penetrating the first insulating layer and the fifth conductive layer and overlapping the fourth conductive layer, a second semiconductor layer having an area in contact with the first insulating layer, an area in contact with the fourth conductive layer, and an area in contact with the fifth conductive layer, a sixth conductive layer having an area serving as the gate electrode of the second transistor and an area configured on the second insulating layer, and a second insulating layer having an area serving as a gate insulating film of the second transistor and an area sandwiched between the second semiconductor layer and the sixth conductive layer in the second opening. In addition, the fourth conductive layer and the third conductive layer are preferably electrically connected to each other.

[0016] In addition, when the bottom surface of the fourth conductive layer is taken as the reference, the height of the top surface of the fourth conductive layer and the height of the bottom surface of the sixth conductive layer may be different. The first semiconductor layer preferably includes an oxide semiconductor. The second semiconductor layer preferably includes an oxide semiconductor.

[0017] Effects of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with a small footprint can be provided. In addition, a semiconductor device with low power consumption can be provided. In addition, a semiconductor device with high reliability can be provided. In addition, a novel semiconductor device can be provided.

[0019] Note that the description of these effects does not prevent the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of the above effects. Note that effects other than the above can be known and extracted from the description of the specification, drawings, claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1A is a diagram showing an example of a shift register. Figure 1B and Figure 1C is a diagram showing an example of a signal output circuit.

[0021] Figure 2 is a diagram showing an example of a signal output circuit.

[0022] Figure 3 is a diagram showing an example of a signal output circuit.

[0023] Figure 4 is a diagram showing an example of a signal output circuit.

[0024] Figure 5is a diagram showing an example of a signal output circuit.

[0025] Figure 6 is a diagram showing an example of a signal output circuit.

[0026] Figure 7 is a diagram showing an example of a signal output circuit.

[0027] Figure 8 is a diagram showing an example of a signal output circuit.

[0028] Fig. 9 is a diagram showing an example of a signal output circuit.

[0029] Fig.10 is a diagram showing an example of a signal output circuit.

[0030] Fig.11A is a plan view of a transistor. Fig. 11B is a cross-sectional view of a transistor. Fig. 11C It is a three-dimensional diagram of a transistor. Fig.11D is the equivalent circuit diagram of a transistor.

[0031] Fig. 12A and Fig. 12B is a cross-sectional view of a transistor. FIG. 12C to FIG. 12F It is a plan view of the opening.

[0032] Fig.13A and Fig. 13B is a plan view of a transistor.

[0033] Fig.14A is a cross-sectional view of a transistor. Fig. 14B is the equivalent circuit diagram of a transistor.

[0034] Fig.15A is a plan view of a transistor. Fig. 15B is a cross-sectional view of a transistor. Fig. 15C It is a three-dimensional diagram of a transistor. Fig.15D is the equivalent circuit diagram of a transistor.

[0035] Fig.16A is a plan view of a transistor. Fig. 16B is a cross-sectional view of a transistor. Fig. 16C It is a three-dimensional diagram of a transistor. Fig.16D is the equivalent circuit diagram of a transistor.

[0036] Fig.17 This is a plan view of the signal output circuit.

[0037] Fig.18 This is a plan view of the signal output circuit.

[0038] Fig.19Aand Fig.19B is a cross-sectional view of the signal output circuit.

[0039] Fig. 20A and Fig. 20B is a cross-sectional view of the signal output circuit.

[0040] Fig.21A and Fig.21B is a cross-sectional view of the signal output circuit.

[0041] Fig. 22 is a diagram showing an example of a signal output circuit.

[0042] Fig.23 This is a timing chart for explaining an operation example of a signal output circuit.

[0043] Fig.24 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0044] Fig.25 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0045] Fig.26 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0046] Fig. 27 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0047] Fig.28 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0048] Fig.29 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0049] Fig.30 This is a circuit diagram for explaining an operation example of a signal output circuit.

[0050] Fig.31 is a diagram showing an example of a signal output circuit.

[0051] Fig.32 is a diagram showing an example of a signal output circuit.

[0052] Fig.33 This is a timing diagram used to illustrate an example of the operation of a shift register.

[0053] Fig.34A It is a perspective view of a display device. Fig.34B is a block diagram of a display device.

[0054] FIG. 35A to FIG. 35D is a circuit diagram of a pixel circuit.

[0055] FIG. 36A to FIG. 36D is a circuit diagram of a pixel circuit.

[0056] Fig.37A and Fig.37B is a circuit diagram of a pixel circuit.

[0057] Fig.38A and Fig.38B is a circuit diagram of a pixel circuit.

[0058] Fig.39A and Fig.39B It is a diagram for explaining a configuration example of a driving circuit.

[0059] FIG. 40A to FIG. 40G is a diagram showing an example of a pixel.

[0060] FIG. 41A to FIG. 41K is a diagram showing an example of a pixel.

[0061] FIG. 42A to FIG. 42F is a diagram showing a structural example of a light emitting device.

[0062] FIG. 43A to FIG. 43C is a diagram showing a structural example of a light emitting device.

[0063] FIG. 44A to FIG. 44D A diagram illustrating a structural example of a light emitting element.

[0064] FIG. 45A to FIG. 45D is a diagram showing a structural example of a light emitting element.

[0065] FIG. 46A to FIG. 46C A diagram illustrating a structural example of a light emitting element.

[0066] FIG. 47A to FIG. 47F is a diagram showing an example of an electronic device.

[0067] FIG. 48A to FIG. 48F is a diagram showing an example of an electronic device.

[0068] Figure 49A1 and Figure 49A2 is a cross-sectional diagram of a transistor. Fig.49B1 and Fig.49B2 is a graph showing Id-Vg characteristics of a transistor. Fig.49C1 and Fig.49C2 is a graph showing Id-Vd characteristics of a transistor. DETAILED DESCRIPTION

[0069] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the method and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below. Note that in the inventive structure described below, the same symbols are used in different drawings to show the same parts or parts with the same functions, and repeated descriptions are sometimes omitted.

[0070] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings, etc., sometimes do not represent their actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a layer and a resist mask are sometimes unintentionally thinned due to a process such as etching, but for ease of understanding of the invention, the description is sometimes omitted.

[0071] In this specification and the like, when an etching step (removal step) is performed after a resist mask is formed by photolithography, unless otherwise specified, the resist mask is removed after the etching step is completed.

[0072] In addition, in particular, in a plan view (also referred to as a top view) or a perspective view, description of some components may be omitted to facilitate understanding of the invention. In addition, description of some hidden lines may be omitted.

[0073] Ordinal numerals such as "first" and "second" in this specification, etc. are added to avoid confusion between constituent elements, and do not indicate a certain order or sequence such as process order or stacking order. Note that for terms that are not added with ordinal numerals in this specification, etc., ordinal numerals are sometimes added to the terms in the claims to avoid confusion between constituent elements. Note that the ordinal numerals added in this specification, etc. are sometimes different from the ordinal numerals added in the claims. Note that for terms that are added with ordinal numerals in this specification, etc., their ordinal numerals are sometimes omitted in the claims, etc.

[0074] In this specification, etc., "electrode", "wiring" and "terminal" do not limit the functions of constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, "electrode" and "wiring" also include a case where a plurality of "electrodes" and "wiring" are provided as one body, etc. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or an "electrode", and vice versa. Furthermore, "terminal" also includes a case where a plurality of "electrodes", "wiring", "terminals", etc. are formed as one body, etc. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal", for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, "electrode", "wiring" and "terminal" etc. can sometimes be replaced by "area" etc.

[0075] In this specification, the supply of a signal refers to the supply of a predetermined potential to a wiring, etc. Therefore, sometimes "signal" can be replaced by "potential", etc. In addition, sometimes "potential" can be replaced by "signal", etc. "Signal" can be a variable potential or a fixed potential. For example, it can also be a power supply potential.

[0076] In addition, depending on the situation or state, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Also, "insulating film" may be replaced with "insulating layer" in some cases.

[0077] In this specification, etc., "capacitor" can be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" can sometimes be replaced by "capacitor". In contrast, "capacitor" can sometimes be replaced by "capacitor", "parasitic capacitance" or "gate capacitance". In addition, "capacitor" (including "capacitor" with more than three terminals) has a structure including an insulator and a pair of conductors sandwiching the insulating layer. Therefore, the "pair of conductive layers" of "capacitor" can be replaced by "a pair of electrodes", "a pair of conductive regions", "a pair of regions" or "a pair of terminals". In addition, sometimes "one of a pair of terminals" is referred to as "a terminal" or "a first terminal". In addition, sometimes "the other of a pair of terminals" is referred to as "another terminal" or "a second terminal". The electrostatic capacitance value can be, for example, more than 0.05fF and less than 10pF. In addition, for example, it can also be more than 1pF and less than 10μF.

[0078] In addition, when using transistors with different polarities or when the current direction of the circuit operation changes, the functions of the "source" and "drain" of the transistor are sometimes interchanged. Therefore, in this specification, etc., "source" and "drain" can be interchanged.

[0079] In this specification, "gate" refers to a part or all of a gate electrode and a gate wiring. A gate wiring is a wiring for electrically connecting a gate electrode of at least one transistor to another electrode or another wiring.

[0080] In this specification, "source" refers to a part or all of a source region, a source electrode, and a source wiring. A source region refers to a region in a semiconductor layer whose resistivity is less than a certain value. A source electrode refers to a conductive layer including a portion connected to a source region. A source wiring refers to wiring for electrically connecting a source electrode of at least one transistor to other electrodes or other wiring.

[0081] In this specification, "drain" refers to a part or all of a drain region, a drain electrode, and a drain wiring. A drain region refers to a region in a semiconductor layer whose resistivity is below a certain value. A drain electrode refers to a conductive layer including a portion connected to a drain region. A drain wiring refers to a wiring used to electrically connect a drain electrode of at least one transistor to other electrodes or other wirings.

[0082] In addition, unless otherwise specified, the transistors shown in this specification, etc. are enhancement-type (normally closed) field-effect transistors. In addition, when the transistors shown in this specification, etc. are n-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is greater than 0V. In addition, when the transistors shown in this specification, etc. are p-channel transistors and there is no special description, the threshold voltage (also referred to as "Vth") of the transistor is less than 0V. In addition, when there is no special description, the Vth of multiple transistors of the same conductivity type are equal.

[0083] In addition, in this specification, etc., unless otherwise specified, the off-state current refers to the current ("drain current" or "Id") flowing between the source and the drain when the transistor is in the off state (also called "non-conducting state" or "blocking state"). Unless otherwise specified, in an n-channel transistor, the off state refers to a state in which the potential difference between the gate and the source when the source is referenced (also called "gate voltage" or "Vg") is lower than the threshold voltage, and in a p-channel transistor, the off state refers to a state in which Vg is higher than the threshold voltage. For example, sometimes the off-state current of an n-channel transistor refers to the drain current when Vg is lower than Vth.

[0084] In this specification, the off-state current may be referred to as leakage current. In this specification, the off-state current may refer to, for example, current flowing between a source and a drain when a transistor is in an off state.

[0085] In this specification, etc., unless otherwise specified, the on-state current refers to the Id when the transistor is in the on state (also referred to as the "on state"). Unless otherwise specified, the on state in an n-channel transistor refers to a state where Vg is greater than Vth, and the on state in a p-channel transistor refers to a state where Vg is less than Vth. For example, the on-state current of an n-channel transistor sometimes refers to the drain current when Vg is greater than Vth.

[0086] In addition, in this specification, etc., a high power supply potential VDD (hereinafter, also simply referred to as "VDD" or "potential H") refers to a power supply potential of a potential higher than a low power supply potential VSS. In addition, a low power supply potential VSS (hereinafter, also simply referred to as "VSS" or "potential L") refers to a power supply potential of a potential lower than the high power supply potential VDD. In addition, a ground potential GND (hereinafter, simply referred to as "GND") may be used as VDD or VSS. For example, when VDD is GND, VSS is a potential lower than GND, and when VSS is GND, VDD is a potential higher than GND. In this specification, etc., unless otherwise stated, VSS is used as a reference potential.

[0087] In addition, "voltage" generally refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential, etc.). In addition, "potential" is relative, and the potential supplied to wiring, etc. sometimes changes according to the reference potential. Therefore, the terms "voltage" and "potential" may sometimes be interchangeable.

[0088] In addition, in this specification, etc., for the sake of convenience, words and phrases indicating configurations such as "upper", "lower", "above" or "below" are sometimes used to illustrate the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of constituent elements is appropriately changed according to the direction in which each structure is described. Therefore, the words and phrases described in the specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the circumstances. For example, if it is an expression "an insulating layer located on the conductive layer", by rotating the direction of the illustrated drawing by 180 degrees, it can be replaced by "an insulating layer located below the conductive layer". For example, the expression "an insulating layer located on the opening" sometimes includes "an insulating layer located on the side of the opening".

[0089] In addition, the terms "above" and "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed on insulating layer A in direct contact, and the case where other components are included between insulating layer A and electrode B may also be included.

[0090] In this specification, the term "overlap" or the like does not limit the state of the stacking order of the constituent elements. For example, "electrode B overlapping with insulating layer A" is not limited to the state of "electrode B formed on insulating layer A", but also includes the state of "electrode B formed under insulating layer A" or "electrode B formed on the right side (or left side) of insulating layer A".

[0091] In this specification, the words "adjacent" and "close to" do not limit the state of direct contact between components. For example, if it is an expression "electrode B adjacent to insulating layer A", it does not necessarily mean that insulating layer A and electrode B are directly in contact with each other, and it may also include the case where other components are included between insulating layer A and electrode B.

[0092] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, it also includes a state where the angle is greater than -5° and less than 5°. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, it also includes a state where the angle is greater than 85° and less than 95°. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0093] In addition, in this specification, unless otherwise stated, when count values ​​or measurement values ​​are "same", "identical", "equal", or "uniform", etc., a variation of ±20% is included as an error.

[0094] In this specification, etc., the end of an object is a tapered shape, which means that the angle formed by the formed surface (bottom surface) and the side surface (surface) in the region of the end is greater than 0 degrees and less than 90 degrees, and has a cross-sectional shape in which the thickness continuously increases from the end. In addition, the taper angle refers to the angle formed by the bottom surface (formed surface) and the side surface (surface) of the end of the object.

[0095] In addition, arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings and the like according to this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and sometimes the positive direction and the negative direction are not distinguished except for the cases clearly stated. The "Y direction" and the "Z direction" are also the same as the "X direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. More specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, sometimes one of the X direction, the Y direction, and the Z direction is referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0096] In this specification, when the same symbol is used for a plurality of components and it is necessary to distinguish them, a symbol such as "A", "b", "_1", "[n]", "[m, n]" is sometimes added to the symbol for identification. For example, the EL layer 172 is sometimes divided into the EL layer 172R, the EL layer 172G, the EL layer 172B, and the EL layer 172W in the figure.

[0097] (Implementation Method 1)

[0098] In this embodiment mode, an example of a signal output circuit which is a type of semiconductor device and a shift register including the signal output circuit are described with reference to the drawings.

[0099] <Structure of Shift Register 100>

[0100] Figure 1A The shift register 100 shown includes n (n is an integer greater than 1) signal output circuits 110. In this specification, the first-stage (first) signal output circuit 110 is sometimes referred to as signal output circuit 110[1], and the n-th-stage (nth) signal output circuit 110 is sometimes referred to as signal output circuit 110[n].

[0101] In addition, the i-th stage (i is an integer greater than 1 and less than n) signal output circuit 110 is sometimes referred to as signal output circuit 110[i]. Note that when any stage number is referred to as i+α and α is a positive value, i+α is not greater than n. In addition, when any stage number is referred to as i-α and α is a positive value, i-α is not less than 1.

[0102] In addition, the shift register 100 includes two signal output circuits 110 (signal output circuit 110 [n+1], signal output circuit 110 [n+2]) as dummy circuits.

[0103] Note that the terminals and input / output signals included in the signal output circuit 110 may be described in the same manner as described above. For example, the signal OUT of the signal output circuit 110[i] may be described as the signal OUT[i].

[0104] In addition, the shift register 100 includes wirings 101 to 104 to which four signals CLK (signal CLK_1 to signal CLK_4) of clock signals are respectively supplied, and wirings 105 to 108 to which four signals PWC (signal PWC_1 to signal PWC_4) are respectively supplied. The wiring 101 is supplied with the signal CLK_1, the wiring 102 is supplied with the signal CLK_2, the wiring 103 is supplied with the signal CLK_3, and the wiring 104 is supplied with the signal CLK_4. The wiring 105 is supplied with the signal PWC_1, the wiring 106 is supplied with the signal PWC_2, the wiring 107 is supplied with the signal PWC_3, and the wiring 108 is supplied with the signal PWC_4.

[0105] The signal output circuit 110 includes terminals 111 to 118 (see Figure 1B ). The terminal 111, the terminal 112, and the terminal 113 are electrically connected to any different wirings among the wirings 101 to 104. For example, in Figure 1A In the first-stage signal output circuit 110[1], the terminal 111 is electrically connected to the wiring 101, the terminal 112 is electrically connected to the wiring 102, and the terminal 113 is electrically connected to the wiring 103. That is, the terminal 111 is supplied with the signal CLK_1, the terminal 112 is supplied with the signal CLK_2, and the terminal 113 is supplied with the signal CLK_3.

[0106] In the second-stage signal output circuit 110[2], the terminal 111 is electrically connected to the wiring 102, the terminal 112 is electrically connected to the wiring 103, and the terminal 113 is electrically connected to the wiring 104. That is, the terminal 111 is supplied with the signal CLK_2, the terminal 112 is supplied with the signal CLK_3, and the terminal 113 is supplied with the signal CLK_4.

[0107] That is, the terminal 111[i] of the signal output circuit 110[i] is supplied with the signal CLK_k (see Figure 1C ). Here, k is an integer greater than or equal to 1 and less than or equal to 4, and when i is less than or equal to 4, k is equal to i, and when i is greater than or equal to 5, k is equal to i-4×g. g is the quotient obtained by dividing i by 4.

[0108] The terminal 112[i] of the signal output circuit 110[i] is supplied with the signal CLK_k+1. Here, k is an integer greater than or equal to 1 and less than or equal to 4, and when k+1 is 5, k is 1. When i is less than or equal to 3, k is equal to i, and when i is greater than or equal to 4, k is equal to i-4×g.

[0109] In addition, the terminal 113[i] of the signal output circuit 110[i] is supplied with the signal CLK_k+2. Here, k+1 is an integer greater than or equal to 1 and less than or equal to 4, and when k+2 is 5, k+2 is 1, and when k+2 is 6, k+2 is 2. In addition, when i is less than 2, k is equal to i, and when i is greater than or equal to 3, k is equal to i-4×g.

[0110] In addition, the terminal 114[i] is electrically connected to the terminal 117[i+1] (not shown) of the next stage signal output circuit 110[i+1] (not shown). Therefore, the terminal 117[i] is electrically connected to the terminal 114[i-1]. For example, the terminal 114 of the signal output circuit 110[1] is electrically connected to the terminal 117 of the signal output circuit 110[2]. In addition, the terminal 117 of the signal output circuit 110[1] is supplied with the start pulse SP.

[0111] In addition, terminal 115[i] is electrically connected to terminal 114[i+2] (not shown) of the next-stage signal output circuit 110[i+2] (not shown). For example, terminal 115 of signal output circuit 110[1] is electrically connected to terminal 114 of signal output circuit 110[3], and terminal 115 of signal output circuit 110[2] is electrically connected to terminal 114 of signal output circuit 110[4]. Therefore, terminal 115 of signal output circuit 110[n-1] is electrically connected to terminal 114 of signal output circuit 110[n+1], and terminal 115 of signal output circuit 110[n] is electrically connected to terminal 114 of signal output circuit 110[n+2]. Note that signal output circuit 110[n+1] and signal output circuit 110[n+2] may not include terminal 115.

[0112] In addition, the terminal 118[i] is electrically connected to any one of the wirings 105 to 108. For example, the terminal 118 of the signal output circuit 110[1] is electrically connected to the wiring 105, and the terminal 118 of the signal output circuit 110[2] is electrically connected to the wiring 106. In other words, the terminal 118[i] of the signal output circuit 110[i] is supplied with the signal PWC_k. Here, k is an integer greater than or equal to 1 and less than or equal to 4, and when i is less than or equal to 4, k is equal to i, and when i is greater than or equal to 5, k is equal to i-4×g.

[0113] In addition, the terminal 116[i] outputs the signal OUT[i]. For example, the terminal 116 of the signal output circuit 110[1] outputs the signal OUT[1]. In addition, the terminal 116 of the n-th stage signal output circuit 110[n] outputs the signal OUT[n]. “The terminal 116[i] outputs the signal OUT[i]” can also be expressed as “the terminal 116[i] is supplied with the signal OUT[i]”.

[0114] In addition, the terminal 114[i] is supplied with the signal SROUT[i]. In other words, the terminal 114[i] outputs the signal SROUT[i]. For example, the terminal 114 of the signal output circuit 110[1] outputs the signal SROUT[1]. In addition, the terminal 114 of the n-th stage signal output circuit 110[n] outputs the signal SROUT[n]. “The terminal 114[i] outputs the signal SROUT[i]” can also be written as “the terminal 114[i] is supplied with the signal SROUT[i]”.

[0115] [Configuration Example of Signal Output Circuit 110]

[0116] Next, the structure of the signal output circuit 110a which can be used as the signal output circuit 110 is described (see Figure 2 The signal output circuit 110a includes transistors 10[1] to 10

[11] and capacitors 20[1] to 20[3].

[0117] The gate of transistor 10[1] is electrically connected to terminal 117 and the gate of transistor 10[6]. The source of transistor 10[1] is electrically connected to the drain of transistor 10[2], and the drain of transistor 10[1] is electrically connected to wiring 131. The gate of transistor 10[2] is electrically connected to one terminal of capacitor 20[1]. The source of transistor 10[2] is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6], and wiring 132.

[0118] The gate of transistor 10[3] is electrically connected to terminal 113, the drain of transistor 10[3] is electrically connected to wiring 131, and the source of transistor 10[3] is electrically connected to the drain of transistor 10[4]. The gate of transistor 10[4] is electrically connected to terminal 112, and the drain of transistor 10[4] is electrically connected to the source of transistor 10[3]. The source of transistor 10[4] is electrically connected to the gates of transistors 10[2], 10[9], and 10

[11] , respectively, and one terminal of capacitor 20[1].

[0119] Note that in this specification, etc., the region where the gates of transistors 10[2], 10[9], and 10

[11] , the source of transistor 10[4], and one terminal of capacitor 20[1] are electrically connected is referred to as node ND[1]. Capacitor 20[1] has a function of suppressing a change in the potential of node ND[1] when node ND[1] is in a floating state and maintaining the potential of node ND[1].

[0120] The gate of transistor 10[5] is electrically connected to terminal 115, and the drain of transistor 10[5] is electrically connected to wiring 131. The source of transistor 10[5] is electrically connected to the gate of transistor 10[2], the gate of transistor 10[9], the gate of transistor 10

[11] , and the drain of transistor 10[6].

[0121] The gate of transistor 10[7] is electrically connected to wiring 131, and one of the source and drain of transistor 10[7] is electrically connected to the source of transistor 10[1] and the drain of transistor 10[2]. The other of the source and drain of transistor 10[7] is electrically connected to the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10

[10] , and one terminal of capacitor 20[3].

[0122] Note that in this specification and the like, a region where one of the source and drain of transistor 10[7], the source of transistor 10[1], and the drain of transistor 10[2] are electrically connected is referred to as node ND[2]. Also, in this specification and the like, a region where the other of the source and drain of transistor 10[7], the gate of transistor 10[8], one terminal of capacitor 20[2], the gate of transistor 10

[10] , and one terminal of capacitor 20[3] are electrically connected is referred to as node ND[3].

[0123] The drain of transistor 10[8] is electrically connected to terminal 111. The source of transistor 10[8] is electrically connected to the other terminal of capacitor 20[2], terminal 114, and the drain of transistor 10[9]. The drain of transistor 10

[10] is electrically connected to terminal 118. The source of transistor 10

[10] is electrically connected to the other terminal of capacitor 20[3], terminal 116, and the drain of transistor 10

[11] .

[0124] The source of transistor 10 [ 9 ] and the source of transistor 10 [ 11 ] are electrically connected to wiring 132 .

[0125] Note that the drain of transistor 10[1], the drain of transistor 10[3], the drain of transistor 10[5], and the gate of transistor 10[7] may be electrically connected to different wirings. In addition, the source of transistor 10[6], the source of transistor 10[9], and the source of transistor 10

[11] may be electrically connected to different wirings.

[0126] For example, Figure 3As shown, the drain of transistor 10[1] may also be electrically connected to wiring 131[1], the drain of transistor 10[3] may also be electrically connected to wiring 131[2], the drain of transistor 10[5] may also be electrically connected to wiring 131[3], and the gate of transistor 10[7] may also be electrically connected to wiring 131[4]. In addition, the source of transistor 10[6] may also be electrically connected to wiring 132[1], the source of transistor 10[9] may also be electrically connected to wiring 132[2], and the source of transistor 10

[11] may also be electrically connected to wiring 132[3]. Note that, as Figure 4 As shown, when the capacitance value of capacitor 20[3] can be sufficiently ensured, capacitor 20[2] may be omitted.

[0127] The signal RIN is supplied to the terminal 115, the signal LIN is supplied to the terminal 117, the signal SROUT is supplied to the terminal 114, and the signal OUT is supplied to the terminal 116. In the first-stage signal output circuit 110a, the signal CLK_1 is supplied to the terminal 111, the signal CLK_2 is supplied to the terminal 112, the signal CLK_3 is supplied to the terminal 113, and the signal PWC_1 is supplied to the terminal 118.

[0128] In the second-stage signal output circuit 110 a , the signal CLK_2 is supplied to the terminal 111 , the signal CLK_3 is supplied to the terminal 112 , the signal CLK_4 is supplied to the terminal 113 , and the signal PWC_2 is supplied to the terminal 118 .

[0129] [Deformation Example 1]

[0130] Alternatively, transistor 10[3] or transistor 10[4] may be omitted. Figure 5 A circuit diagram of a signal output circuit 110b is shown as a modified example of the signal output circuit 110a. The signal output circuit 110b has a structure in which the transistor 10[4] is removed from the signal output circuit 110a. In addition, the source of the transistor 10[3] is electrically connected to the node ND[1]. By omitting the transistor 10[3] or the transistor 10[4], a signal output circuit 110b with a small footprint can be realized.

[0131] [Deformation Example 2]

[0132] Figure 6 A circuit diagram of a signal output circuit 110c is shown as a modified example of the signal output circuit 110a. Both the transistor 10[2] and the transistor 10[6] may be multi-gate transistors. Figure 6 An example is shown in which both transistor 10 [ 2 ] and transistor 10 [ 6 ] are configured using a dual-gate transistor which is a type of multi-gate transistor.

[0133] The source of transistor 10[2]a is electrically connected to the drain of transistor 10[2]b, and the drain of transistor 10[2]a is electrically connected to the source of transistor 10[1] and one of the source and drain of transistor 10[7]. The source of transistor 10[2]b is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[6]b, and wiring 132. The gate of transistor 10[2]a is electrically connected to the gate of transistor 10[2]b. That is, transistor 10[2]a and transistor 10[2]b are connected in series and combined to function as one transistor 10[2]. In addition, the gate of transistor 10[2]a and the gate of transistor 10[2]b are electrically connected to node ND[1]. Transistor 10[2] may also be a multi-gate transistor formed by connecting three or more transistors in series.

[0134] In addition, the source of transistor 10[6]a is electrically connected to the drain of transistor 10[6]b, and the drain of transistor 10[6]a is electrically connected to node ND[1]. The source of transistor 10[6]b is electrically connected to the other terminal of capacitor 20[1], the source of transistor 10[2]b, and wiring 132. The gate of transistor 10[6]a is electrically connected to the gate of transistor 10[6]b. That is, transistor 10[6]a and transistor 10[6]b are connected in series and combined to function as one transistor 10[6]. In addition, the gate of transistor 10[6]a and the gate of transistor 10[6]b are electrically connected to the gate of transistor 10[1] and terminal 117. Transistor 10[6] may also be a multi-gate transistor formed by connecting three or more transistors in series.

[0135] The insulation withstand voltage between the source and the drain of the multi-gate transistor is high. Therefore, the reliability of the circuit using the multi-gate transistor can be improved. Therefore, the reliability of the semiconductor device including the circuit can be improved. In addition, the multi-gate transistor can also be used for transistors other than transistor 10[2] and transistor 10[6].

[0136] [Deformation Example 3]

[0137] Figure 7 A circuit diagram of a signal output circuit 110d which is a modified example of the signal output circuit 110c is shown. The signal output circuit 110d is also a modified example of the signal output circuit 110a. The signal output circuit 110d includes a transistor 10

[12] . The source and drain of the transistor 10

[12] are electrically connected to the node ND[1] and the wiring 131, respectively. In addition, the gate of the transistor 10

[12] is electrically connected to the terminal 119.

[0138] The terminal 119 is supplied with a signal INIRES. The signal INIRES is used as a reset signal. While the potential H is supplied to the terminal 119 as the signal INIRES, the signal OUT and the signal SROUT become the potential L. Specifically, when the potential H is supplied to the terminal 119 as the signal INIRES, the transistor 10

[12] is turned on and the potential of the node ND1 becomes the potential H. When the potential of the node ND1 becomes the potential H, the transistor 10[9] is turned on and the potential L is supplied to the terminal 114. In addition, the transistor 10

[11] is turned on and the potential L is supplied to the terminal 116.

[0139] By providing the transistor 10

[12] , the operation of the signal output circuit 110d can be stopped at any timing.

[0140] [Deformation Example 4]

[0141] Figure 8 A circuit diagram of a signal output circuit 110e is shown as a modified example of the signal output circuit 110a. In the signal output circuit 110e, transistors including back gates are used as the transistors 10[2], 10[6], 10[9], and 10

[11] . The back gates of the transistors 10[2], 10[6], 10[9], and 10

[11] are electrically connected to the terminal 121 via the wiring 133.

[0142] The terminal 121 is supplied with a signal SEL. The signal SEL may be a fixed potential or a variable potential. When the signal SEL is a fixed potential, the potential L (VSS) or a potential lower than the potential L may be sufficient.

[0143] Here, the reliability of the transistor is explained. As one of the indicators for evaluating the reliability of the transistor, there is a GBTS (Gate Bias Temperature Stress) test in which an electric field is applied to the gate. Among them, the test in which a positive potential (positive bias) is applied to the gate relative to the source potential and the drain potential and the state is maintained at a high temperature is called a PBTS (Positive Bias Temperature Stress) test, and the test in which a negative potential (negative bias) is applied to the gate and the state is maintained at a high temperature is called an NBTS (Negative Bias Temperature Stress) test. In addition, the PBTS test and the NBTS test performed under the state of irradiation with light are respectively called the PBTIS (Positive Bias Temperature Illumination Stress) test and the NBTIS (Negative Bias Temperature Illumination Stress) test.

[0144] In an n-type transistor, a positive potential is applied to the gate when the transistor is turned on, so the change in threshold voltage in the PBTS test is one of the important factors to be considered as a reliability indicator of the transistor. In addition, in a p-type transistor, a negative potential is applied to the gate when the transistor is turned on, so the change in threshold voltage in the NBTS test is one of the important factors to be considered as a reliability indicator of the transistor. It can be said that the smaller the change in threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0145] During the operation of the shift register 100, the potential H (VDD) is maintained for a long period at the node ND[1] of the signal output circuit 110 (signal output circuit 110a, etc.). Therefore, the transistor 10[2], the transistor 10[9], and the transistor 10

[11] are applied with PBTS for a long period. In addition, the transistor 10[6] is applied with NBTS for a long period. By using a transistor including a back gate as the transistor 10[2], the transistor 10[6], the transistor 10[9], and the transistor 10

[11] , the degradation of the transistor characteristics caused by NBTS and PBTS can be suppressed.

[0146] In addition, even if the threshold voltage of the transistor drifts negatively (normally turned on) due to degradation of transistor characteristics, the transistor can be surely turned off by supplying a potential lower than the potential L to the back gate. Therefore, the potential of the node ND[1] can be surely ensured. Therefore, the operation of the signal output circuit 110 becomes stable and the reliability of the semiconductor device including the signal output circuit 110 can be improved.

[0147] In addition, when the operating speed of the shift register 100 is slow (the driving frequency is low), the period during which the node ND[1] and the like are in a floating state is long. By supplying a potential lower than the potential L to the back gate in such a case, the potential of the node ND[1] and the like can be reliably maintained. Therefore, the operation of the signal output circuit 110 becomes stable and the reliability of the semiconductor device including the signal output circuit 110 can be improved.

[0148] As described above, transistors 10[2], 10[9], and 10

[11] are subjected to PBTS for a long period, and transistor 10[6] is subjected to NBTS for a long period. Therefore, there is a possibility that transistors 10[2], 10[9], and 10

[11] may experience a difference in degradation of transistor characteristics compared to transistor 10[6].

[0149] Therefore, if Fig. 9 As shown, the back gates of transistors 10[2], 10[9], and 10

[11] may be electrically connected to terminal 121 via wiring 133, and the back gate of transistor 10[6] may be electrically connected to terminal 122 via wiring 134. In this case, terminal 121 is supplied with signal SEL_A as signal SEL, and terminal 122 is supplied with signal SEL_B as signal SEL. The potential of signal SEL_A may be the same as or different from the potential of signal SEL_B. For example, the potential of signal SEL_A may be different from the potential of signal SEL_B to make the transistor characteristics of transistors 10[2], 10[9], and 10

[11] different from the transistor characteristics of transistor 10[6].

[0150] In addition, the signal SEL_A may be synchronized with the signal RIN. For example, when the signal RIN is at a potential H, the signal SEL_A may be changed to a potential H. In addition, when the signal RIN is at a potential L, the signal SEL_A may be changed to a potential L or a potential lower than the potential L. When the signal SEL_A and the signal RIN are both at a potential H, the operating speed of the transistor 10[2], the transistor 10[9], and the transistor 10

[11] may be increased.

[0151] In addition, the signal SEL_B may be synchronized with the signal LIN. For example, when the signal LIN is at a potential H, the signal SEL_B may be at a potential H. In addition, when the signal LIN is at a potential L, the signal SEL_B may be at a potential L or a potential lower than the potential L. When both the signal SEL_B and the signal LIN are at a potential H, the operating speed of the transistor 10[6] may be increased.

[0152] [Deformation Example 5]

[0153] Fig.10A circuit diagram of a signal output circuit 110f which is a modified example of the signal output circuit 110c is shown. The signal output circuit 110f has a structure in which a transistor 10

[13] and a transistor 10

[14] are added to the signal output circuit 110c.

[0154] The gate of transistor 10

[13] is electrically connected to the source of transistor 10[1], the drain of transistor 10[2]a, and one of the source and drain of transistor 10[7]. The source of transistor 10

[13] is electrically connected to the source of transistor 10[2]a and the drain of transistor 10[2]b. The drain of transistor 10

[13] is electrically connected to wiring 135.

[0155] The gate of transistor 10

[14] is electrically connected to node ND[1]. The source of transistor 10

[14] is electrically connected to the source of transistor 10[6]a and the drain of transistor 10[6]b. The drain of transistor 10

[14] is electrically connected to wiring 136.

[0156] A potential SMP is supplied to the wiring 135 and the wiring 136. The potential SMP is preferably a potential higher than the potential L+Vth, and more preferably a potential higher than the potential L+2×Vth.

[0157] When the node ND[2] is supplied with a potential H (more precisely, a potential H-Vth), the transistor 10

[13] is turned on and the source of the transistor 10[2]a is supplied with a potential SMP. In addition, when the node ND[1] is supplied with a potential H, the transistor 10

[14] is turned on and the source of the transistor 10[6]a is supplied with a potential SMP. The potential SMP is preferably a fixed potential, but may also be a variable potential.

[0158] By setting the potential SMP to a potential higher than the potential L, when the gates of the transistors 10

[13] and 10

[14] are supplied with the potential L, the potential difference between the source and the gate becomes negative based on the potential of the source. Therefore, the transistors 10

[13] and 10

[14] can be more reliably turned off.

[0159] The signal output circuit 110 (signal output circuit 110a, signal output circuit 110c, and signal output circuit 110d) according to one embodiment of the present invention is a unipolar circuit formed using transistors of the same conductivity type (n-channel type). It is not necessary to use transistors of different conductivity types (p-channel type), so a signal output circuit with reduced manufacturing cost and high productivity can be realized. In addition, there is no need for a process for forming transistors of different conductivity types, so the manufacturing period is shortened and the yield rate is improved.

[0160] If necessary, p-channel transistors may be used in part of the signal output circuit 110. That is, transistors of different conductivity types may be used in part of the signal output circuit 110. For example, the signal output circuit 110 may include a CMOS (Complementary Metal-Oxide-Semiconductor) circuit including n-channel transistors and p-channel transistors. Note that in this embodiment, an example is shown in which all transistors constituting the signal output circuit 110 are n-channel transistors, but all of the above transistors may be replaced by p-channel transistors.

[0161] [Structure example of transistor]

[0162] An example of the structure of a transistor that can be used as the transistor 10 is described. Fig.11A is a plan view of the transistor 10 . Fig. 11B It is along Fig.11A A cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 11C is a perspective view of the transistor 10 . Fig.11D is an equivalent circuit diagram of transistor 10. In order to easily understand the structure of transistor 10, Fig.11A and Fig. 11C Part of the description of the components of the transistor 10 is omitted. Fig.11A and Fig. 11C in, omit Fig. 11B The insulating layer 164 etc. shown in FIG.

[0163] Fig. 12A and Fig. 12B yes Fig. 11B FIG. 1 is an enlarged view of transistor 10. In addition, Fig. 12C This is a diagram when the opening 159 is viewed from the Z direction.

[0164] In the transistor 10, an insulating layer 154 is provided over a substrate 153, and a conductive layer 155 is provided over the insulating layer 154. Furthermore, an insulating layer 156 is provided over the conductive layer 155, an insulating layer 157 is provided over the insulating layer 156, and an insulating layer 158 is provided over the insulating layer 157. Furthermore, a conductive layer 160 is provided over the insulating layer 158. In this specification and the like, the insulating layer 156, the insulating layer 157, and the insulating layer 158 are sometimes collectively referred to as an insulating layer 145.

[0165] In a region overlapping with a portion of the conductive layer 155, the conductive layer 160, the insulating layer 158, the insulating layer 157, and the insulating layer 156, an opening 159 is provided (see Fig. 11B and Fig. 12A). In addition, the opening 159 includes a semiconductor layer 161. The semiconductor layer 161 has a region overlapping with the bottom of the opening 159 and a region overlapping with the side of the opening 159. The semiconductor layer 161 has a region in contact with the insulating layer 145 in the opening 159. Specifically, the semiconductor layer 161 has a region in contact with the side of the insulating layer 158, a region in contact with the side of the insulating layer 157, and a region in contact with the side of the insulating layer 156. In addition, in the opening 159, a portion of the semiconductor layer 161 is in contact with the conductive layer 160, and another portion of the semiconductor layer 161 is in contact with the conductive layer 155. That is, a portion of the semiconductor layer 161 is electrically connected to the conductive layer 160, and another portion of the semiconductor layer 161 is electrically connected to the conductive layer 155.

[0166] An insulating layer 162 is provided on the insulating layer 158, the conductive layer 160, and the semiconductor layer 161, and a conductive layer 163 is provided on the insulating layer 162. In addition, an insulating layer 164 is provided on the insulating layer 162 and the conductive layer 163. The insulating layer 162 has a region overlapping with the side surface of the opening 159 via the semiconductor layer 161. The conductive layer 163 is provided so as to cover the semiconductor layer 161. Therefore, the conductive layer 163 has a region extending beyond the end of the semiconductor layer 161. In addition, the conductive layer 163 has a region overlapping with the side surface of the opening 159 via the insulating layer 162 and the semiconductor layer 161.

[0167] The conductive layer 155 has a region that functions as one of a source electrode and a drain electrode of the transistor 10. Further, the conductive layer 160 has a region that functions as the other of the source electrode and the drain electrode of the transistor 10. For example, when the conductive layer 155 is used as the drain electrode of the transistor 10, the conductive layer 160 is used as the source electrode of the transistor 10.

[0168] The semiconductor layer 161 has a region serving as a semiconductor layer forming a channel of the transistor 10 , the insulating layer 162 has a region serving as a gate insulating layer, and the conductive layer 163 has a region serving as a gate electrode. Thus, the transistor 10 is provided in a region including the opening 159 .

[0169] In the transistor 10, a source electrode and a drain electrode are arranged in the Z direction. Therefore, the source and drain of the transistor 10 are arranged at different positions in the Z direction, respectively. For example, with respect to the top surface of the substrate 153, the source and drain of the transistor 10 are arranged in a manner that the distances from the top surface of the reference substrate 153 are different from each other. Note that "arranged at different positions in the Z direction" is also referred to as "arranged at different heights". This transistor is sometimes also referred to as a "vertical channel transistor", "vertical channel transistor", "vertical transistor" or "VFET (Vertical Field Effect Transistor)". In a vertical channel transistor, the direction in which Id flows includes a component in the Z direction (longitudinal direction). For example, in the transistor 10 as a vertical channel transistor, when a cross section passing through the center (or center of gravity) of the opening 159 viewed in the Z direction is viewed from the X direction or the Y direction, the angle θ (refer to Fig. 12A ) is greater than 5 degrees and less than 110 degrees, greater than 10 degrees and less than 90 degrees, greater than 30 degrees and less than 90 degrees, or greater than 60 degrees and less than 90 degrees.

[0170] In addition, as described above, the semiconductor layer 161 has a region in contact with the side surface of the insulating layer 157. Therefore, Id flows along the side surface of the insulating layer 157. Therefore, the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the direction in which Id flows can also be expressed as the angle θ formed by the formed surface of the semiconductor layer 161 on the conductive layer 155 and the side surface of the insulating layer 157.

[0171] The vertical channel transistor can reduce the area occupied by the transistor because the source electrode and the drain electrode are arranged in the Z direction. By using the vertical channel transistor as a semiconductor device, the area occupied by the semiconductor device can be significantly reduced.

[0172] Here, an example of a material that can be used for the transistor 10 or the semiconductor device according to one embodiment of the present invention is described.

[0173] [Substrate]

[0174] There is no particular limitation on the material used for the substrate 153, the substrate 148 described later, and the substrate 152. The material can be determined based on the purpose, such as whether it is necessary to have light transmittance and heat resistance to withstand heat treatment. For example, a glass substrate such as barium borosilicate glass and aluminum borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or other insulating substrate can be used. In addition, a semiconductor substrate, a flexible substrate, a bonding film, a base film, etc. can also be used.

[0175] For example, the semiconductor substrate may be a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. The semiconductor substrate may be a single crystal semiconductor or a polycrystalline semiconductor.

[0176] When the transistor 10 according to one embodiment of the present invention is used as a substrate for a display device, for example, a glass substrate with a large area such as the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), or the tenth generation (2950 mm × 3400 mm) can be used. Thus, a large display device can be manufactured. Since more display devices can be manufactured from one substrate, the manufacturing cost can be reduced by enlarging the substrate.

[0177] As materials for flexible substrates, bonding films, base films, etc., for example, the following materials can be used: polyesters such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile, acrylic resin, polyimide, polymethyl methacrylate, polycarbonate (PC), polyether sulfone (PES), polyamide (nylon, aromatic polyamide, etc.), polysiloxane, cycloolefin resin, polystyrene, polyamide-imide, polyurethane, polyvinyl chloride, polyvinylidene chloride, polypropylene, polytetrafluoroethylene (PTFE), ABS resin, and cellulose nanofibers, etc.

[0178] By using the above-mentioned material as a substrate, a lightweight semiconductor device including the transistor 10 can be provided. In addition, by using the above-mentioned material as a substrate, a semiconductor device with high impact resistance can be provided. In addition, by using the above-mentioned material as a substrate, a semiconductor device that is not easily damaged can be provided.

[0179] The lower the linear expansion coefficient of the flexible substrate used as the substrate, the more deformation due to the environment can be suppressed, so it is preferred. For example, a flexible substrate with a linear expansion coefficient of 1×10 -3 / K or less, 5×10 -5 / K or less or 1×10 -5 / K or less. In particular, aramid has a low linear expansion coefficient and is therefore suitable for use in flexible substrates.

[0180] [Conductive layer]

[0181] As the conductive material that can be used for the gate electrode, source electrode and drain electrode of the transistor 10, the conductive layer of various wirings and electrodes constituting the semiconductor device, etc., metal elements selected from aluminum (Al), chromium (Cr), copper (Cu), silver (Ag), gold (Au), platinum (Pt), tantalum (Ta), nickel (Ni), titanium (Ti), molybdenum (Mo), tungsten (W), hafnium (Hf), vanadium (V), niobium (Nb), manganese (Mn), magnesium (Mg), zirconium (Zr), beryllium (Be), etc., alloys containing the above metal elements as components, or alloys combining the above metal elements, etc. can be used. In addition, semiconductors represented by polycrystalline silicon containing impurity elements such as phosphorus and silicides such as nickel silicide can also be used. There is no particular limitation on the method for forming the conductive material, and various formation methods such as evaporation, atomic layer deposition (ALD: Atomic Layer Deposition) method, chemical vapor deposition (CVD: Chemical Vapor Deposition) method, sputtering method, spin coating method, etc. can be used.

[0182] In addition, as a conductive material, a Cu-X alloy (X is Mn, Ni, Cr, Fe, Co, Mo, Ta or Ti) can also be used. The layer formed using the Cu-X alloy can be processed by a wet etching process, thereby suppressing the manufacturing cost. In addition, as a conductive material, an aluminum alloy containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0183] As the conductive material that can be used for the conductive layer, a conductive material containing oxygen such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. can also be used. In addition, a conductive material containing nitrogen such as titanium nitride, tantalum nitride, tungsten nitride, etc. can also be used. In addition, the conductive layer can also adopt a laminated structure in which a conductive material containing oxygen, a conductive material containing nitrogen, and a material containing the above-mentioned metal element are appropriately combined.

[0184] For example, the conductive layer can adopt a single-layer structure of an aluminum layer containing silicon, a two-layer structure of a titanium layer stacked on an aluminum layer, a two-layer structure of a titanium layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a titanium nitride layer, a two-layer structure of a tungsten layer stacked on a tantalum nitride layer, and a three-layer structure of a titanium layer, an aluminum layer, and a titanium layer stacked in sequence.

[0185] In addition, a plurality of conductive layers formed of the above conductive materials may be stacked. For example, the conductive layer may also adopt a laminated structure in which a material containing the above metal element and a conductive material containing oxygen are combined. In addition, a laminated structure in which a material containing the above metal element and a conductive material containing nitrogen are combined may be adopted. In addition, a laminated structure in which a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined may be adopted.

[0186] For example, the conductive layer may also have a three-layer structure in which a conductive layer containing at least one of indium and zinc and oxygen, a conductive layer containing copper, and a conductive layer containing at least one of indium and zinc and oxygen are sequentially stacked. In this case, it is preferred that the side of the conductive layer containing copper is also covered with a conductive layer containing at least one of indium and zinc and oxygen. In addition, for example, as the conductive layer, a plurality of conductive layers containing at least one of indium and zinc and oxygen may be stacked.

[0187] [Insulation layer]

[0188] As each insulating layer, a single layer or a stack of insulating materials selected from the following may be used: aluminum nitride, aluminum oxide, aluminum oxynitride, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon oxynitride, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, aluminosilicate, etc. In addition, a material formed by mixing multiple types of oxide materials, nitride materials, oxynitride materials, and oxynitride materials may also be used.

[0189] The method for forming the insulating material is not particularly limited, and various formation methods such as vapor deposition, ALD, CVD, sputtering, and spin coating can be used.

[0190] In this specification, etc., nitrogen oxide refers to a material containing more nitrogen than oxygen. In addition, oxynitride refers to a material containing more oxygen than nitrogen. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

[0191] For example, the insulating layer 154 and the insulating layer 164 are preferably formed using an insulating material that does not easily allow impurities to pass through. For example, a single layer or a stack of insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used. For example, as an example of an insulating material that does not easily allow impurities to pass through, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon nitride, etc. can be cited.

[0192] By using an insulating material that does not easily allow impurities to pass through as the insulating layer 154, diffusion of impurities from the substrate 153 side can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of the semiconductor device including the transistor 10 can be improved. By using an insulating material that does not easily allow impurities to pass through as the insulating layer 164, diffusion of impurities from above the insulating layer 164 can be suppressed, and the reliability of the transistor 10 can be improved. That is, the reliability of the semiconductor device including the transistor 10 can be improved.

[0193] In addition, as the insulating layer, an insulating layer used as a planarization layer can also be used. As the material of the insulating layer used as the planarization layer, acrylic resin, polyimide, epoxy resin, polyamide, polyimide amide, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of these resins can be cited. In addition to the above-mentioned organic materials, low dielectric constant materials (low-k materials), siloxane resins, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass) and the like can also be used. In addition, multiple insulating layers formed of these materials can also be stacked.

[0194] In addition, siloxane resin is equivalent to a resin containing Si-O-Si bonds formed using siloxane materials as starting materials. Siloxane resin can also use organic groups (such as alkyl groups or aryl groups) or fluoro groups as substituents. In addition, the organic group can also include a fluoro group.

[0195] In addition, the surface of the insulating layer etc. may be subjected to CMP treatment. By performing CMP treatment, the surface irregularities of the insulating layer etc. can be reduced, and the coverage of the insulating layer and the conductive layer to be formed later can be improved.

[0196] [Semiconductor layer]

[0197] As the semiconductor layer 161, a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used alone or in combination. As the semiconductor material, for example, a semiconductor material having a band gap such as silicon or germanium (a semiconductor material that is not a zero band gap semiconductor) can be used. For example, it is preferred to use a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, etc.) for the semiconductor material. As the compound semiconductor, an organic substance having semiconductor characteristics or a metal oxide having semiconductor characteristics (also referred to as an oxide semiconductor) can be used. Note that these semiconductor materials may also contain impurities as dopants.

[0198] For example, single crystal silicon, polycrystalline silicon, microcrystalline silicon, or amorphous silicon may be used as the semiconductor layer 161. As the polycrystalline silicon, for example, low temperature polycrystalline silicon (LTPS: Low Temperature Poly Silicon) may be used.

[0199] A transistor using amorphous silicon as the semiconductor layer 161 can be formed on a large glass substrate and can be manufactured at low cost. A transistor using polycrystalline silicon as the semiconductor layer 161 has high field effect mobility and can operate at high speed. In addition, a transistor using microcrystalline silicon as the semiconductor layer 161 has high field effect mobility compared to a transistor using amorphous silicon and can operate at high speed.

[0200] As compound semiconductors that can be used as semiconductor materials, silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide can be cited. Boron nitride that can be used for the semiconductor layer preferably has an amorphous structure. Boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.

[0201] The semiconductor layer 161 may also include a layered material used as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. A layered crystalline structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked by bonds such as van der Waals forces that are weaker than covalent bonds and ionic bonds. The layered material has high conductivity in a unit layer, that is, has high two-dimensional conductivity. By using a material used as a semiconductor and having high two-dimensional conductivity in a channel formation region, a transistor with a large on-state current can be provided.

[0202] As layered substances, for example, graphene, silicene, boron carbonitride, chalcogenides, etc. can be cited. In boron carbonitride as a layered substance, carbon atoms, nitrogen atoms and boron atoms are arranged on a plane in a hexagonal lattice structure. Chalcogenides are compounds containing chalcogen elements. In addition, chalcogen elements are a general term for elements belonging to the 16th group, including oxygen, sulfur, selenium, tellurium, polonium, and lead. In addition, as chalcogenides, transition metal chalcogenides, 13th group chalcogenides, etc. can be cited. As transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically, molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. By using the above transition metal chalcogenides for the semiconductor layer, a storage device with a large on-state current can be provided.

[0203] The band gap of an oxide semiconductor is greater than 2 eV, so the off-state current of a transistor (also referred to as an "OS transistor") that uses an oxide semiconductor of one of the metal oxides in a semiconductor layer in which a channel is formed is extremely small. As a result, the power consumption of a semiconductor device including an OS transistor can be reduced. In addition, an OS transistor operates stably even in a high-temperature environment, and its characteristics vary less. For example, even in a high-temperature environment, the off-state current hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, the off-state current hardly increases. In addition, even in a high-temperature environment, the on-state current is not easy to drop. Therefore, a semiconductor device including an OS transistor operates stably even in a high-temperature environment and has high reliability.

[0204] In this embodiment and the like, an OS transistor is preferably used as the transistor 10. Since the insulation withstand voltage between the source and the drain of the OS transistor is high, the channel length can be shortened. Therefore, the on-state current can be increased. The OS transistor is suitable for a vertical channel transistor.

[0205] The channel length L may be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, or 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L may be set to 100 nm or more and 1 μm or less.

[0206] As metal oxides that can be used for the semiconductor layer of the OS transistor, for example, indium oxide, gallium oxide, and zinc oxide can be cited. The metal oxide preferably contains at least indium (In) or zinc (Zn). In addition, the metal oxide preferably contains two or three selected from indium, element M, and zinc. Note that element M is a metal element or a semi-metal element having a high bonding energy with oxygen, for example, a metal element or a semi-metal element having a higher bonding energy with oxygen than indium.

[0207] Element M specifically includes aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. Element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and further preferably gallium. Note that in this specification, etc., metal elements and semi-metal elements are sometimes collectively referred to as "metal elements", and sometimes the "metal elements" described in this specification, etc. include semi-metal elements.

[0208] For example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also denoted as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0209] By increasing the ratio of the number of atoms of indium contained in the metal oxide relative to the total number of atoms of all metal elements, the field effect mobility of the transistor can be increased.

[0210] Metal oxides may also replace indium or include one or more of the metal elements with a large period number in addition to indium. Metal oxides have a tendency that the greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As metal elements with a large period number, metal elements belonging to the fifth period and metal elements belonging to the sixth period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0211] The metal oxide may also contain one or more non-metallic elements. The inclusion of non-metallic elements in the metal oxide may sometimes improve the field effect mobility of the transistor. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0212] By increasing the ratio of the number of zinc atoms in the main component elements contained in the metal oxide relative to the total number of metal element atoms, a highly crystalline metal oxide is obtained, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed and the reliability can be improved.

[0213] By increasing the ratio of the number of atoms of the element M in the main component elements contained in the metal oxide relative to the sum of the number of atoms of the metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the variation of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0214] The electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the semiconductor layer. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required for the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0215] When In-Zn oxide is used as the semiconductor layer of the OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of zinc. For example, a metal oxide in which the atomic ratio of the metal elements is In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, In:Zn=10:1 or a metal oxide in the vicinity thereof can be used.

[0216] When In-Sn oxide is used as the semiconductor layer of the OS transistor, it is preferable to use a metal oxide in which the atomic ratio of indium is greater than the atomic ratio of tin. For example, a metal oxide in which the atomic ratio of the metal elements is In:Sn=1:1, In:Sn=2:1, In:Sn=3:1, In:Sn=4:1, In:Sn=5:1, In:Sn=7:1, In:Sn=10:1 or a metal oxide in the vicinity thereof can be used.

[0217] When In-Sn-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of tin can be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of tin. For example, the atomic ratios of the metal elements In:Sn:Zn=2:1:3, In:Sn:Zn=3:1:2, In:Sn:Zn=4:2:3, In:Sn:Zn=4:2:4.1, In:Sn:Zn=5:1:3, In:Sn:Zn=5:1:6, In:Sn:Zn=5:1:7, In:Sn:Zn=5:1:8, In:Sn:Zn =6:1:6、In:Sn:Zn=10:1:3、In:Sn:Zn=10:1:6、In:Sn:Zn=10:1:7、In:Sn:Zn=10:1:8、In :Sn:Zn=5:2:5, In:Sn:Zn=10:1:10, In:Sn:Zn=20:1:10, In:Sn:Zn=40:1:10 or metal oxides near them.

[0218] When In-Al-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of aluminum can be used. Furthermore, it is preferred to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of aluminum. For example, the atomic ratios of the metal elements In:Al:Zn=2:1:3, In:Al:Zn=3:1:2, In:Al:Zn=4:2:3, In:Al:Zn=4:2:4.1, In:Al:Zn=5:1:3, In:Al:Zn=5:1:6, In:Al:Zn=5:1:7, In:Al:Zn=5:1:8, In:Al:Zn=6:1:

[0219] 6. In: Al: Zn = 10: 1: 3, In: Al: Zn = 10: 1: 6, In: Al: Zn = 10: 1:

[0220] 7. In:Al:Zn=10:1:8, In:Al:Zn=5:2:5, In:Al:Zn=10:1:10, In:Al:Zn=20:1:10, In:Al:Zn=40:1:10 or metal oxides thereof.

[0221] When In-Ga-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the atomic ratio of gallium can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. For example, the atomic ratios of the metal elements In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In:Ga:Zn =6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereof.

[0222] When In-M-Zn oxide is used as the semiconductor layer of the OS transistor, a metal oxide in which the atomic ratio of indium relative to the atomic ratio of the metal element is higher than the atomic ratio of the element M can be used. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of the element M. For example, the atomic ratios of the metal elements In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M:Zn =6:1:6, In:M:Zn=10:1:3, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10 or metal oxides thereabouts.

[0223] Note that when a plurality of metal elements are included as the element M, the sum of the atomic ratios of the metal elements may be the atomic ratio of the element M. For example, when an In-Ga-Al-Zn oxide including gallium and aluminum is used as the element M, the sum of the atomic ratio of gallium and the atomic ratio of aluminum may be the atomic ratio of the element M. In addition, the atomic ratio of indium, the element M, and zinc is preferably within the above range.

[0224] It is preferable to use a metal oxide in which the ratio of the number of atoms of indium in the main component elements contained in the metal oxide to the total number of atoms of the metal elements is 30 atomic % or more and 100 atomic % or less, preferably 30 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 95 atomic % or less, more preferably 35 atomic % or more and 90 atomic % or less, more preferably 40 atomic % or more and 90 atomic % or less, more preferably 45 atomic % or more and 90 atomic % or less, more preferably 50 atomic % or more and 80 atomic % or less, more preferably 60 atomic % or more and 80 atomic % or less, more preferably 70 atomic % or more and 80 atomic % or less. For example, in the case of using In-M-Zn oxide as the semiconductor layer, the ratio of the number of atoms of indium to the total number of atoms of indium, element M and zinc is preferably within the above range.

[0225] As described above, when the ratio of the number of atoms of indium relative to the sum of the number of atoms of metal elements in the main component elements contained in the metal oxide is increased, the field effect mobility of the transistor can be increased. By using this transistor, a circuit capable of high-speed operation can be manufactured. Furthermore, the occupied area of ​​the circuit can be reduced. For example, when the transistor is used in a large display device or a high-definition display device, the signal delay of each wiring can also be reduced when the number of wirings increases, thereby suppressing uneven display. In addition, since the occupied area of ​​the circuit can be reduced, the frame of the display device can be reduced.

[0226] The composition of metal oxides can be analyzed, for example, using energy dispersive X-ray analysis (EDX: Energy Dispersive X-ray spectroscopy), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy), inductively coupled plasma mass spectrometry (ICP-MS: Inductively Coupled Plasma-Mass Spectrometry) or inductively coupled plasma atomic emission spectrometry (ICP-AES: Inductively Coupled Plasma-Atomic Emission Spectrometry). Alternatively, multiple of the above methods can be combined for analysis. Note that the actual content of elements with low content is sometimes different from the content obtained by analysis due to the influence of analysis accuracy. For example, when the content of element M is low, the content of element M obtained by analysis is sometimes lower than the actual content.

[0227] The metal oxide is preferably formed by sputtering or ALD. Note that when the metal oxide is formed by sputtering, the atomic ratio of the target material is sometimes different from the atomic ratio of the metal oxide. In particular, the atomic ratio of zinc in the metal oxide is sometimes smaller than the atomic ratio of zinc in the target material. Specifically, the atomic ratio of zinc is sometimes about 40% or more and 90% or less of the atomic ratio of zinc in the target material.

[0228] By using a metal oxide that does not contain gallium or has a low gallium content in the semiconductor layer, a transistor with high reliability for forward bias application can be realized. In other words, a transistor with a small change in threshold voltage in a PBTS test can be realized. In addition, when a metal oxide containing gallium is used, the gallium content is preferably lower than the indium content. Thus, a transistor with high reliability can be realized.

[0229] One of the reasons for the change in threshold voltage in the PBTS test is the defect state at or near the interface between the semiconductor layer and the gate insulating layer. The greater the defect state density, the more significant the degradation in the PBTS test. The generation of the defect state can be suppressed by reducing the gallium content in the region of the semiconductor layer that contacts the gate insulating layer.

[0230] The reason why the change of the threshold voltage in the PBTS test can be suppressed by using a metal oxide that does not contain gallium or has a low gallium content as a semiconductor layer is, for example, as follows. Gallium contained in the metal oxide is more likely to absorb oxygen than other metal elements (such as indium or zinc). Therefore, it can be inferred that at the interface between the metal oxide containing more gallium and the gate insulating layer, carrier (here, electron) trap sites are easily generated by bonding between gallium and excess oxygen in the gate insulating layer. Therefore, when a positive potential is applied to the gate, carriers are captured at the interface between the semiconductor layer and the gate insulating layer, and the threshold voltage will change.

[0231] More specifically, when In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of gallium can be used for the semiconductor layer. It is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of gallium. In other words, a metal oxide in which the atomic ratio of metal elements satisfies In>Ga and Zn>Ga is used for the semiconductor layer.

[0232] For example, the semiconductor layer of the OS transistor may use metal elements with atomic ratios of In:Ga:Zn=2:1:3, In:Ga:Zn=3:1:2, In:Ga:Zn=4:2:3, In:Ga:Zn=4:2:4.1, In:Ga:Zn=5:1:3, In:Ga:Zn=5:1:6, In:Ga:Zn=5:1:7, In:Ga:Zn=5:1:8, In: Ga:Zn=6:1:6, In:Ga:Zn=10:1:3, In:Ga:Zn=10:1:6, In:Ga:Zn=10:1:7, In:Ga:Zn=10:1:8, In:Ga:Zn=5:2:5, In:Ga:Zn=10:1:10, In:Ga:Zn=20:1:10, In:Ga:Zn=40:1:10 or metal oxides thereabouts.

[0233] The semiconductor layer of the OS transistor preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is higher than 0 atomic % and is less than 50 atomic %, preferably greater than 0.1 atomic % and less than 40 atomic %, more preferably greater than 0.1 atomic % and less than 35 atomic %, more preferably greater than 0.1 atomic % and less than 30 atomic %, more preferably greater than 0.1 atomic % and less than 25 atomic %, more preferably greater than 0.1 atomic % and less than 20 atomic %, more preferably greater than 0.1 atomic % and less than 15 atomic %, more preferably greater than 0.1 atomic % and less than 10 atomic %. By reducing the ratio of the number of atoms of gallium to the number of atoms of the metal element in the semiconductor layer, a transistor with high resistance to the PBTS test can be realized. Note that by containing gallium in the metal oxide, it is less likely to generate oxygen vacancies (V O : Oxygen Vacancy) effect.

[0234] As the semiconductor layer of the OS transistor, a metal oxide that does not contain gallium can also be used. For example, In-Zn oxide can be used for the semiconductor layer. At this time, when the atomic number ratio of indium contained in the metal oxide relative to the atomic number of the metal element is increased, the field effect mobility of the transistor can be improved. On the other hand, when the atomic number ratio of zinc contained in the metal oxide relative to the atomic number of the metal element is increased, the metal oxide has high crystallinity, so the variation of the electrical characteristics of the transistor is suppressed, and the reliability can be improved. In addition, as the semiconductor layer, a metal oxide such as indium oxide that does not contain gallium and zinc can also be used. By using a metal oxide that does not contain gallium, the variation of the threshold voltage in the PBTS test can be made extremely small, especially.

[0235] For example, an oxide containing indium and zinc can be used as the semiconductor layer. In this case, for example, a metal oxide having an atomic ratio of metal elements of In:Zn=2:3, In:Zn=4:1 or a ratio close to this can be used.

[0236] Note that although gallium is used as an example for the description, the invention can also be applied to the case where element M is used instead of gallium. As the semiconductor layer, a metal oxide in which the atomic ratio of indium is higher than the atomic ratio of element M is preferably used. In addition, a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M is preferably used.

[0237] A transistor having high reliability in case of forward bias application can be realized by using a metal oxide having a low content of element M as a semiconductor layer. A semiconductor device having high reliability can be realized by using this transistor as a transistor that needs to have high reliability in case of forward bias application.

[0238] Next, the reliability of transistors with respect to light will be described.

[0239] When light enters a transistor, the electrical characteristics of the transistor may change. It is particularly preferred that the transistor used in an area where light may enter has small changes in electrical characteristics under light irradiation and high reliability to light. Reliability to light can be evaluated, for example, by the change in threshold voltage in an NBTIS test.

[0240] By increasing the content of the element M in the metal oxide used for the semiconductor layer, a transistor with high reliability to light can be realized. That is, a transistor with a small change in threshold voltage in the NBTIS test can be realized. Specifically, the band gap of the metal oxide in which the atomic number ratio of the element M is greater than the atomic number ratio of indium is larger, and the change in threshold voltage in the NBTIS test of the transistor can be reduced. The band gap of the metal oxide contained in the semiconductor layer is preferably greater than 2.0 eV, more preferably greater than 2.5 eV, more preferably greater than 3.0 eV, more preferably greater than 3.2 eV, more preferably greater than 3.3 eV, more preferably greater than 3.4 eV, and more preferably greater than 3.5 eV.

[0241] For example, the semiconductor layer can use a metal oxide having an atomic ratio of metal elements of In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4 or thereabouts.

[0242] The semiconductor layer particularly preferably uses the following metal oxide: the ratio of the number of atoms of element M relative to the number of atoms of the metal element contained is greater than 20 atomic % and less than 70 atomic %, preferably greater than 30 atomic % and less than 70 atomic %, more preferably greater than 30 atomic % and less than 60 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0243] When In-Ga-Zn oxide is used as the semiconductor layer, a metal oxide in which the atomic ratio of indium to the atomic ratio of the metal element is less than the atomic ratio of gallium can be used. For example, a metal oxide in which the atomic ratio of the metal element is In:Ga:Zn=1:1:1, In:Ga:Zn=1:1:1.2, In:Ga:Zn=1:3:2, In:Ga:Zn=1:3:3, In:Ga:Zn=1:3:4 or a metal oxide in the vicinity thereof can be used.

[0244] The semiconductor layer particularly preferably uses a metal oxide in which the ratio of the number of atoms of gallium to the number of atoms of the metal element contained is greater than 20 atomic % and less than 60 atomic %, preferably greater than 20 atomic % and less than 50 atomic %, more preferably greater than 30 atomic % and less than 50 atomic %, more preferably greater than 40 atomic % and less than 60 atomic %, and more preferably greater than 50 atomic % and less than 60 atomic %.

[0245] A transistor with high reliability against light can be realized by using a metal oxide having a high content of the element M for the semiconductor layer. A semiconductor device with high reliability can be realized by using this transistor as a transistor that needs to have high reliability against light.

[0246] The semiconductor layer may also have a stacked structure including two or more metal oxide layers. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form it, thereby reducing the manufacturing cost.

[0247] The compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other. For example, a two-layer stacked structure may be used, in which a first metal oxide layer having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto and a second metal oxide layer having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto superimposed on the first metal oxide layer. In addition, gallium or aluminum is particularly preferably used as the element M. For example, a stacked structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one of IAZO, IAGZO, and ITZO (registered trademark) may be used.

[0248] For example, a stacked structure may be used in which a first metal oxide layer has a composition of In:M:Zn=1:1:1 [atomic ratio] or thereabouts and a second metal oxide layer has a composition of In:Zn=4:1 [atomic ratio] or thereabouts provided on the first metal oxide layer.

[0249] For example, a three-layer stacked structure may be used, in which a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the first layer, a semiconductor layer having an atomic ratio of metal elements of In:Zn=4:1 is used as the second layer, and a semiconductor layer having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is used as the third layer. The band gap of the semiconductor layers of the first and third layers is preferably larger than the band gap of the semiconductor layer of the second layer. By adopting this structure, the second layer can be used as the main current path, so a so-called buried channel structure can be realized.

[0250] As the semiconductor layer, a crystalline metal oxide layer is preferably used. For example, a metal oxide layer having a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, a microcrystalline (nc: nano-crystal) structure, etc. can be used. By using a crystalline metal oxide layer for the semiconductor layer, the defect state density in the semiconductor layer can be reduced, thereby realizing a display device with high reliability.

[0251] The higher the crystallinity of the metal oxide layer used for the semiconductor layer, the lower the defect state density in the semiconductor layer can be. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0252] When a metal oxide layer is formed by sputtering, the higher the substrate temperature (stage temperature) during formation, the more crystalline the metal oxide layer can be formed. In addition, the higher the flow rate ratio of the oxygen gas relative to the entire deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio) is, the more crystalline the metal oxide layer can be formed.

[0253] The semiconductor layer of the OS transistor may also have a stacked structure of two or more metal oxide layers with different crystallinity. For example, a stacked structure may have a first metal oxide layer and a second metal oxide layer disposed on the first metal oxide layer, and the second metal oxide layer may include a region whose crystallinity is higher than that of the first metal oxide layer. Alternatively, the second metal oxide layer may include a region whose crystallinity is lower than that of the first metal oxide layer. The compositions of the two or more metal oxide layers included in the semiconductor layer may also be the same or substantially the same as each other. By adopting a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used to form them, thereby reducing manufacturing costs. For example, by using the same sputtering target to make the oxygen flow ratio different, a stacked structure of two or more metal oxide layers with different crystallinity can be formed. Note that the compositions of the two or more metal oxide layers included in the semiconductor layer may also be different from each other.

[0254] The transistor 10 shown in this embodiment mode has a channel length L determined by the thickness of the insulating layer provided between the conductive layer 160 and the conductive layer 155. Therefore, a transistor having a short channel length L can be manufactured with high precision. In addition, the characteristic non-uniformity among the plurality of transistors 10 can also be reduced. Therefore, the operation of the semiconductor device including the transistor 10 is stable, and the reliability can be improved. In addition, when the characteristic non-uniformity is reduced, the circuit design freedom of the semiconductor device is improved, and thus the operating voltage can also be reduced. Thus, the power consumption of the semiconductor device can be reduced.

[0255] When an oxide semiconductor is used for the semiconductor layer 161, a hydrogen-containing material is preferably used for the insulating layer 156 and the insulating layer 158. Since the insulating layer containing hydrogen is in contact with the oxide semiconductor, the oxide semiconductor in the region in contact with the insulating layer is converted to n-type, and thus can be used as a source region or a drain region. As the insulating layer, for example, a material containing silicon, nitrogen, and hydrogen can be used. Specifically, hydrogen-containing silicon nitride or hydrogen-containing silicon nitride oxide can be used.

[0256] When an oxide semiconductor is used for the semiconductor layer 161, a conductive material that converts the oxide semiconductor into an n-type is preferably used as the conductive layer 155 in contact with the semiconductor layer 161 and the conductive layer 160 in contact with the semiconductor layer 161. For example, a conductive material containing nitrogen may be used. For example, a conductive material containing titanium or tantalum and nitrogen may be used. In addition, other conductive materials may be provided in a manner overlapping with the conductive material containing nitrogen.

[0257] On the other hand, the insulating layer 157 preferably uses a material in which hydrogen is reduced and contains oxygen. For example, a material containing silicon and oxygen may be used. Specifically, silicon oxide or silicon oxynitride may be used. Since hydrogen is an impurity element in an oxide semiconductor, when the semiconductor layer 161 as an oxide semiconductor contacts the insulating layer 157 in which hydrogen is reduced, the semiconductor layer 161 is not easily converted to an n-type. When the semiconductor layer 161 as an oxide semiconductor contacts the insulating layer 157 containing oxygen, oxygen vacancies in the semiconductor layer 161 are reduced, the characteristics of the transistor 10 are stabilized, and the reliability is improved.

[0258] When an oxide semiconductor is used for the semiconductor layer 161, the insulating layer 157 preferably contains excess oxygen. In this specification, etc., "excess oxygen" refers to oxygen released by heating. In addition, when a material containing excess oxygen is used for the insulating layer 157, a material that is not easily permeable to oxygen is preferably used for the insulating layer 156 and the insulating layer 158. As a material that is not easily permeable to oxygen, for example, an oxide containing one or both of aluminum and hafnium, a nitride of silicon, or the like can be used. By using a material that is not easily permeable to oxygen for the insulating layer 156 and the insulating layer 158, the excess oxygen contained in the insulating layer 157 is not easily released to the lower layer or the upper layer. Therefore, sufficient oxygen can be supplied to the oxide semiconductor. For example, an insulating layer (insulating layer 157) containing silicon and oxygen can be included between two insulating layers (insulating layer 156, insulating layer 158) containing silicon and nitrogen.

[0259] When an oxide semiconductor is used for the semiconductor layer 161 and a hydrogen-containing material is used for the insulating layer 156 and the insulating layer 158, a region of the semiconductor layer 161 in contact with the conductive layer 160 and a region of the semiconductor layer 161 in contact with the insulating layer 158 are used as one of the source (source region) and the drain (drain region). In addition, a region of the semiconductor layer 161 in contact with the conductive layer 155 and a region of the semiconductor layer 161 in contact with the insulating layer 156 are used as the other of the source (source region) and the drain (drain region). Therefore, the channel length L of the transistor 10 is determined by the thickness t of the insulating layer 157 (see Fig. 12A ).

[0260] The insulating layer 156 and the insulating layer 158 may also use a material that does not contain hydrogen or contains very little hydrogen. For example, silicon nitride with very little hydrogen or silicon nitride oxide with very little hydrogen may be used. At this time, the region of the semiconductor layer 161 that is in contact with the insulating layer 156 and the region of the semiconductor layer 161 that is in contact with the insulating layer 158 are not converted to n-type. Therefore, the region of the semiconductor layer 161 that is in contact with the conductive layer 160 is used as one of the source (source region) and the drain (drain region). In addition, the region of the semiconductor layer 161 that is in contact with the conductive layer 155 is used as the other of the source (source region) and the drain (drain region). At this time, the total thickness ts of the insulating layer 156, the insulating layer 157, and the insulating layer 158 corresponds to the channel length L of the transistor 10 (see Fig. 12A ).

[0261] The channel length L can be controlled by adjusting the thickness of the insulating layer 156, the insulating layer 157, and the insulating layer 158. The channel length L can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more and less than 3 μm, 2.5 μm or less, 2 μm or less, 1.5 μm or less, 1.2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less. For example, the channel length L can be set to be 100 nm or more and 1 μm or less.

[0262] In this embodiment, three insulating layers (insulating layer 156, insulating layer 157, insulating layer 158) are included between conductive layer 155 and conductive layer 160, but the number of insulating layers between conductive layer 155 and conductive layer 160 is not limited thereto. The number of insulating layers between conductive layer 155 and conductive layer 160 may be one, two, or four or more layers.

[0263] The semiconductor layer 161 is disposed in the opening 159, and the perimeter p of the opening 159 is equal to the channel width W of the transistor 10 (refer to Fig. 12C ). The perimeter p can be obtained, for example, from the position where the thickness t of the insulating layer 157 is half (t / 2) or the position where the thickness ts is half (ts / 2). Note that the perimeter of any position of the opening 159 can be set as the channel width W as needed. For example, the perimeter p of the lowest portion of the opening 159 can be set as the channel width W, or the perimeter p of the highest portion of the opening 159 can be set as the channel width W.

[0264] exist Fig. 12C In the figure, the outline (planar shape) of the opening 159 viewed from the Z direction is shown as a circle, but the present invention is not limited to this. For example, the outline of the opening 159 viewed from the Z direction may also be an ellipse (see Fig.12D ) or rectangle (refer to Fig.12E ).Notice, Fig.12EIn addition, for example, the outline of the opening 159 viewed from the Z direction may also be a shape including one or both of a straight line portion and a curved line portion (see Fig.12F ).

[0265] In the transistor 10 according to one embodiment of the present invention, the capacitance value of the parasitic capacitance generated between the gate and the source is different from the capacitance value of the parasitic capacitance generated between the gate and the drain. Specifically, of the capacitor C1 formed in the region where the conductive layer 160 and the conductive layer 163 overlap on the insulating layer 145 and the capacitor C2 formed in the region where the conductive layer 155 and the conductive layer 163 overlap in the opening 159, the capacitance value of the capacitor C1 is larger than the capacitance value of the capacitor C2 (see Fig.11D and Fig. 12B ).

[0266] Fig.13A and Fig. 13B Shown with Fig.11A When the transistor 10 according to one embodiment of the present invention is viewed from the Z direction, the conductive layer 163 overlaps with the conductive layer 160 so as to surround the opening 159 at the periphery of the opening 159 and overlaps with the conductive layer 160 at the bottom of the opening 159 .

[0267] exist Fig.13A In FIG. 1 , a region used as the capacitor C1 when viewed from the Z direction is hatched. A region on the insulating layer 145 where the conductive layer 160 and the conductive layer 163 overlap each other via the semiconductor layer 161 and the insulating layer 162 is used as the capacitor C1 (see FIG. 1 ). Fig. 12B and Fig.13A ). Note that Fig.13A The description of the insulating layer 145 and the insulating layer 162 is omitted.

[0268] exist Fig. 13B In FIG. 1 , a region used as capacitor C2 when viewed from the Z direction is hatched. At the bottom of the opening 159, a region where the conductive layer 155 and the conductive layer 163 overlap each other via the semiconductor layer 161 and the insulating layer 162 is used as capacitor C2 (see FIG. 1 ). Fig. 12B and Fig. 13B ). Note that Fig. 13B The description of the insulating layer 145 and the insulating layer 162 is omitted.

[0269] from Fig.13A and Fig. 13B It can be seen that the area of ​​the region used as capacitor C2 is larger than the area of ​​the region used as capacitor C1. Since the area of ​​the region used as capacitor C2 is larger than the area of ​​the region used as capacitor C1, the capacitance value of capacitor C1 is larger than that of capacitor C2.

[0270] When the overlapping area of ​​conductive layer 155 and conductive layer 163 is changed to change the capacitance value of capacitor C2, the shape of opening 159 is changed, thereby changing the perimeter p of opening 159. Since the change of perimeter p directly affects the electrical characteristics of transistor 10, it is difficult to adjust the capacitance value of capacitor C2.

[0271] On the other hand, the overlapping area between the conductive layer 163 and the conductive layer 160 can be easily adjusted without affecting the electrical characteristics of the transistor 10. For example, by increasing the overlapping area between the conductive layer 163 and the conductive layer 160, the capacitance of the capacitor C1 can be increased.

[0272] like Fig.14A As shown in the cross-sectional view of FIG. 1 , a conductive layer 166 close to the semiconductor layer 161 may be provided in the insulating layer 157. In addition, the conductive layer 166 is provided in a manner not to contact the semiconductor layer 161. In addition, the conductive layer 166 is preferably provided in a manner surrounding the semiconductor layer 161. By providing the conductive layer 166 close to the semiconductor layer 161 without contacting the semiconductor layer 161, the conductive layer 166 can be used as a back gate electrode of the transistor 10. Therefore, Fig.14A The transistor 10 shown is used as a transistor including a back gate (back gate electrode). In addition, Fig. 14B yes Fig.14A An equivalent circuit diagram of transistor 10 is shown.

[0273] Here, the back gate electrode is described. Generally speaking, the back gate electrode is formed by a conductive layer and is configured in a manner that the channel forming region of the semiconductor layer is clamped by the gate electrode and the back gate electrode. Therefore, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can also be equal to that of the gate electrode, or it can be a GND potential or an arbitrary potential. By electrically connecting the gate electrode to the back gate electrode, the on-state current of the transistor can be increased. In addition, by changing the potential of the back gate electrode independently without being equal to that of the gate electrode, the threshold voltage of the transistor can be changed.

[0274] In addition, since the gate electrode and the back gate electrode are formed using a conductive layer, they have the function of preventing the electric field generated outside the transistor from affecting the channel formation region of the semiconductor layer (especially the electric field shielding function for static electricity, etc.). As a result, the unevenness of the characteristics of each transistor is reduced. In addition, the degradation of the transistor characteristics caused by the GBTS test is suppressed. For example, by including a back gate electrode, the change in the threshold voltage before and after the GBTS test can be suppressed. In addition, the change in the threshold voltage before and after the GBTS test of the transistor including the back gate electrode is also smaller than that of the transistor not including the back gate electrode.

[0275] GBTS (NBTS and PBTS) testing is a type of accelerated testing that can evaluate the characteristic changes (changes over time) of transistors caused by long-term use in a short period of time. In particular, the change in the threshold voltage of the transistor before and after the GBTS test is an important indicator for checking reliability. It can be said that the smaller the change in the threshold voltage before and after the GBTS test, the higher the reliability of the transistor.

[0276] In addition, when light is incident from the back gate electrode side, the back gate electrode is formed using a conductive film having a light-shielding property, so that light can be prevented from being incident on the semiconductor layer from the back gate electrode side. Similarly, by forming the gate electrode using a conductive film having a light-shielding property, light can be prevented from being incident on the semiconductor layer from the gate electrode side. By forming one or both of the gate electrode and the back gate electrode using a conductive film having a light-shielding property, light degradation of the semiconductor layer can be prevented, and degradation of electrical characteristics such as threshold voltage shift of the transistor can be prevented.

[0277] In addition, the gate electrode and the back gate electrode can shield the electric field generated by the drain electrode from affecting the semiconductor layer. Therefore, the change in the rising voltage of the on-state current caused by the change in the drain voltage can be suppressed. Note that this effect is significantly produced when the gate electrode and the back gate electrode are supplied with a potential.

[0278] By connecting a plurality of transistors 10 in parallel, the apparent channel width W of the transistor 10 can be increased. By increasing the channel width W, the resistance value between the source and the drain of the transistor 10 when it is in the on state becomes smaller, and the Id in the on state can be increased.

[0279] Fig.15A 10 is a plan view of the transistor 10 including the transistor 10a and the transistor 10b. Fig. 15B It is along Fig.15A A cross-sectional view of a portion taken along the dashed-dotted line A1 - A2 . Fig. 15C 1 is a perspective view of a transistor 10 including a transistor 10 a and a transistor 10 b . Fig.15D 1 is an equivalent circuit diagram of a transistor 10 including a transistor 10a and a transistor 10b. Fig.15A and Fig. 15C Part of the description of the components of the transistor 10 is omitted.

[0280] The transistor 10a and the transistor 10b have the same FIG. 11A to FIG. 11D and FIG. 12A to FIG. 12F The transistor 10a is provided in a region including the opening 159a, and the transistor 10b is provided in a region including the opening 159b. The openings 159a and 159b can be formed in the same manner as the opening 159.

[0281] A portion of the conductive layer 155 is used as one of the source electrode and the drain electrode of the transistor 10a, and another portion of the conductive layer 155 is used as one of the source electrode and the drain electrode of the transistor 10b. In addition, a portion of the conductive layer 160 is used as the other of the source electrode and the drain electrode of the transistor 10a, and another portion of the conductive layer 160 is used as the other of the source electrode and the drain electrode of the transistor 10b. In addition, a portion of the conductive layer 163 is used as the gate electrode of the transistor 10a, and another portion of the conductive layer 163 is used as the gate electrode of the transistor 10b.

[0282] In the description Fig.15D In the equivalent circuit diagram of , one of the source and drain of transistor 10a is electrically connected to one of the source and drain of transistor 10b, and the other of the source and drain of transistor 10a is electrically connected to the other of the source and drain of transistor 10b. In addition, the gate of transistor 10a is electrically connected to the gate of transistor 10b. Therefore, the on state and the off state of transistor 10a and transistor 10b are switched at the same time, and are used as one transistor 10.

[0283] By connecting a plurality of transistors 10 (here, transistor 10a and transistor 10b) in series, it is possible to increase the apparent channel length L of the transistor 10. By increasing the channel length L, the saturation characteristics of the transistor 10 can be improved.

[0284] Fig.16A 10 is a plan view of the transistor 10 including the transistor 10a and the transistor 10b. Fig. 16B It is along Fig.16A A cross-sectional view of the portion taken along the dashed line A1 - A2 in FIG. Fig. 16C 1 is a perspective view of a transistor 10 including a transistor 10 a and a transistor 10 b . Fig.16D 1 is an equivalent circuit diagram of a transistor 10 including a transistor 10a and a transistor 10b. Fig.16A and Fig. 16C Part of the description of the components of the transistor 10 is omitted.

[0285] The transistor 10 a and the transistor 10 b have a structure similar to that of the transistor 10 described with reference to FIG. 15 , but are different from the transistor 10 in that the conductive layer 155 is divided into a conductive layer 155 a and a conductive layer 155 b .

[0286] The conductive layer 155a is used as one of the source electrode and the drain electrode of the transistor 10a, and a portion of the conductive layer 160 is used as the other of the source electrode and the drain electrode of the transistor 10a. In addition, another portion of the conductive layer 160 is used as one of the source electrode and the drain electrode of the transistor 10b, and the conductive layer 155b is used as the other of the source electrode and the drain electrode of the transistor 10b. In addition, similar to the transistor 10 described using FIG. 15, a portion of the conductive layer 163 is used as the gate electrode of the transistor 10a, and another portion of the conductive layer 163 is used as the gate electrode of the transistor 10b.

[0287] In use Fig.16D In the equivalent circuit diagram of , the other of the source and drain of transistor 10a is electrically connected to one of the source and drain of transistor 10b, and the gate of transistor 10a is electrically connected to the gate of transistor 10b. Therefore, the on and off states of transistors 10a and 10b are switched at the same time, and are used as one transistor 10.

[0288] [Examples of Planar and Cross-sectional Structures of the Signal Output Circuit 110]

[0289] Next, examples of the planar and cross-sectional structures of the signal output circuit 110 will be described using the drawings. Figure 2 The planar and cross-sectional structural examples of the signal output circuit 110a shown in FIG.

[0290] Fig.17 110a is a diagram showing a planar structural example of the signal output circuit 110a. Fig.18 Yes Fig.17 An enlarged plan view of the region from transistor 10[7] to transistor 10

[11] in FIG. Fig.19A It is shown along Fig.17 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A1 - A2 in FIG. Fig.19B It is shown along Fig.17 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A2 - A3 in FIG. Fig. 20A It is shown along Fig.17 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A4 - A5 in FIG. Fig. 20B It is shown along Fig.17 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A6 - A7 in FIG. Fig.21A It is shown along Fig.18 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A8 - A9 in FIG. Fig.21B It is shown along Fig.18 FIG. 1 is a diagram showing an example of a cross-sectional structure of a portion taken along a dashed line A9 - A10 in FIG.

[0291] In this embodiment, a structure example using the above-described VFET as the transistor 10 of the signal output circuit 110a is described. The signal output circuit 110a includes an insulating layer 154 on a substrate 148, and includes a conductive layer 155 (for example, Fig.19A The conductive layer 155[1] and the conductive layer 155[3], Fig.19B 20 ). The conductive layer 155[3] and the conductive layer 155[4] of FIG. 20 , the conductive layer 155

[10] and the conductive layer 155

[11] of FIG. 20 ).

[0292] Note that the stacked structure of the signal output circuit 110a using the VFET as the transistor 10 has a common portion with the structural example of the transistor 10. Therefore, the portion different from the structural example of the transistor 10 will be mainly described here.

[0293] In this specification and the like, identification symbol [1] may be added to the symbol of the constituent element related to transistor 10[1]. For example, conductive layer 163 used as the gate electrode of transistor 10[1] may be referred to as conductive layer 163[1]. Note that identification symbol of any one of the plurality of transistors 10 may be added to the symbol of the constituent element common to a plurality of transistors 10. For example, conductive layer 163 used as the gate electrode of each of transistors 10[2], transistor 10[9], and transistor 10

[11] may be referred to as conductive layer 163[2].

[0294] For example, the opening 159 and the semiconductor layer 161 of the transistor 10[3] are sometimes referred to as the opening 159[3] and the semiconductor layer 161[3], respectively. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[4] are sometimes referred to as the opening 159[4] and the semiconductor layer 161[4], respectively. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[7] are sometimes referred to as the opening 159[7] and the semiconductor layer 161[7], respectively. For example, the opening 159 and the semiconductor layer 161 of the transistor 10[8] are sometimes referred to as the opening 159[8] and the semiconductor layer 161[8], respectively. For example, the opening 159 and the semiconductor layer 161 of the transistor 10

[10] are sometimes referred to as the opening 159

[10] and the semiconductor layer 161

[10] , respectively.

[0295] The signal output circuit 110a includes conductive layers 181[1] to 181[4] on the insulating layer 158 (see Fig.17 and Fig. 20A ). Conductive layer 181 (conductive layer 181[1] to conductive layer 181[4]) can be formed using the same material and method as conductive layer 160. Alternatively, conductive layer 181 and conductive layer 160 can be formed at the same time.

[0296] In addition, the signal output circuit 110a includes an insulating layer 187 on the insulating layer 164. The insulating layer 187 is preferably used as a planarization layer for reducing steps caused by transistors, capacitors, wiring, etc. formed in the lower layer. As a material used for the planarization layer, an organic insulating film is preferably used. In addition, after the insulating layer 187 is formed using an inorganic material or an organic material, the insulating layer 187 may be planarized using a chemical mechanical polishing (CMP) method or the like.

[0297] The signal output circuit 110a includes conductive layers 191 to 199, wirings 131 and 132 on the insulating layer 187 (see FIG. 11A ). Fig.17 , Fig.19A , Fig.19B and Fig. 20A ). Conductive layers 191 to 199, wiring 131, and wiring 132 can be formed using the same material and method as other conductive layers. Conductive layer 191 is used as terminal 111, conductive layer 192 is used as terminal 112, conductive layer 193 is used as terminal 113, conductive layer 194 is used as terminal 114, conductive layer 195 is used as terminal 115, conductive layer 196 is used as terminal 116, conductive layer 197 is used as terminal 117, and conductive layer 198 is used as terminal 118.

[0298] In addition, in the signal output circuit 110a, openings penetrating the insulating layer 162, the insulating layer 164 and the insulating layer 187 are provided on the conductive layer 160[2], the conductive layer 160[3], the conductive layer 181[1], the conductive layer 181[2], the conductive layer 181[3] and the conductive layer 181[4].

[0299] Wiring 132 and conductive layer 160 [ 2 ] are electrically connected in the opening provided in conductive layer 160 [ 2 ]. More specifically, wiring 132 and conductive layer 160 [ 2 ] are electrically connected at the bottom of the opening provided in conductive layer 160 [ 2 ].

[0300] Conductive layer 160[3] is provided with two openings. Wiring 131 and conductive layer 160[3] are electrically connected in one of the two openings. Also, conductive layer 199 and conductive layer 160[3] are electrically connected in the other of the two openings.

[0301] In addition, in the opening provided in the conductive layer 181[1], the conductive layer 191 is electrically connected to the conductive layer 181[1]. In addition, in the opening provided in the conductive layer 181[2], the conductive layer 194 is electrically connected to the conductive layer 181[2]. In addition, in the opening provided in the conductive layer 181[3], the conductive layer 198 is electrically connected to the conductive layer 181[3]. In addition, in the opening provided in the conductive layer 181[4], the conductive layer 196 is electrically connected to the conductive layer 181[4].

[0302] In the signal output circuit 110a, openings penetrating the insulating layer 164 and the insulating layer 187 are provided in the conductive layer 163[1], the conductive layer 163[3], the conductive layer 163[4], the conductive layer 163[5], and the conductive layer 163[7].

[0303] In the opening provided on the conductive layer 163[1], the conductive layer 197 is electrically connected to the conductive layer 163[1]. In addition, in the opening provided on the conductive layer 163[3], the conductive layer 193 is electrically connected to the conductive layer 163[3]. In addition, in the opening provided on the conductive layer 163[4], the conductive layer 192 is electrically connected to the conductive layer 163[4]. In addition, in the opening provided on the conductive layer 163[5], the conductive layer 195 is electrically connected to the conductive layer 163[5]. In addition, in the opening provided on the conductive layer 163[7], the conductive layer 199 is electrically connected to the conductive layer 163[7]. Note that the conductive layer 160[3] and the conductive layer 163[7] are electrically connected via the conductive layer 199.

[0304] In addition, in the signal output circuit 110a, openings penetrating the insulating layer 156, the insulating layer 157 and the insulating layer 158 are provided on the conductive layer 155[1], the conductive layer 155[2], the conductive layer 155[3], the conductive layer 155[4], the conductive layer 155[8], the conductive layer 155[9], the conductive layer 155

[10] and the conductive layer 155

[11] .

[0305] In the opening provided in the conductive layer 155[1], the conductive layer 160[3] is electrically connected to the conductive layer 155[1]. In addition, in the opening provided in the conductive layer 155[2], the conductive layer 160[1] is electrically connected to the conductive layer 155[2]. In addition, in the opening provided in the conductive layer 155[3], the conductive layer 160[4] is electrically connected to the conductive layer 155[3].

[0306] In addition, in the opening provided in the conductive layer 155[8], the conductive layer 181[1] is electrically connected to the conductive layer 155[8]. In addition, in the opening provided in the conductive layer 155

[10] , the conductive layer 181[3] is electrically connected to the conductive layer 155

[10] .

[0307] The conductive layer 155[9] is provided with two openings. The conductive layer 160[8] and the conductive layer 155[9] are electrically connected in one of the two openings. In addition, the conductive layer 181[2] and the conductive layer 155[9] are electrically connected in the other of the two openings.

[0308] The conductive layer 155

[11] is provided with two openings. The conductive layer 160

[10] is electrically connected to the conductive layer 155

[11] in one of the two openings. In addition, the conductive layer 181[4] is electrically connected to the conductive layer 155

[11] in the other of the two openings.

[0309] In the signal output circuit 110 a , openings penetrating the insulating layer 156 , the insulating layer 157 , and the insulating layer 158 are provided in the conductive layer 155 [ 4 ] and the conductive layer 155 [ 7 ] .

[0310] In the opening provided on the conductive layer 155[4], the conductive layer 163[2] and the conductive layer 155[4] are electrically connected (see Fig. 20B ). In the opening provided on the conductive layer 155[7], the conductive layer 163[8] and the conductive layer 155[7] are electrically connected (refer to Fig.21A and Fig.21B ).

[0311] Note that the conductive layer 155[4] is also used as the conductive layer 155[5] and the conductive layer 155[6]. In addition, the conductive layer 160[1] is also used as the conductive layer 160[7]. In addition, the conductive layer 160[2] is also used as the conductive layer 160[6], the conductive layer 160[9], and the conductive layer 160

[11] . In addition, the conductive layer 160[3] is also used as the conductive layer 160[5]. In addition, the conductive layer 163[1] is also used as the conductive layer 163[6]. In addition, the conductive layer 163[2] is also used as the conductive layer 163[9] and the conductive layer 163

[11] . In addition, the conductive layer 163[8] is also used as the conductive layer 163

[10] .

[0312] The area where the conductive layer 155[4] and the conductive layer 160[6] overlap with each other via the insulating layer 156, the insulating layer 157, and the insulating layer 158 is used as the capacitor 20[1].

[0313] Furthermore, by electrically connecting the conductive layer 160[8] and the conductive layer 155[9], the capacitor C1 of the transistor 10[8] can be used as the capacitor 20[2]. By using the capacitor C1 of the transistor 10[8] as the capacitor 20[2], it is not necessary to separately provide the capacitor 20[2], thereby realizing a semiconductor device with a small footprint (see Fig.17 ). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10[8].

[0314] Furthermore, by electrically connecting the conductive layer 160

[10] and the conductive layer 155

[11] , the capacitor C1 of the transistor 10

[10] can be used as the capacitor 20[3]. By using the capacitor C1 of the transistor 10

[10] as the capacitor 20[3], it is not necessary to separately provide the capacitor 20[3], thereby realizing a semiconductor device with a small footprint (see Fig.17 and Fig. 20A ). Therefore, it is preferable to use a VFET according to one embodiment of the present invention as the transistor 10

[10] .

[0315] Fig. 22 A circuit diagram of the signal output circuit 110 a is shown when the capacitor C1 of the transistor 10 [ 8 ] is used as the capacitor 20 [ 2 ] and the capacitor C1 of the transistor 10 [ 10 ] is used as the capacitor 20 [ 3 ].

[0316] The transistor 10

[10] and transistors other than the transistor 10

[10] may also be formed of transistors other than VFETs. Note that in order to realize a semiconductor device with a reduced footprint, it is preferred that more transistors according to one embodiment of the present invention be used in the signal output circuit 110a. Therefore, it is preferred that all transistors included in the signal output circuit 110a use transistors according to one embodiment of the present invention.

[0317] 〔Example of signal output circuit operation〕

[0318] Next, an operation example of the signal output circuit 110 will be described using the drawings. Figure 2 An operation example of the signal output circuit 110a shown will be described.

[0319] Fig.23 It is a timing chart for explaining an example of the operation of the signal output circuit 110a[i]. Figures 24 to 30 It is a circuit diagram for explaining an operation example of the signal output circuit 110a[i].

[0320] In the drawings, in order to indicate the potential of a wiring or the like, "H" indicating a potential H or "L" indicating a potential L is sometimes added to a position adjacent to the wiring or the like. Also, "H" or "L" is sometimes added to a wiring or the like whose potential changes in some cases in a frame. Also, when a transistor is in an off state, a symbol "×" is sometimes added to overlap the transistor.

[0321] The potential H (VDD) is supplied to the wiring 131, and the potential L (VSS) is supplied to the wiring 132. The signal CLK_1 is supplied to the terminal 111, the signal CLK_2 is supplied to the terminal 112, the signal CLK_3 is supplied to the terminal 113, and the signal PWC_1 is supplied to the terminal 118.

[0322] As the state before period T1, signal CLK_1 is at potential L, signal CLK_2 is at potential H, signal CLK_3 is at potential H, signal PWC_1 is at potential L, and signal LIN is at potential L. In addition, transistor 10[2], transistor 10[3], transistor 10[4], transistor 10[9], and transistor 10

[11] are in the on state. In addition, transistor 10[1], transistor 10[5], transistor 10[6], transistor 10[7], transistor 10[8], and transistor 10

[10] are in the off state.

[0323] In addition, the signal CLK_4 and the signals PWC_2 to PWC_4 are at a potential L. Note that the signal CLK_4 and the signals PWC_2 to PWC_4 are not related to the operation of the signal output circuit 110 a [i] described here, and therefore are not used in the description of the operation of the signal output circuit 110 a [i].

[0324] During the period T1, the signal CLK_2 becomes the potential L, and the signal LIN becomes the potential H (refer to Fig.23 and Fig.24 ). As a result, transistors 10[1] and 10[6] are turned on. At this time, the potential of node ND[1] becomes potential L and transistors 10[2], 10[9] and 10

[11] are turned off.

[0325] In addition, the potentials of the nodes ND[2] and ND[3] become a potential lower than the potential H by the Vth of the transistor 10[1] (potential H-Vth). Here, the value of the potential H-Vth is greater than the Vth of the transistor. Therefore, the transistors 10[8] and 10

[10] become turned on. The terminal 116 outputs the potential L as the signal OUT, and the terminal 114 outputs the potential L as the signal SROUT.

[0326] During period T2, signal CLK_1 becomes potential H, signal CLK_3 becomes potential L, and signal PWC_1 becomes potential H. As a result, transistor 10[3] becomes off. In addition, at time T2a (refer to Fig.23 and Fig.25 ), the potential of node ND[3] is the potential H-Vth, so the potential of terminal 114 becomes the potential H-Vth-Vth, and the potential of terminal 116 becomes the potential H-Vth-Vth.

[0327] On the other hand, terminal 114 and node ND[3] are connected via capacitor 20[2] (capacitive coupling). In addition, terminal 116 and node ND[3] are connected via capacitor 20[3]. Capacitor 20[2] and capacitor 20[3] are used as bootstrap capacitors. Therefore, as the potentials of terminal 114 and terminal 116 rise, the potential of node ND[3] rises.

[0328] At this time, the potential of the node ND[2] also rises, but at the moment when the potential of the node ND[2] exceeds the potential H-Vth, the transistor 10[1] and the transistor 10[7] become off and the node ND[2] and the node ND[3] are in a floating state. In addition, the potential of the node ND[3] rises to the potential H-Vth + potential H (2×potential H-Vth) (time T2b. Refer to Fig.23 and Fig.26 ). This potential is higher than the potential H+Vth, so the potentials of the terminal 114 and the terminal 116 can be changed to the potential H.

[0329] Here, when the signal output circuit 110a does not include the transistor 10[7], a voltage of 2× the potential H-Vth-Vss is applied to the drain of the transistor 10[2]. Since Vss is applied to the source of the transistor 10[2], an excessively high voltage (2× the potential H-Vth-Vss) is applied between the source and drain of the transistor 10[2]. As a result, the transistor 10[2] is prone to characteristic degradation or damage.

[0330] When transistor 10[7] is included between the drain of transistor 10[2] and node ND[3], even if the potential of node ND[3] becomes 2×potential H-Vth, the potential of node ND[2] (drain of transistor 10[2]) does not rise, thereby preventing transistor 10[2] from experiencing characteristic degradation and damage.

[0331] During period T3, the signal CLK_2 becomes a potential H, the signal PWC_1 becomes a potential L, and the signal LIN becomes a potential L (see Fig.23 and Fig. 27 ). As a result, the transistor 10[4] becomes on. In addition, the potential of the terminal 116 becomes the potential L. In addition, the transistor 10[6] becomes off and the node ND[1] and the node ND[2] are in a floating state.

[0332] During the period T4, the signal CLK_1 changes to a potential L, the signal CLK_3 changes to a potential H, and the signal RIN changes to a potential H (see Fig.23 and Fig.28). As a result, transistors 10[3] and 10[5] are turned on, and the potential of node ND[1] becomes potential H. When the potential of node ND[1] becomes potential H, transistors 10[2], 10[9], and 10

[11] are turned on.

[0333] When transistor 10[2] is turned on, the potential of node ND[2] becomes potential L. As a result, transistor 10[7] is turned on, and the potential of node ND[3] also becomes potential L. Therefore, transistor 10[8] and transistor 10

[10] are turned off. In addition, since transistor 10[9] and transistor 10

[11] are turned on, potential L is supplied to terminal 114, and the potential of terminal 116 (potential L) is maintained.

[0334] like Fig.18 , Fig.21A and Fig.21B As shown, in a signal output circuit 110a according to one embodiment of the present invention, a conductive layer 163[8] and a conductive layer 155[7] are electrically connected. The conductive layer 163[8] is used as a gate electrode of the transistor 10[8] and the transistor 10

[10] . The conductive layer 155[7] is used as a drain electrode (or source electrode) of the transistor 10[7]. In addition, the conductive layer 155[7] is used as a node ND[3]. The conductive layer 160[1] is used as a source electrode (or drain electrode) of the transistor 10[7]. In addition, the conductive layer 160[1] is used as a node ND[2].

[0335] As described in later embodiments, by using the conductive layer 155 [ 7 ] as a drain (drain electrode), the on-state current of the transistor 10 [ 7 ] can be increased compared to the case where the conductive layer 155 [ 7 ] is used as a source (source electrode).

[0336] When one or both of capacitor 20[2] and capacitor 20[3] are connected to node ND[3], the charging time and discharging time required to change the potential of node ND[3] become longer. The larger the on-state current of transistor 10[7], the shorter the charging time and discharging time required to change the potential of node ND[3].

[0337] By electrically connecting the conductive layer 163[8] and the conductive layer 155[7], the conductive layer 155[7] is used as a drain and the conductive layer 160[1] is used as a source during the period T3. Therefore, when the transistor 10[7] is turned on during the period T4, the potential of the node ND[3] can be quickly changed to the potential L. Therefore, the operating speed of the signal output circuit 110a can be increased. In addition, the operating speed of the semiconductor device using the signal output circuit 110a can be increased.

[0338] In addition, after the period T4, if the potential of the node ND[3] does not change to the potential L indefinitely, a through current may flow between the terminal 118 and the wiring 132. Similarly, a through current may flow between the terminal 111 and the wiring 132. By electrically connecting the conductive layer 163[8] and the conductive layer 155[7], the potential of the node ND[3] can be reliably changed to the potential L during the period T4. Therefore, the power consumption of the signal output circuit 110a can be reduced. In addition, the power consumption of the semiconductor device using the signal output circuit 110a can be reduced.

[0339] In addition, by electrically connecting the conductive layer 163[8] and the conductive layer 160[1] (conductive layer 160[7]), the conductive layer 155[7] is used as a source and the conductive layer 160[1] is used as a drain in the period before the period T1. Therefore, the time required for the potential change of the node ND[3] in the period T1 can be shortened. That is, the potential of the node ND[3] can be quickly changed to the potential H-Vth. Therefore, the operating speed of the signal output circuit 110a can be increased. In addition, the operating speed of the semiconductor device using the signal output circuit 110a can be increased.

[0340] On the other hand, when the conductive layer 155[7] is used as the source of the transistor 10[7] and the conductive layer 160[1] is used as the drain of the transistor 10[7], it is not easy to obtain the power consumption reduction effect. Therefore, it is preferable that the conductive layer 155[7] is used as the drain of the transistor 10[7] and the conductive layer 160[1] is used as the source of the transistor 10[7]. It is preferable that the conductive layer 163[8] and the conductive layer 155[7] are electrically connected.

[0341] During period T5, the signal CLK_2 changes to a potential L (see Fig.23 and Fig.29 ). As a result, transistor 10[4] becomes off.

[0342] During period T6, the signal CLK_3 and the signal RIN become at a potential L (see Fig.23 and Fig.30 ). As a result, transistor 10[3] and transistor 10[5] are turned off. Since transistor 10[5] is turned off, node ND[1] is in a floating state.

[0343] Thereafter, until the terminal 117 is supplied with the potential H as the signal LIN, the terminal 114 and the terminal 116 are supplied with the potential L. That is, until the terminal 117 is supplied with the potential H as the signal LIN, the potential L is output as the signal OUT and the signal SROUT.

[0344] In this way, the signal output circuit [i] can output pulse signals from the terminal 114 and the terminal 116 in synchronization with a specific signal combination. Note that the pulse width (time when the potential H is output) of the signal SROUT, which is the pulse signal output from the terminal 114, is linked to the signal CLK. In addition, the pulse width (time when the potential H is output) of the signal OUT, which is the pulse signal output from the terminal 116, is linked to the signal PWC.

[0345] When the signal output circuit [i] according to one embodiment of the present invention includes a capacitor used as a bootstrap capacitor, the power supply potential (potential H) can be reliably output from the terminal 114 and the terminal 116. Therefore, in the signal output circuit [i] according to one embodiment of the present invention, the output impedance is small, and the potential H can be reliably supplied to a load such as a circuit connected to the terminal 114 or the terminal 116. Therefore, the operation of the semiconductor device including the signal output circuit [i] according to one embodiment of the present invention becomes stable, and the reliability of the semiconductor device can be improved.

[0346] The capacitor C1 of the transistor 10[1] is preferably formed between the node ND[1] and the gate of the transistor 10[1]. In addition, the capacitor C2 of the transistor 10[1] is preferably formed between the wiring 131 to which the power supply potential is supplied and the gate of the transistor 10[1] (see Fig.31 ).

[0347] In addition, the node ND[1] is in a floating state during the period other than the period when the signal CLK_2 and the signal CLK_3 are both at the potential H. In order to suppress the potential variation of the node ND[1] during this period and make the signal output circuit [i] according to one embodiment of the present invention operate more stably, preferably, in each of the transistors 10[2], 10[6], 10[9] and 10

[11] , the capacitor C1 is formed between the wiring 132 supplied with the power supply potential and the gate. Specifically, the conductive layer 160[2] is preferably electrically connected to the wiring 132 (see Fig.17 ). The conductive layer 160[2] is used as a source electrode of each of the transistors 10[2], 10[6], 10[9] and 10

[11] .

[0348] By forming capacitor C1 between wiring 132 and the gate in each of transistors 10[2], 10[9], and 10

[11] , each capacitor C1 can be connected in parallel with capacitor 20[1]. This can improve the effect of suppressing the potential variation of node ND[1] (see Fig.31 ).

[0349] Furthermore, by forming the capacitor C2 of the transistor 10[6] between the node ND[1] and the gate of the transistor 10[6], the effect of the potential change of the signal input to the gate of the transistor 10[6] on the node ND[1] can be reduced compared to the case where the capacitor C1 is formed between the node ND[1] and the gate of the transistor 10[6].

[0350] In order to suppress the potential variation of the node ND[1] and make the signal output circuit [i] according to one embodiment of the present invention operate more stably, it is preferred that the capacitor C2 is formed between the node ND[1] and the gate in each of the transistors 10[4] and 10[5]. In addition, it is preferred that the capacitor C1 of the transistor 10[5] is formed between the wiring 131 supplied with the power supply potential and the gate. Specifically, the conductive layer 160[3] is preferably electrically connected to the wiring 131 (see Fig.17 ). The conductive layer 160[3] is used as a drain electrode of the transistor 10[5].

[0351] In addition, the capacitor C1 of the transistor 10[4] is preferably formed between the drain and the gate of the transistor 10[4]. In addition, the capacitor C1 of the transistor 10[3] is preferably formed between the wiring 131 and the gate of the transistor 10[3]. Specifically, the conductive layer 160[3] is preferably electrically connected to the wiring 131 (see Fig.17 ). The conductive layer 160[3] is used as a drain electrode of the transistor 10[3]. In addition, the capacitor C2 of the transistor 10[3] is preferably formed between the source and the gate of the transistor 10[3].

[0352] In addition, in order to make the signal output circuit [i] according to one embodiment of the present invention operate more stably, the capacitance value of the parasitic capacitance generated between the node ND [3] and the gate of the transistor 10 [7] is preferably smaller than the capacitance values ​​of the capacitor 20 [2] and the capacitor 20 [3]. Therefore, it is preferred that in the transistor 10 [7], the capacitor C1 is formed between one of the source and the drain of the transistor 10 [7] and the gate, and the capacitor C2 is formed between the other of the source and the drain of the transistor 10 [7] and the gate (see Fig.31 ).

[0353] in addition, Fig.10 The signal output circuit 110f shown includes a transistor 10

[13] and a transistor 10

[14] . The capacitor C1 of the transistor 10

[13] is preferably formed between the wiring 135 and the gate of the transistor 10

[13] (see Fig.32 ). That is, it is preferably formed between the drain and gate of the transistor 10

[13] . Therefore, the capacitor C2 of the transistor 10

[13] is preferably formed between the source and gate of the transistor 10

[13] .

[0354] The potential SMP supplied to the wiring 135 is set to a fixed potential, so that the gate of the transistor 10

[13] is electrically connected to the node ND[2]. Since the capacitor C1 is formed between the wiring 135 and the gate of the transistor 10

[13] , the effect of suppressing the potential variation of the node ND[2] when the node ND[2] is in a floating state can be improved.

[0355] In addition, the capacitor C1 of the transistor 10

[14] is preferably formed between the wiring 136 and the gate of the transistor 10

[14] . That is, it is preferably formed between the drain and the gate of the transistor 10

[14] (see Fig.32 ). Therefore, the capacitor C2 of the transistor 10

[14] is preferably formed between the source and the gate of the transistor 10

[14] .

[0356] The potential SMP supplied to the wiring 136 is set to a fixed potential, so that the gate of the transistor 10

[14] is electrically connected to the node ND[1]. Since the capacitor C1 is formed between the wiring 136 and the gate of the transistor 10

[14] , the effect of suppressing the potential variation of the node ND[1] when the node ND[1] is in a floating state can be improved.

[0357] <Operation Example of Shift Register 100>

[0358] Next, refer to Fig.33 illustrate Figure 1A An example of the operation of the shift register 100 is shown. Fig.33 1 is a timing chart for explaining an example of the operation of the shift register 100 . Fig.33 The diagram shows the potential changes of clock signal signals CLK_1 to CLK_4, signals PWC_1 to PWC_4 that determine the pulse width of signal OUT, signal LIN[1] input to signal output circuit 110[1], signals OUT[1] to OUT[4] output from signal output circuit 110[1] to signal output circuit 110[4], signal OUT[n] output from signal output circuit 110[n], signal OUT[n+1] output from signal output circuit 110[n+1], and signal OUT[n+2] output from signal output circuit 110[n+2].

[0359] First, during period T51 , the signal output circuit 110 [ 1 ] is supplied with the signal LIN[ 1 ] of potential H. During period T52 , the signal output circuit 110 [ 1 ] outputs the signal OUT[ 1 ] of potential H in synchronization with the signal LIN[ 1 ], the signal CLK_1 , the signal CLK_4 , and the signal PWC_1 .

[0360] Next, during period T53, the potential L is output as the signal OUT[1]. In addition, the potential H is output as the signal OUT[2] in synchronization with the signals CLK_1, CLK_2, and PWC_2.

[0361] Next, during period T54, the potential L is output as the signal OUT[2]. In addition, the potential H is output as the signal OUT[3] in synchronization with the signals CLK_3, CLK_4, and PWC_3.

[0362] Next, during period T55, potential L is output as signal OUT[3]. In addition, potential H is output as signal OUT[4] in synchronization with signals CLK_3, CLK_4, and PWC_4. In this way, potential H is sequentially output as signal OUT from the 1st stage to the n+2nd stage.

[0363] Then, when the signal output circuit 110[1] is supplied with the potential H as the signal LIN[1] again, the shift register 100 can repeat the above operation. The period from when the potential H is input as the signal LIN[1] to when the potential H is input as the signal LIN[1] again to the signal output circuit 110[1] is sometimes referred to as the frame period 176. In addition, the signal LIN input to the signal output circuit 110[1] is sometimes referred to as the "start pulse SP".

[0364] As a transistor used in a semiconductor device such as a signal output circuit according to one embodiment of the present invention, a transistor having a structure other than VFET such as a planar transistor or a staggered transistor may be used. Alternatively, a VFET and a transistor having a structure other than VFET may be used in combination.

[0365] Note that the signal output circuit 110 used in the shift register 100 is not limited to the configuration disclosed in this specification, etc. The signal output circuit 110 used in the shift register 100 can adopt various circuit configurations.

[0366] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0367] (Implementation Method 2)

[0368] In this embodiment, a metal oxide (hereinafter referred to as an oxide semiconductor) which can be used for the OS transistor described in the above embodiment will be described.

[0369] The metal oxide used for the OS transistor preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, antimony and tin, and more preferably gallium.

[0370] The metal oxide can be formed by a sputtering method, a CVD method such as a metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition) method, or an ALD method.

[0371] The ALD method can deposit atoms layer by layer, so it has the effects of being able to deposit extremely thin layers, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with excellent coverage, and being able to deposit at low temperatures. In addition, the ALD method also includes a thermal ALD (thermal ALD) method that uses a thermal deposition method and a plasma ALD (PEALD: Plasma Enhanced ALD) method that uses a plasma deposition method. By using plasma, deposition can be performed at a lower temperature, so it is sometimes preferred. The precursors used in the ALD method sometimes contain elements such as carbon or chlorine. Therefore, the film formed by the ALD method sometimes contains more elements such as carbon or chlorine than the film formed by other deposition methods. In addition, the quantification of the above elements can be performed using XPS or secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry).

[0372] Unlike a deposition method in which particles released from a target material or the like are deposited, the ALD method is a deposition method in which a film is formed by a reaction on the surface of the object to be processed. Therefore, the ALD method is a deposition method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has good step coverage and thickness uniformity, so it is suitable for use in cases where the surface of an opening with a high aspect ratio is to be covered.

[0373] Hereinafter, an oxide containing indium (In), gallium (Ga), and zinc (Zn) will be described as an example of a metal oxide. Note that an oxide containing indium (In), gallium (Ga), and zinc (Zn) may be referred to as an In-Ga-Zn oxide.

[0374] <Classification of Crystal Structure>

[0375] Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystalline.

[0376] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. For example, an XRD spectrum measured by GIXD (Grazing-Incidence XRD) can be used for evaluation. In addition, the GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement is sometimes simply referred to as an XRD spectrum.

[0377] For example, the peak shape of the XRD spectrum of a quartz glass substrate is roughly bilaterally symmetrical. On the other hand, the peak shape of the XRD spectrum of an In-Ga-Zn oxide film having a crystalline structure is not bilaterally symmetrical. The fact that the peak shape of the XRD spectrum is not bilaterally symmetrical indicates that there is crystal in the film or substrate. In other words, unless the peak shape of the XRD spectrum is bilaterally symmetrical, it cannot be said that the film or substrate is in an amorphous state.

[0378] In addition, the crystal structure of the film or substrate can be evaluated using a diffraction pattern observed by a nanobeam electron diffraction method (NBED: Nano Beam Electron Diffraction) (also called a nanobeam electron diffraction pattern). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, and it can be confirmed that the quartz glass is in an amorphous state. In addition, a spot-like pattern is observed in the diffraction pattern of an In-Ga-Zn oxide film deposited at room temperature, but no halo is observed. Therefore, it can be inferred that the In-Ga-Zn oxide deposited at room temperature is in an intermediate state that is neither single crystal or polycrystalline nor amorphous, and it is difficult to conclude that the In-Ga-Zn oxide film is amorphous.

[0379] 〔Structure of oxide semiconductor〕

[0380] In addition, when the structure of the oxide semiconductor is focused, the classification of the oxide semiconductor is sometimes different from the above classification. For example, oxide semiconductors can be classified into single crystal oxide semiconductors and non-single crystal oxide semiconductors other than single crystal oxide semiconductors. As non-single crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductors) and amorphous oxide semiconductors.

[0381] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0382] [CAAC-OS]

[0383] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axis of the plurality of crystalline regions is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0384] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystals with a maximum diameter less than 10nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, sometimes the maximum diameter of the crystallization region is about tens of nm.

[0385] In addition, in In-Ga-Zn oxide, CAAC-OS has a tendency to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing gallium (Ga), zinc (Zn) and oxygen (hereinafter, (Ga, Zn) layer) are stacked. In addition, indium and gallium can replace each other. Therefore, sometimes the (Ga, Zn) layer contains indium. In addition, sometimes the In layer contains gallium. Note that sometimes the In layer contains zinc. This layered structure is observed as a lattice image in a high-resolution TEM (Transmission Electron Microscope) image, for example.

[0386] For example, when the CAAC-OS film is structurally analyzed using an XRD device, a peak indicating c-axis orientation is detected at or near 2θ = 31° in Out-of-plane XRD measurement using θ / 2θ scanning. Note that the position (2θ value) of the peak indicating c-axis orientation sometimes varies depending on the type or composition of the metal elements constituting the CAAC-OS.

[0387] In addition, for example, multiple bright spots (spots) are observed in the electron diffraction pattern of the CAAC-OS film. In addition, when the spot of the incident electron beam passing through the sample (also called the direct spot) is used as the symmetry center, a certain spot and other spots are observed at point-symmetrical positions.

[0388] When observing the crystallized region from the above-mentioned specific direction, although the lattice arrangement in the crystallized region is basically a hexagonal lattice, the unit lattice is not limited to a regular hexagon, and there are cases where it is a non-regular hexagon. In addition, in the above-mentioned distortion, sometimes there is a pentagonal, heptagonal, and other lattice arrangement. In addition, no clear grain boundary is observed near the distortion of CAAC-OS. In other words, the distortion of the lattice arrangement inhibits the formation of grain boundaries. This may be because CAAC-OS can accommodate distortion due to the low density of the arrangement of oxygen atoms in the ab plane direction or the change in the bonding distance between atoms due to the substitution of metal atoms.

[0389] In addition, a crystalline structure in which clear grain boundaries are confirmed is called a so-called polycrystalline. The grain boundaries become recombination centers and carriers are captured, which may lead to a decrease in the on-state current of the transistor and a decrease in the field effect mobility. Therefore, CAAC-OS, in which no clear grain boundaries are confirmed, is one of the crystalline oxides that provide the semiconductor layer of the transistor with an excellent crystalline structure. Note that in order to form CAAC-OS, a structure containing Zn is preferably used. For example, compared with In oxide, In-Zn oxide and In-Ga-Zn oxide can further suppress the occurrence of grain boundaries, so they are preferred.

[0390] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of an oxide semiconductor is sometimes reduced due to the mixing of impurities and / or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called thermal budget) in the manufacturing process. Therefore, by using CAAC-OS in OS transistors, the degree of freedom of the manufacturing process can be expanded.

[0391] [nc-OS]

[0392] In nc-OS, the atomic arrangement in a tiny region (for example, a region of 1 nm or more and 10 nm or less, especially a region of 1 nm or more and 3 nm or less) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is 1 nm or more and 10 nm or less, especially 1 nm or more and 3 nm or less, and the tiny crystal is called a nanocrystal. In addition, no regularity of crystal orientation is observed between different nanocrystals in nc-OS. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS and amorphous oxide semiconductors in certain analysis methods. For example, when an XRD device is used to perform structural analysis on an nc-OS film, no peak indicating crystallinity is detected in the Out-of-plane XRD measurement using θ / 2θ scanning. In addition, when an electron diffraction (also called selected area electron diffraction) is performed on the nc-OS film using an electron beam whose beam diameter is larger than that of a nanocrystal (for example, 50 nm or more), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction using an electron beam whose beam diameter is close to or smaller than the size of the nanocrystal (for example, greater than 1 nm and less than 30 nm) (also called nanobeam electron diffraction), an electron diffraction pattern is sometimes obtained in which multiple spots are observed in a ring-shaped area centered on the direct spot.

[0393] [a-like OS]

[0394] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0395] [Composition of oxide semiconductor]

[0396] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0397] [CAC-OS]

[0398] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0399] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is divided into a first region and a second region to form a mosaic shape and the first region is distributed in the film (hereinafter also referred to as a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0400] Here, each of the atomic ratios of In, Ga, and Zn relative to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is recorded as [In], [Ga], and [Zn]. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is greater than [In] in the composition of the CAC-OS film. In addition, the second region is a region where [Ga] is greater than [Ga] in the composition of the CAC-OS film. In addition, for example, the first region is a region where [In] is greater than [In] in the second region and [Ga] is less than [Ga] in the second region. In addition, the second region is a region where [Ga] is greater than [Ga] in the first region and [In] is less than [In] in the first region.

[0401] Specifically, the first region is a region with indium oxide or indium zinc oxide as a main component. In addition, the second region is a region with gallium oxide or gallium zinc oxide as a main component. In other words, the first region can be referred to as a region with In as a main component. In addition, the second region can be referred to as a region with Ga as a main component.

[0402] Note that a clear boundary between the first region and the second region may not be observed.

[0403] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a part of the main component of Ga and a part of the main component of In exist irregularly in a mosaic shape in a material structure containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0404] CAC-OS can be formed, for example, by sputtering without intentionally heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is made greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0405] For example, in CAC-OS in In-Ga-Zn oxide, based on the EDX surface analysis (mapping) image obtained by energy dispersive X-ray spectroscopy (EDX), it can be confirmed that the structure has a region with In as the main component (first region) and a region with Ga as the main component (second region) that are unevenly distributed and mixed.

[0406] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, the conductivity as a metal oxide is exhibited. Therefore, when the first region is distributed in the metal oxide in a cloud-like manner, a high field effect mobility (μ) can be achieved.

[0407] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0408] Therefore, when CAC-OS is used for a transistor, the complementary effect of the conductivity caused by the first region and the insulation caused by the second region can make CAC-OS have a switching function (a function of controlling on / off). In other words, a part of the material of CAC-OS has a conductive function and another part has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on ), high field effect mobility (μ) and good switching performance.

[0409] In addition, transistors using CAC-OS have high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

[0410] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0411] <Transistor Having Oxide Semiconductor>

[0412] Next, a case where the above-mentioned oxide semiconductor is used in a transistor is described.

[0413] By using the above oxide semiconductor for a transistor, a transistor having high field effect mobility can be realized. In addition, a transistor having high reliability can be realized.

[0414] In particular, as a semiconductor layer forming a channel, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also recorded as IGZO) is preferably used. Alternatively, as a semiconductor layer, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also recorded as IAZO) may be used. Alternatively, as a semiconductor layer, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also recorded as IAGZO) may be used.

[0415] It is preferable to use an oxide semiconductor with a low carrier concentration for a transistor. For example, the carrier concentration in an oxide semiconductor is 1×10 17 cm -3 Below, preferably 1×10 15 cm -3 Below, more preferably 1×10 13 cm -3 Below, more preferably 1×10 11 cm -3Below, more preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 When the carrier concentration in the oxide semiconductor film is reduced, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0416] Since a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a lower defect state density, it is possible to have a lower trap state density.

[0417] Charges trapped in trap states of an oxide semiconductor take a long time to disappear, and may behave like fixed charges. Therefore, the electrical characteristics of a transistor having a channel formation region formed in an oxide semiconductor with a high trap state density may be unstable.

[0418] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0419] <Impurities>

[0420] Here, the influence of each impurity in the oxide semiconductor is described.

[0421] When the oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect states are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm3 In addition, the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS was set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 3×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, preferably 3×10 18 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0422] When an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form a carrier. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal tends to have a normally-on characteristic. Therefore, the concentration of the alkali metal or alkaline earth metal in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0423] When an oxide semiconductor contains nitrogen, electrons as carriers are easily generated, which increases the carrier concentration and turns into n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have a normally-on characteristic. Alternatively, when an oxide semiconductor contains nitrogen, a trap state is sometimes formed. As a result, the electrical characteristics of the transistor are sometimes unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0424] Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to generate water, so oxygen vacancies are sometimes formed. When hydrogen enters the oxygen vacancy, electrons as carriers are sometimes generated. In addition, electrons as carriers are sometimes generated because part of the hydrogen is bonded to oxygen bonded to metal atoms. Therefore, transistors using oxide semiconductors containing hydrogen tend to have normally-on characteristics. Therefore, it is preferred to reduce the hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor measured by SIMS is set to 1×10 20 atoms / cm 3 Below, preferably 5×10 19 atoms / cm 3 Below, more preferably 1×10 19 atoms / cm 3 Below, more preferably 5×10 18 atoms / cm 3 Below, preferably 1×10 18 atoms / cm 3 Below, more preferably 5×10 17 atoms / cm 3 the following.

[0425] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0426] <Microwave treatment>

[0427] After forming the oxide semiconductor, microwave treatment is performed in an oxygen-containing atmosphere to reduce the impurity concentration of the oxide semiconductor. Microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma using microwaves.

[0428] By performing microwave treatment in an oxygen-containing atmosphere, the oxygen gas can be plasmatized using microwaves or high frequencies such as RF to allow the oxygen plasma to act. In addition, as oxygen acting on the oxide semiconductor, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen free radicals (also known as atoms, molecules, or ions with unpaired electrons, also known as O free radicals). In addition, the oxygen acting on the oxide semiconductor can be any one or more of the above forms, and oxygen free radicals are particularly preferred.

[0429] In addition, heating the substrate during the microwave treatment in the oxygen-containing atmosphere is preferred because the impurity concentration in the oxide semiconductor can be further reduced. The substrate can be heated at a temperature of 100° C. to 650° C., preferably 200° C. to 600° C., and more preferably 300° C. to 450° C.

[0430] By heating the substrate during the microwave treatment in the oxygen-containing atmosphere as described above, the carbon concentration in the oxide semiconductor measured by SIMS can be set to 1×10 20 atoms / cm 3 Below, preferably 1×10 19 atoms / cm 3 Below, more preferably 1×10 18 atoms / cm 3 the following.

[0431] Note that the above shows a structural example of microwave treatment of an oxide semiconductor in an oxygen-containing atmosphere, but is not limited to this. For example, microwave treatment may also be performed on an insulating layer located near the oxide semiconductor, specifically, a silicon oxide layer, in an oxygen-containing atmosphere. By performing microwave treatment on the silicon oxide layer in an oxygen-containing atmosphere, hydrogen contained in the silicon oxide layer can be released to the outside as H2O. By releasing hydrogen from the oxide layer located near the oxide semiconductor, the reliability of a transistor using an oxide semiconductor as a semiconductor layer can be improved. Therefore, a semiconductor device with high reliability can be provided.

[0432] In addition, crystallization of an oxide semiconductor may be promoted by microwave treatment. That is, by subjecting an oxide semiconductor or an insulating layer located near the oxide semiconductor to microwave treatment, the crystallinity of the oxide semiconductor can be improved.

[0433] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0434] (Implementation 3)

[0435] In this embodiment, a configuration example of a display device 200 in which the transistor 10 , the shift register 100 , the signal output circuit 110 , and the like according to one embodiment of the present invention can be used is described.

[0436] Fig.34A FIG. 2 shows a perspective view of a display device 200. The display device 200 has a structure in which a substrate 152 and a substrate 148 are bonded together. Fig.34A In FIG. 1 , the substrate 152 is indicated by a dotted line.

[0437] The display device 200 includes a display portion 235 , a connection portion 140 , a first driving circuit portion 231 , a second driving circuit portion 232 , wiring 165 , and the like. Fig.34A FIG. 2 shows an example in which IC 178 and FPC 179 are mounted in the display device 200. Fig.34A The structure shown is called a display module including a display device 200, an IC (integrated circuit), and an FPC.

[0438] The connection portion 140 is disposed outside the display portion 235. The connection portion 140 may be disposed along one side or multiple sides of the display portion 235. The number of the connection portions 140 may also be one or more. Fig.34A An example is shown in which the connection portion 140 is provided so as to surround four sides of the display portion. In the connection portion 140, the common electrode of the light emitting device is electrically connected to the conductive layer, and power can be supplied to the common electrode.

[0439] The wiring 165 has a function of supplying signals and power to the display portion 235, the first driver circuit portion 231, and the second driver circuit portion 232. The signals and power are input to the wiring 165 from the outside through the FPC 179 or from the IC 178.

[0440] Fig.34A An example of providing IC 178 on substrate 148 by COG (Chip On Glass) method or COF (Chip On Film) method is shown. IC 178 may include, for example, a scanning line driving circuit or a signal line driving circuit. Note that the display device 200 and the display module do not necessarily have to be provided with IC. Alternatively, the IC may be mounted on FPC by COF method or the like.

[0441] The display unit 235 includes a plurality of pixels 230 arranged in a matrix of m rows (m is an integer greater than 1) and n columns (n ​​is an integer greater than 1). In addition, the plurality of pixels 230 are classified into, for example, pixels 230a, pixels 230b, and pixels 230c. The pixels 230a, pixels 230b, and pixels 230c have functions of presenting different light. For example, the pixels 230a, pixels 230b, and pixels 230c may also have functions of presenting red (R) light, presenting green (G) light, and presenting blue (B) light, respectively. Alternatively, for example, the pixels 230a, pixels 230b, and pixels 230c may also have functions of presenting yellow (Y) light, presenting cyan (C) light, and presenting magenta (M) light, respectively.

[0442] By using one pixel 230a, one pixel 230b, and one pixel 230c to form one pixel 240, full-color display can be achieved. Therefore, the pixel 230 is used as a sub-pixel. Fig.34A In the display device 200 shown, an example of a pixel 230 used as a sub-pixel in a stripe arrangement is shown. The number of sub-pixels constituting one pixel 240 is not limited to three, and may be four or more. For example, four sub-pixels presenting light of R, G, B, and white (W) may be included. Alternatively, four sub-pixels presenting four types of light of R, G, B, and Y may be included.

[0443] Fig.34B 2 is a block diagram for explaining the display device 200. The display device 200 includes a display unit 235, a first driving circuit unit 231, and a second driving circuit unit 232. Fig.34B In the display unit 235, the pixel 230 in the first row and the nth column is recorded as pixel 230[1,n], the pixel 230 in the mth row and the first column is recorded as pixel 230[m,1], and the pixel 230 in the mth row and the nth column is recorded as pixel 230[m,n]. In addition, an arbitrary pixel 230 in the display unit 235 is sometimes recorded as pixel 230[r,s]. r is an integer greater than 1 and less than m, and s is an integer greater than 1 and less than n.

[0444] The circuit included in the first driving circuit portion 231 is used as, for example, a scanning line driving circuit. The circuit included in the second driving circuit portion 232 is used as, for example, a signal line driving circuit. Note that a certain circuit may be provided at a position opposite to the first driving circuit portion 231 across the display portion 235. A certain circuit may be provided at a position opposite to the second driving circuit portion 232 across the display portion 235. Note that in this specification, etc., the circuits included in the first driving circuit portion 231 and the second driving circuit portion 232 are sometimes collectively referred to as a peripheral driving circuit 233.

[0445] The first drive circuit unit 231 used as a scan line drive circuit has a function of selecting pixels 230 in rows. The first drive circuit unit 231 sequentially selects a plurality of pixels 230 arranged in the mth row from the plurality of pixels 230 arranged in the first row, and writes the image signal supplied by the second drive circuit unit 232 to the selected pixels 230, thereby rewriting the image displayed on the display unit 235.

[0446] The following period is referred to as a "frame period": the period from when the first row of pixels 230 is selected by the first driving circuit unit 231 to when the m-th row of pixels 230 is selected. Therefore, the frame period is a period required to rewrite the image displayed on the display unit 235 once. In addition, the number of times the image is rewritten per second is referred to as a "frame rate". The frame rate is equivalent to the inverse of the frame period. Note that the "frame rate" is sometimes referred to as a "driving frequency".

[0447] When displaying dynamic images with the display device 200, the higher the frame rate, the better. Specifically, the frame rate is set to 60 Hz or more, preferably 120 Hz or more, and more preferably 240 Hz or more. On the other hand, the higher the frame rate, the higher the power consumption of the display device 200.

[0448] As the peripheral driver circuit 233, various circuits such as a shift register circuit, a level converter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit can be used.

[0449] In the peripheral driver circuit 233, the transistor 10 according to one embodiment of the present invention or the like can be used. In addition, as the shift register circuit, the shift register 100 or the signal output circuit 110 according to one embodiment of the present invention or the like can be used. Note that the transistor in the peripheral driver circuit can also be formed using the same process as the transistor in the pixel 230. By using the transistor 10 according to one embodiment of the present invention or the like in the peripheral driver circuit 233, the area occupied by the peripheral driver circuit 233 can be reduced.

[0450] The display device 200 includes m wirings 236 arranged substantially in parallel with each other and whose potentials are controlled by the circuit in the first driving circuit portion 231 , and n wirings 237 arranged substantially in parallel with each other and whose potentials are controlled by the circuit in the second driving circuit portion 232 .

[0451] exist Fig.34B 2 shows an example in which the wiring 236 and the wiring 237 are connected to the pixel 230. However, the wiring 236 and the wiring 237 are just examples, and the wiring connected to the pixel 230 is not limited to the wiring 236 and the wiring 237.

[0452] <Display Components>

[0453] The display device 200 can be in various ways or have various display elements. As an example of a display element, a display medium whose contrast, brightness, reflectivity, transmittance, etc. change due to electrical or magnetic effects can be cited, such as an EL (electroluminescent) element (organic EL element, inorganic EL element, or EL element containing organic and inorganic substances), an LED (white LED, red LED, green LED, blue LED, etc.), a transistor (a transistor that emits light according to current), an electron emission element, a liquid crystal element, an electronic ink, an electrophoretic element, a grating light valve (GLV), a display element using a MEMS (micro-electromechanical system), a digital micromirror device (DMD), a DMS (digital micro shutter), a MIRASOL (registered trademark), an IMOD (interference measurement adjustment) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting (electrowetting) element, a piezoelectric ceramic display, a display element using a carbon nanotube, etc. In addition, as a display element, quantum dots can also be used.

[0454] As an example of a display device using EL elements, there are EL displays, etc. As an example of a display device using electron emission elements, there are field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display: surface-conduction electron emission display), etc. As an example of a display device using quantum dots, there are quantum dot displays, etc. As an example of a display device using liquid crystal elements, there are liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electronic ink, electronic powder fluid (registered trademark) or electrophoretic elements, there are electronic paper, etc. The display device can also be a plasma display (PDP).

[0455] Note that when implementing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may function as a reflective electrode. For example, part or all of the pixel electrode may contain aluminum, silver, etc. In addition, a storage circuit such as SRAM may be disposed under the reflective electrode. Thus, power consumption can be further reduced.

[0456] Note that when an LED is used, graphene or graphite may also be disposed under the electrode or nitride semiconductor of the LED. Graphene or graphite may also be a multilayer film having a plurality of layers stacked thereon. Thus, by providing graphene or graphite, a nitride semiconductor such as an n-type GaN semiconductor layer having crystallization may be more easily formed thereon. Furthermore, a p-type GaN semiconductor layer having crystallization may be provided thereon, thereby enabling an LED to be formed. Furthermore, an AlN layer may also be provided between the graphene or graphite and the n-type GaN semiconductor layer having crystallization. Furthermore, the GaN semiconductor layer included in the LED may also be deposited by MOCVD. Note that the GaN semiconductor layer included in the LED may also be deposited by sputtering by providing graphene.

[0457] <Configuration Example of Pixel Circuit>

[0458] FIG. 35A to FIG. 35D , FIG. 36A to FIG. 36D , Fig.37A and Fig.37B , Fig.38A and Fig.38B 2 shows an example of the structure of the pixel 230. The pixel 230 includes a pixel circuit 51 (a pixel circuit 51A, a pixel circuit 51B, a pixel circuit 51C, a pixel circuit 51D, a pixel circuit 51E, a pixel circuit 51F, a pixel circuit 51G, a pixel circuit 51H, a pixel circuit 51I, a pixel circuit 51J, a pixel circuit 51K, or a pixel circuit 51L) and a light-emitting element 61.

[0459] The light-emitting element (also called light-emitting device) described in this embodiment and the like refers to a self-luminous light-emitting device such as an organic EL element (also called an OLED (Organic Light Emitting Diode)). In addition, the light-emitting element electrically connected to the pixel circuit may be a self-luminous light-emitting element such as an LED (Light Emitting Diode), a micro-LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0460] Fig.35A The pixel circuit 51A shown is a 2Tr1C type pixel circuit including a transistor 52A, a transistor 52B, and a capacitor 53 .

[0461] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. One of the source and drain of the transistor 52A is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. One of the source and drain of the transistor 52B is electrically connected to the wiring ANO. The other of the source and drain of the transistor 52B is electrically connected to the other terminal of the capacitor 53 and the anode of the light emitting element 61. The cathode of the light emitting element 61 is electrically connected to the wiring VCOM. The region where the other of the source and drain of the transistor 52A, the gate of the transistor 52B, and one terminal of the capacitor 53 are electrically connected is used as a node ND.

[0462] The wiring GL corresponds to the wiring 236, and the wiring SL corresponds to the wiring 237. The wiring VCOM is a wiring for supplying a potential for supplying a current to the light emitting element 61. The transistor 52A has a function of controlling the conduction state or non-conduction state between the wiring SL and the gate of the transistor 52B according to the potential of the wiring GL. For example, VDD is supplied to the wiring ANO, and VSS is supplied to the wiring VCOM.

[0463] By turning on the transistor 52A, the image signal is supplied from the wiring SL to the node ND. Then, by turning off the transistor 52A, the image signal is held in the node ND. In order to surely hold the image signal supplied to the node ND, it is preferable to use a transistor with a small off-state current as the transistor 52A. For example, it is preferable to use an OS transistor as the transistor 52A.

[0464] By using an OS transistor as the transistor 52A, the display unit 235 can keep displaying an image even if the frame rate is extremely low (e.g., below 1 Hz). For example, when displaying a static image that does not need to be rewritten for each frame, the image can continue to be displayed even if the operation of the peripheral drive circuit 233 is stopped. The above-mentioned driving method of stopping the operation of the peripheral drive circuit 233 when displaying a static image is also called "idle stop drive". By performing the idle stop drive, the power consumption of the display device can be reduced.

[0465] The transistor 52B has a function of controlling the amount of current flowing through the light emitting element 61. The capacitor 53 has a function of holding the gate potential of the transistor 52B. The intensity of light emitted by the light emitting element 61 is controlled according to an image signal supplied to the gate (node ​​ND) of the transistor 52B.

[0466] Fig.35B The pixel circuit 51B shown is a 3Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53 . Fig.35B The pixel circuit 51B shown has a Fig.35A The pixel circuit 51A shown in the figure has a structure in which a transistor 52C is added.

[0467] One of the source and drain of the transistor 52C is electrically connected to the other of the source and drain of the transistor 52B. The gate of the transistor 52C is electrically connected to the wiring GL. The other of the source and drain of the transistor 52C is electrically connected to the wiring V0. For example, the wiring V0 is supplied with a reference potential.

[0468] The transistor 52C has a function of controlling the conduction state or non-conduction state between the other of the source and the drain of the transistor 52B and the wiring V0 according to the potential of the wiring GL. The wiring V0 is a wiring for supplying a reference potential. When an n-channel transistor is used as the transistor 52B, the potential variation between the gate and the source of the transistor 52B can be suppressed by the reference potential of the wiring V0 supplied through the transistor 52C.

[0469] In addition, the wiring V0 can be used to obtain a current value that can be used for setting pixel parameters. More specifically, the wiring V0 can be used as a monitoring line for outputting the current flowing through the transistor 52B or the current flowing through the light-emitting element 61 to the outside. The current output to the wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A / D converter or the like and output to the outside.

[0470] Fig.35C The pixel circuit 51C shown is an example in which the transistor 52A and the transistor 52B of the pixel circuit 51A are transistors including a back gate and the back gate is electrically connected to the gate. Fig.35D The pixel circuit 51D shown is an example of a pixel circuit 51B using this transistor. Thus, the current that can flow through the transistor can be increased. Note that all transistors shown here use transistors in which the gate and the back gate are electrically connected, but are not limited to this. In addition, a transistor including a gate and a back gate and which are electrically connected to different wirings can also be used. For example, by using a transistor in which one of the gate and the back gate is electrically connected to the source, reliability can be improved.

[0471] Fig.36A The pixel circuit 51E shown has a Fig.35B The pixel circuit 51B shown has a structure in which a transistor 52D is added. Fig.36A The pixel circuit 51E shown is a 4Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, and a capacitor 53 .

[0472] One of the source and the drain of the transistor 52D is electrically connected to the node ND, and the other of the source and the drain is electrically connected to the wiring V0.

[0473] The pixel circuit 51E is electrically connected to the wiring GL1, the wiring GL2, and the wiring GL3. The wiring GL1 is electrically connected to the gate of the transistor 52A, the wiring GL2 is electrically connected to the gate of the transistor 52C, and the wiring GL3 is electrically connected to the gate of the transistor 52D. Note that in this embodiment and the like, the wiring GL1, the wiring GL2, and the wiring GL3 are sometimes collectively referred to as the wiring GL. Therefore, the wiring GL is not limited to one, and may be multiple.

[0474] By turning on transistors 52C and 52D at the same time, the source and gate of transistor 52B have the same potential, so that transistor 52B can be turned off. This can forcibly cut off the current flowing through light-emitting element 61. This pixel circuit is preferably used when a display method in which a display period and a light-off period are alternately set is used.

[0475] Fig.36B The pixel circuit 51F shown in the figure is an example in which a capacitor 53A is added to the pixel circuit 51E described above. The capacitor 53A is used as a storage capacitor. Fig.36A The pixel circuit 51E shown is a 4Tr1C type pixel circuit. In addition, Fig.36B The pixel circuit 51F shown is a 4Tr2C type pixel circuit.

[0476] Fig.36C The pixel circuit 51G and Fig.36DThe pixel circuit 51H shown is an example of a case where the pixel circuit 51E or the pixel circuit 51F uses a transistor including a back gate. The transistors 52A, 52C, and 52D use transistors whose gates are electrically connected to the back gates, and the transistor 52B uses a transistor whose gate and the back gate are electrically connected to the source.

[0477] Fig.37A The pixel circuit 51I shown is a 6Tr1C type pixel circuit including a transistor 52A, a transistor 52B, a transistor 52C, a transistor 52D, a transistor 52E, a transistor 52F, and a capacitor 53 .

[0478] One of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL1. One of the source and drain of the transistor 52D is electrically connected to the wiring ANO, and the gate of the transistor 52D is electrically connected to the wiring GL2. The other of the source and drain of the transistor 52D is electrically connected to one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52B is electrically connected to the other of the source and drain of the transistor 52A and one of the source and drain of the transistor 52F. The gate of the transistor 52F is electrically connected to the wiring GL3.

[0479] One of the source and drain of the transistor 52E is electrically connected to the other of the source and drain of the transistor 52D and one of the source and drain of the transistor 52B. The other of the source and drain of the transistor 52E is electrically connected to the gate of the transistor 52B and one terminal of the capacitor 53. The other terminal of the capacitor 53 is electrically connected to the other of the source and drain of the transistor 52F, the anode of the light emitting element 61, and one of the source and drain of the transistor 52C.

[0480] The gate of the transistor 52E and the gate of the transistor 52C are electrically connected to the wiring GL4. The other of the source and the drain of the transistor 52C is electrically connected to the wiring V0. The region where the other of the source and the drain of the transistor 52E, the gate of the transistor 52B, and one terminal of the capacitor 53 are electrically connected is used as a node ND. In the pixel circuit 51I, it is particularly preferable to use an OS transistor as the transistor 52E.

[0481] like Fig.37B As shown, a transistor including a back gate may be used as a transistor included in the pixel circuit 51J. The transistors 52A, 52C, 52D, 52E, and 52F are transistors in which the gate and the back gate are electrically connected, and the transistor 52B is a transistor in which the back gate is electrically connected to the other of the source and the drain.

[0482] As the transistor 52A, the transistor 52C, the transistor 52D, the transistor 52E, and the transistor 52F, the transistor 10 according to one embodiment of the present invention can be used.

[0483] Fig.38A The pixel 230 shown in FIG. 1 includes a pixel circuit 51K and a liquid crystal element 62. The pixel circuit 51K includes a transistor 52A and a capacitor 53. Fig.38A In the embodiment, one of the source and drain of the transistor 52A is electrically connected to the wiring SL, and the gate of the transistor 52A is electrically connected to the wiring GL. The other of the source and drain of the transistor 52A is electrically connected to one terminal of the capacitor 53 and the liquid crystal element 62. The other terminal of the capacitor 53 is electrically connected to the wiring VCOM. The region where the other of the source and drain of the transistor 52A, one terminal of the capacitor 53, and the liquid crystal element 62 are electrically connected is used as a node ND. The orientation state of the liquid crystal element 62 depends on the data written in the node ND.

[0484] As a driving method for a display device having a liquid crystal element 62, for example, a TN (Twisted Nematic) mode, a STN (Super Twisted Nematic) mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode or a TBA (Transverse Bend Alignment) mode can be used. In addition, as a driving method of the display device, in addition to the above-mentioned driving method, there are ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, guest-host mode, etc. However, it is not limited to these, and various liquid crystal elements and their driving methods can be used.

[0485] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. can be used. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on the conditions.

[0486] In addition, a liquid crystal presenting a blue phase without using an orientation film can also be used. The blue phase is a type of liquid crystal phase, and refers to a phase that appears just before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase only appears in a narrow temperature range, a liquid crystal composition mixed with a chiral agent of more than 5wt.% is used in the liquid crystal layer in order to improve the temperature range. Since the response speed of the liquid crystal composition including the liquid crystal presenting the blue phase and the chiral agent is short, that is, less than 1msec, and it has optical isotropy, it does not require an orientation treatment, and has low viewing angle dependence. In addition, since an orientation film is not required and a friction treatment is not required, electrostatic damage caused by the friction treatment can be prevented, thereby reducing the defects and damage of the liquid crystal display device in the manufacturing process. Therefore, the productivity of the liquid crystal display device can be improved.

[0487] Alternatively, a method called multi-domain design may be used in which a pixel is divided into several regions (sub-pixels) and molecules are tilted in different directions.

[0488] In addition, the intrinsic resistance of liquid crystal materials is 1×10 9 Ω·cm or more, preferably 1×10 11 Ω·cm or more, more preferably 1×10 12 Ω·cm or more. In addition, the value of the specific resistance in this specification is a value measured at 20°C.

[0489] In addition, if Fig.38B As shown, the pixel 230 may also include a pixel circuit 51L instead of the pixel circuit 51K. The pixel circuit 51L includes a transistor 52A having a back gate. Fig.38B In the transistor 52A shown, the gate and the back gate are electrically connected, so the gate and the back gate are always at the same potential.

[0490] By using the transistor 10 according to one embodiment of the present invention in a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced. Therefore, the definition of the display device can be improved. For example, a display device having a definition of 1000 ppi or more, preferably 2000 ppi or more, more preferably 3000 ppi or more, further preferably 4000 ppi or more, further preferably 5000 ppi or more, further preferably 6000 ppi or more and 10000 ppi or less, 9000 ppi or less, or 8000 ppi or less can be realized.

[0491] In addition, by reducing the area occupied by the pixel circuit, the number of pixels of the display device can be increased (the resolution can be improved). For example, extremely high-resolution display devices such as HD (1280×720 pixels), FHD (1920×1080 pixels), WQHD (2560×1440 pixels), WQXGA (2560×1600 pixels), 4K2K (3840×2160 pixels), or 8K4K (7680×4320 pixels) can be realized.

[0492] Therefore, by using the transistor 10 according to one embodiment of the present invention in a pixel circuit of a display device, the display quality of the display device can be improved. In addition, the aperture ratio of the pixel can be increased in a bottom emission type display device using an EL element. A pixel with a high aperture ratio can emit light with the same brightness as a pixel with a low aperture ratio at a lower current density than a pixel with a low aperture ratio. Therefore, the reliability of the display device can be improved.

[0493] [Example of the configuration of peripheral circuits]

[0494] Fig.39A 2 shows an example of the structure of the second driver circuit unit 232. The second driver circuit unit 232 includes a shift register 512, a latch circuit 513, and a buffer 514. In addition, wiring 237 [1], wiring 237 [2], wiring 237 [3], and wiring 237 [n] are shown as wiring 237. In addition, Fig.39B 2 shows a configuration example of the first driver circuit unit 231. The first driver circuit unit 231 includes a shift register 522 and a buffer 523. In addition, as the wiring 236, a wiring 236[1], a wiring 236[2], a wiring 236[3], and a wiring 236[n] are shown.

[0495] The start pulse SP, the signal CLK, etc. are input to the shift register 512 and the shift register 522. As the shift register 512 and the shift register 522, the shift register 100 disclosed in the above embodiment can be used.

[0496] <Pixel Layout>

[0497] use FIG. 40A to FIG. 40G and Figures 41A to 41K Main description and Fig.34A Different pixel layouts. There is no particular limitation on the arrangement of sub-pixels, and various pixel layouts can be used. Examples of sub-pixel arrangements include stripe arrangement, S-stripe arrangement, matrix arrangement, Delta arrangement, Bayer arrangement, Pentile arrangement, and the like.

[0498] Notice, Fig.34A , FIG. 40A to FIG. 40G and Figures 41A to 41K The planar shape of the sub-pixel shown corresponds to the planar shape of the light-emitting region.

[0499] Examples of the planar shape of the sub-pixel include a triangle, a quadrangle (including a rectangle and a square), a polygon such as a pentagon, the above polygonal shapes with rounded corners, an ellipse, or a circle.

[0500] The pixel circuit 51 included in the sub-pixel (pixel 230 ) may be arranged to overlap with the light-emitting region or may be arranged outside the light-emitting region.

[0501] Fig.40A The pixels 240 are shown in an S-stripe arrangement. Fig.40A The pixel 240 shown is composed of three sub-pixels: a pixel 230 a , a pixel 230 b , and a pixel 230 c .

[0502] Fig.40B The pixel 240 shown includes a pixel 230a having a planar shape of a trapezoid with rounded corners, a pixel 230b having a planar shape of a trapezoid with rounded corners, and a pixel 230c having a planar shape of a quadrangular or hexagonal shape with rounded corners. In addition, the light-emitting area of ​​the pixel 230a is larger than that of the pixel 230b. In this way, the shape and size of each sub-pixel can be determined independently. For example, the size of the sub-pixel including a light-emitting device with high reliability can be smaller.

[0503] Fig.40C The pixel 240A and the pixel 240B shown are arranged in a Pentile arrangement. Fig.40C An example is shown in which pixels 240A including pixels 230 a and pixels 230 b and pixels 240B including pixels 230 b and pixels 230 c are alternately arranged.

[0504] FIG. 40D to FIG. 40FThe pixel 240A and the pixel 240B shown are arranged in a delta arrangement. The pixel 240A includes two sub-pixels (pixel 230a and pixel 230b) in the upper row (first row) and one sub-pixel (pixel 230c) in the lower row (second row). The pixel 240B includes one sub-pixel (pixel 230c) in the upper row (first row) and two sub-pixels (pixel 230a and pixel 230b) in the lower row (second row).

[0505] Fig.40D This is an example in which each sub-pixel has a planar shape that is approximately quadrilateral with rounded corners. Fig.40E is an example in which each sub-pixel has a circular planar shape, Fig.40F This is an example in which each sub-pixel has a planar shape that is approximately hexagonal with rounded corners.

[0506] exist Fig.40F In the embodiment, each sub-pixel is arranged inside the hexagonal area that is arranged most closely. Each sub-pixel is arranged in a manner that it is surrounded by six sub-pixels when focusing on one of the sub-pixels. In addition, sub-pixels that present light of the same color are arranged in a manner that they are not adjacent. For example, each sub-pixel is arranged in a manner that three pixels 230b and three pixels 230c that are alternately arranged surround the pixel 230a when focusing on the pixel 230a.

[0507] Figure 40G An example is shown in which the sub-pixels of each color are arranged in a zigzag shape. Specifically, in a plan view, the positions of the upper sides of two sub-pixels arranged in the column direction (for example, pixel 230a and pixel 230b or pixel 230b and pixel 230c) are offset.

[0508] exist FIG. 40A to FIG. 40G In the pixels shown, for example, it is preferred that a sub-pixel R emitting red light is used as the pixel 230a, a sub-pixel G emitting green light is used as the pixel 230b, and a sub-pixel B emitting blue light is used as the pixel 230c. Note that the structure of the sub-pixels is not limited thereto, and the colors emitted by the sub-pixels and the arrangement order can be appropriately determined. For example, a sub-pixel R emitting red light can be used as the pixel 230b, and a sub-pixel G emitting green light can be used as the pixel 230a.

[0509] In photolithography, the finer the pattern being processed, the more important it is to ignore the effect of light diffraction. Therefore, when the pattern of the photomask is transferred by exposure, its fidelity decreases, and it is difficult to process the resist mask into a desired shape. Therefore, even if the pattern of the photomask is rectangular, it is easy to form a pattern with rounded corners. Therefore, the planar shape of the sub-pixel is sometimes a polygon with rounded corners, an ellipse, or a circle.

[0510] Furthermore, when the EL layer is processed into an island shape using a resist mask, the resist film formed on the EL layer needs to be cured at a temperature lower than the heat resistance temperature of the EL layer. Therefore, depending on the heat resistance temperature of the material of the EL layer and the curing temperature of the resist material, the curing of the resist film may be insufficient. The insufficiently cured resist film may have a shape that is far from the desired shape when processed. As a result, the planar shape of the EL layer may be a polygonal shape with rounded corners, an ellipse, a circle, or the like. For example, when a resist mask having a square planar shape is to be formed, a resist mask having a circular planar shape may be formed, and the planar shape of the EL layer may be circular.

[0511] In order to make the planar shape of the EL layer a desired shape, a technique (OPC (Optical Proximity Correction) technique) of pre-correcting the mask pattern in such a way that the design pattern and the transfer pattern are consistent can also be used. Specifically, in the OPC technique, correction patterns are added to the corners of the pattern on the mask pattern.

[0512] like FIG. 41A to FIG. 41I As shown, a pixel may include four types of sub-pixels.

[0513] FIG. 41A to FIG. 41C The pixels 240 are shown arranged in a stripe pattern.

[0514] Fig.41A is an example in which each sub-pixel has a rectangular planar shape, Fig.41B is an example in which each sub-pixel has a planar shape connecting two semicircles and a rectangle, Fig.41C This is an example in which each sub-pixel has an elliptical planar shape.

[0515] FIG. 41D to FIG. 41F The pixels 240 are shown arranged in a matrix.

[0516] Fig.41D is an example in which each sub-pixel has a square planar shape, Fig.41E This is an example in which each sub-pixel has a planar shape that is approximately square with rounded corners. Fig.41F This is an example in which each sub-pixel has a circular planar shape.

[0517] Figure 41G and Fig.41H An example is shown in which one pixel 240 is formed using sub-pixels arranged in two rows and three columns.

[0518] Figure 41GThe pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) of the pixel 240 and one sub-pixel (pixel 230d) in the lower row (second row). In other words, the pixel 240 includes the pixel 230a in the left column (first column), the pixel 230b in the middle column (second column), the pixel 230c in the right column (third column), and the pixel 230d spanning the three columns.

[0519] Fig.41H The pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) and three pixels 230d in the lower row (second row). In other words, the pixel 240 includes pixel 230a and pixel 230d in the left column (first column) of the pixel 240, includes pixel 230b and pixel 230d in the middle column (second column), and includes pixel 230c and pixel 230d in the right column (third column). Fig.41H As shown, by adopting a structure in which the sub-pixels of the upper row and the lower row are aligned, dust and the like that may be generated in the manufacturing process can be efficiently removed. Therefore, a display device with high display quality can be provided.

[0520] Fig.41I An example is shown in which one pixel 240 is formed using sub-pixels arranged in three rows and two columns.

[0521] Fig.41I The illustrated pixel 240 includes a pixel 230a in the upper row (first row) of the pixel 240, includes a pixel 230b in the middle row (second row), includes a pixel 230c that spans the first row to the second row, and includes a sub-pixel (pixel 230d) in the lower row (third row). In other words, the pixel 240 includes the pixel 230a and the pixel 230b in the left column (first column) of the pixel 240, includes the pixel 230c in the right column (second column), and includes a pixel 230d that spans the two columns.

[0522] FIG. 41A to FIG. 41I The pixel 240 shown is composed of four sub-pixels, namely, a pixel 230 a , a pixel 230 b , a pixel 230 c , and a pixel 230 d .

[0523] The pixels 230a, 230b, 230c, and 230d may include light-emitting devices that emit light of different colors. The pixels 230a, 230b, 230c, and 230d may include sub-pixels of four colors: R, G, B, and white (W); sub-pixels of four colors: R, G, B, and Y; and sub-pixels of R, G, B, and infrared light (IR); and the like.

[0524] exist FIG. 41A to FIG. 41IIn each pixel 240 shown, for example, a sub-pixel R emitting red light may be used as a pixel 230a, a sub-pixel G emitting green light may be used as a pixel 230b, a sub-pixel B emitting blue light may be used as a pixel 230c, and a sub-pixel W emitting white light, a sub-pixel emitting yellow light, or a sub-pixel emitting near-infrared light may be used as a pixel 230d. Figure 41G and Fig.41H In the pixel 240 shown in FIG. 1 , the layout of R, G, and B is a stripe arrangement, so the display quality can be improved. Fig.41I In the pixel 240 shown, the layout of R, G, and B is a so-called S-stripe arrangement, so the display quality can be improved.

[0525] In addition, the pixel 240 may include a sub-pixel having a light-receiving element (also referred to as a light-receiving device).

[0526] exist FIG. 41A to FIG. 41I In each pixel 240 shown, any one of the pixels 230 a to 230 d may be a sub-pixel including a light-receiving device.

[0527] exist FIG. 41A to FIG. 41I In the pixels 240 shown, for example, a sub-pixel R emitting red light may be used as the pixel 230a, a sub-pixel G emitting green light may be used as the pixel 230b, a sub-pixel B emitting blue light may be used as the pixel 230c, and a sub-pixel S including a light-receiving device may be used as the pixel 230d. Figure 41G and Fig.41H In the pixel 240 shown in FIG. 1 , the layout of R, G, and B is a stripe arrangement, so the display quality can be improved. Fig.41I In the pixel 240 shown, the layout of R, G, and B is a so-called S-stripe arrangement, so the display quality can be improved.

[0528] There is no particular limitation on the wavelength of light detected by the sub-pixel S including the light-receiving device. The sub-pixel S can detect one or both of visible light and infrared light.

[0529] like Fig.41J and Figure 41K As shown, one pixel 240 may also include five sub-pixels.

[0530] Fig.41J An example is shown in which one pixel 240 is formed using sub-pixels arranged in two rows and three columns.

[0531] Fig.41JThe pixel 240 shown includes three sub-pixels (pixel 230a, pixel 230b, pixel 230c) in the upper row (first row) of the pixel 240 and two sub-pixels (pixel 230d, pixel 230e) in the lower row (second row). In other words, the pixel 240 includes the pixel 230a and the pixel 230d in the left column (first column) of the pixel 240, includes the pixel 230b in the middle column (second column), includes the sub-pixel 230c in the right column (third column), and includes the pixel 230e spanning from the second column to the third column.

[0532] Figure 41K An example is shown in which one pixel 240 is formed using sub-pixels arranged in three rows and two columns.

[0533] Figure 41K The pixel 240 shown includes a pixel 230a in the upper row (first row) of the pixel 240, a pixel 230b in the middle row (second row), a pixel 230c spanning from the first row to the second row, and two sub-pixels (pixel 230d and pixel 230e) in the lower row (third row). In other words, the pixel 240 includes a pixel 230a, a pixel 230b, and a pixel 230d in the left column (first column), and includes a pixel 230c and a pixel 230e in the right column (second column).

[0534] exist Fig.41J and Figure 41K In the pixels 240 shown, for example, it is preferred that a sub-pixel R emitting red light is used as the pixel 230a, a sub-pixel G emitting green light is used as the pixel 230b, and a sub-pixel B emitting blue light is used as the pixel 230c. Fig.41J In the pixel 240 shown in FIG. 1 , the sub-pixels are arranged in a stripe pattern, so the display quality can be improved. Figure 41K In the pixel 240 shown, the layout of the sub-pixels is a so-called S-stripe arrangement, so that the display quality can be improved.

[0535] exist Fig.41J and Figure 41K In each pixel 240 shown, for example, a sub-pixel S including a light-receiving device may also be used as at least one of the pixel 230d and the pixel 230e. When a light-receiving device is used in both the pixel 230d and the pixel 230e, the structure of the light-receiving device may also be different from each other. For example, at least one part in the wavelength region of the detected light may also be different from each other. Specifically, one of the pixel 230d and the pixel 230e may include a light-receiving device that mainly detects visible light, and the other may include a light-receiving device that mainly detects infrared light.

[0536] In addition, Fig.41J and Figure 41KIn each pixel 240 shown, for example, a sub-pixel S including a light-receiving device may be used as one of the pixel 230d and the pixel 230e, and a sub-pixel including a light-emitting device that can be used as a light source may be used as the other. For example, a sub-pixel IR (not shown) that emits infrared light may be used as one of the pixel 230d and the pixel 230e, and a sub-pixel S (not shown) that includes a light-receiving device that detects infrared light may be used as the other.

[0537] In a pixel including sub-pixels R, G, B, IR, and S, images can be displayed using sub-pixels R, G, and B and sub-pixel IR can be used as a light source while sub-pixel S detects reflected light of infrared light emitted by sub-pixel IR.

[0538] As described above, in the display device of one embodiment of the present invention, various sub-pixel (pixel 230) layouts can be adopted as pixel 240. In addition, a structure including both a light-emitting device and a light-receiving device in pixel 240 can also be adopted. In this case, various layouts can also be adopted.

[0539] The structure described in this embodiment mode can be used in combination with the structures described in other embodiment modes as appropriate.

[0540] (Implementation 4)

[0541] In this embodiment, a light-emitting device that can be used as the light-emitting element 61 is described.

[0542] like Fig.42A As shown in FIG. 1 , the light-emitting device includes an EL layer 763 between a pair of electrodes (a lower electrode 761 and an upper electrode 762). The EL layer 763 may be composed of a plurality of layers such as a layer 780, a light-emitting layer 771, and a layer 790.

[0543] The light-emitting layer 771 contains at least a light-emitting substance (also referred to as a light-emitting material).

[0544] In the case where the lower electrode 761 and the upper electrode 762 are respectively the anode and the cathode, the layer 780 includes one or more of a layer containing a substance with high hole injection property (hole injection layer), a layer containing a substance with high hole transport property (hole transport layer), and a layer containing a substance with high electron blocking property (electron blocking layer). In addition, the layer 790 includes one or more of a layer containing a substance with high electron injection property (electron injection layer), a layer containing a substance with high electron transport property (electron transport layer), and a layer containing a substance with high hole blocking property (hole blocking layer). In the case where the lower electrode 761 and the upper electrode 762 are respectively the cathode and the anode, the structures of the layers 780 and 790 are reversed from the above.

[0545] The structure including the layer 780 disposed between a pair of electrodes, the light-emitting layer 771, and the layer 790 can be used as a single light-emitting unit. Fig.42A The structure is called a simple structure.

[0546] Fig.42B Show Fig.42A 1 is a modified example of the EL layer 763 included in the light-emitting device shown in FIG. Fig.42B The light-emitting device shown includes a layer 781 on a lower electrode 761 , a layer 782 on layer 781 , a light-emitting layer 771 on layer 782 , a layer 791 on light-emitting layer 771 , a layer 792 on layer 791 , and an upper electrode 762 on layer 792 .

[0547] When the lower electrode 761 and the upper electrode 762 are respectively an anode and a cathode, for example, the layers 781, 782, 791, and 792 may be respectively a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. In addition, when the lower electrode 761 and the upper electrode 762 are respectively a cathode and an anode, the layers 781, 782, 791, and 792 may be respectively an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer. By adopting the above-mentioned layer structure, carriers can be efficiently injected into the light-emitting layer 771, thereby improving the efficiency of the recombination of carriers in the light-emitting layer 771.

[0548] In addition, if Fig.42C and Fig.42D As shown in FIG. 1 , a structure in which a plurality of light-emitting layers (light-emitting layers 771, 772, and 773) are provided between layer 780 and layer 790 is also a modified example of a single structure. Fig.42C and Fig.42D An example including three light-emitting layers is shown, but the light-emitting layers in the light-emitting device with a single structure may be two layers, or may be four or more layers. In addition, the light-emitting device with a single structure may also include a buffer layer between the two light-emitting layers. The buffer layer may use, for example, a carrier transport layer (hole transport layer and electron transport layer).

[0549] In addition, if Fig.42E and Fig.42F As shown, in this specification, a structure in which multiple light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via a charge generation layer 785 (also referred to as an intermediate layer) is referred to as a series structure. In addition, the series structure may also be referred to as a stacked structure. By adopting a series structure, a light-emitting device capable of emitting light with high brightness can be realized. In addition, the series structure can improve reliability because it can reduce the current required to obtain the same brightness compared to a single structure.

[0550] Fig.42D and Fig.42FAn example is shown in which the display device includes a layer 764 overlapping the light-emitting device. Fig.42D Layer 764 is shown overlapping Fig.42C Examples of light emitting devices shown, Fig.42F Layer 764 is shown overlapping Fig.42E An example of a light emitting device is shown. Fig.42D and Fig.42F In the embodiment, the upper electrode 762 uses a conductive film that transmits visible light to extract light to the upper electrode 762 side.

[0551] As the layer 764, one or both of a color conversion layer and a color filter (coloring layer) can be used.

[0552] exist Fig.42C and Fig.42D In the embodiment, a luminescent material that emits light of the same color, or even the same luminescent material, may be used for the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773. For example, a luminescent material that emits blue light may be used for the luminescent layer 771, the luminescent layer 772, and the luminescent layer 773. For a sub-pixel that emits blue light, the blue light emitted by the light-emitting device may be extracted. In addition, for a sub-pixel that emits red light and a sub-pixel that emits green light, by using Fig.42D The layer 764 shown is provided with a color conversion layer, which can convert the blue light emitted by the light-emitting device into light with a longer wavelength and extract it as red light or green light. In addition, it is preferred to use both a color conversion layer and a coloring layer as the layer 764. A part of the light emitted by the light-emitting device sometimes passes through without being converted by the color conversion layer. By extracting the light that passes through the color conversion layer through the coloring layer, the color purity of the light presented by the sub-pixel can be improved by absorbing light other than the desired color light by the coloring layer.

[0553] exist Fig.42C and Fig.42D In the embodiment, light-emitting materials having different luminescent colors may be used for the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. When the light emitted by the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 is in a complementary color relationship, white light emission can be obtained. For example, a light-emitting device having a single structure preferably includes a light-emitting layer containing a light-emitting material that emits blue light and a light-emitting layer containing a light-emitting material that emits visible light having a longer wavelength than blue.

[0554] As Fig.42D The layer 764 shown may also be provided with a color filter, and light of a desired color may be obtained by passing white light through the color filter.

[0555] For example, in the case where a light-emitting device having a single structure includes three light-emitting layers, it is preferred to include a light-emitting layer containing a light-emitting substance that emits red (R) light, a light-emitting layer containing a light-emitting substance that emits green (G) light, and a light-emitting layer containing a light-emitting substance that emits blue (B) light. As the stacking order of the light-emitting layers, the order of stacking R, G, and B in sequence from the anode side or the order of stacking R, B, and G in sequence from the anode side can be adopted. At this time, a buffer layer can also be provided between R and G or B.

[0556] For example, in the case where a light-emitting device having a single structure includes two light-emitting layers, it is preferable to adopt a structure including a light-emitting layer containing a light-emitting substance emitting blue (B) light and a light-emitting layer containing a light-emitting substance emitting yellow (Y) light. This structure is sometimes referred to as a light-emitting device with a BY single structure.

[0557] A light-emitting device that emits white light preferably includes two or more light-emitting substances. In order to obtain white light emission, the light-emitting substances may be selected in such a way that the light emission of the two or more light-emitting substances is in a complementary color relationship. For example, by making the light emission color of the first light-emitting layer and the light emission color of the second light-emitting layer in a complementary color relationship, a light-emitting device that emits white light as a whole can be obtained. In addition, the same is true for a light-emitting device including three or more light-emitting layers.

[0558] Notice, Fig.42C , Fig.42D The layers 780 and 790 in the embodiment may also be independently selected. Fig.42B The laminated structure shown is composed of two or more layers.

[0559] exist Fig.42E and Fig.42F In the embodiment, a luminescent material that emits light of the same color, or even the same luminescent material, may be used for the luminescent layer 771 and the luminescent layer 772. For example, in a luminescent device included in a sub-pixel that presents light of each color, a luminescent material that emits blue light may be used for the luminescent layer 771 and the luminescent layer 772. For a sub-pixel that presents blue light, the blue light emitted by the luminescent device can be extracted. In addition, for a sub-pixel that presents red light and a sub-pixel that presents green light, by using Fig.42F The layer 764 shown is provided with a color conversion layer, which can convert the blue light emitted by the light-emitting device into light with a longer wavelength and extract it as red light or green light. In addition, it is preferable to use both a color conversion layer and a coloring layer as the layer 764.

[0560] In addition, Fig.42E or Fig.42FWhen the light-emitting device of the structure shown is used to present sub-pixels of each color, different light-emitting materials can be used according to the sub-pixels. Specifically, in the light-emitting device included in the sub-pixel presenting red light, the light-emitting material that emits red light can also be used for the light-emitting layer 771 and the light-emitting layer 772. Similarly, in the light-emitting device included in the sub-pixel presenting green light, the light-emitting material that emits green light can also be used for the light-emitting layer 771 and the light-emitting layer 772. In the light-emitting device included in the sub-pixel presenting blue light, the light-emitting material that emits blue light can also be used for the light-emitting layer 771 and the light-emitting layer 772. It can be said that the display device with such a structure uses a light-emitting device with a series structure and has an SBS (Side By Side) structure. Thus, it has the advantages of both the series structure and the SBS structure. Thus, a light-emitting device with high brightness and high reliability can be realized.

[0561] In addition, Fig.42E and Fig.42F In the embodiment, light-emitting materials having different luminescent colors may be used for the light-emitting layer 771 and the light-emitting layer 772. When the light emitted by the light-emitting layer 771 and the light emitted by the light-emitting layer 772 are in a complementary color relationship, white light emission can be obtained. Fig.42F The layer 764 shown may also be provided with a color filter. By passing white light through the color filter, light of a desired color may be obtained.

[0562] Note that although Fig.42E and Fig.42F The example in which the light-emitting unit 763a includes one light-emitting layer 771 and the light-emitting unit 763b includes one light-emitting layer 772 is shown, but the present invention is not limited thereto. The light-emitting unit 763a and the light-emitting unit 763b may each include two or more light-emitting layers.

[0563] Although Fig.42E and Fig.42F The light emitting device including two light emitting units is shown as an example, but is not limited thereto. The light emitting device may also include more than three light emitting units. Note that the structure including two light emitting units and the structure including three light emitting units may also be referred to as a two-stage series structure and a three-stage series structure, respectively.

[0564] exist Fig.42E and Fig.42F In the embodiment, the light emitting unit 763a includes a layer 780a, a light emitting layer 771, and a layer 790a, and the light emitting unit 763b includes a layer 780b, a light emitting layer 772, and a layer 790b.

[0565] In the case where the lower electrode 761 and the upper electrode 762 are respectively an anode and a cathode, the layers 780a and 780b each include one or more of a hole injection layer, a hole transport layer, and an electron blocking layer. In addition, the layers 790a and 790b each include one or more of an electron injection layer, an electron transport layer, and a hole blocking layer. In the case where the lower electrode 761 and the upper electrode 762 are respectively a cathode and an anode, the structures of the layers 780a and 790a are reversed from the above, and the structures of the layers 780b and 790b are also reversed from the above.

[0566] In the case where the lower electrode 761 and the upper electrode 762 are respectively the anode and the cathode, for example, the layer 780a includes a hole injection layer and a hole transport layer on the hole injection layer, and may also include an electron blocking layer on the hole transport layer. In addition, the layer 790a includes an electron transport layer, and may also include a hole blocking layer between the light-emitting layer 771 and the electron transport layer. In addition, the layer 780b includes a hole transport layer, and may also include an electron blocking layer on the hole transport layer. In addition, the layer 790b includes an electron transport layer and an electron injection layer on the electron transport layer, and may also include a hole blocking layer between the light-emitting layer 772 and the electron transport layer. In the case where the lower electrode 761 and the upper electrode 762 are respectively the cathode and the anode, for example, the layer 780a includes an electron injection layer and an electron transport layer on the electron injection layer, and may also include a hole blocking layer on the electron transport layer. In addition, the layer 790a includes a hole transport layer, and may also include an electron blocking layer between the light-emitting layer 771 and the hole transport layer. In addition, layer 780b includes an electron transport layer and may also include a hole blocking layer on the electron transport layer. In addition, layer 790b includes a hole transport layer and a hole injection layer on the hole transport layer and may also include an electron blocking layer between the light emitting layer 772 and the hole transport layer.

[0567] When manufacturing a light-emitting device having a tandem structure, two light-emitting units are stacked via a charge generation layer 785. The charge generation layer 785 has at least a charge generation region. The charge generation layer 785 has a function of injecting electrons into one of the two light-emitting units and injecting holes into the other when a voltage is applied between a pair of electrodes.

[0568] As an example of a tandem structure light emitting element, there can be cited FIG. 43A to FIG. 43C The structure shown.

[0569] Fig.43A FIG. 4 shows a structure including three light emitting units. Fig.43AIn the embodiment, a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series with each other via a charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b includes layer 780b, light-emitting layer 772, and layer 790b, and light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c. Note that layer 780c may adopt a structure applicable to layer 780a and layer 780b, and layer 790c may adopt a structure applicable to layer 790a and layer 790b.

[0570] exist Fig.43A In the embodiment, the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 preferably contain a light-emitting substance that emits light of the same color. Specifically, the following structures can be adopted: a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a red (R) light-emitting substance (so-called R\R\R three-stage tandem structure); a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a green (G) light-emitting substance (so-called G\G\G three-stage tandem structure); or a structure in which the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773 all contain a blue (B) light-emitting substance (so-called B\B\B three-stage tandem structure). Note that "a\b" means that a light-emitting unit containing a light-emitting substance that emits light a is provided with a light-emitting unit containing a light-emitting substance that emits light b via a charge generation layer, and a and b represent colors.

[0571] exist Fig.43A In the embodiment, light-emitting materials having different light-emitting colors may be used for part or all of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773. As a combination of light-emitting colors of the light-emitting layer 771, the light-emitting layer 772, and the light-emitting layer 773, for example, a structure in which any two of them are blue (B) and the remaining one is yellow (Y) and a structure in which any one of them is red (R), another one is green (G), and the remaining one is blue (B) can be cited.

[0572] Note that the light-emitting materials that emit the same color are not limited to the above structures. Fig.43B As shown in FIG. 1 , a tandem type light emitting element in which light emitting units including a plurality of light emitting layers are stacked may also be used. Fig.43B In the embodiment, two light-emitting units (light-emitting unit 763a and light-emitting unit 763b) are connected in series via charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771a, light-emitting layer 771b, light-emitting layer 771c, and layer 790a, and light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b.

[0573] exist Fig.43BIn the embodiment, the luminescent materials of the luminescent layer 771a, the luminescent layer 771b, and the luminescent layer 771c are selected to be in a complementary color relationship, so that the luminescent unit 763a has a structure capable of achieving white luminescence (W). In addition, the luminescent materials of the luminescent layer 772a, the luminescent layer 772b, and the luminescent layer 772c are also selected to be in a complementary color relationship, so that the luminescent unit 763b has a structure capable of achieving white luminescence (W). That is, Fig.43B The structure shown is a W\W two-stage series structure. Note that there is no particular restriction on the stacking order of the luminescent materials in a non-color relationship. The implementer can appropriately select the most appropriate stacking order. Although not shown in the figure, a W\W\W three-stage series structure or a series structure of four or more stages can also be used.

[0574] In addition, when using a light-emitting device with a series structure, examples include: a B\Y or Y\B two-stage series structure including a light-emitting unit emitting yellow (Y) light and a light-emitting unit emitting blue (B) light; an R·G\B or B\R·G two-stage series structure including a light-emitting unit emitting red (R) light and green (G) light and a light-emitting unit emitting blue (B) light; a B\Y\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting yellow (Y) light, and a light-emitting unit emitting blue (B) light in sequence; a B\YG\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting yellow-green (YG) light, and a light-emitting unit emitting blue (B) light in sequence; and a B\G\B three-stage series structure including a light-emitting unit emitting blue (B) light, a light-emitting unit emitting green (G) light, and a light-emitting unit emitting blue (B) light in sequence, etc. Note that “a·b” means that one light-emitting unit includes a light-emitting substance that emits light of a and a light-emitting substance that emits light of b.

[0575] like Fig.43C As shown, a light-emitting unit including one light-emitting layer and a light-emitting unit including a plurality of light-emitting layers may also be combined.

[0576] Specifically, in Fig.43C In the structure shown, a plurality of light-emitting units (light-emitting unit 763a, light-emitting unit 763b, and light-emitting unit 763c) are connected in series with each other via a charge generation layer 785. In addition, light-emitting unit 763a includes layer 780a, light-emitting layer 771, and layer 790a, light-emitting unit 763b includes layer 780b, light-emitting layer 772a, light-emitting layer 772b, light-emitting layer 772c, and layer 790b, and light-emitting unit 763c includes layer 780c, light-emitting layer 773, and layer 790c.

[0577] For example, in Fig.43CThe structure shown can adopt a B\R·G·YG\B three-stage series structure, wherein the light-emitting unit 763a is a light-emitting unit that emits blue (B) light, the light-emitting unit 763b is a light-emitting unit that emits red (R) light, green (G) light and yellow-green (YG) light, and the light-emitting unit 763c is a light-emitting unit that emits blue (B) light.

[0578] For example, as the number of layers and color sequence of the light-emitting unit, there can be cited a two-stage structure in which B and Y are stacked from the anode side, a two-stage structure in which B and the light-emitting unit X are stacked, a three-stage structure in which B, Y and B are stacked, and a three-stage structure in which B, X and B are stacked. As the number of layers and color sequence of the light-emitting layer in the light-emitting unit X, there can be adopted a two-stage structure in which R and Y are stacked from the anode side, a two-stage structure in which R and G are stacked, a two-stage structure in which G and R are stacked, a three-stage structure in which G, R and G are stacked, or a three-stage structure in which R, G and R are stacked. In addition, another layer may be provided between two light-emitting layers.

[0579] Next, materials that can be used for the light-emitting device are described.

[0580] A conductive film that transmits visible light is used as the electrode on the light extraction side of the lower electrode 761 and the upper electrode 762. In addition, a conductive film that reflects visible light is preferably used as the electrode on the side that does not extract light. In addition, when the display device includes a light-emitting device that emits infrared light, it is preferred that a conductive film that transmits visible light and infrared light is used as the electrode on the light extraction side, and a conductive film that reflects visible light and infrared light is used as the electrode on the side that does not extract light.

[0581] Alternatively, a conductive film that transmits visible light may be used as the electrode on the side that does not extract light. In this case, the electrode is preferably arranged between the reflective layer and the EL layer 763. In other words, light emitted from the EL layer 763 can also be reflected by the reflective layer and extracted from the display device.

[0582] As the material for forming a pair of electrodes of the light-emitting device, metals, alloys, conductive compounds and mixtures thereof can be appropriately used. As the material, specifically, metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium and neodymium and alloys appropriately combined therewith can be cited. In addition, as the material, indium tin oxide (also referred to as In-Sn oxide, ITO), In-Si-Sn oxide (also referred to as ITSO), indium zinc oxide (In-Zn oxide) and In-W-Zn oxide can be cited. In addition, as the material, aluminum alloys (aluminum alloys) such as aluminum, nickel and lanthanum alloys (Al-Ni-La), silver and magnesium alloys and silver, palladium and copper alloys (Ag-Pd-Cu, also referred to as APC) and other silver-containing alloys can be cited. Examples of the material include elements belonging to Group 1 or Group 2 of the periodic table that are not listed above (e.g., lithium, cesium, calcium, and strontium), rare earth metals such as europium and ytterbium, alloys of appropriately combined elements, and graphene.

[0583] The light emitting device preferably adopts an optical microcavity resonator (microcavity) structure. Therefore, one of a pair of electrodes included in the light emitting device preferably includes an electrode that is transparent and reflective to visible light (semi-transmissive-semi-reflective electrode), and the other preferably includes an electrode that is reflective to visible light (reflective electrode). When the light emitting device has a microcavity structure, the light emitted from the light emitting layer can be resonated between the two electrodes, and the light emitted from the light emitting device can be increased.

[0584] The light transmittance of the electrode having visible light transmittance is 40% or more. For example, when using an electrode having visible light transmittance for a light-emitting device, it is preferred to use an electrode having a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more. The reflectivity of the semi-transmissive-semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectivity of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. In addition, the resistivity of these electrodes is preferably 1×10 -2 Ωcm or less.

[0585] The light-emitting device includes at least a light-emitting layer. In addition, as a layer other than the light-emitting layer, the light-emitting device may also include a layer containing a substance with high hole injection property, a substance with high hole transport property, a hole blocking material, a substance with high electron transport property, an electron blocking material, a substance with high electron injection property, or a bipolar material (a substance with high electron transport property and hole transport property). For example, the light-emitting device may include one or more of a hole injection layer, a hole transport layer, a hole blocking layer, a charge generation layer, an electron blocking layer, an electron transport layer, and an electron injection layer in addition to the light-emitting layer.

[0586] The light emitting device may use a low molecular weight compound or a high molecular weight compound, and may also contain an inorganic compound. The layers constituting the light emitting device may be formed by a method such as evaporation (including vacuum evaporation), transfer, printing, inkjet, or coating.

[0587] The light-emitting layer contains one or more light-emitting substances. As the light-emitting substance, a substance that emits light in a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange or red is appropriately used. In addition, as the light-emitting substance, a substance that emits near-infrared light can also be used.

[0588] Examples of the light-emitting substance include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0589] Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, and naphthalene derivatives.

[0590] As phosphorescent materials, for example, there can be mentioned organic metal complexes (especially iridium complexes) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, a pyridine skeleton, organic metal complexes (especially iridium complexes) with phenylpyridine derivatives having electron-withdrawing groups as ligands, platinum complexes, rare earth metal complexes, and the like.

[0591] The light-emitting layer may also contain one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As one or more organic compounds, one or both of a substance with high hole transport (hole transport material) and a substance with high electron transport (electron transport material) may be used. As a hole transport material, the following materials with high hole transport that can be used for a hole transport layer may be used. As an electron transport material, the following materials with high electron transport that can be used for an electron transport layer may be used. In addition, as one or more organic compounds, a bipolar material or a TADF material may also be used.

[0592] For example, the light-emitting layer preferably includes a combination of a phosphorescent material, a hole transport material that easily forms an exciplex, and an electron transport material. By adopting such a structure, light emission by ExTET (Exciplex-Triplet Energy Transfer) utilizing energy transfer from the exciplex to the luminescent substance (phosphorescent material) can be efficiently obtained. By selecting a combination of exciplexes that form light emitting at a wavelength overlapping with the absorption band on the lowest energy side of the luminescent substance, energy transfer can be smoothed, thereby efficiently obtaining light emission. By adopting the above structure, high efficiency, low voltage drive, and long life of the light-emitting device can be achieved simultaneously.

[0593] The hole injection layer is a layer containing a material with high hole injection properties and injects holes from the anode into the hole transport layer. Examples of materials with high hole injection properties include aromatic amine compounds and composite materials containing a hole transport material and an acceptor material (electron acceptor material).

[0594] As the hole transport material, the following materials having high hole transport properties that can be used in the hole transport layer can be used.

[0595] As the acceptor material, for example, an oxide of a metal belonging to Group 4 to Group 8 of the periodic table can be used. Specifically, molybdenum oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, tungsten oxide, manganese oxide and rhenium oxide can be cited. Molybdenum oxide is particularly preferably used because it is stable in the atmosphere, has low hygroscopicity, and is easy to handle. In addition, an organic acceptor material containing fluorine can also be used. In addition to the above, organic acceptor materials such as quinone dimethane derivatives, tetrachlorobenzoquinone derivatives and hexaazatriphenylene derivatives can also be used.

[0596] For example, as the material having a high hole injecting property, a material containing a hole transport material and an oxide of the metal belonging to Group 4 to Group 8 of the periodic table (typically molybdenum oxide) can be used.

[0597] The hole transport layer is a layer that transports holes injected from the anode through the hole injection layer to the light-emitting layer. The hole transport layer is a layer containing a hole transport material. As the hole transport material, preferably a hole transport material having a hole mobility of 1×10 -6 cm 2 / Vs or more. Note that as long as the hole transport property is higher than the electron transport property, substances other than the above can be used. As hole transport materials, it is preferred to use materials with high hole transport properties such as π-electron-rich heteroaromatic compounds (such as carbazole derivatives, thiophene derivatives, furan derivatives, etc.) or aromatic amines (compounds containing aromatic amine skeletons).

[0598] The electron blocking layer is provided in contact with the light emitting layer. The electron blocking layer is a layer having hole transport properties and containing a material capable of blocking electrons. The electron blocking material among the hole transport materials can be used for the electron blocking layer.

[0599] The electron blocking layer has a hole transporting property, so it can also be called a hole transporting layer. In addition, the layer having an electron blocking property in the hole transporting layer can also be called an electron blocking layer.

[0600] The electron transport layer is a layer that transports electrons injected from the cathode through the electron injection layer to the light-emitting layer. The electron transport layer is a layer containing an electron transport material. As the electron transport material, it is preferred to use an electron transport material with an electron mobility of 1×10 -6 cm 2 / Vs or more. Note that as long as the electron transport property is higher than the hole transport property, substances other than the above can be used. As electron transport materials, metal complexes having a quinoline skeleton, metal complexes having a benzoquinoline skeleton, metal complexes having an oxazole skeleton, or metal complexes having a thiazole skeleton can be used. Materials with high electron transport properties such as oxadiazole derivatives, triazole derivatives, imidazole derivatives, oxazole derivatives, thiazole derivatives, phenanthroline derivatives, quinoline derivatives with quinoline ligands, benzoquinoline derivatives, quinoxaline derivatives, dibenzoquinoxaline derivatives, pyridine derivatives, bipyridine derivatives, pyrimidine derivatives, or nitrogen-containing heteroaromatic compounds and other π-electron-deficient heteroaromatic compounds can also be used.

[0601] The hole blocking layer is provided in contact with the light emitting layer. The hole blocking layer is a layer having electron transport properties and containing a material capable of blocking holes. The hole blocking material among the above-mentioned electron transport materials can be used for the hole blocking layer.

[0602] The hole blocking layer has an electron transporting property, so it may also be called an electron transporting layer. In addition, the layer having a hole blocking property in the electron transporting layer may also be called a hole blocking layer.

[0603] The electron injection layer is a layer containing a material with high electron injection property that injects electrons from the cathode into the electron transport layer. As a material with high electron injection property, an alkali metal, an alkaline earth metal or a compound thereof can be used. As a material with high electron injection property, a composite material containing an electron transport material and a donor material (electron donor material) can also be used.

[0604] It is preferred that the difference between the lowest unoccupied molecular orbital (LUMO) energy level of the material having high electron injectability and the work function value of the material used for the cathode be small (specifically, 0.5 eV or less).

[0605] The electron injection layer can be made of, for example, lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), calcium fluoride (CaF x , X is an arbitrary number), 8-(hydroxyquinoline) lithium (abbreviated as Liq), 2-(2-pyridyl) phenol lithium (abbreviated as LiPP), 2-(2-pyridyl)-3-hydroxypyridine (pyridinolato) lithium (abbreviated as LiPPy), 4-phenyl-2-(2-pyridyl) phenol lithium (abbreviated as LiPPP), lithium oxide (LiO x ) or alkali metals such as cesium carbonate, alkaline earth metals or their compounds. In addition, the electron injection layer can also have a stacked structure of more than two layers. As this stacked structure, for example, a structure in which lithium fluoride is used as the first layer and ytterbium is provided as the second layer can be cited.

[0606] The electron injection layer may also contain an electron transport material. For example, a compound having a non-shared electron pair and an electron-deficient heteroaromatic ring may be used as the electron transport material. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring) and a triazine ring may be used.

[0607] The LUMO energy level of an organic compound having an unshared electron pair is preferably greater than -3.6 eV and less than -2.3 eV. Generally, the highest occupied molecular orbital (HOMO) energy level and the LUMO energy level of an organic compound can be estimated using CV (cyclic voltammetry), photoelectron spectroscopy, absorption spectroscopy, or inverse photoelectron spectroscopy.

[0608] For example, 4,7-diphenyl-1,10-phenanthroline (abbreviation: BPhen), 2,9-di(naphthalene-2-yl)-4,7-diphenyl-1,10-phenanthroline (abbreviation: NBPhen), 2,2'-(1,3-phenylene)bis(9-phenyl-1,10-phenanthroline) (abbreviation: mPPhen2P), diquinoxalino[2,3-a:2',3'-c]phenazine (abbreviation: HATNA), 2,4,6-tris[3'-(pyridin-3-yl)biphenyl-3-yl]-1,3,5-triazine (abbreviation: TmPPPyTz), etc. can be used as organic compounds having non-shared electron pairs. In addition, NBPhen has a high glass transition point (Tg) compared to BPhen, thereby having high heat resistance.

[0609] As described above, the charge generation layer has at least a charge generation region. The charge generation region preferably includes an acceptor material, for example, preferably includes a hole transport material and an acceptor material that can be used in the hole injection layer.

[0610] The charge generation layer preferably includes a layer containing a material with high electron injection properties. This layer may also be referred to as an electron injection buffer layer. The electron injection buffer layer is preferably disposed between the charge generation region and the electron transport layer. By providing an electron injection buffer layer, the injection barrier between the charge generation region and the electron transport layer can be relaxed, so that the electrons generated in the charge generation region are easily injected into the electron transport layer.

[0611] The electron injection buffer layer preferably comprises an alkali metal or an alkaline earth metal, for example, a compound of an alkali metal or a compound of an alkaline earth metal. Specifically, the electron injection buffer layer preferably comprises an inorganic compound containing an alkali metal and oxygen or an inorganic compound containing an alkaline earth metal and oxygen, more preferably an inorganic compound containing lithium and oxygen (lithium oxide (Li2O) etc.). In addition, as the electron injection buffer layer, a material applicable to the above-mentioned electron injection layer is preferably used.

[0612] The charge generation layer preferably includes a layer containing a material with high electron transport properties. This layer may also be referred to as an electron relay layer. The electron relay layer is preferably disposed between the charge generation region and the electron injection buffer layer. When the charge generation layer does not include an electron injection buffer layer, the electron relay layer is preferably disposed between the charge generation region and the electron transport layer. The electron relay layer has the function of preventing the interaction between the charge generation region and the electron injection buffer layer (or electron transport layer) and smoothly transferring electrons.

[0613] As the electron relay layer, it is preferable to use a phthalocyanine material such as copper (II) phthalocyanine (abbreviation: CuPc) or a metal complex having a metal-oxygen bond and an aromatic ligand.

[0614] Note that the charge generation region, the electron injection buffer layer, and the electron relay layer may not be clearly distinguished from each other due to their cross-sectional shape, characteristics, or the like.

[0615] In addition, the charge generation layer may include a donor material instead of an acceptor material. For example, the charge generation layer may include a layer containing an electron transport material applicable to the electron injection layer and a donor material.

[0616] When stacking light-emitting units, by providing a charge generation layer between two light-emitting units, an increase in driving voltage can be suppressed.

[0617] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0618] (Implementation method 5)

[0619] In this embodiment, an example of a method for forming the light emitting element 61 is described.

[0620] Fig.44AFIG. 2 is a schematic plan view of the light emitting element 61. The light emitting element 61 includes a plurality of light emitting elements 61R that emit red light, a plurality of light emitting elements 61G that emit green light, and a plurality of light emitting elements 61B that emit blue light. Fig.44A In order to distinguish the light-emitting elements, the symbols "R", "G", and "B" are attached to the light-emitting areas of the light-emitting elements. Fig.44A Although a structure having three luminous colors of red (R), green (G), and blue (B) is shown as an example, the present invention is not limited thereto and a structure having four or more colors may be used.

[0621] The light emitting elements 61R, 61G, and 61B are arranged in a matrix. Fig.44A A so-called stripe arrangement, that is, an arrangement in which light-emitting elements of the same color are arranged in one direction, is shown, but the arrangement method of the light-emitting elements is not limited to this.

[0622] As the light emitting element 61R, the light emitting element 61G, and the light emitting element 61B, it is preferable to use an organic EL device such as OLED (Organic Light Emitting Diode) or QOLED (Quantum-dot Organic Light Emitting Diode). As the light emitting substance contained in the EL element, there can be cited substances that emit fluorescence (fluorescent materials), substances that emit phosphorescence (phosphorescent materials), substances that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), etc. As the light emitting substance contained in the EL element, in addition to organic compounds, inorganic compounds (quantum dot materials, etc.) can also be used.

[0623] Fig.44B To correspond to Fig.44A Schematic cross-sectional view of the dot-dash line A1-A2 in FIG. Fig.44B 1 shows a cross section of the light emitting element 61R, the light emitting element 61G, and the light emitting element 61B. The light emitting element 61R, the light emitting element 61G, and the light emitting element 61B are all provided on the insulator 363 and include a conductor 171 used as a pixel electrode and a conductor 173 used as a common electrode. As the insulator 363, one or both of an inorganic insulating film and an organic insulating film can be used. As the insulator 363, an inorganic insulating film is preferably used. As the inorganic insulating film, for example, oxide insulating films and nitride insulating films such as silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, aluminum oxynitride film, and hafnium oxide film can be cited.

[0624] The light-emitting element 61R includes an EL layer 172R between a conductor 171 serving as a pixel electrode and a conductor 173 serving as a common electrode. The EL layer 172R contains a light-emitting organic compound that emits light having a peak at least in a red wavelength region. The EL layer 172G in the light-emitting element 61G contains a light-emitting organic compound that emits light having a peak at least in a green wavelength region. The EL layer 172B in the light-emitting element 61B contains a light-emitting organic compound that emits light having a peak at least in a blue wavelength region.

[0625] Each of the EL layer 172R, the EL layer 172G, and the EL layer 172B may include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting substance (light-emitting layer).

[0626] Each light-emitting element is provided with a conductor 171 used as a pixel electrode. In addition, the conductor 173 used as a common electrode is a continuous layer used in common by each light-emitting element. Either the conductor 171 used as a pixel electrode or the conductor 173 used as a common electrode uses a conductive film that is translucent to visible light, and the other uses a conductive film that is reflective. By making the conductor 171 used as a pixel electrode translucent and the conductor 173 used as a common electrode reflective, a bottom emission type (bottom emission structure) display device can be manufactured. On the contrary, by making the conductor 171 used as a pixel electrode reflective and the conductor 173 used as a common electrode translucent, a top emission type (top emission structure) display device can be manufactured. Note that by making both the conductor 171 used as a pixel electrode and the conductor 173 used as a common electrode translucent, a double-sided emission type (double-sided emission structure) display device can also be manufactured.

[0627] For example, when light emitting element 61R has a top emission structure, light 175R from light emitting element 61R is emitted to the conductor 173 side. When light emitting element 61G has a top emission structure, light 175G from light emitting element 61G is emitted to the conductor 173 side. When light emitting element 61B has a top emission structure, light 175B from light emitting element 61B is emitted to the conductor 173 side.

[0628] The insulator 272 is provided so as to cover the end of the conductor 171 used as the pixel electrode. The end of the insulator 272 is preferably tapered. The insulator 272 can be made of the same material as that used for the insulator 363.

[0629] The insulator 272 is provided to prevent unintentional electrical short circuit between adjacent light emitting elements 61 and unintentional light emission from the light emitting element 61. The insulator 272 also has a function of preventing the metal mask from coming into contact with the conductor 171 when the EL layer 172 is formed using a metal mask.

[0630] Each of the EL layer 172R, the EL layer 172G, and the EL layer 172B includes a region in contact with the plane of the conductor 171 functioning as a pixel electrode and a region in contact with the surface of the insulator 272. In addition, the ends of the EL layer 172R, the EL layer 172G, and the EL layer 172B are located on the insulator 272.

[0631] like Fig.44B As shown, between the light-emitting elements with different luminous colors, a gap is provided between the two EL layers. In this way, it is preferred to provide the EL layer 172R, the EL layer 172G, and the EL layer 172B in a manner that they do not contact each other. Thus, it is possible to prevent the current from flowing through the two adjacent EL layers and generating unintentional luminescence (also called crosstalk). Therefore, the contrast can be improved and a display device with high display quality can be realized.

[0632] The EL layer 172R, the EL layer 172G, and the EL layer 172B can be separately formed by vacuum evaporation using a shielding mask such as a metal mask. Alternatively, the EL layers can be separately manufactured by photolithography. By using photolithography, a high-definition display device that is difficult to achieve when a metal mask is used can be realized. Furthermore, since the leakage current between adjacent EL layers is reduced, a display device with a very clear and high-contrast display quality can be realized.

[0633] For example, in the formation method using a metal mask, it is difficult to achieve a distance between adjacent light-emitting elements 61 of less than 10 μm, but by using a photolithography method, the distance can be reduced to less than 8 μm, less than 3 μm, less than 2 μm, or less than 1 μm. Here, the distance between adjacent light-emitting elements 61 can be specified based on the distance between the ends of two adjacent pixel electrodes. Alternatively, the distance between adjacent light-emitting elements 61 can be specified based on the distance between the ends of two adjacent EL layers.

[0634] Note that in this specification, etc., a device manufactured using a metal mask or FMM (Fine Metal Mask) is sometimes referred to as a device with an MM (Metal Mask) structure. In addition, in this specification, etc., a device manufactured without using a metal mask or FMM is sometimes referred to as a device with an MML (Metal Mask Less) structure.

[0635] By reducing the interval between adjacent light emitting elements 61 in this way, the area of ​​the non-light emitting region that may exist between two light emitting elements can be greatly reduced, and the aperture ratio can be close to 100%. For example, an aperture ratio of more than 50%, more than 60%, more than 70%, more than 80%, or even more than 90% and less than 100% can be achieved.

[0636] In addition, the pattern of the EL layer itself (also referred to as the processing size) can also be significantly reduced compared to the case of using a metal mask. In addition, for example, when the EL layer is formed separately using a metal mask, the thickness of the center and the end of the EL layer is different, so the effective area that can be used as the light-emitting area relative to the area of ​​the EL layer becomes smaller. On the other hand, in the above-mentioned manufacturing method, the EL layer is formed by processing a film deposited to a uniform thickness, so the thickness of the EL layer can be made uniform, and almost all of its area can be used as a light-emitting area even if a fine pattern is used. Therefore, the above-mentioned manufacturing method can achieve both high definition and high aperture ratio.

[0637] Most of the organic films formed by FMM are films with extremely small taper angles (for example, greater than 0 degrees and less than 30 degrees) where the thickness decreases as it approaches the end. Therefore, the side of the organic film formed by FMM is continuously connected to the plane, and it is difficult to clearly identify the side. On the other hand, the EL layer processed without FMM has a clear side. The side of the EL layer preferably has a portion with a taper angle of more than 30 degrees and less than 120 degrees, preferably a portion with a taper angle of more than 60 degrees and less than 120 degrees.

[0638] A protective layer 271 is provided on the conductor 173 used as a common electrode so as to cover the light emitting elements 61R, 61G, and 61B. The protective layer 271 has a function of preventing impurities such as water from diffusing from above to each light emitting element.

[0639] The protective layer 271 can, for example, have a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. As the inorganic insulating film, for example, oxide films or nitride films such as silicon oxide film, silicon oxynitride film, silicon nitride oxide film, silicon nitride film, aluminum oxide film, aluminum oxynitride film, and hafnium oxide film can be cited. In addition, semiconductor materials such as indium gallium oxide and indium gallium zinc oxide (IGZO) can also be used as the protective layer 271. In addition, the protective layer 271 can be formed using an ALD method, a CVD method, and a sputtering method. Note that, although a structure including an inorganic insulating film is illustrated as the protective layer 271, it is not limited thereto. For example, the protective layer 271 may also have a stacked-layer structure of an inorganic insulating film and an organic insulating film.

[0640] In this specification, nitrogen oxide refers to a compound in which the nitrogen content is greater than the oxygen content. In addition, oxynitride refers to a compound in which the oxygen content is greater than the nitrogen content. In addition, the content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS) or the like.

[0641] When the protective layer 271 is made of indium gallium zinc oxide, it can be processed by wet etching or dry etching. For example, when the protective layer 271 is made of IGZO, oxalic acid, phosphoric acid, or a mixed solution (for example, a mixed solution of phosphoric acid, acetic acid, nitric acid, and water (also called a mixed acid aluminum etching solution)) can be used. The mixed acid aluminum etching solution can be prepared in a volume ratio of phosphoric acid: acetic acid: nitric acid: water = 53.3: 6.7: 3.3: 36.7 or thereabouts.

[0642] In addition, you can also Fig.44B The structure shown is called the SBS structure.

[0643] Fig.44C An example different from the above structure is shown. Specifically, Fig.44C The light emitting element 61W that emits white light is included. The light emitting element 61W includes an EL layer 172W that emits white light between a conductor 171 that functions as a pixel electrode and a conductor 173 that functions as a common electrode.

[0644] The EL layer 172W may have a structure in which two or more light-emitting layers selected so that their respective luminescent colors are complementary to each other may be stacked. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0645] Fig.44C Three light emitting elements 61W are shown in parallel. A coloring layer 264R is provided on the upper portion of the left light emitting element 61W. The coloring layer 264R is used as a bandpass filter that allows red light to pass. Similarly, a coloring layer 264G that allows green light to pass is provided on the upper portion of the middle light emitting element 61W, and a coloring layer 264B that allows blue light to pass is provided on the upper portion of the right light emitting element 61W. Thus, the display device can display a color image.

[0646] Here, between two adjacent light-emitting elements 61W, the EL layer 172W and the conductor 173 used as a common electrode are separated from each other. Thus, it is possible to prevent the current from flowing through the EL layer 172W in the two adjacent light-emitting elements 61W and causing unintentional light emission. In particular, when a stacked EL layer with a charge generation layer provided between two light-emitting layers is used as the EL layer 172W, there is the following problem: when the definition is higher, that is, the distance between adjacent pixels is smaller, the influence of crosstalk becomes more significant, and the contrast is reduced. Therefore, by adopting this structure, a display device with both high definition and high contrast can be realized.

[0647] The EL layer 172 and the conductor 173 used as a common electrode are preferably separated by photolithography. This can reduce the gap between light-emitting elements, and can realize a display device with a high aperture ratio compared to the case of using a shadow mask such as a metal mask.

[0648] Note that in a light-emitting element having a bottom emission structure, a colored layer may be provided between the conductor 171 serving as a pixel electrode and the insulator 363 .

[0649] Fig.44D An example different from the above structure is shown. Specifically, Fig.44D In the embodiment, no insulator 272 is provided between the light emitting element 61R, the light emitting element 61G and the light emitting element 61B. By adopting this structure, a display device with a high aperture ratio can be realized. In addition, since the insulator 272 is not provided and the concavoconvexity of the light emitting element 61 is reduced, the viewing angle of the display device is improved. Specifically, the viewing angle can be set to be greater than 150 degrees and less than 180 degrees, preferably greater than 160 degrees and less than 180 degrees.

[0650] In addition, the protective layer 271 covers the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B. With this structure, impurities (typically water, etc.) that may enter from the side surfaces of the EL layer 172R, the EL layer 172G, and the EL layer 172B can be suppressed. In addition, the leakage current between adjacent light-emitting elements 61 is reduced, so the saturation and contrast are improved and the power consumption is reduced.

[0651] In addition, Fig.44D In the structure shown, the planar shapes of the conductor 171, the EL layer 172R, and the conductor 173 are substantially the same. This structure can be formed at once using a resist mask or the like after the conductor 171, the EL layer 172R, and the conductor 173 are formed. This process can also be called self-aligned patterning because the conductor 173 is used as a mask to process the EL layer 172R and the conductor 173. Note that although the EL layer 172R is described here, the EL layer 172G and the EL layer 172B can also have the same structure.

[0652] In addition, Fig.44D In the embodiment, a protective layer 273 is further provided on the protective layer 271. For example, by forming the protective layer 271 using an apparatus capable of depositing a film with high coverage (typically an ALD apparatus or the like) and forming the protective layer 273 using an apparatus capable of depositing a film with lower coverage than the protective layer 271 (typically a sputtering apparatus), a region 275 can be provided between the protective layer 271 and the protective layer 273. In other words, the region 275 is located between the EL layer 172R and the EL layer 172G and between the EL layer 172G and the EL layer 172B.

[0653] Region 275, for example, contains any one or more selected from air, nitrogen, oxygen, carbon dioxide, and Group 18 elements (typically helium, neon, argon, krypton, xenon, etc.). In addition, region 275 sometimes contains, for example, a gas used when depositing protective layer 273. For example, when protective layer 273 is deposited by sputtering, region 275 sometimes contains any one or more of the above-mentioned Group 18 elements. Note that when region 275 contains a gas, gas chromatography or the like can be used to identify the gas. Alternatively, when protective layer 273 is deposited by sputtering, the film of protective layer 273 sometimes contains the gas used when sputtering is performed. In this case, when protective layer 273 is analyzed by energy dispersive X-ray analysis (EDX analysis) or the like, elements such as argon are sometimes detected.

[0654] In addition, when the refractive index of the region 275 is lower than the refractive index of the protective layer 271, light emitted from the EL layer 172R, the EL layer 172G, or the EL layer 172B is reflected at the interface between the protective layer 271 and the region 275. As a result, it is possible to suppress the light emitted from the EL layer 172R, the EL layer 172G, or the EL layer 172B from entering an adjacent pixel. As a result, mixing of different emission colors from adjacent pixels can be suppressed, and the display quality of the display device can be improved.

[0655] In addition, in adopting Fig.44D When the structure shown is used, the area between the light-emitting element 61R and the light-emitting element 61G or the area between the light-emitting element 61G and the light-emitting element 61B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to less than 1 μm, preferably less than 500 nm, more preferably less than 200 nm, less than 100 nm, less than 90 nm, less than 70 nm, less than 50 nm, less than 30 nm, less than 20 nm, less than 15 nm or less than 10 nm. In other words, the area having the interval between the side surface of the EL layer 172R and the side surface of the EL layer 172G or the interval between the side surface of the EL layer 172G and the side surface of the EL layer 172B is less than 1 μm, preferably less than 0.5 μm (500 nm), and more preferably less than 100 nm.

[0656] In addition, for example, when the region 275 contains a gas, it is possible to suppress mixing or crosstalk of light from each light emitting element while performing element isolation between the light emitting elements.

[0657] In addition, the region 275 may be a space or may be filled with a filler. Examples of fillers include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimides, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In addition, a photoresist may be used as a filler. The photoresist used as a filler may be either a positive photoresist or a negative photoresist.

[0658] Fig.45A An example different from the above structure is shown. Specifically, Fig.45A The structure shown is Fig.44D The difference in the structure shown is the structure of the insulator 363. When processing the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, a portion of the plane of the insulator 363 is cut off and has a recess. A protective layer 271 is formed in the recess. In other words, a region where the bottom surface of the protective layer 271 is located below the bottom surface of the conductor 171 when viewed from a cross section. By having this region, impurities (typically water, etc.) that can enter the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B from below can be suppressed. In addition, the above-mentioned recess can be formed when impurities (also called residues) that can adhere to the side of each light-emitting element during the processing of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B are removed by wet etching or the like. By covering the side of each light-emitting element with the protective layer 271 after removing the above-mentioned residue, a display device with high reliability can be achieved.

[0659] in addition, Fig.45B An example different from the above structure is shown. Specifically, Fig.45B The structure shown in Fig.45AIn addition to the structure shown, an insulator 276 and a microlens array 277 are also included. The insulator 276 is used as an adhesive layer. In addition, when the refractive index of the insulator 276 is lower than the refractive index of the microlens array 277, the microlens array 277 can gather the light emitted by the light-emitting element 61R, the light-emitting element 61G and the light-emitting element 61B. As a result, the light extraction efficiency of the display device can be improved. In particular, when the user looks at the display surface from the front of the display surface of the display device, a bright image can be seen, so this is preferred. In addition, as the insulator 276, various curing adhesives such as light-curing adhesives such as ultraviolet curing adhesives, reaction curing adhesives, heat curing adhesives, and anaerobic adhesives can be used. As these adhesives, epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimides, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, EVA (ethylene-vinyl acetate) resins, etc. can be cited. In particular, it is preferred to use materials with low moisture permeability such as epoxy resins. In addition, two-liquid mixed resins can also be used. In addition, adhesive sheets can also be used.

[0660] in addition, Fig.45C An example different from the above structure is shown. Specifically, Fig.45C The structure shown includes three light emitting elements 61W instead of Fig.45A The light emitting element 61R, the light emitting element 61G, and the light emitting element 61B in the structure shown. In addition, an insulator 276 is included above the three light emitting elements 61W, and a coloring layer 264R, a coloring layer 264G, and a coloring layer 264B are included above the insulator 276. Specifically, a coloring layer 264R that transmits red light is provided at a position overlapping the light emitting element 61W on the left, a coloring layer 264G that transmits green light is provided at a position overlapping the light emitting element 61W in the center, and a coloring layer 264B that transmits blue light is provided at a position overlapping the light emitting element 61W on the right. Thus, the semiconductor device can display a color image. Fig.45C The structure shown is also Fig.44C A modified example of the structure shown.

[0661] in addition, Fig.45D An example different from the above structure is shown. Specifically, Fig.45D In the structure shown in the figure, the protective layer 271 is provided adjacent to the side surfaces of the conductor 171 and the EL layer 172. In addition, the conductor 173 is provided as a continuous layer commonly used by each light-emitting element. Fig.45D In the illustrated configuration, region 275 is preferably filled with a filler.

[0662] By making the light emitting element 61 have an optical microcavity resonator (microcavity) structure, the color purity of the luminescent color can be improved. When the light emitting element 61 has a microcavity structure, the product (optical distance) of the distance d between the conductor 171 and the conductor 173 and the refractive index ...

Claims

1. A shift register, comprising: Multiple signal output circuits, Wherein, at least one of the plurality of signal output circuits comprises a first transistor, At least one of the plurality of signal output circuits has a function of outputting a first signal through the first transistor, The shift register comprises: a first conductive layer having a region serving as one of a source electrode and a drain electrode of the first transistor; a first insulating layer having a region disposed on the first conductive layer; a second conductive layer having a region serving as the other of a source electrode and a drain electrode of the first transistor and a region disposed on the first insulating layer; A first opening penetrating the first insulating layer and the second conductive layer and overlapping the first conductive layer; a first semiconductor layer having a region in contact with the first insulating layer, a region in contact with the first conductive layer, and a region in contact with the second conductive layer; a third conductive layer having a region serving as a gate electrode of the first transistor; and a second insulating layer having a region serving as a gate insulating film of the first transistor and a region sandwiched between the first semiconductor layer and the third conductive layer in the first opening, And, the first signal is input to one of a source electrode and a drain electrode of the first transistor.

2. The shift register according to claim 1, The third conductive layer has a region overlapping with the first conductive layer in the first opening and a region overlapping with the second conductive layer on the first insulating layer.

3. The shift register according to claim 1 or 2, wherein at least one of the plurality of signal output circuits comprises a second transistor, The shift register comprises: a fourth conductive layer having a region serving as one of a source electrode and a drain electrode of the second transistor; the first insulating layer having a region disposed on the fourth conductive layer; a fifth conductive layer having a region serving as the other of a source electrode and a drain electrode of the first transistor and a region disposed on the first insulating layer; A second opening penetrating the first insulating layer and the fifth conductive layer and overlapping the fourth conductive layer; a second semiconductor layer having a region in contact with the first insulating layer, a region in contact with the fourth conductive layer, and a region in contact with the fifth conductive layer; a sixth conductive layer having a region serving as a gate electrode of the second transistor and disposed on the second insulating layer; as well as the second insulating layer having a region serving as a gate insulating film of the second transistor and a region sandwiched between the second semiconductor layer and the sixth conductive layer in the second opening, And the fourth conductive layer and the third conductive layer are electrically connected to each other.

4. The shift register according to claim 3, When the bottom surface of the fourth conductive layer is taken as a reference, the height of the top surface of the fourth conductive layer is different from the height of the bottom surface of the sixth conductive layer.

5. The shift register according to claim 1 or 2, The first semiconductor layer includes an oxide semiconductor.

6. The shift register according to claim 3, The second semiconductor layer includes an oxide semiconductor.

7. The shift register according to claim 4, The second semiconductor layer includes an oxide semiconductor.

Images