Chip packaging method and packaging structure

Abstract

The embodiment of the invention provides a chip packaging method and a chip packaging structure. The method comprises the following steps: providing a substrate, a chip, a silicon passive element and a heat dissipation cover; mounting the chip and the silicon passive element on the substrate at one time by adopting a flip chip mounting process, and performing reflow soldering; forming an underfill adhesive layer among the chip, the silicon passive element and the substrate; a heat dissipation cover is fixed to the side, away from the substrate, of the chip, and the edge area of the heat dissipation cover is fixed to the substrate; and forming a plurality of solder balls on one side, deviating from the chip, of the substrate. By adopting the silicon passive element, the reliability is enhanced, a passive element protector is not needed, the thermal resistance is reduced, the heat dissipation efficiency is improved, and the integration level and portability of the electronic equipment are improved. The flip chip mounting process is adopted to mount and fix the chip and the silicon passive element on the substrate at one time, so that the production efficiency is improved, the mounting error is reduced, the high reliability of a product is ensured, the production process is simplified, the production cost is reduced, the mounting of a passive element protector is omitted, and the mounting steps are reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a chip packaging method and packaging structure. Background Art

[0002] In the field of high-power servers, FCBGA (Flip-Chip Ball Grid Array) combined with indium sheet heat dissipation technology is widely used. Figure 1 and Figure 2 As shown, this packaging structure mainly includes a substrate 1, a bottom sealant 2, a chip 3, passive components 4 (mainly capacitors), a passive component protector 5 (protective cover or protective glue), a heat dissipation cover 6, a thermal conductive interface material 7 (such as an indium sheet) and solder balls 8. The FCBGA package uses SMT technology to realize the welding of the passive components 4 and the substrate 1. The chip 3 is soldered to the substrate 1 through FC flip-chip welding, and the circuit connection is realized by solder balls 8. At the same time, the indium sheet, as a thermal interface material (TIM) with high thermal conductivity, is cleverly placed between the chip 3 and the heat dissipation cover 6, and a reflow furnace process is used to achieve stable welding to ensure that the heat generated by the chip 3 can be quickly transferred to the heat sink.

[0003] Under the existing technology, the mounting process of passive components such as chips and capacitors is to first print solder on the substrate, then flip the chip through FC, and then connect the passive components, chips and substrate in the reflow oven. The mounting process of passive components usually adopts SMT mounting process, and the main process is as follows: use screen printing technology to evenly apply solder paste on the pads of the substrate; use high-precision mounting equipment to accurately place the capacitor components on the corresponding positions of the substrate; send the components with mounted capacitor components into the reflow oven, and through precise control of temperature and time, melt the solder paste and wet the pins of the capacitor components and the pads of the substrate to form an electrical connection, and complete the subsequent inspection and cleaning work.

[0004] However, the existing chip packaging structure with passive component protectors and the mounting of passive components such as capacitors have the following problems:

[0005] 1) Although the design of traditional capacitors and passive component protectors can prevent liquid heat dissipation materials from splashing out and causing capacitor short circuits, traditional capacitors may have reduced reliability in harsh environments due to problems such as loose protective covers and corrosion. The design of protective glue has problems such as poor adhesion strength and durability, which affects capacitor reliability, thereby reducing the reliability of the chip packaging structure;

[0006] 2) The design of traditional capacitors and passive component protectors increases the volume and weight of the overall assembly, which is not conducive to the integration and lightweight of electronic equipment.

[0007] 3) The traditional capacitor mounting process (SMT) is relatively complex, and the production of passive component protectors such as protective covers and the coating process of protective glue are complex, which increases manufacturing costs and installation time. In addition, during the mounting process of components such as capacitors, SMT technology often faces welding defects caused by uneven solder paste printing, stickiness and residue, and the "tombstone" phenomenon caused by solder pulling during reflow soldering reduces the reliability of capacitors and chip packaging structures.

[0008] In view of the above problems, it is necessary to propose a chip packaging method and a chip packaging structure that are reasonably designed and effectively solve the above problems. Summary of the invention

[0009] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a chip packaging method and a chip packaging structure.

[0010] An aspect of an embodiment of the present disclosure provides a chip packaging method, the method comprising:

[0011] Provide substrates, chips, silicon passive components and heat sink covers;

[0012] The chip and the silicon passive component are mounted on the substrate at one time by using a flip chip mounting process and then reflow soldering is performed;

[0013] forming an underfill layer between the chip, the silicon passive component and the substrate;

[0014] Fixing the heat dissipation cover to a side of the chip facing away from the substrate, and fixing an edge area of ​​the heat dissipation cover to the substrate;

[0015] A plurality of solder balls are formed on a side of the substrate facing away from the chip.

[0016] Optionally, the method of mounting the chip and the silicon passive component on the substrate at one time using a flip chip mounting process includes:

[0017] forming a plurality of chip bumps on a side of the chip facing the substrate;

[0018] forming a plurality of connection bumps on a side of the silicon passive component facing the substrate;

[0019] A high-precision mounting machine is used to accurately absorb the chip and the silicon passive component in sequence, and mount them on corresponding positions of the substrate through the chip bumps and the connection bumps.

[0020] Optionally, the distance between the chip and the silicon passive component after mounting is less than 3 mm.

[0021] Optionally, forming an underfill layer between the chip, the silicon passive component and the substrate includes:

[0022] The gaps between the chip, the silicon passive element and the substrate are filled with an underfill material at one time to form the underfill glue layer.

[0023] Optionally, the silicon passive component includes a silicon capacitor, a silicon inductor or a silicon resistor.

[0024] Another aspect of the disclosed embodiment provides a chip packaging structure, including a substrate, a chip, a silicon passive component, an underfill layer, a heat dissipation cover, and a plurality of solder balls;

[0025] The chip is flip-chip mounted in the central area of ​​the substrate, and the silicon passive component is flip-chip mounted in the edge area of ​​the substrate;

[0026] The bottom filling layer is arranged between the chip, the silicon passive component and the substrate;

[0027] The heat dissipation cover is disposed on a side of the chip away from the substrate, and an edge area of ​​the heat dissipation cover is fixed to the substrate;

[0028] The plurality of solder balls are arranged on a side of the substrate away from the chip.

[0029] Optionally, a side of the chip facing the substrate is provided with a plurality of chip bumps, and a side of the silicon passive component facing the substrate is provided with a plurality of connection bumps;

[0030] The chip and the silicon passive component are flip-chip mounted on the substrate through the chip bumps and the connection bumps respectively.

[0031] Optionally, the distance between the chip and the silicon passive component is less than 3 mm.

[0032] Optionally, the bottom filling layer is made of bottom filling material.

[0033] Optionally, the silicon passive component includes a silicon capacitor, a silicon inductor or a silicon resistor.

[0034] The chip packaging method and chip packaging structure of the disclosed embodiment adopt silicon passive components with excellent temperature resistance, moisture resistance, corrosion resistance and other characteristics, which improves the stability and reliability of silicon passive components in harsh environments, and can ensure long-term stable operation without the need for additional protective covers. At the same time, the high stability and corrosion resistance of the silicon passive components themselves also reduce the need for external protection, so that the passive component protector can be omitted, further reducing thermal resistance and improving heat dissipation efficiency. With its small size and light and thin characteristics, silicon passive components can significantly reduce the occupied space, reduce the overall weight, and improve the integration and portability of electronic devices. The flip chip mounting process is used to mount and fix the chip and silicon passive components to the substrate at one time, which not only greatly improves the production efficiency, but also significantly reduces the mounting error, ensures the high reliability of the product, simplifies the production process, and reduces the production cost. At the same time, the mounting of the passive component protector is omitted, and the installation steps are also reduced, further improving the production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a flip chip packaging structure according to an embodiment of the prior art;

[0036] Figure 2 It is a structural schematic diagram of a flip chip packaging structure of another embodiment in the prior art;

[0037] Figure 3 A schematic diagram of a chip packaging method according to an embodiment of the present disclosure;

[0038] Figures 4 to 8 A schematic diagram of a chip packaging method according to another embodiment of the present disclosure;

[0039] Fig. 9 It is a structural schematic diagram of a chip packaging structure of another embodiment of the present disclosure. DETAILED DESCRIPTION

[0040] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0041] In the existing flip chip packaging method, in order to prevent the liquid indium from causing potential damage due to high temperature fluidity during the reflow process, especially for passive components such as peripheral sensitive capacitors, it is necessary to add a protective cover or apply protective glue. Although this is expected to protect the passive components from damage, it also significantly increases the complexity of the packaging process. It not only requires precise installation and positioning, but may also slow down the production pace and increase manufacturing costs. Secondly, the introduction of passive component protectors may also bring new reliability risks, such as loosening, shedding and corrosion caused by material compatibility, improper process control or environmental factors, which may threaten the overall stability and service life of the system.

[0042] In view of the above problems existing in the prior art, Figure 3 As shown, one aspect of an embodiment of the present disclosure provides a chip packaging method S100, the method S100 comprising:

[0043] S110, provide substrate, chip, silicon passive components and heat dissipation cover.

[0044] Specifically, Figures 4 to 8 As shown, a substrate 110 , a chip 120 , a silicon passive component 130 and a heat dissipation cover 140 are provided.

[0045] For example, the silicon passive component 130 may include a silicon capacitor, a silicon inductor, a silicon resistor, etc. In this embodiment, the silicon passive component 130 is described as a silicon capacitor.

[0046] In this embodiment, silicon passive components with excellent temperature resistance, moisture resistance, corrosion resistance and other characteristics are used to improve the stability and reliability of silicon passive components in harsh environments, and long-term stable operation can be ensured without additional protective covers. At the same time, the high stability and corrosion resistance of silicon passive components themselves also reduce the need for external protection, so that passive component protectors can be omitted, further reducing thermal resistance and improving heat dissipation efficiency. Silicon passive components, with their small size and light and thin characteristics, can significantly reduce the occupied space, reduce the overall weight, and improve the integration and portability of electronic equipment.

[0047] S120, using a flip chip mounting process to mount the chip and the silicon passive component on the substrate at one time and perform reflow soldering.

[0048] Wherein, step S120 may specifically include the following steps:

[0049] First, if Figure 4 As shown, a plurality of chip bumps 121 are formed on the side of the chip 120 facing the substrate 110. The chip bumps 121 may be copper bumps.

[0050] Secondly, if Figure 4As shown, a plurality of connection bumps 131 are formed on the side of the silicon passive component 130 facing the substrate 110 through a precision machining process to achieve efficient connection with the substrate 110. The connection bumps 131 may also be copper bumps.

[0051] Then, if Figure 5 As shown, a high-precision placement machine is used to accurately absorb the chip 120 and the silicon passive component 130 in sequence, and mount them on corresponding positions of the substrate 110 through the chip bumps 121 and the connection bumps 131 .

[0052] Finally, the mounted substrate 110, chip 120 and silicon passive component 130 are placed in a reflow oven for reflow soldering to ensure a firm solder connection between the chip 120 and the substrate 120 and between the silicon passive component 130 and the substrate 110. The substrate 110, chip 120 and silicon passive component 130 that have completed reflow soldering are plasma cleaned.

[0053] In this embodiment, the flip chip mounting process is used to mount the chip and the silicon passive component on the substrate at one time, which not only greatly improves the production efficiency, but also significantly reduces the mounting error, ensuring the high reliability of the product. In addition, it is no longer necessary to mount the silicon passive component through SMT technology, which simplifies the production process and reduces the production cost. At the same time, the installation of the passive component protector is omitted, which also reduces the installation steps and improves the production efficiency.

[0054] Exemplarily, the distance between the chip 120 and the silicon passive component 130 after mounting is less than 3 mm.

[0055] Specifically, under the existing SMT process conditions, the passive component needs to maintain a distance of at least 3mm from the chip. By using silicon passive components and using the chip flipping process to mount the silicon passive components on the substrate, the silicon passive components can be as close to the chip as possible, so that the distance between the silicon passive component 130 and the chip 120 can be less than 3mm, and the silicon passive component 130 and the chip 120 can achieve a shorter communication time.

[0056] S130, forming an underfill layer between the chip, the silicon passive component and the substrate.

[0057] Specifically, Figure 6 As shown, the gaps between the chip 120 , the silicon passive component 130 and the substrate 110 are filled with an underfill material at one time, and then baked and cured to form an underfill layer 150 .

[0058] In this embodiment, the bottom filling material has good fluidity, adhesion and thermal stability, and can fill the tiny gaps between the chip, silicon passive components and the substrate at one time, effectively reducing the thermal resistance problem caused by the air gap and enhancing the overall heat dissipation performance. At the same time, the curing effect of the bottom filling material further strengthens the connection between the chip, silicon passive components and the substrate, reduces the mechanical stress caused by vibration or temperature changes, and improves the long-term stability and reliability of the product. In addition, the chip, silicon passive components and the substrate are directly cured as a whole through the bottom filling material, which avoids the problem of capacitor failure of traditional passive components due to the inflow of bottom filling materials or adhesives, and shortens the distance between the silicon passive components and the chip, thereby improving the electrical transmission efficiency between the two.

[0059] S140, fixing the heat dissipation cover to a side of the chip facing away from the substrate, and fixing an edge area of ​​the heat dissipation cover to the substrate.

[0060] Specifically, Figure 7 As shown, the chip 120 is welded and fixed to the heat dissipation cover 140 at the side facing away from the substrate 110 by using a thermal interface material layer. Adhesive is dispensed at the edge region of the substrate 110 to form an adhesive layer 160 at the edge region of the substrate 110. The edge region of the heat dissipation cover 140 is fixed to the edge region of the substrate 110 by the adhesive layer 160, thereby completing the mounting of the heat dissipation cover 140.

[0061] S150, forming a plurality of solder balls on a side of the substrate away from the chip.

[0062] Specifically, Figure 8 As shown, a plurality of solder balls 170 are formed on a side of the substrate 110 facing away from the chip 120 , and signals of the entire chip packaging structure are led out through the solder balls 170 .

[0063] The chip packaging method of the disclosed embodiment adopts silicon passive components with excellent temperature resistance, moisture resistance, corrosion resistance and other characteristics, which improves the stability and reliability of silicon passive components in harsh environments, and can ensure long-term stable operation without the need for additional protective covers. At the same time, the high stability and corrosion resistance of the silicon passive components themselves also reduce the need for external protection, so that the passive component protector can be omitted, further reducing thermal resistance and improving heat dissipation efficiency. With its small size and light and thin characteristics, silicon passive components can significantly reduce the occupied space, reduce the overall weight, and improve the integration and portability of electronic devices. The flip-chip mounting process is used to mount and fix the chip and silicon passive components to the substrate at one time, which not only greatly improves the production efficiency, but also significantly reduces the mounting error, ensures the high reliability of the product, simplifies the production process, and reduces the production cost. At the same time, the mounting of the passive component protector is omitted, and the installation steps are also reduced, further improving the production efficiency.

[0064] like Fig. 9 As shown, another aspect of the embodiment of the present disclosure provides a chip package structure 100 , including a substrate 110 , a chip 120 , a silicon passive component 130 , an underfill layer 150 , a heat dissipation cover 140 and a plurality of solder balls 170 .

[0065] The chip 120 is flip-chip mounted on the central region of the substrate 110 , and the silicon passive component 130 is flip-chip mounted on the edge region of the substrate 110 .

[0066] The underfill layer 150 is disposed between the chip 120 , the silicon passive component 130 and the substrate 110 to further fix the chip 120 and the substrate 110 as well as the silicon passive component 130 and the substrate 110 .

[0067] The heat dissipation cover 140 is disposed on the side of the chip 120 away from the substrate 110, and the edge area of ​​the heat dissipation cover 140 is fixed to the substrate 110 through the adhesive layer 160. The heat generated by the chip 120 is quickly transferred to the heat sink through the heat dissipation cover 140.

[0068] A plurality of solder balls 170 are disposed on a side of the substrate 110 away from the chip 120. The signals of the entire chip package structure are led out through the plurality of solder balls 170.

[0069] The chip packaging structure of the disclosed embodiment adopts silicon passive components with excellent temperature resistance, moisture resistance, corrosion resistance and other characteristics, which improves the stability and reliability of silicon passive components in harsh environments and ensures long-term stable operation without the need for additional protective covers. At the same time, the high stability and corrosion resistance of the silicon passive components themselves also reduce the need for external protection, so that the passive component protector can be omitted, further reducing thermal resistance and improving heat dissipation efficiency. With its small size and light and thin characteristics, silicon passive components can significantly reduce the occupied space, reduce the overall weight, and improve the integration and portability of electronic equipment. The excellent performance of silicon passive components also helps to reduce the energy consumption and maintenance costs of the entire chip packaging structure.

[0070] For example, Fig. 9 As shown, a plurality of chip bumps 121 are disposed on the side of the chip 120 facing the substrate 110, and a plurality of connection bumps 131 are disposed on the side of the silicon passive component 130 facing the substrate 110. The chip 120 and the silicon passive component 130 are flip-chip mounted on the substrate 110 via the chip bumps 121 and the connection bumps 131, respectively.

[0071] For example, the distance between the chip 120 and the silicon passive component 130 is less than 3 mm, so that the communication time between the silicon passive component 130 and the chip 120 can be shortened, thereby improving the electrical transmission efficiency between the two.

[0072] Exemplarily, the material of the bottom fill glue layer 150 can be a bottom fill material. Among them, the bottom fill material has good fluidity, adhesion and thermal stability, and can fill the tiny gaps between the silicon passive components, chips and substrates at one time, effectively reducing the thermal resistance problem caused by the air gap and enhancing the overall heat dissipation performance. At the same time, the curing effect of the bottom fill material further strengthens the connection between the silicon passive components, chips and substrates, reduces the mechanical stress caused by vibration or temperature changes, and improves the long-term stability and reliability of the product.

[0073] Illustratively, in this embodiment, the silicon passive component 130 may include a silicon capacitor, a silicon inductor, or a silicon resistor, etc., and the corresponding passive component may be selected according to actual needs.

[0074] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.

Claims

1. A chip packaging method, characterized in that: The method comprises: Provide substrates, chips, silicon passive components and heat sink covers; The chip and the silicon passive component are mounted on the substrate at one time by using a flip chip mounting process and then reflow soldering is performed; forming an underfill layer between the chip, the silicon passive component and the substrate; Fixing the heat dissipation cover to a side of the chip facing away from the substrate, and fixing an edge area of ​​the heat dissipation cover to the substrate; A plurality of solder balls are formed on a side of the substrate facing away from the chip.

2. The method according to claim 1, characterized in that The method of mounting the chip and the silicon passive component on the substrate at one time by using a flip chip mounting process comprises: forming a plurality of chip bumps on a side of the chip facing the substrate; forming a plurality of connection bumps on a side of the silicon passive component facing the substrate; A high-precision mounting machine is used to accurately absorb the chip and the silicon passive component in sequence, and mount them on corresponding positions of the substrate through the chip bumps and the connection bumps.

3. The method according to claim 1, characterized in that The distance between the chip and the silicon passive component after mounting is less than 3 mm.

4. The method according to claim 1, characterized in that: The step of forming an underfill layer between the chip, the silicon passive component and the substrate comprises: The gaps between the chip, the silicon passive element and the substrate are filled with an underfill material at one time to form the underfill glue layer.

5. The method according to any one of claims 1 to 4, characterized in that: The silicon passive component includes a silicon capacitor, a silicon inductor or a silicon resistor.

6. A chip packaging structure, characterized in that: It includes a substrate, a chip, a silicon passive component, an underfill layer, a heat dissipation cover and a plurality of solder balls; The chip is flip-chip mounted in the central area of ​​the substrate, and the silicon passive component is flip-chip mounted in the edge area of ​​the substrate; The bottom filling layer is arranged between the chip, the silicon passive component and the substrate; The heat dissipation cover is disposed on a side of the chip away from the substrate, and an edge area of ​​the heat dissipation cover is fixed to the substrate; The plurality of solder balls are arranged on a side of the substrate away from the chip.

7. The structure according to claim 6, characterized in that A plurality of chip bumps are arranged on a side of the chip facing the substrate, and a plurality of connection bumps are arranged on a side of the silicon passive component facing the substrate; The chip and the silicon passive component are flip-chip mounted on the substrate through the chip bumps and the connection bumps respectively.

8. The structure according to claim 6, characterized in that The distance between the chip and the silicon passive component is less than 3 mm.

9. The structure according to any one of claims 6 to 8, characterized in that: The material of the bottom filling glue layer is bottom filling material.

10. The structure according to any one of claims 6 to 8, characterized in that: The silicon passive component includes a silicon capacitor, a silicon inductor or a silicon resistor.

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