Packaging method and packaging structure of filter module

Abstract

The invention discloses a packaging method and a packaging structure of a filter module, and the packaging structure of the filter module comprises a substrate which is provided with at least two filter parts; each filter component comprises a functional area located in the center and a non-functional area surrounding the functional area; the wall structure is located on the non-functional area and surrounds all the functional areas; the two ends of the covering layer are located on the wall body structure, and a cavity is formed among the covering layer, the wall body structure and the filter component; the buffer layer is located on the covering layer and at least corresponds to the cavity; the dielectric layer covers the covering layer and the buffer layer; the rewiring layer is positioned in the dielectric layer, the covering layer and the wall body structure and is electrically connected with the filter component; and the solder ball is electrically connected with the rewiring layer. According to the invention, the integration level is improved and the usable area is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging method and packaging structure of a filter module. Background Art

[0002] A RF module is a module chip that contains two or more devices such as low-noise amplifiers, switches, filters and amplifiers. Due to its advantages such as high integration and high performance, it has been widely used in mobile terminals such as mobile phones and wearable devices.

[0003] As terminal devices become smaller and smaller in space, RF front-end modules are required to have higher integration and smaller usage area.

[0004] In the related art, each filter component is packaged separately, so that there is a large distance between the filter components in the RF front-end module, resulting in a larger area of ​​the RF front-end module. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, the present application provides a packaging structure of a filter module, wherein the packaging structure of the filter module comprises:

[0007] A substrate, on which at least two filter components are formed; each of the filter components comprises a functional area located at the center and a non-functional area surrounding the functional area;

[0008] A wall structure, located on the non-functional area and surrounding the entire functional area;

[0009] a covering layer, wherein two ends of the covering layer are located on the wall structure, and a cavity is formed between the covering layer, the wall structure and the filter component;

[0010] a buffer layer, located on the cover layer and at least corresponding to the cavity;

[0011] a dielectric layer, covering the cover layer and the buffer layer;

[0012] a redistribution layer, located in the dielectric layer, the cover layer and the wall structure and electrically connected to the filter component;

[0013] The solder ball is electrically connected to the redistribution layer.

[0014] In some embodiments of the present application, it also includes:

[0015] A release hole is located in the cover layer, and the buffer layer covers the release hole.

[0016] In some embodiments of the present application, it also includes:

[0017] An opening is located in the dielectric layer and exposes a portion of the redistribution layer, and the solder ball is formed in the opening.

[0018] In some embodiments of the present application, it also includes:

[0019] A pad is located in the opening and is electrically connected to the redistribution layer.

[0020] In some embodiments of the present application, it also includes:

[0021] A passivation layer is located on the dielectric layer, and the passivation layer covers the edge area of ​​the pad and exposes the middle area of ​​the pad.

[0022] In another aspect, the present application provides a packaging method for a filter module, the packaging method comprising:

[0023] Providing a substrate on which at least two filter components are formed; each of the filter components comprises a functional area located at the center and a non-functional area surrounding the functional area;

[0024] Forming a wall structure surrounding all the functional areas on the non-functional areas;

[0025] Filling the wall structure with a sacrificial layer;

[0026] forming a covering layer on the surface of the wall structure and the sacrificial layer;

[0027] forming a release hole in the cover layer to expose the sacrificial layer;

[0028] removing the sacrificial layer through the release hole to form a cavity;

[0029] forming a buffer layer at least on a region of the cover layer corresponding to the cavity, wherein the buffer layer covers all of the release holes;

[0030] forming a dielectric layer covering the cover layer and the buffer layer;

[0031] forming a redistribution layer electrically connected to the filter component in the dielectric layer, the cover layer and the wall structure;

[0032] Solder balls are formed to be electrically connected to the redistribution layer.

[0033] In some embodiments of the present application, forming a solder ball electrically connected to the redistribution layer includes:

[0034] An opening is formed in the dielectric layer to expose a portion of the redistribution layer, and the solder ball electrically connected to the redistribution layer is formed in the opening.

[0035] In some embodiments of the present application, before forming the solder ball electrically connected to the redistribution layer in the opening, the step of forming a solder pad electrically connected to the redistribution layer in the opening is also included.

[0036] In some embodiments of the present application, after forming the pad, a step of forming a passivation layer on the dielectric layer is further included, wherein the passivation layer covers an edge region of the pad and exposes a middle region of the pad.

[0037] In some embodiments of the present application, the capping layer includes a silicon nitride layer formed by PECVD.

[0038] The packaging method and packaging structure of the filter module of the present application reduce the spacing between filter components in the packaging structure by packaging at least two filter components together, thereby improving integration and reducing the usage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The following drawings of the present application are used as a part of the present application for understanding the present application. The drawings show the embodiments of the present application and their descriptions, which are used to explain the principle of the present application.

[0040] In the attached figure:

[0041] Figure 1 A flow chart showing a method for packaging a filter module according to a specific embodiment of the present application is shown;

[0042] Figures 2A-2J A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a packaging method for a filter module according to a specific embodiment of the present application is shown.

[0043] Figure 3 A top view of the packaging structure of a filter module according to a specific embodiment of the present application is shown. DETAILED DESCRIPTION

[0044] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is apparent to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described.

[0045] It should be understood that the present application can be implemented in different forms and should not be construed as being limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present application to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0046] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present application, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0047] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0048] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0049] In order to thoroughly understand the present application, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present application. The preferred embodiments of the present application are described in detail below, but in addition to these detailed descriptions, the present application may also have other implementation methods.

[0050] In the related art, each filter component is packaged separately, so that there is a large distance between the filter components in the RF front-end module, resulting in a larger area of ​​the RF front-end module.

[0051] Therefore, in view of the existence of the aforementioned technical problems, the present application proposes a packaging structure of a filter module, comprising:

[0052] A substrate, on which at least two filter components are formed; each of the filter components comprises a functional area located at the center and a non-functional area surrounding the functional area;

[0053] A wall structure, located on the non-functional area and surrounding the entire functional area;

[0054] a covering layer, wherein two ends of the covering layer are located on the wall structure, and a cavity is formed between the covering layer, the wall structure and the filter component;

[0055] a buffer layer, located on the cover layer and at least corresponding to the cavity;

[0056] a dielectric layer, covering the cover layer and the buffer layer;

[0057] a redistribution layer, located in the dielectric layer, the cover layer and the wall structure and electrically connected to the filter component;

[0058] The solder ball is electrically connected to the redistribution layer.

[0059] In the embodiment of the present application, by packaging at least two filter components together, the distance between the filter components in the packaging structure is reduced, the integration is improved and the usage area is reduced.

[0060] Embodiment 1

[0061] The following refers to Figure 2J and Figure 3 to describe the packaging structure of a filter module according to an embodiment of the present application. The packaging structure of the filter module includes: a substrate 210, on which at least two filter components 220 are formed; each filter component 220 includes a functional area 221 located at the center and a non-functional area 222 surrounding the functional area; a wall structure 230, located on the non-functional area 222 and surrounding all the functional areas 221; a cover layer 250, both ends of the cover layer 250 are located on the wall structure 230, and a cavity 260 is formed between the cover layer 250, the wall structure 230 and the filter component 220; a release hole 251, located in the cover layer 250; a buffer layer 270, located on the cover layer 250 and at least corresponding to the cavity 260; the buffer layer 270 covers all the release holes 251; a dielectric layer 280, covering the cover layer 250 and the buffer layer 270; a redistribution layer 291, located in the dielectric layer 280, the cover layer 250 and the wall structure 230 and electrically connected to the filter component 220; a solder ball 293, electrically connected to the redistribution layer 291.

[0062] Exemplarily, the substrate 210 can be any suitable semiconductor substrate, such as a silicon substrate, which can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductor materials, etc., or is silicon-on-insulator (SOI), silicon-on-insulator stacked silicon (SSOI), silicon-germanium-on-insulator stacked silicon (S-SiGeOI), germanium-silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or can also be a double-sided polished wafer (DSP), and can also be a ceramic substrate 210 such as alumina, quartz or glass substrate, etc.

[0063] It can be understood that any suitable method can be adopted to form the filter component 220 on the substrate 210.

[0064] In one example, the at least two filter components 220 formed on the substrate 210 can be arranged regularly or irregularly, and no limitation is imposed thereon. Exemplarily, as Figure 3 shown, four filter components 220 arranged in a "field" shape can be formed on the substrate 210.

[0065] In one example, the wall structure 230 is formed on the non-functional area 222 and surrounds all the functional areas 221. Exemplarily, various deposition methods commonly used in the art can be used to form the wall structure 230, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). Exemplarily, the material of the wall structure 230 can be polyimide (PI) glue, etc., which is not limited in this application. Exemplarily, after forming the wall structure 230, it also includes: flattening the wall structure 230, and the wall structure 230 after flattening is higher than the height of the functional area on the filter component 220. Exemplarily, non-limiting examples of the flattening method include a mechanical flattening method or a chemical mechanical polishing flattening method.

[0066] In one example, the covering layer 250 may be formed as follows:

[0067] First, if Figure 2C As shown, the wall structure 230 is filled with a sacrificial layer 240 .

[0068] Specifically, after forming a wall structure 230 surrounding all functional areas 221 on the non-functional area 222, a groove is formed between the wall structure 230 and the filter component 220. Afterwards, the sacrificial layer 240 can be filled in the groove. Exemplarily, the material of the sacrificial layer 240 can be photoresist, etc., which is not limited in this application. Exemplarily, a photoresist solution can be dripped in the groove, and then the substrate 210 is rotated at high speed. Under the action of centrifugal force, the photoresist solution will diffuse to the edge of the groove and also fill the groove. By adjusting parameters such as the rotation speed and the amount of photoresist solution added, the thickness and filling effect of the sacrificial layer 240 can be controlled.

[0069] Afterwards, if Figure 2D As shown, a covering layer 250 is formed on the surface of the wall structure 230 and the sacrificial layer 240 .

[0070] For example, the covering layer 250 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD). For example, the covering layer 250 may be made of silicon nitride, etc., which is not limited in the present application. For example, after forming the covering layer 250, the covering layer 250 is further included: performing a planarization process on the covering layer 250. For example, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0071] In some embodiments, the covering layer 250 is formed on the surface of the wall structure 230 and the sacrificial layer 240 by using plasma enhanced chemical vapor deposition, and the roof process can be eliminated, so that the height of the cavity 260 formed subsequently is reduced to less than 10 um.

[0072] In one example, in order to form the cavity 260 between the cover layer 250, the wall structure 230 and the filter component 220, the following steps may be performed:

[0073] First, if Figure 2E As shown, a release hole 251 exposing the sacrificial layer 240 is formed in the cover layer 250 .

[0074] Exemplarily, a photolithography process or the like may be used to form a release hole 251 exposing the sacrificial layer 240 in the cover layer 250. Specifically, a photoresist mask layer may be formed on the cover layer 250, and the photoresist mask layer may be patterned through processes such as exposure and development to form a patterned mask layer for defining the release hole 251 to be formed; then, the cover layer 250 may be etched with the patterned mask layer to form a release hole 251 exposing the sacrificial layer 240 in the cover layer 250.

[0075] Among them, one or more release holes 251 exposing the sacrificial layer 240 may be formed in the cover layer 250 , and the number of the release holes 251 is set according to actual conditions and is not limited thereto.

[0076] Afterwards, if Figure 2F As shown, the sacrificial layer 240 is removed through the release hole 251 to form a cavity 260 .

[0077] For example, a wet process or a dry process may be used to remove the sacrificial layer 240 filled in the wall structure 230, so as to form a cavity 260 between the filter component 220, the wall structure 230 and the cover layer 250. For example, if the sacrificial layer 240 filled in the wall structure 230 is made of photoresist and a dry process is used to remove the photoresist filled in the wall structure 230, the photoresist may be oxidized in an oxygen atom environment to generate CO, CO2, H2O and other volatile oxides, and the generated CO, CO2, H2O and other volatile oxides are discharged from the release hole 251, thereby removing the sacrificial layer 240.

[0078] In one example, the release hole 251 is located in the cover layer 250, and the buffer layer 270 covers the release hole 251. For example, the buffer layer 270 formed is located above the central area of ​​the cover layer 250 and corresponds to the cavity 260. The buffer layer 270 covers all the release holes 251, and the buffer layer 270 plays a buffering role between the lower cover layer 250 and the upper dielectric layer 280 grown subsequently. For example, the buffer layer 270 can be formed by various deposition methods commonly used in the art, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). For example, the buffer layer 270 can be a benzocyclobutene (BCB) film, etc., which is not limited in this application. For example, after the buffer layer 270 is formed, it also includes: flattening the buffer layer 270. For example, non-limiting examples of the flattening method include a mechanical flattening method or a chemical mechanical polishing flattening method.

[0079] Exemplarily, the dielectric layer 280 may be formed by various deposition methods commonly used in the art, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer 280 may be silicon dioxide, etc., which is not limited in the present application. Exemplarily, after forming the dielectric layer 280, the process further includes: performing a planarization process on the dielectric layer 280. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0080] Exemplarily, various methods commonly used in the art may be used to form the redistribution layer 291, for example, it may be formed by a multi-through hole structure method, a support structure method, or a build-up layer method. In a specific embodiment, a multi-through hole structure is formed in the dielectric layer 280, the cover layer 250, and the wall structure 230 by photolithography and etching processes, and then a conductive material such as copper or aluminum is deposited, and metal lines, i.e., the redistribution layer 291, are formed by photolithography and etching processes. Taking the deposition of copper in the multi-through hole structure as an example, physical vapor deposition (PVD), Cu-Damascene deposition, or any other suitable deposition method may be used.

[0081] In this embodiment, the I / O interfaces of at least two filter components 220 can be interconnected and re-integrated through the redistribution layer 291, thereby reducing the number of I / O interfaces and reducing the complexity of subsequent packaging processes. In addition, the use of the redistribution layer 291 can save the area of ​​the pad (PAD) on a single filter component 220 and improve the integration.

[0082] In one example, if Fig.2I and Figure 2JAs shown, the structure further includes: an opening 292 located in the dielectric layer 280 and exposing a portion of the redistribution layer 291 , and a solder ball 293 is formed in the opening 292 .

[0083] Specifically, an opening 292 exposing a portion of the redistribution layer 291 may be formed in the dielectric layer 280 , and then a solder ball 293 electrically connected to the redistribution layer 291 may be formed in the opening 292 .

[0084] Exemplarily, a screen printing / electroplating process can be used to form solder balls 293 electrically connected to the redistribution layer 291. Taking screen printing ball planting as an example, it is a method of accurately placing solder ball 293 material (usually tin balls or tin-containing alloy balls) at a specific position through a screen template. The screen template is a screen with a specific pattern, and the openings in the pattern correspond to the positions where the balls need to be planted, that is, the openings 292 of the redistribution layer 291 exposed on the second dielectric layer 280. The solder ball paste (composed of solder ball powder and flux, etc.) is squeezed through a scraper to pass through the opening of the screen and deposited on the opening 292. After printing is completed, a drying process is performed to remove the solvent components in the solder ball paste and solidify the solder ball paste, thereby forming a solder ball 293 electrically connected to the redistribution layer 291.

[0085] In one example, it further includes: a pad located in the opening 292 and electrically connected to the redistribution layer 291. The solder ball 293 is electrically connected to the redistribution layer 291 through the pad.

[0086] In one example, it further includes: a passivation layer, located on the dielectric layer 280, the passivation layer covers the edge area of ​​the pad and exposes the middle area of ​​the pad. The passivation layer can prevent corrosion from environmental moisture. Exemplarily, the material of the passivation layer can be polyimide glue, etc., which is not limited in this application.

[0087] This completes the introduction to the structure of the semiconductor device of the present application. The complete device may also include other component structures, which will not be described in detail here.

[0088] In summary, the packaging structure of the filter module of the embodiment of the present application reduces the distance between the filter components in the packaging structure by packaging at least two filter components together, thereby improving the integration and reducing the usage area.

[0089] Embodiment 2

[0090] On the other hand, the present application provides a method for packaging a filter module, such as Figure 1 As shown, it mainly includes the following steps:

[0091] Step S1, providing a substrate, on which at least two filter components are formed; each of the filter components comprises a functional area located in the center and a non-functional area surrounding the functional area;

[0092] Step S2, forming a wall structure surrounding all the functional areas on the non-functional areas;

[0093] Step S3, filling the wall structure with a sacrificial layer;

[0094] Step S4, forming a covering layer on the surface of the wall structure and the sacrificial layer;

[0095] Step S5, forming a release hole in the cover layer to expose the sacrificial layer;

[0096] Step S6, removing the sacrificial layer through the release hole to form a cavity;

[0097] Step S7, forming a buffer layer at least on a region of the cover layer corresponding to the cavity, wherein the buffer layer covers all the release holes;

[0098] Step S8, forming a dielectric layer covering the cover layer and the buffer layer;

[0099] Step S9, forming a redistribution layer electrically connected to the filter component in the dielectric layer, the cover layer and the wall structure;

[0100] Step S10, forming solder balls electrically connected to the redistribution layer.

[0101] In the embodiment of the present application, by packaging at least two filter components together, the distance between the filter components in the packaging structure is reduced, the integration is improved and the usage area is reduced.

[0102] Below, reference FIG. 2A to FIG. 2J , Figure 3 The packaging method of the filter module of the present application is described in detail, wherein: Figures 2A-2J A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a packaging method for a filter module according to a specific embodiment of the present application is shown, Figure 3 A top view of the packaging structure of a filter module according to a specific embodiment of the present application is shown.

[0103] Exemplarily, the packaging method of the filter module of the present application comprises the following steps:

[0104] First, execute step S1, such as Figure 2AAs shown, a substrate 210 is provided, on which at least two filter components 220 are formed; each filter component 220 includes a functional area 221 at the center and a non-functional area 222 surrounding the functional area 221.

[0105] Exemplarily, the substrate 210 can be any suitable semiconductor substrate, such as a silicon substrate, which can also be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III / V compound semiconductors, and also includes multi-layer structures composed of these semiconductor materials, etc., or is silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI) and germanium-on-insulator (GeOI), or can also be double-sided polished wafers (DSP), and can also be a ceramic substrate 210 such as alumina, quartz or glass substrate, etc.

[0106] It can be understood that any suitable method can be adopted to form the filter component 220 on the substrate 210.

[0107] In one example, the at least two filter components 220 formed on the substrate 210 can be arranged regularly or irregularly, and this is not limited. Exemplarily, as Figure 3 shown, four filter components 220 arranged in a "field" shape can be formed on the substrate 210.

[0108] Next, step S2 is executed. As Figure 2B shown, a wall structure 230 surrounding all the functional areas 221 is formed on the non-functional area 222.

[0109] Specifically, the wall structure 230 is formed on the non-functional area 222 and surrounds all the functional areas 221. Exemplarily, various deposition methods commonly used in the art can be adopted to form the wall structure 230, for example, it can be formed by chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method or atomic layer deposition (ALD) method, etc. Exemplarily, the material of the wall structure 230 can be polyimide (PI) glue, etc., and this application does not limit this. Exemplarily, after the wall structure 230 is formed, it further includes: performing a planarization treatment on the wall structure 230, and the planarized wall structure 230 is higher than the height of the functional area on the filter component 220. Exemplarily, non-limiting examples of this planarization method include mechanical planarization method or chemical mechanical polishing planarization method.

[0110] Next, step S3 is executed. As Figure 2CAs shown, the wall structure 230 is filled with a sacrificial layer 240 .

[0111] Specifically, after forming a wall structure 230 surrounding all functional areas 221 on the non-functional area 222, a groove is formed between the wall structure 230 and the filter component 220. Afterwards, the sacrificial layer 240 can be filled in the groove. Exemplarily, the material of the sacrificial layer 240 can be photoresist, etc., which is not limited in this application. Exemplarily, a photoresist solution can be dripped in the groove, and then the substrate 210 is rotated at high speed. Under the action of centrifugal force, the photoresist solution will diffuse to the edge of the groove and also fill the groove. By adjusting parameters such as the rotation speed and the amount of photoresist solution added, the thickness and filling effect of the sacrificial layer 240 can be controlled.

[0112] Next, step S4 is performed, such as Figure 2D As shown, a covering layer 250 is formed on the surface of the wall structure 230 and the sacrificial layer 240 .

[0113] For example, the covering layer 250 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or plasma enhanced chemical vapor deposition (PECVD). For example, the covering layer 250 may be made of silicon nitride, etc., which is not limited in the present application. For example, after forming the covering layer 250, the covering layer 250 is further included: performing a planarization process on the covering layer 250. For example, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0114] In some embodiments, the covering layer 250 is formed on the surface of the wall structure 230 and the sacrificial layer 240 by using plasma enhanced chemical vapor deposition, and the roof process can be eliminated, so that the height of the cavity 260 formed subsequently is reduced to less than 10 um.

[0115] Next, step S5 is performed, such as Figure 2E As shown, a release hole 251 exposing the sacrificial layer 240 is formed in the cover layer 250 .

[0116] Exemplarily, a photolithography process or the like may be used to form a release hole 251 exposing the sacrificial layer 240 in the cover layer 250. Specifically, a photoresist mask layer may be formed on the cover layer 250, and the photoresist mask layer may be patterned through processes such as exposure and development to form a patterned mask layer for defining the release hole 251 to be formed; then, the cover layer 250 may be etched with the patterned mask layer to form a release hole 251 exposing the sacrificial layer 240 in the cover layer 250.

[0117] Among them, one or more release holes 251 exposing the sacrificial layer 240 may be formed in the cover layer 250 , and the number of the release holes 251 is set according to actual conditions and is not limited thereto.

[0118] Next, step S6 is performed, such as Figure 2F As shown, the sacrificial layer 240 is removed through the release hole 251 to form a cavity 260 .

[0119] For example, a wet process or a dry process may be used to remove the sacrificial layer 240 filled in the wall structure 230, so as to form a cavity 260 between the filter component 220, the wall structure 230 and the cover layer 250. For example, if the sacrificial layer 240 filled in the wall structure 230 is made of photoresist and a dry process is used to remove the photoresist filled in the wall structure 230, the photoresist may be oxidized in an oxygen atom environment to generate CO, CO2, H2O and other volatile oxides, and the generated CO, CO2, H2O and other volatile oxides are discharged from the release hole 251, thereby removing the sacrificial layer 240.

[0120] Next, step S7 is performed, such as Figure 2G As shown, a buffer layer 270 is formed at least on the region of the cover layer 250 corresponding to the cavity 260 , and the buffer layer 270 covers all the release holes 251 .

[0121] The formed buffer layer 270 is located above the central area of ​​the cover layer 250 and corresponds to the cavity 260. The buffer layer 270 covers all the release holes 251. The buffer layer 270 plays a buffering role between the lower cover layer 250 and the subsequently grown upper dielectric layer 280. For example, the buffer layer 270 can be formed by various deposition methods commonly used in the art, for example, it can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). For example, the buffer layer 270 can be a benzocyclobutene (BCB) film, etc., which is not limited in this application. For example, after the buffer layer 270 is formed, it also includes: flattening the buffer layer 270. For example, non-limiting examples of the flattening method include a mechanical flattening method or a chemical mechanical polishing flattening method.

[0122] Next, step S8 is performed, such as Figure 2H As shown, a dielectric layer 280 covering the cap layer 250 and the buffer layer 270 is formed.

[0123] Exemplarily, the dielectric layer 280 may be formed by various deposition methods commonly used in the art, for example, by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). Exemplarily, the material of the dielectric layer 280 may be silicon dioxide, etc., which is not limited in the present application. Exemplarily, after forming the dielectric layer 280, the process further includes: performing a planarization process on the dielectric layer 280. Exemplarily, non-limiting examples of the planarization method include a mechanical planarization method or a chemical mechanical polishing planarization method.

[0124] Next, step S9 is performed, such as Fig.2I As shown, a redistribution layer 291 (RDL) electrically connected to the filter component 220 is formed in the dielectric layer 280 , the cover layer 250 and the wall structure 230 .

[0125] Exemplarily, various methods commonly used in the art may be used to form the redistribution layer 291, for example, it may be formed by a multi-through hole structure method, a support structure method, or a build-up layer method. In a specific embodiment, a multi-through hole structure is formed in the dielectric layer 280, the cover layer 250, and the wall structure 230 by photolithography and etching processes, and then a conductive material such as copper or aluminum is deposited, and metal lines, i.e., the redistribution layer 291, are formed by photolithography and etching processes. Taking the deposition of copper in the multi-through hole structure as an example, physical vapor deposition (PVD), Cu-Damascene deposition, or any other suitable deposition method may be used.

[0126] In this embodiment, the I / O interfaces of at least two filter components 220 can be interconnected and re-integrated through the redistribution layer 291, thereby reducing the number of I / O interfaces and reducing the complexity of subsequent packaging processes. In addition, the use of the redistribution layer 291 can save the area of ​​the pad (PAD) on a single filter component 220 and improve the integration.

[0127] Next, step S10 is performed, such as Figure 2J As shown, solder balls 293 electrically connected to the redistribution layer 291 are formed.

[0128] Forming the solder ball 293 electrically connected to the redistribution layer 291 may include: first forming an opening 292 in the dielectric layer 280 to expose a portion of the redistribution layer 291 , and then forming the solder ball 293 electrically connected to the redistribution layer 291 in the opening 292 .

[0129] Exemplarily, a screen printing / electroplating process can be used to form solder balls 293 electrically connected to the redistribution layer 291. Taking screen printing ball planting as an example, it is a method of accurately placing solder ball 293 material (usually tin balls or tin-containing alloy balls) at a specific position through a screen template. The screen template is a screen with a specific pattern, and the openings in the pattern correspond to the positions where the balls need to be planted, that is, the openings 292 of the redistribution layer 291 exposed on the second dielectric layer 280. The solder ball paste (composed of solder ball powder and flux, etc.) is squeezed through a scraper to pass through the opening of the screen and deposited on the opening 292. After printing is completed, a drying process is performed to remove the solvent components in the solder ball paste and solidify the solder ball paste, thereby forming a solder ball 293 electrically connected to the redistribution layer 291.

[0130] In one example, before forming a solder ball 293 electrically connected to the redistribution layer 291 in the opening 292, a solder pad electrically connected to the redistribution layer 291 can be first formed in the opening 292, and then a solder ball 293 is formed on the solder pad, and the solder ball 293 is electrically connected to the redistribution layer 291 through the solder pad.

[0131] In one example, after forming the pad, a passivation layer is formed on the dielectric layer 280, the passivation layer covers the edge area of ​​the pad and exposes the middle area of ​​the pad, and then a solder ball 293 is formed on the pad, and the solder ball 293 is electrically connected to the redistribution layer 291 through the pad. The passivation layer can prevent corrosion from environmental moisture. Exemplarily, the material of the passivation layer can be polyimide glue, etc., which is not limited in this application.

[0132] So far, the description of the key steps of the packaging method of the filter module of the present application has been completed. The packaging method of the complete filter module may also include other steps, which will not be elaborated here one by one. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0133] In summary, the packaging method of the embodiment of the present application reduces the distance between filter components in the packaging structure by packaging at least two filter components together, thereby improving the integration and reducing the usage area.

[0134] Embodiment 3

[0135] The present application also provides a radio frequency module, which includes the packaging structure of the filter module as above or the packaging structure of the filter module obtained by the packaging method of the filter module as above. Some details of this embodiment can be referred to the relevant description of the method in the previous text, which will not be repeated here.

[0136] Among them, the RF module can adopt SIP-Molding (SIP stands for System in Package, which refers to system-level packaging) packaging form or any other suitable packaging form to improve the reliability of packaging.

[0137] Embodiment 4

[0138] The present application also provides an electronic device, which includes the above-mentioned radio frequency module.

[0139] The electronic device may be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, game console, television, VCD, DVD, navigator, camera, camcorder, voice recorder, MP3, MP4, PSP, etc., or an intermediate product having the above-mentioned semiconductor device, such as a mobile phone motherboard having the integrated circuit.

[0140] The present application has been described through the above-mentioned embodiments, but it should be understood that the above-mentioned embodiments are only for the purpose of example and illustration, and are not intended to limit the present application to the scope of the described embodiments. In addition, it can be understood by those skilled in the art that the present application is not limited to the above-mentioned embodiments, and more variations and modifications can be made according to the teachings of the present application, and these variations and modifications all fall within the scope of protection claimed by the present application. The scope of protection of the present application is defined by the attached claims and their equivalents.

Claims

1. A packaging structure of a filter module, characterized in that: The packaging structure of the filter module includes: A substrate, on which at least two filter components are formed; each of the filter components comprises a functional area located at the center and a non-functional area surrounding the functional area; A wall structure, located on the non-functional area and surrounding the entire functional area; a covering layer, wherein two ends of the covering layer are located on the wall structure, and a cavity is formed between the covering layer, the wall structure and the filter component; a buffer layer, located on the cover layer and at least corresponding to the cavity; a dielectric layer, covering the cover layer and the buffer layer; a redistribution layer, located in the dielectric layer, the cover layer and the wall structure and electrically connected to the filter component; The solder ball is electrically connected to the redistribution layer.

2. The packaging structure of the filter module according to claim 1, characterized in that: Also includes: A release hole is located in the cover layer, and the buffer layer covers the release hole.

3. The packaging structure of the filter module according to claim 1, characterized in that: Also includes: An opening is located in the dielectric layer and exposes a portion of the redistribution layer, and the solder ball is formed in the opening.

4. The packaging structure of the filter module according to claim 3, characterized in that: Also includes: A pad is located in the opening and is electrically connected to the redistribution layer.

5. The packaging structure of the filter module according to claim 4, characterized in that: Also includes: A passivation layer is located on the dielectric layer, and the passivation layer covers the edge area of ​​the pad and exposes the middle area of ​​the pad.

6. A packaging method for a filter module, characterized in that: The packaging method comprises: Providing a substrate on which at least two filter components are formed; each of the filter components comprises a functional area located at the center and a non-functional area surrounding the functional area; Forming a wall structure surrounding all the functional areas on the non-functional areas; Filling the wall structure with a sacrificial layer; forming a covering layer on the surface of the wall structure and the sacrificial layer; forming a release hole in the cover layer to expose the sacrificial layer; removing the sacrificial layer through the release hole to form a cavity; forming a buffer layer at least on a region of the cover layer corresponding to the cavity, wherein the buffer layer covers all of the release holes; forming a dielectric layer covering the cover layer and the buffer layer; forming a redistribution layer electrically connected to the filter component in the dielectric layer, the cover layer and the wall structure; Solder balls are formed to be electrically connected to the redistribution layer.

7. The packaging method according to claim 6, characterized in that: The forming of solder balls electrically connected to the redistribution layer comprises: An opening is formed in the dielectric layer to expose a portion of the redistribution layer, and the solder ball electrically connected to the redistribution layer is formed in the opening.

8. The packaging method according to claim 7, characterized in that: Before forming the solder ball electrically connected to the redistribution layer in the opening, the method further includes forming a pad electrically connected to the redistribution layer in the opening.

9. The packaging method according to claim 8, characterized in that: After forming the pad, the method further includes forming a passivation layer on the dielectric layer, wherein the passivation layer covers the edge area of ​​the pad and exposes the middle area of ​​the pad.

10. The packaging method according to claim 6, characterized in that: The capping layer includes a silicon nitride layer formed by PECVD.

Images