Packaging structure for high-power TVS (Transient Voltage Suppressor)

Abstract

The invention provides a packaging structure for a high-power TVS (Transient Voltage Suppressor). The packaging structure comprises a substrate material; each layer of stacked chips and pad regions thereof; through hole regions which are manufactured by using the TVS technology exist in pad regions on the edges of the two sides of each chip layer; interlayer solder balls used for forming electrical connection exist between the bottom layer chip and the substrate and between the through hole layers of all the layers of chips; colloid regions which are arranged between the substrate and the first chip layer and between the chip layers and are used for adhering each layer of chip and providing support; and the electrode region exists at the contact part of the substrate and the first layer of solder balls and is used for forming a packaged electrode. By introducing the TSV technology, the problems that the packaging area is increased, the reliability of the device is reduced and the like caused by a traditional lead bonding packaging mode are solved, and the potential of stacking more layers of chips under the same packaging area is further improved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic science and technology, and is mainly used for transient voltage suppression (TVS) technology. Further, it is an advanced packaging technology that can be used for high-power TVS devices, a method for improving power density and reliability through through-silicon via (TSV) technology, and its related structures. Background Art

[0002] TVS is a highly efficient circuit protection component, commonly used in various AC and DC power supply circuits. Its main purpose is to meet the needs of modern electronic equipment for voltage transient and surge protection, and to suppress instantaneous overvoltage.

[0003] With the improvement of integrated circuit manufacturing technology, its minimum line width has dropped to the sub-micron or even nanometer level. While improving chip performance, its sensitivity to voltage surges has increased, so the challenges faced by TVS technology are more severe. The generation of transient overvoltage can cause fatal damage to integrated circuits, thereby reducing the life and reliability of integrated circuits, and further causing the degradation of system functions, which is a great obstacle to achieving large-scale high-reliability integration.

[0004] In order to meet the industry's demand for high-power, high-density TVS devices, the traditional solution is to develop more advanced packaging technology. In the traditional bulk silicon industry, limited by the physical limitations of materials and packaging technology, in order to improve the power capability of TVS devices per unit area, a common method is to Figure 1 As shown, the specific approach is to stack the devices and lead out the electrodes by wire bonding to achieve 2.5D / 3D packaging. However, the disadvantage of this method is that the size of each layer of chips is different, which not only increases the complexity of the process, but also limits the number of stacked layers. And when the number of stacked layers increases, the length difference of the metal wires for leading out the electrodes in each layer is too large, which will cause problems such as increased packaging area and reliability. In addition, there is also SiC-based TVS technology. The advantage of this technology is that when the size of a single device is the same, the SiC device has better single-tube performance. However, the disadvantage of this technology is that the yield of SiC devices is too low, which will lead to excessively high costs, and the SiC material is hard and not easy to grind and thin, which reduces the packaging efficiency.

[0005] Based on this, the present invention proposes an advanced packaging technology based on through silicon via technology, which not only solves the problems brought by the traditional wire bonding solution, but also does not have the disadvantages of low yield and difficulty in thinning compared with SiC-based. It can also meet the needs of electronic components for protecting high-power surge voltage through multi-layer TVS stacking. Summary of the invention

[0006] The technical problem to be solved by the present invention is to improve power density and reliability through TSV technology without significantly increasing the packaging area.

[0007] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0008] A packaging structure for a high-power TVS, comprising a TVS device area 01, an anode pad area 02, and a cathode pad area 03;

[0009] Line 1 is a line perpendicular to the chip pad direction, connecting the center of the fourth through hole area of ​​the cathode and the center of the fourth through hole area of ​​the anode; unfolding along Line 1, a longitudinal section of the packaged device is obtained, including:

[0010] Substrate 801; Substrate 801 is located at the bottom of the entire structure and serves as a base for packaging;

[0011] Five layers of chips are stacked on the substrate 801, from bottom to top, chip layer A101, chip layer B102, chip layer C103, chip layer D104, and chip layer E105;

[0012] There are through-hole areas manufactured by the TVS method in the pad areas at the edges of both sides of each chip layer, the left anode through-hole area and the right cathode through-hole area, including: the anode fourth through-hole area 214 and the cathode fourth through-hole area 414 of chip layer A, the anode fourth through-hole area 224 and the cathode fourth through-hole area 424 of chip layer B, the anode fourth through-hole area 234 and the cathode fourth through-hole area 434 of chip layer C, the anode fourth through-hole area 244 and the cathode fourth through-hole area 444 of chip layer D, and the anode fourth through-hole area 254 and the cathode fourth through-hole area 454 of chip layer E;

[0013] Between the through-hole layers at the edge of each layer of chip pad, there are interlayer solder balls that form electrical connections with the through-holes of each layer of chips, anode solder balls on the left and cathode solder balls on the right, including: anode fourth solder balls 314 between chip layer A and substrate, cathode fourth solder balls 514 between chip layer A and substrate, anode fourth solder balls 324 between chip layer B and chip layer A, cathode fourth solder balls 524 between chip layer B and chip layer A, anode fourth solder balls 334 between chip layer C and chip layer B, cathode fourth solder balls 534 between chip layer C and chip layer B, anode fourth solder balls 344 between chip layer D and chip layer C, cathode fourth solder balls 544 between chip layer D and chip layer C, anode fourth solder balls 354 between chip layer E and chip layer D, cathode fourth solder balls 554 between chip layer E and chip layer D;

[0014] There are colloid regions between the substrate 801 and the first chip layer 101 and between the chip layers for adhering the chips of each layer and providing support, which are the first colloid region 601 to the fifth colloid region 605 from bottom to top;

[0015] There is an anode electrode area 701 for forming a post-package electrode at the contact point between the anode fourth solder ball 314 and the substrate 801 between the chip layer A and the substrate, and there is a cathode electrode area 702 for forming a post-package electrode at the contact point between the cathode fourth solder ball 514 and the substrate 801 between the chip layer A and the substrate.

[0016] As a preferred method, Line 2 is a tangent line parallel to the chip pad direction and along the center of the chip anode pad through-hole area; unfolding along the dotted line 2, the anode cross section of the package device pad is obtained, including:

[0017] The anode pad areas of each layer of chips are, from bottom to top: anode pad area A121 to anode pad area E125;

[0018] There are through-hole areas manufactured by using the TVS method in the pad area at the edges of both sides of each chip layer, including: the first through-hole area of ​​the anode of chip layer A to the eighth through-hole area 211-218, the first through-hole area of ​​the anode of chip layer B to the eighth through-hole area 221-228, the first through-hole area of ​​the anode of chip layer C to the eighth through-hole area 231-238, the first through-hole area of ​​the anode of chip layer D to the eighth through-hole area 241-248, and the first through-hole area of ​​the anode of chip layer E to the eighth through-hole area 251-258;

[0019] Interlayer solder balls electrically connected to the through holes of each layer of chips include: anode first solder balls to eighth solder balls 311-318 between chip layer A and substrate, anode first solder balls to eighth solder balls 321-328 between chip layer B and chip layer A, anode first solder balls to eighth solder balls 331-338 between chip layer C and chip layer B, anode first solder balls to eighth solder balls 341-348 between chip layer D and chip layer C, and anode first solder balls to eighth solder balls 351-358 between chip layer E and chip layer D;

[0020] The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region 601 to the fifth colloid region 605;

[0021] an anode electrode region 701 located on the left side of the substrate;

[0022] The substrate 801 is located at the bottom of the entire structure and serves as the base of the package.

[0023] As a preferred method, Line 3 is a tangent line parallel to the chip pad direction and along the center of the chip cathode pad through-hole area. Expand along Line 3 to obtain the cathode cross section of the package device pad, including:

[0024] The cathode pad areas of the chips in each layer are, from bottom to top, cathode pad area F121 to cathode pad area J125;

[0025] There are through-hole areas manufactured by using the TVS method in the pad areas at the edges of both sides of each chip layer, including: the first through-hole area of ​​the cathode to the eighth through-hole area 411-418 of the chip layer A, the first through-hole area of ​​the cathode to the eighth through-hole area 421-428 of the chip layer B, the first through-hole area of ​​the cathode to the eighth through-hole area 431-438 of the chip layer C, the first through-hole area of ​​the cathode to the eighth through-hole area 441-448 of the chip layer D, and the first through-hole area of ​​the cathode to the eighth through-hole area 451-458 of the chip layer E;

[0026] Interlayer solder balls electrically connected to the through holes of each layer of chips include: cathode first solder ball to eighth solder ball 511-518 between chip layer A and substrate, cathode first solder ball to eighth solder ball 521-528 between chip layer B and chip layer A, cathode first solder ball to eighth solder ball 531-538 between chip layer C and chip layer B, cathode first solder ball to eighth solder ball 541-548 between chip layer D and chip layer C, cathode first solder ball to eighth solder ball 551-558 between chip layer E and chip layer D;

[0027] The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region 601 to the fifth colloid region 605;

[0028] a cathode electrode region 702 located on the right side of the substrate;

[0029] Substrate 801: Substrate 801 is located at the bottom of the entire structure and serves as the base of the package.

[0030] As a preferred embodiment, the shape of the solder ball structure is spherical or cylindrical.

[0031] As a preferred embodiment, the TSV has a cylindrical or cubic shape.

[0032] As a preferred approach, the number of stacked series or stacked packages is changed according to different application scenarios.

[0033] The beneficial effects of the present invention are as follows: the TSV technology is introduced, and the through-hole technology is used in the chip pad to realize the electrical interconnection of each chip layer, thereby avoiding the problems of large packaging area, large parasitic resistance and capacitance brought by the traditional wire bonding packaging mode, and reducing the packaging area under the same power density and improving the potential for stacking multiple layers of chips under the same packaging area.

[0034] While continuing to use silicon materials and maintaining high yield, TSV technology is introduced to avoid problems such as increased packaging area and excessive wire resistance affecting device performance caused by traditional wire bonding packaging methods, and further enhances the potential for stacking more layers of chips in the same packaging area. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 It is a TVS packaging structure with traditional wire bonding mode.

[0036] Figure 2 This is a new packaging structure using TSV technology proposed by the present invention.

[0037] Figure 3 This is a schematic longitudinal cross-sectional view of the new packaging structure proposed by the present invention.

[0038] Figure 4 This is a schematic diagram of the anode cross-section of the new packaging structure proposed by the present invention.

[0039] Figure 5 This is a schematic diagram of the cathode cross-section of the new packaging structure proposed by the present invention.

[0040] Among them, 01-TVS device area, 02-anode pad area, 03-cathode pad area, 101-chip layer A, 102-chip layer B, 103-chip layer C, 104-chip layer D, 105-chip layer E, 111-cathode pad area A, 112-cathode pad area B, 113-cathode pad area C, 114-cathode pad area D, 115-cathode pad area E, 121-anode pad area F, 122-anode pad area G, 123-anode pad area H, 124-anode pad area I, 125-anode pad area J, 211-218 are the first anode area of ​​chip layer A through-hole area to the eighth through-hole area; 221-228 are the first through-hole area of ​​the anode of chip layer B to the eighth through-hole area; 231-238 are the first through-hole area of ​​the anode of chip layer C to the eighth through-hole area; 241-248 are the first through-hole area of ​​the anode of chip layer D to the eighth through-hole area; 251-258 are the first through-hole area of ​​the anode of chip layer E to the eighth through-hole area; 311-318 are the first through-hole area of ​​the anode to the eighth through-hole area between chip layer A and the substrate; 321-328 are the first through-hole area of ​​the anode to the eighth through-hole area between chip layer B and chip layer A; 331-338 are the first through-hole area of ​​the anode to the eighth through-hole area between chip layer C and chip layer B; 341-348 351-358 are the anode first solder ball to the eighth anode solder ball between chip layer D and chip layer C; 411-418 are the cathode first through hole area to the eighth through hole area of ​​chip layer A; 421-428 are the cathode first through hole area to the eighth through hole area of ​​chip layer B; 431-438 are the cathode first through hole area to the eighth through hole area of ​​chip layer C; 441-448 are the cathode first through hole area to the eighth through hole area of ​​chip layer D; 451-458 are the cathode first through hole area to the eighth through hole area of ​​chip layer E; 511-518 are the cathode first through hole area to the eighth through hole area between chip layer A and substrate The eighth solder ball; 521-528 are the cathode first solder ball to the eighth solder ball between chip layer B and chip layer A; 531-538 are the cathode first solder ball to the eighth solder ball between chip layer C and chip layer B; 541-548 are the cathode first solder ball to the eighth solder ball between chip layer D and chip layer C; 551-558 are the cathode first solder ball to the eighth solder ball between chip layer E and chip layer D; 601-first layer colloid area, 602-second layer colloid area, 603-third layer colloid area, 604-fourth layer colloid area, 605-fifth layer colloid area; 701-anode electrode area, 702-cathode electrode area; 801-substrate. DETAILED DESCRIPTION

[0041] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Embodiment 1:

[0043] like Figure 2 As shown, this embodiment provides a packaging structure for a high-power TVS, including a TVS device area 01, an anode pad area 02, and a cathode pad area 03;

[0044] Line 1 is a line perpendicular to the chip pad direction, connecting the center of the fourth through hole area of ​​the cathode and the center of the fourth through hole area of ​​the anode; unfolding along Line 1, a longitudinal section of the packaged device is obtained, including:

[0045] Substrate 801; Substrate 801 is located at the bottom of the entire structure and serves as a base for packaging;

[0046] Five layers of chips are stacked on the substrate 801, from bottom to top, chip layer A101, chip layer B102, chip layer C103, chip layer D104, and chip layer E105;

[0047] like Figure 3 As shown, there are through-hole areas manufactured by the TVS method in the pad areas at the edges of both sides of each chip layer, the left anode through-hole area and the right cathode through-hole area, including: the anode fourth through-hole area 214 and the cathode fourth through-hole area 414 of chip layer A, the anode fourth through-hole area 224 and the cathode fourth through-hole area 424 of chip layer B, the anode fourth through-hole area 234 and the cathode fourth through-hole area 434 of chip layer C, the anode fourth through-hole area 244 and the cathode fourth through-hole area 444 of chip layer D, and the anode fourth through-hole area 254 and the cathode fourth through-hole area 454 of chip layer E;

[0048] Between the through-hole layers at the edge of each layer of chip pad, there are interlayer solder balls that form electrical connections with the through-holes of each layer of chips, anode solder balls on the left and cathode solder balls on the right, including: anode fourth solder balls 314 between chip layer A and substrate, cathode fourth solder balls 514 between chip layer A and substrate, anode fourth solder balls 324 between chip layer B and chip layer A, cathode fourth solder balls 524 between chip layer B and chip layer A, anode fourth solder balls 334 between chip layer C and chip layer B, cathode fourth solder balls 534 between chip layer C and chip layer B, anode fourth solder balls 344 between chip layer D and chip layer C, cathode fourth solder balls 544 between chip layer D and chip layer C, anode fourth solder balls 354 between chip layer E and chip layer D, cathode fourth solder balls 554 between chip layer E and chip layer D;

[0049] There are colloid regions between the substrate 801 and the first chip layer 101 and between the chip layers for adhering the chips of each layer and providing support, which are the first colloid region 601 to the fifth colloid region 605 from bottom to top;

[0050] There is an anode electrode area 701 for forming a post-package electrode at the contact point between the anode fourth solder ball 314 and the substrate 801 between the chip layer A and the substrate, and there is a cathode electrode area 702 for forming a post-package electrode at the contact point between the cathode fourth solder ball 514 and the substrate 801 between the chip layer A and the substrate.

[0051] Line 2 is a tangent line parallel to the chip pad direction and along the center of the chip anode pad through-hole area; unfold along the dotted line 2 to obtain the anode cross section of the package device pad, including:

[0052] like Figure 4 As shown, the anode pad areas of the chips in each layer are, from bottom to top, anode pad area A121 to anode pad area E125;

[0053] There are through-hole areas manufactured by using the TVS method in the pad area at the edges of both sides of each chip layer, including: the first through-hole area of ​​the anode of chip layer A to the eighth through-hole area 211-218, the first through-hole area of ​​the anode of chip layer B to the eighth through-hole area 221-228, the first through-hole area of ​​the anode of chip layer C to the eighth through-hole area 231-238, the first through-hole area of ​​the anode of chip layer D to the eighth through-hole area 241-248, and the first through-hole area of ​​the anode of chip layer E to the eighth through-hole area 251-258;

[0054] Interlayer solder balls electrically connected to the through holes of each layer of chips include: anode first solder balls to eighth solder balls 311-318 between chip layer A and substrate, anode first solder balls to eighth solder balls 321-328 between chip layer B and chip layer A, anode first solder balls to eighth solder balls 331-338 between chip layer C and chip layer B, anode first solder balls to eighth solder balls 341-348 between chip layer D and chip layer C, and anode first solder balls to eighth solder balls 351-358 between chip layer E and chip layer D;

[0055] The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region 601 to the fifth colloid region 605;

[0056] an anode electrode region 701 located on the left side of the substrate;

[0057] The substrate 801 is located at the bottom of the entire structure and serves as the base of the package.

[0058] Line 3 is a tangent line parallel to the chip pad direction and along the center of the chip cathode pad through-hole area. Expand along Line 3 to obtain the cathode cross section of the package device pad, including:

[0059] The cathode pad areas of the chips in each layer are, from bottom to top, cathode pad area F121 to cathode pad area J125;

[0060] like Figure 5 As shown, there are through-hole areas manufactured by using the TVS method in the pad areas at the edges of both sides of each chip layer, including: the first cathode through-hole area to the eighth through-hole area 411-418 of chip layer A, the first cathode through-hole area to the eighth through-hole area 421-428 of chip layer B, the first cathode through-hole area to the eighth through-hole area 431-438 of chip layer C, the first cathode through-hole area to the eighth through-hole area 441-448 of chip layer D, and the first cathode through-hole area to the eighth through-hole area 451-458 of chip layer E;

[0061] Interlayer solder balls electrically connected to the through holes of each layer of chips include: cathode first solder ball to eighth solder ball 511-518 between chip layer A and substrate, cathode first solder ball to eighth solder ball 521-528 between chip layer B and chip layer A, cathode first solder ball to eighth solder ball 531-538 between chip layer C and chip layer B, cathode first solder ball to eighth solder ball 541-548 between chip layer D and chip layer C, cathode first solder ball to eighth solder ball 551-558 between chip layer E and chip layer D;

[0062] The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region 601 to the fifth colloid region 605;

[0063] a cathode electrode region 702 located on the right side of the substrate;

[0064] Substrate 801: Substrate 801 is located at the bottom of the entire structure and serves as the base of the package.

[0065] Preferably, the shape of the solder ball structure is spherical or cylindrical.

[0066] Preferably, the through hole in the silicon wafer has a cylindrical or cubic shape.

[0067] Preferably, the number of stacked series connections or stacked packages is changed according to different application scenarios.

[0068] In summary, the present invention proposes an advanced packaging technology that can be used for high-power TVS, which can not only continue the high yield of silicon-based devices, but also avoid the problems of increased packaging area and excessive lead resistance affecting device performance caused by the traditional wire bonding packaging mode by introducing TSV technology, further improving the potential for stacking more layers of chips under the same packaging area. For different processes and application scenarios, the materials and shapes of the colloid area, solder balls, and through-hole areas are all variable and are not limited to the situations listed in the present invention. Therefore, the new structure and manufacturing method proposed by the present invention are very suitable for the application of high-power TVS packaging.

[0069] The packaging structure, manufacturing method and drawings proposed in the present invention are only a display and explanation of the new packaging technology for high-power TVS. In addition to the structure in the drawings, anyone familiar with this technology can modify or change the above structure without violating the spirit and scope of the present invention, such as changing the solder ball structure described above from a spherical shape to a cylindrical shape, changing the silicon through-hole morphology from a cylindrical shape to a cubic shape, changing the metal type, etc., or changing the number of stacked series or stacked packages according to different application scenarios, and these structures should obviously be within the protection scope of the present invention.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A packaging structure for high-power TVS, characterized in that: It includes a TVS device area (01), an anode pad area (02), and a cathode pad area (03); Line 1 is a line perpendicular to the chip pad direction, connecting the center of the fourth through hole area of ​​the cathode and the center of the fourth through hole area of ​​the anode; Expand along Line 1 to obtain the longitudinal section of the packaged device, including: Substrate (801); The substrate (801) is located at the bottom of the entire structure and serves as a base for packaging; Five layers of chips are stacked on the substrate (801), from bottom to top, chip layer A (101), chip layer B (102), chip layer C (103), chip layer D (104), and chip layer E (105); There are through-hole areas manufactured by using the TVS method in the pad areas at the edges of both sides of each chip layer, the left anode through-hole area and the right cathode through-hole area, including: the anode fourth through-hole area (214) and the cathode fourth through-hole area (414) of chip layer A, the anode fourth through-hole area (224) and the cathode fourth through-hole area (424) of chip layer B, the anode fourth through-hole area (234) and the cathode fourth through-hole area (434) of chip layer C, the anode fourth through-hole area (244) and the cathode fourth through-hole area (444) of chip layer D, and the anode fourth through-hole area (254) and the cathode fourth through-hole area (454) of chip layer E; Between the through-hole layers at the edge of each layer of chip pad, there are interlayer solder balls that form electrical connections with the through-holes of each layer of chips, anode solder balls on the left and cathode solder balls on the right, including: an anode fourth solder ball (314) between chip layer A and the substrate, a cathode fourth solder ball (514) between chip layer A and the substrate, an anode fourth solder ball (324) between chip layer B and chip layer A, a cathode fourth solder ball (524) between chip layer B and chip layer A, an anode fourth solder ball (334) between chip layer C and chip layer B, a cathode fourth solder ball (534) between chip layer C and chip layer B, an anode fourth solder ball (344) between chip layer D and chip layer C, a cathode fourth solder ball (544) between chip layer D and chip layer C, an anode fourth solder ball (354) between chip layer E and chip layer D, and a cathode fourth solder ball (554) between chip layer E and chip layer D; There are colloid regions between the substrate (801) and the first chip layer (101) and between the chip layers for adhering the chips of each layer and providing support, which are the first colloid region (601) to the fifth colloid region (605) from bottom to top; An anode electrode region (701) for forming a post-package electrode exists at the contact point between the fourth anode solder ball (314) between the chip layer A and the substrate and the substrate (801), and a cathode electrode region (702) for forming a post-package electrode exists at the contact point between the fourth cathode solder ball (514) between the chip layer A and the substrate and the substrate (801).

2. A cross-sectional view of a packaging structure for a high-power TVS according to claim 1, characterized in that: Line2 is parallel to the chip pad direction and is a tangent line along the center of the chip anode pad through-hole area; Expand along Line2 to obtain the anode cross section of the package device pad, including: The anode pad regions of each layer of chips are, from bottom to top, anode pad region A (121) to anode pad region E (125); There are through-hole areas manufactured by using the TVS method in the pad areas at the edges of both sides of each chip layer, including: the first through-hole area to the eighth through-hole area (211-218) of the anode of chip layer A, the first through-hole area to the eighth through-hole area (221-228) of the anode of chip layer B, the first through-hole area to the eighth through-hole area (231-238) of the anode of chip layer C, the first through-hole area to the eighth through-hole area (241-248) of the anode of chip layer D, and the first through-hole area to the eighth through-hole area (251-258) of the anode of chip layer E; Interlayer solder balls that form electrical connections with the through holes of each layer of chips include: anode first solder balls to eighth solder balls (311-318) between chip layer A and substrate, anode first solder balls to eighth solder balls (321-328) between chip layer B and chip layer A, anode first solder balls to eighth solder balls (331-338) between chip layer C and chip layer B, anode first solder balls to eighth solder balls (341-348) between chip layer D and chip layer C, and anode first solder balls to eighth solder balls (351-358) between chip layer E and chip layer D; The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region (601) to the fifth colloid region (605); an anode electrode region (701) located on the left side of the substrate; The substrate (801) is located at the bottom of the entire structure and serves as the base of the package.

3. A cross-sectional view of a packaging structure for a high-power TVS according to claim 1, characterized in that: Line 3 is a tangent line parallel to the chip pad direction and along the center of the chip cathode pad through-hole area. Expand along Line 3 to obtain the cathode cross section of the package device pad, including: The cathode pad regions of each layer of chips are, from bottom to top, cathode pad region F (121) to cathode pad region J (125); There are through-hole areas manufactured by using the TVS method in the pad areas at the edges of both sides of each chip layer, including: the first through-hole area of ​​the cathode to the eighth through-hole area (411-418) of chip layer A, the first through-hole area of ​​the cathode to the eighth through-hole area (421-428) of chip layer B, the first through-hole area of ​​the cathode to the eighth through-hole area (431-438) of chip layer C, the first through-hole area of ​​the cathode to the eighth through-hole area (441-448) of chip layer D, and the first through-hole area of ​​the cathode to the eighth through-hole area (451-458) of chip layer E; Interlayer solder balls that form electrical connections with the through holes of each layer of chips include: cathode first solder ball to eighth solder ball (511-518) between chip layer A and substrate, cathode first solder ball to eighth solder ball (521-528) between chip layer B and chip layer A, cathode first solder ball to eighth solder ball (531-538) between chip layer C and chip layer B, cathode first solder ball to eighth solder ball (541-548) between chip layer D and chip layer C, cathode first solder ball to eighth solder ball (551-558) between chip layer E and chip layer D; The colloid regions that adhere the chips of each layer and provide support are, from bottom to top, the first colloid region (601) to the fifth colloid region (605); a cathode electrode region (702) located on the right side of the substrate; Substrate (801); The substrate (801) is located at the bottom of the entire structure and serves as a base for the package.

4. The packaging structure for high-power TVS according to claim 1, characterized in that: The shape of the solder ball structure is spherical or cylindrical.

5. The packaging structure for high-power TVS according to claim 1, characterized in that: The shape of the through hole in the silicon wafer is cylindrical or cubic.

6. The packaging structure for high-power TVS according to claim 1, characterized in that: Change the number of stacked series or stacked packages according to different application scenarios.

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