Arithmetic circuits and computing devices

Abstract

The present disclosure relates to an arithmetic circuit and a computing device, wherein the arithmetic circuit includes: a multi-stage adding module, wherein the input end of the subsequent adding module is communicatively connected to the output end of the previous adding module of the adjacent adding module, and the subsequent adding module is configured to at least calculate the sum of a first operand output by the previous adding module and a product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficient is generated based on at least one element in a first vector, and the second operand is generated based on at least one element in a second vector.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and more particularly, to an operation circuit and a computing device. Background Art

[0002] Data processing often involves dot product operations between vectors. In some cases, multiple accumulated items in a dot product (for example, the product of an element in one vector multiplied by the corresponding element in another vector) may not be available simultaneously. Therefore, the accumulation calculation to obtain the dot product result typically requires waiting until all accumulated items are available. However, this processing approach can lead to a high risk of timing violations in related circuits and may also degrade circuit performance, necessitating improvements. Summary of the Invention

[0003] One of the objectives of the present disclosure is to provide an arithmetic circuit and a computing device.

[0004] According to a first aspect of the present disclosure, a calculation circuit is provided, the calculation circuit being configured to calculate at least a dot product of a first vector and a second vector, wherein the first vector is a pre-known coefficient vector, and the calculation circuit comprises:

[0005] A multi-stage addition module, wherein an input end of a subsequent stage addition module is communicatively connected to an output end of a previous stage addition module adjacent to the stage addition module, and the subsequent stage addition module is configured to at least calculate the sum of a first operand output by the previous stage addition module and a product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficients are generated based on at least one element in a first vector, and the second operands are generated based on at least one element in a second vector.

[0006] In some embodiments, when the dimensions of the first vector and the second vector are each N, the operation circuit has an N-1-stage addition module, wherein:

[0007] The 0th-stage addition module is configured to calculate A0*B0+A1*B1, where A0 is a first coefficient generated based on the 0th element a0 in the first vector, A1 is a first coefficient generated based on the 1st element a1 in the first vector, B0 is a second operand generated based on the 0th element b0 in the second vector, and B1 is a second operand generated based on the 1st element b1 in the second vector; and,

[0008] The i-th stage addition module is configured to calculate S i +A i+1 *B i+1 , where S iis the first operand output by the i-1th level addition module, A i+1 It is based on the i+1th element a in the first vector i+1 The first coefficient generated, and B i+1 It is based on the i+1th element b in the second vector i+1 The second operand generated, where i is an integer and 0 <i<N-1。

[0009] In some embodiments, the operation circuit further includes:

[0010] One or more data transmission lines, each of the one or more data transmission lines is communicatively connected to at least one stage of the addition module, and the data transmission line is configured to transmit an element in the second vector or a second operand to a corresponding addition module.

[0011] In some embodiments, at least one level of the multi-level addition module is configured to obtain a third operand, and is configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the second coefficient and the third operand, wherein the third operand is a preset multiple of the corresponding fourth operand, and the fourth operand is generated based on at least one target element in the second vector. In the dot product calculation, the absolute value of the element in the first vector multiplied by the target element in the second vector is greater than or equal to the absolute value of the preset multiple, the preset multiple is greater than 1, and for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple is less than or equal to the first coefficient.

[0012] In some embodiments, the at least one stage addition module is further configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on a product obtained by multiplying the third coefficient and a fourth operand corresponding to the third operand, wherein, for each fourth operand and the corresponding third operand, a sum of a product of the second coefficient and a preset multiple plus the third coefficient equals the first coefficient; and / or,

[0013] The at least one stage addition module is further configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the first coefficient and the fifth operand, wherein the fifth operand is generated based on at least one element in the second vector other than the element used to generate the third operand.

[0014] In some embodiments, the operation circuit further includes:

[0015] A multiple operation module is configured to calculate a preset multiple of the fourth operand to generate a corresponding third operand.

[0016] In some embodiments, the preset multiple is determined according to the first vector; or,

[0017] The preset magnification includes at least one of 3 times, 5 times, and 7 times.

[0018] In some embodiments, the multiple calculation module includes one or more multiple calculation units, each of which includes:

[0019] A first shifter is configured to shift the sixth operand to the left by p bits to generate a seventh operand, wherein the seventh operand is 2 p times the sixth operand, the sixth operand is a positive integer multiple of the second operand, and p is a positive integer; or,

[0020] A first adding unit is configured to add an eighth operand and a ninth operand to generate a tenth operand, wherein the eighth operand is a positive integer multiple of the second operand and the ninth operand is a positive integer multiple of the second operand.

[0021] In some embodiments, the addition module includes at least one of the following:

[0022] A second shifter is configured to shift the eleventh operand left by q bits to generate a twelfth operand, wherein the twelfth operand is 2 q times an eleventh operand, the eleventh operand being generated based on the second operand, and q being a positive integer; and,

[0023] A second adding unit is configured to calculate the sum of at least two operands, wherein the at least two operands include a first operand output by a previous stage adding module, one or more operands output by a corresponding second shifter, or a preset constant.

[0024] In some embodiments, the operation circuit further includes:

[0025] One or more register modules, wherein the register modules are communicatively connected to the input end or the output end of the corresponding first-stage adding module in the multi-stage adding module.

[0026] In some embodiments, when the arithmetic circuit has M-stage addition modules, the arithmetic circuit includes at least M register modules, wherein the output end of the m-th stage addition module is communicatively connected to the input end of the m-th register module, and the m-th register module is configured to register the first operand output by the m-th stage addition module, wherein m is an integer and 0≤m <M。

[0027] In some embodiments, the one or more register modules include a primary register module, which is communicatively connected to the input end of the 0th stage addition module, and the primary register module is configured to store A0*B0, where A0 is a first coefficient generated based on the 0th element a0 in the first vector, and B0 is a second operand generated based on the 0th element b0 in the second vector.

[0028] In some embodiments, the operation circuit further includes:

[0029] A bitwise inversion module is configured to, when an element in the first vector is a negative number, bitwise invert at least one operand generated by multiplying an element in the second vector by the element in the first vector.

[0030] In some embodiments, the operation circuit is configured to perform an image interpolation operation, the first vector is a coefficient vector for image interpolation, and at least two elements in the second vector are not provided to the operation circuit at the same time.

[0031] According to a second aspect of the present disclosure, a computing device is provided, comprising one or more arithmetic circuits as described above.

[0032] In some embodiments, when the computing device includes multiple computing circuits, at least two computing circuits operate in parallel.

[0033] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0035] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0036] Figure 1 A schematic diagram showing a computing device performing image interpolation is shown;

[0037] Figure 2 Shown Figure 1 a schematic diagram of an arithmetic circuit in a computing device;

[0038] Figure 3 A block diagram of a computing device according to an exemplary embodiment of the present disclosure is shown;

[0039] Figure 4 A block diagram of an arithmetic circuit according to an exemplary embodiment of the present disclosure is shown;

[0040] Figure 5 shows a block diagram of an arithmetic circuit according to another exemplary embodiment of the present disclosure;

[0041] Figure 6 A block diagram of a multiple operation module in an operation circuit according to a specific embodiment of the present disclosure is shown;

[0042] Figure 7 shows a block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure;

[0043] Figure 8 FIG2 shows a block diagram of a multiple operation module in an operation circuit according to another specific embodiment of the present disclosure;

[0044] Figure 9 FIG2 shows a block diagram of an addition module in an arithmetic circuit according to a specific embodiment of the present disclosure;

[0045] Figure 10 A block diagram of an arithmetic circuit according to yet another exemplary embodiment of the present disclosure is shown.

[0046] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0047] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0048] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present disclosure.

[0049] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. In other words, the structures and methods herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that these are merely exemplary of the disclosure that may be implemented, and are not exhaustive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0050] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0051] In all examples shown and discussed herein, any specific values should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0052] In various data processing processes, vector dot product operation is a common operation form. For example, the dot product P between the first vector A and the second vector B, each with dimension N, is d It can be expressed as:

[0053] (1)

[0054] in, represents the i-th component of the first vector A, represents the i-th component of the second vector B, where i is an integer and (Those skilled in the art will appreciate that the value of i may also be an integer greater than or equal to 1, which does not affect the essence of the operation. Therefore, in this article, the value of i starting from zero will be used as an example for detailed explanation).

[0055] In some examples, vector dot product operations can be used in image interpolation. Specifically, image interpolation is the process of inferring the values of new pixels from the values of known pixels. The new pixels may not be at integer coordinates of the original image. In this case, the values of these new pixels can be obtained through image interpolation algorithms. When the size, shape or position of the image changes, or in the process of video processing, in order to fill in missing frames or generate smooth slow motion effects, image interpolation related to images or video frames may be required.

[0056] Depending on the image interpolation algorithm used, a corresponding coefficient vector can be determined, which can be used as the first vector in the vector dot product operation. In one specific example, in Advanced Video Coding (AVC, H.264), a pixel value at a half-pixel position can be generated based on the coefficient vector (0, 1, -5, 20, 20, -5, 1, 0). In another specific example, in High Efficiency Video Coding (HEVC, H.265), a pixel value at a half-pixel position can be generated based on the coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1), a pixel value at a quarter-pixel position can be generated based on the coefficient vector (-1, 4, -10, 58, 17, -5, 1, 0), or a pixel value at a three-quarter-pixel position can be generated based on the coefficient vector (0, 1, -5, 17, 58, -10, 4, -1). In some specific embodiments below, the technical solution of the present disclosure will be described in detail using the H.265 coefficient vector (-1, 4, -11, 40, 40, -11, 4, -1) as a first vector and the pixel values of eight pixels to be processed in an image as a second vector. However, it is understood that the arithmetic circuit and computing device of the present disclosure can also be used to calculate dot products between other types of vectors or in applications other than image interpolation, without limitation herein.

[0057] like Figure 1 and Figure 2 As shown, a computing device 200' may include multiple computing circuits 100', and the multiple computing circuits 100' may run in parallel to process image interpolation operations associated with multiple groups of pixel points 910 in an image 900 in parallel. Figure 1 In the image 900 shown, taking the plurality of pixels 910 in the first row at the top of the image 900 as an example, the pixels 910 in this row can be divided into a plurality of pixel groups, each of which can include eight consecutive pixels 910. For each pixel group, the pixel values of the pixels 910 therein can be sequentially input from right to left into the corresponding operation circuit 100' in the computing device 200' to perform image interpolation operation. After completing the image interpolation operation associated with the first row of pixels 910, the image interpolation operation associated with the next row of pixels 910 can be continued until the interpolation of the entire image 900 is completed. For example, Figure 1 The respective operation circuits 100′ shown in FIG. 1 can be used to respectively execute operations on a pixel group including pixel points p0 to p7, a pixel group including pixel points p1 to p8, and a pixel group including pixel points p1 to p8. n ~p n+7For each operation circuit 100', the operation circuit 100' can sequentially receive the pixel values of the pixel points 910 in the corresponding pixel group in different clock cycles. Figure 1 As shown, each operation circuit 100' may include an input terminal (din) to receive the pixel value of pixel point 910, and may also include an output terminal (dout) to output the dot product of the first vector and the second vector, or the result of the image interpolation operation. It is understood that in other specific examples, the pixel values of corresponding pixels may also be input into the corresponding operation circuit 100' in the computing device 200' according to pixel columns in the image, or according to diagonals in the image, to achieve the desired image interpolation operation, which is not limited here. For example, each operation circuit 100' can be responsible for image interpolation operations associated with pixel points 910 in a row or column of image 900.

[0058] According to the above formula (1), a large number of multiplication and addition operations are usually involved in vector dot product or image interpolation operations. In order to simplify the operation circuit, the multiplication and addition operations in the above formula (1) can be converted into shift and addition operations. Taking the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7) as an example, each element in the first vector can be converted into the form of the sum of integer powers of 2, that is: A=(-1, 4, -8-2-1, 32+8, 32+8, -8-2-1, 4, -1). Furthermore, the dot product of the first vector A and the second vector B can be expressed as:

[0059] (2)

[0060] In some examples, the Figure 2 The operation circuit 100' shown is used to perform the operation in the above formula (2). Specifically, the operation circuit 100' may include a plurality of registers 110' and an addition module 120'. Among them, the plurality of registers 110' can be connected in series to respectively store the corresponding elements in the second vector input into the operation circuit 100' in sequence, or the register 110' can be used for beating to ensure the correct timing in the operation circuit 100'. After obtaining all the elements in the second vector from the corresponding register 110', the addition module 120' can perform shift and addition operations to obtain the dot product of the first vector and the second vector. Figure 2, the inputs d0~d7 received by the addition module 120' from the register 110' can be equal to the pixel values of the pixel points p0~p7 respectively. It can be seen that the pixel values input to the operation circuit 100' earlier will be stored in more registers 110', which allows the pixel values of multiple pixel points to be transmitted to the addition module 120' within the same clock cycle to participate in the shift and addition operations. However, this setting will result in the existence of multiple registers 110' directly connected inside the operation circuit 100', which will lead to a greater risk of hold time violations, and solving these hold time violation problems often requires a great deal of effort. In addition, a large number of shift and addition operations may need to be performed in the addition module 120', which results in a generally large delay, thereby reducing the performance of the operation circuit 100' and increasing the area and power consumption of the operation circuit 100'.

[0061] In order to solve the above problems, the present disclosure proposes an operation circuit and a computing device including the same. In an exemplary embodiment of the present disclosure, Figure 3 As shown, the computing device 200 may include one or more computing circuits 100, wherein the computing circuit 100 may be used to calculate the dot product of a first vector and a second vector. In an embodiment of the present disclosure, the first vector may be a pre-known coefficient vector, so that the specific setting mode of various components in the computing circuit 100 can be determined according to the pre-known coefficients in the first vector. Compared with the case where both the first vector and the second vector are uncertain, the computing circuit 100 of the present disclosure only needs to consider the uncertain second vector, thereby helping to simplify the circuit structure of the computing circuit 100 and the computing device 200. Furthermore, in the case where the computing device 200 includes multiple computing circuits 100, at least two computing circuits 100 can run in parallel to improve computing efficiency.

[0062] In some embodiments, the operation circuit 100 and the computing device 200 including the same may be configured to perform image interpolation operations, and the operation thereof may refer to the above description of the operation circuit 100 and the computing device 200 including the same. Figure 1 As described above, for example, the pixel values of corresponding pixels can be input into the corresponding operation circuit 100 in the computing device 200 according to the pixel rows, pixel columns or diagonals in the image to achieve the desired image interpolation operation, which will not be described in detail here. It is understood that in other embodiments, the computing device 200 and operation circuit 100 of the present disclosure can also be used for vector dot product operations and the like involved in other application scenarios, which is not limited here.

[0063] In the present disclosure, examples of the computing device 200 may include, but are not limited to, video encoders, consumer electronic products, components of consumer electronic products, electronic test equipment, image processing equipment, cellular communication infrastructure such as base stations, etc. Examples of the computing device 200 may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, portable video cameras, cameras such as digital cameras, portable memory chips, peripheral devices, clocks, etc. In addition, the computing device 200 may include an incomplete product.

[0064] In an exemplary embodiment of the present disclosure, Figure 4 As shown, the operation circuit 100 may include a multi-stage addition module 120. The input end of the subsequent stage addition module 120 may be communicatively connected to the output end of the previous stage addition module 120 adjacent to the stage addition module 120. In some embodiments, two adjacent stages of addition modules 120 may be directly connected. Alternatively, in other embodiments, in order to improve the performance of the operation circuit 100, other components such as a register module 110 may be provided between the two adjacent stages of addition modules 120, as will be described in detail later. The subsequent stage addition module 120 may be configured to at least calculate the sum of the first operand output by the previous stage addition module 120 and the product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficient may be generated based on at least one element in the first vector, and the second operand may be generated based on at least one element in the second vector. By setting up the multi-stage addition module 120, the operation circuit 100 originally generated by the previous stage addition module 120 may be further configured to ... Figure 2 All the multiplication-accumulation operations or shift-and-addition operations to be performed by the single addition module 120' shown in the figure are converted into partial multiplication-accumulation operations or shift-and-addition operations respectively performed by multiple stages of addition modules 120. On the one hand, this can help reduce or even eliminate the situation where multiple registers are directly connected, thereby reducing or even eliminating the cost of repairing hold time violations. On the other hand, it can reduce the amount of operations of each stage of addition module 120, thereby helping to reduce delays, improve the performance of the operation circuit 100, and also reduce the area and power consumption of the operation circuit 100.

[0065] In some embodiments, the single-stage addition module 120 can be configured to perform calculations associated with one or more accumulated terms in the above formula (1) or formula (2). For example, when the dimensions of the first vector and the second vector are each 8, the dot product operation of the first vector and the second vector generally involves the accumulation of a total of 8 product terms, where each product term is obtained by multiplying the elements in the first vector and the second vector at the same position. In a specific example, the operation circuit 100 may include a two-stage addition module 120, wherein the first-stage addition module 120 may be configured to calculate , and the subsequent addition module 120 may be configured to calculate. Alternatively, in another specific example, the previous addition module 120 may be configured to calculate , and then the first-stage addition module 120 can be configured to calculate That is, the number of items accumulated by each level of adding module 120 is not limited. In addition, more levels of adding modules 120 can be provided in the operation circuit 100 to further reduce the amount of calculation that each level of adding module 120 may need to perform, which is also not limited here.

[0066] In some embodiments, a corresponding element in the first vector may be directly used as the first coefficient, and a corresponding element in the second vector may be used as the second operand, so that each stage of the addition module 120 performs the corresponding calculation. Alternatively, in other embodiments, the elements in the first vector and / or the second vector may be appropriately processed in advance to generate the corresponding first coefficient and / or second operand, thereby simplifying the calculation.

[0067] For example, the first vector may contain negative elements. While a direct subtraction calculation can be used to represent the negative coefficient, this may complicate the structure of the operation circuit 100. Alternatively, the subtraction calculation can be converted to an addition calculation by, for example, bitwise inverting the elements in the second vector that will be multiplied by the negative coefficient. In this case, the first coefficient can be the absolute value of a corresponding element in the first vector. It is understood that, depending on specific operational requirements, other methods may also be used to generate the corresponding first coefficient based on at least one element in the first vector, and this is not limited here.

[0068] For another example, during a dot product operation, if the elements of a first vector that are multiplied by two or more elements of a second vector have equal absolute values, the sum or difference of the two or more elements of the second vector may be first calculated, and then the product of the resulting sum or difference and the coefficients may be calculated. For example, if the first vector is A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector is B=(p0, p1, p2, p3, p4, p5, p6, p7), the values of p0+p7, p1+p6, p2+p5, or p3+p4 may be calculated first, and then their products with the corresponding coefficients may be calculated. In this case, the second operand may be the sum or difference of the two or more elements of the second vector, or may be the bitwise inverse of the above sum or difference. Alternatively, as will be described in detail later, the second operand may also be a preset multiple of an element in the second vector, or a preset multiple of the sum or difference of multiple elements, etc., to help reduce the number of shift and / or addition calculations required to be performed in the corresponding addition module 120. It will be understood that, depending on specific computational requirements, other methods may also be used to generate the corresponding second operand based on at least one element in the second vector, and this is not limited here.

[0069] In a specific embodiment, when the dimensions of the first vector and the second vector are each N, the operation circuit 100 may have N-1 stages of addition modules 120, and each stage of addition module 120 may be configured to perform a calculation associated with a corresponding term to be accumulated in the above formula (1). Specifically, the 0th stage addition module (i.e., the first stage addition module) 120 may be configured to calculate A0*B0+A1*B1, wherein A0 may be a first coefficient generated according to the 0th element a0 in the first vector A, A1 may be a first coefficient generated according to the 1st element a1 in the first vector A, B0 may be a second operand generated according to the 0th element b0 in the second vector B, and B1 may be a second operand generated according to the 1st element b1 in the second vector B; and the i-th stage addition module may be configured to calculate S i +A i+1 *B i+1 , where S i It can be the first operand output by the i-1th level addition module, A i+1 It can be based on the i+1th element a in the first vector A i+1 The first coefficient generated, and B i+1 It can be based on the i+1th element b in the second vector B i+1The generated second operand, where i is an integer and 0 < i < N - 1. Especially when each element in the second vector or the second operand generated according to the element is provided to the arithmetic circuit 100 within a corresponding clock cycle, this setting method can eliminate the direct connection of the registers in the arithmetic circuit 100, thereby improving the performance of the arithmetic circuit.

[0070] In some embodiments, such as Figure 4 and Figure 5 shown, the arithmetic circuit 100 may further include one or more data transmission lines 130. Each data transmission line 130 may be formed by, for example, a data bus. Each data transmission line 130 may be communicatively connected to at least one stage of the addition module 120, and the data transmission line 130 may be configured to transmit the elements in the second vector or the second operand to the corresponding addition module. Which addition modules 120 each data transmission line 130 is specifically communicatively connected to may be determined according to the coefficients in the first vector, and this is not limited herein. In a specific example, as Figure 4 shown, each stage of the multi-stage addition module 120 may be respectively communicatively connected to the same data transmission line 130, so that the data transmission line 130 can sequentially transmit the elements in the second vector or the second operand to the corresponding addition module 120. In another specific example, as Figure 5 shown, the same addition module 120 may be communicatively connected to multiple data transmission lines 130 simultaneously to obtain all the data required for the operation of the addition module 120. For example, in the case where multiple product terms in formula (1) are to be accumulated in the addition module 120 (the addition module 120 may need to respectively obtain different elements in the second vector or different second operands from different data transmission lines 130), or in the case of performing a multiply-accumulate operation based on a preset multiple of the corresponding element in the second vector as described later (the addition module 120 may need to respectively obtain the element in the second vector and the preset multiple of the element from different data transmission lines 130).

[0071] In some embodiments, as mentioned above, to simplify operations, at least one stage of the multi-stage addition module 120 may be configured to obtain a third operand and to determine, based on the product of the second coefficient multiplied by the third operand, the product of the corresponding set of first coefficients and the second operand (it will be appreciated that, in some cases, the third operand may be equal to the second operand). The third operand may be a preset multiple of the corresponding fourth operand, and the fourth operand may be generated based on at least one target element in the second vector. In the dot product calculation, the absolute value of the element in the first vector multiplied by the target element in the second vector is greater than or equal to the absolute value of the preset multiple, and the preset multiple is greater than 1. Thus, by pre-calculating the preset multiples of at least some of the target elements in the second vector, the number of shifts and / or addition / subtraction operations required to be performed by the corresponding addition module 120 may be reduced, thereby simplifying the structure of the operation circuit 100.

[0072] Further, in order to generate the third operand, in a specific example, as Figure 5 As shown, the operation circuit 100 may further include a multiple operation module 140. The multiple operation module 140 may be configured to calculate a preset multiple of the fourth operand to generate a third operand. In other words, the third operand is equal to the product of the fourth operand and the preset multiple. Alternatively, in other specific examples, other methods may be used to obtain the third operand without providing the multiple operation module 140 in the operation circuit 100. This is not limited here.

[0073] In some specific examples, the fourth operand can be generated based on a single target element in the second vector. For example, the fourth operand can be a target element in the second vector itself. Alternatively, the fourth operand can be equal to the bitwise inversion of a target element in the second vector. In particular, when the element in the first vector corresponding to the target element is negative, the bitwise inversion operation can convert the subtraction calculation in the dot product operation into an addition calculation, thereby further simplifying the structure of the operation circuit 100.

[0074] In other specific examples, the fourth operand can be generated based on at least two target elements in the second vector. For example, during the dot product operation, if the elements in the first vector that are multiplied by two or more target elements in the second vector have absolute values equal to each other, then the sum or difference of the two or more target elements in the second vector can be calculated first, and then the product of the obtained sum or difference and the coefficient can be calculated. For example, when the first vector is A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector is B=(p0, p1, p2, p3, p4, p5, p6, p7), the values of p0+p7, p1+p6, p2+p5 or p3+p4 can be calculated first, and then the products of them and the corresponding coefficients can be calculated. That is to say, as needed, the fourth operand can be the sum or difference of two or more target elements, or it can also be equal to the bitwise inversion of the above-mentioned sum or difference. It is understandable that, as needed, the fourth operand may also be obtained by calculating one or more target elements in the second vector in other ways, which is not limited here.

[0075] In addition, it should be noted that, in the second vector, there may be multiple target elements that meet the above conditions, but in some embodiments of the present disclosure, it is not necessarily necessary to ultimately convert all target elements into the form of a third operand. For example, if an element in the first vector is 6 and the preset multiple is 5, then for the element b in the second vector that is multiplied by the coefficient 6, the multiple operation module 140 can be used to calculate 5b, thereby expressing 6b in the form of 5b+b for further calculation. Alternatively, 6b can be expressed in the form of 4b+2b instead of calculating 5 times this element for further calculation. The number of addition operations brought about by these two methods is the same. Generally speaking, it is only necessary to generate the corresponding third operand based on a part of the target elements, so as to reduce the number of required shifts and / or addition calculations, thereby simplifying the operation circuit 100 to a certain extent.

[0076] In some embodiments, the arithmetic circuit 100 may include one or more multiplication operation modules 140 to convert the corresponding fourth operand into the third operand. In addition, when there are multiple multiplication operation modules 140, these multiplication operation modules 140 can be used to calculate the product of the corresponding fourth operand and the same preset multiplication multiple. Alternatively, as needed, multiple different preset multiplication multiples can also be set. In this case, these multiplication operation modules 140 can also be used to calculate multiple preset multiplication multiples of the same fourth operand, which is not limited here.

[0077] In some embodiments, the preset multiple can be determined based on the first vector. Generally speaking, the larger the preset multiple, the more likely it is to convert the multiplication calculation related to the coefficient with a larger absolute value in the first vector into fewer shift and / or addition calculations. However, for the coefficient with a smaller absolute value in the first vector, it generally cannot be rewritten into a form related to the preset multiple, but can only use the original shift and addition calculation method. Therefore, the specific value of the preset multiple can be weighed according to the specific first vector. In order to simplify the operation, the preset multiple can be an integer. Furthermore, in some embodiments, considering that multiples of integer powers of 2 can be achieved through shift operations, the preset multiple can be set to an odd number or a prime number to simplify the operation as much as possible. For example, the preset multiple can include at least one of 3 times, 5 times and 7 times. In some specific examples below, the technical solution of the present disclosure will be described in detail using a preset multiple of 5 times as an example.

[0078] In some embodiments, as Figures 6 to 8 As shown, the multiple operation module 140 may include one or more multiple calculation units, wherein the multiple calculation unit may include a first shifter 141 or a first addition unit 142 .

[0079] exist Figure 6 In the specific example shown, the multiple calculation unit may include a first shifter 141, which may be configured to shift the sixth operand to the left by p bits to generate a seventh operand, that is, the seventh operand is 2 p times the sixth operand, wherein the sixth operand can be a positive integer multiple of the second operand, and p is a positive integer. For example, the value of m can be 1. Depending on the specific value of the sixth operand, the first shifter 141 can be configured to generate various even multiples of the second operand.

[0080] exist Figure 7 In the specific example shown, the multiple calculation unit may include a first adding unit 142, and the first adding unit 142 may be configured to add the eighth operand and the ninth operand to produce the tenth operand, that is, the tenth operand is the sum of the eighth operand and the ninth operand, wherein the eighth operand can be a second operand of a positive integer multiple, and the ninth operand can be a second operand of a positive integer multiple. As can be seen from this, depending on the specific value of the eighth operand and the ninth operand, the first adding unit 142 may be configured to produce the second operand of various integer multiples. In some specific examples, the first adding unit 142 may include an adder, to perform the addition of two operands.

[0081] In addition, various multiple calculation units can also be used in combination, which is not limited here. Figure 8In the specific example shown, the first adding unit 142 may be connected to the output end of the first shifter 141 to conveniently generate the required third operand.

[0082] Furthermore, in some embodiments, Figures 6 to 8 As shown, the multiple operation module 140 may further include a first register 143, the first register 143 may be communicatively connected to at least one multiple calculation unit, and the first register 143 may be configured to register the seventh operand or the tenth operand from the multiple calculation unit. Figures 6 to 8 In the specific example shown, the first register 143 can be connected to the output of the last-stage multiple calculation unit in the multiple operation module 140, thereby reducing glitches in the signal, helping to control the timing in the operation circuit 100, and ensuring the correct execution of the operation. However, in other embodiments, particularly when the addition module 120 of the operation circuit 100 is communicatively connected to the register module 110, the first register 143 in the multiple operation module 140 can be omitted, and the register module 110 can instead implement the desired register function, thereby simplifying the structure of the operation circuit 100 and reducing the area of the operation circuit 100.

[0083] In some embodiments, as Figure 5 As shown, one end of at least one data transmission line 130 in the operation circuit 100 can be communicatively connected to the multiplication operation module 140, and the other end can be communicatively connected to the corresponding addition module 120, thereby transmitting the third operand from the multiplication operation module 140 to the corresponding addition module 120.

[0084] As described above, the addition module 120 can be configured to determine a corresponding set of products obtained by multiplying the first coefficient and the second operand based on the product obtained by multiplying the second coefficient and the third operand. Wherein, for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple can be less than or equal to the first coefficient. It should be noted that, in this specific example, the fourth operand that has not yet been multiplied by the preset multiple is used as the second operand. For example, if the first vector A=(5, 15, -10, 5, 5, -10, 15, 5) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), the preset multiple is 5, the operation circuit 100 has 7 levels of addition modules 120, and each level of addition module 120 is configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1), then for each level of addition module 120, the product of the second coefficient and the preset multiple is equal to the first coefficient, that is, the product obtained by multiplying the second coefficient and the third operand is equal to the product obtained by multiplying the corresponding set of first coefficients and the second operand. Taking the first level addition module 120 in the operation circuit 100 as an example, it can be configured to calculate , the third operand 5p1 can be pre-calculated by the multiplication operation module 140, and the second coefficient corresponding to the third operand 5p1 is 3.

[0085] In some embodiments, depending on the specific value of the first coefficient in the first vector, a target element in the second vector may be converted into the form of the sum of the third operand and the product of the target element and an integer power of 2. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the corresponding addition module 120 can also be configured to determine the product of a corresponding set of first coefficients and the second operand based on the product of the third coefficient and the fourth operand corresponding to the third operand, wherein, for each fourth operand and the corresponding third operand, the product of the second coefficient and the preset multiple plus the sum of the third coefficient is equal to the first coefficient. It should be noted that in this specific example, the fourth operand that has not yet been multiplied by the preset multiple is also used as the second operand. For example, if the first vector A=(5, 16,-10, 5, 5, -10, 15, 5) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), the preset multiple is 5, the operation circuit 100 has 7 levels of addition modules 120, and each level of addition module 120 is configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1), then for the first level addition module 120, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient. That is, the first level addition module in the operation circuit 100 can be configured to calculate , where the third operand 5p1 can be pre-calculated by the multiplication operation module 140. In addition, for the term related to the fourth operand p1, its second coefficient is 3 and the third coefficient is 1, that is, 16p1=3*5p1+1*p1.

[0086] In some embodiments, depending on the specific value of the first coefficient in the first vector, an element in the second vector may not be converted into a form containing the third operand. In this case, in order to correctly calculate the dot product of the first vector and the second vector, the corresponding addition module 120 can also be configured to determine the product of the corresponding set of first coefficients and the second operand based on the product obtained by multiplying the first coefficient and the fifth operand. The fifth operand can be generated based on at least one element in the second vector other than the element used to generate the fourth operand. In some specific examples, the fifth operand can be generated based on a single element in the second vector. For example, the fifth operand can be an element in the second vector itself. Alternatively, the fifth operand can be equal to the bitwise inversion of an element in the second vector. In particular, when the coefficient corresponding to this element in the first vector is negative, the bitwise inversion operation can convert the subtraction calculation in the dot product operation into an addition calculation, thereby further simplifying the structure of the operation circuit 100. In other specific examples, the fifth operand can be generated based on at least two elements in the second vector. For example, during the dot product operation, if the coefficients of the first vector multiplied by two or more elements in the second vector have equal absolute values, then the sum or difference of the two or more elements in the second vector can be first calculated, and then the product of the sum or difference and the coefficients can be calculated, similar to the explanation above for the fourth operand. As needed, the fifth operand can be the sum or difference of the two or more elements in the second vector, or can be equal to the bitwise negation of the above sum or difference. It is understood that, as needed, the fifth operand can also be obtained by calculating one or more elements in the second vector in other ways, without limitation. For example, if the first vector A=(-1, 4, -11, 40,40, -11, 4, -1), the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7), the preset multiplier is 5, the operation circuit 100 has 7 levels of addition modules 120, and each level of addition module 120 is configured to perform a calculation associated with a corresponding item to be accumulated in the above formula (1), then for the first level of addition module 120, it can be configured to calculate , the first coefficient corresponding to the fifth operand p1 is 4.

[0087] In some embodiments, as Figure 9 As shown, the adding module 120 may include at least one of a second shifter 121 and a second adding unit 122 .

[0088] The second shifter 121 may be configured to shift the eleventh operand to the left by q bits to generate a twelfth operand, that is, the twelfth operand is 2 qThe eleventh operand is a multiple of the first operand A and the second operand B, where the eleventh operand may be generated based on the second operand, for example, the third operand, the fourth operand, or the fifth operand (depending on the specific dot product operation), and q is a positive integer. In a special case, if the dot product of the first vector A and the second vector B can be expressed as the product of a single operand and an integer power of 2, then the addition module 120 may only include the second shifter 121.

[0089] The second adding unit 122 can be configured to calculate the sum of at least two operands, where the at least two operands may include the first operand output by the previous adding module 120, one or more operands output by the corresponding second shifter 121, or a preset constant. Specifically, if the adding module 120 is not the first adding module, it can be configured to perform addition related to the first operand output by the previous adding module 120. Furthermore, the second adding unit 122 can be configured to calculate the sum of at least a portion of the products of the third operand and the second coefficient, the fourth operand and the third coefficient, and the fifth operand and the first coefficient involved in the adding module 120 in which it resides (depending on the specific dot product operation). Furthermore, in cases involving bitwise inversion of elements in the first or second vector to convert a subtraction operation into an addition operation, the second adding units 122 in at least some adding modules 120 can also be configured to perform addition with a preset constant resulting from the bitwise inversion operation to obtain a correct dot product result, as will be explained in detail below.

[0090] In some specific examples, the second addition unit 122 can be implemented by a compression tree. The compression tree can efficiently compress multiple data into the form of the sum of two or three data. In addition, as needed, the shift operation of the relevant data can be implemented inside the compression tree, thereby realizing the shift and addition operations involved in the dot product operation, and shifting and compressing multiple numbers into the sum of two or three numbers. Common compression trees can include compression trees with two output ends such as 4:2 compression trees and 3:2 compression trees, and can also include compression trees with three output ends such as 5:3 compression trees, 6:3 compression trees, and 7:3 compression trees. The compression tree here can be a compression tree with any number of input and output ends that is currently available or developed in the future, or it can be a compression tree module with any number of input and output ends that is implemented by combining multiple existing compression trees.

[0091] In some other specific examples, the second adding unit 122 may also be alternatively implemented as a full adder or a combination of a full adder and a half adder, etc. In this case, it may be necessary to use the second shifter 121 and the second adding unit 122 in combination to implement the shift and addition calculations in the dot product operation.

[0092] In some further specific examples, the second adder unit 122 may include a compression tree and a full adder or a combination of a full adder and a half adder. For example, for the sake of simplicity, in the embodiments of the present disclosure, a compression tree with two output terminals may be adopted, and then the two output data of the compression tree are added by an adder to obtain the final dot product operation result.

[0093] In some embodiments, as Figure 4 and Figure 5 shown, the arithmetic circuit 100 may further include one or more storage modules 110, and the storage module 110 may be communicatively connected to the input end or the output end of the corresponding first-stage adder module 120 in the multi-stage adder module 120, so as to store the data from the adder module 120 as needed. In a specific example, the storage module 110 may be formed by registers and the like.

[0094] In some embodiments, as Figure 4 and Figure 5 shown, when the arithmetic circuit 100 has an M-stage adder module 120, the arithmetic circuit may include at least M storage modules 110. Among them, the output end of the mth-stage adder module 120 may be communicatively connected to the input end of the mth storage module 110, and the mth storage module 110 may be configured to store the first operand output by the mth-stage adder module 120, where m is an integer and 0≤m<M. By setting a corresponding storage module 110 for each stage of the adder module 120, the glitches in the signal can be effectively reduced or even eliminated, which helps to control the correct timing in the arithmetic circuit 100, thereby improving the performance of the arithmetic circuit 100.

[0095] Furthermore, in some embodiments, as Figure 4 and Figure 5 shown, one or more storage modules 110 may include a primary storage module 110, and the primary storage module 110 may be communicatively connected to the input end of the 0th-stage adder module 120, and the primary storage module 110 may be configured to store A0*B0, where A0 may be a first coefficient generated according to the 0th element a0 in the first vector, and B0 may be a second operand generated according to the 0th element b0 in the second vector. In Figure 4 and Figure 5 the specific example shown, the primary storage module 110 may also be communicatively connected to at least one data transmission line 130 to obtain the 0th element or the corresponding second operand in the second vector.

[0096] As mentioned above, when the first vector includes negative coefficients, in order to simplify the operation, the subtraction in the dot product operation can be converted into addition by a bit-by-bit inversion operation. For example, when a negative number is represented by two's complement, (-1)*b=~b+1, where ~b is the bit-by-bit inversion of b. It can be seen that the product of a negative coefficient and an element in the second vector can be expressed as the sum of the product of the absolute value of the coefficient and the element and a constant term, where the constant term is determined according to the specific value of the coefficient, and the constant term can be extracted for subsequent processing. Accordingly, in some embodiments, such as Figure 10 As shown, the operation circuit 100 may further include a bit-by-bit inversion module 150, which may be configured to, when the first coefficient in the first vector is a negative number, bit-by-bit invert at least one operand generated by multiplying the element in the second vector by the element in the first vector. As needed, the bit-by-bit inversion module 150 may be provided outside the addition modules 120 at each level, or the bit-by-bit inversion module 150 may be included within at least one level of addition modules 120, without limitation herein. Based on the constant term extracted during the bit-by-bit inversion process, a preset constant as described above may be determined, and the preset constant may be added to the dot product operation result at an appropriate position, without limitation herein. In some embodiments, the bit-by-bit inversion module 150 may be formed by a plurality of inverters. Alternatively, the bit-by-bit inversion module 150 may be formed in other ways, without limitation herein.

[0097] In a specific embodiment of the present disclosure, taking the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7) as an example, the operation circuit has the following steps: Figure 4 The eight register modules 110 and the seven-stage adding module 120 are arranged in a manner as shown in FIG. 1 . The data transmission lines in the arithmetic circuit 100 can sequentially transmit pixel values p0, p1, p2, p3, p4, p5, p6, and p7. The operation process can be described as follows:

[0098] First, the primary register module 110 obtains din=p0 and registers S0=-p0;

[0099] Then, the 0th stage addition module 120 calculates S1=S0+4din and registers S1 in the 0th register module 110 connected to the output terminal of the 0th stage addition module 120, where din=p1;

[0100] Then, the first-stage adding module 120 calculates S2=S1-8din-2din-din, and stores S2 in the first register module 110 connected to the output terminal of the first-stage adding module 120, where din=p2;

[0101] Then, the second-stage adding module 120 calculates S3=S2+32din+8din, and stores S3 in the second register module 110 connected to the output terminal of the second-stage adding module 120, where din=p3;

[0102] Then, the third-stage adding module 120 calculates S4=S3+32din+8din, and stores S4 in the third register module 110 connected to the output terminal of the third-stage adding module 120, where din=p4;

[0103] Then, the 4th stage adding module 120 calculates S5=S4-8din-2din-din, and registers S5 in the 4th register module 110 connected to the output terminal of the 4th stage adding module 120, where din=p5;

[0104] Then, the fifth-stage adding module 120 calculates S6=S5+4din and registers S6 in the fifth register module 110 connected to the output terminal of the fifth-stage adding module 120, where din=p6;

[0105] Finally, the sixth-stage addition module 120 calculates S7=S6−din and stores S7 in the sixth register module 110 connected to the output terminal of the sixth-stage addition module 120 , ie, the dot product operation result of the first vector and the second vector.

[0106] In another specific example of the present disclosure, taking the first vector A=(-1, 4, -11, 40, 40, -11, 4, -1) and the second vector B=(p0, p1, p2, p3, p4, p5, p6, p7) as an example, the operation circuit 100 has the following steps: Figure 5 The eight register modules 110 and the seven-stage adding modules 120 are arranged in a manner, and the arithmetic circuit 100 has two data transmission lines 130 for transmitting din and 5din respectively. The data transmission line 130 for transmitting din can be connected to the primary register module 110 and the adding modules 120 of the 0th, 1st, 4th, 5th, and 6th stages, while the data transmission line 130 for transmitting 5din can be connected to the adding modules 120 of the 1st, 2nd, 3rd, and 4th stages. The operation process of the arithmetic circuit 100 can be described as follows:

[0107] First, the primary register module 110 obtains din=p0 and registers S0=-p0;

[0108] Then, the 0th stage addition module 120 calculates S1=S0+4din and registers S1 in the 0th register module 110 connected to the output terminal of the 0th stage addition module 120, where din=p1;

[0109] Then, the first-stage adding module 120 calculates S2=S1-2*5din-din, and stores S2 in the first register module 110 connected to the output terminal of the first-stage adding module 120, where din=p2;

[0110] Then, the second-stage adding module 120 calculates S3=S2+8*5din and stores S3 in the second register module 110 connected to the output terminal of the second-stage adding module 120, where din=p3;

[0111] Then, the third-stage adding module 120 calculates S4=S3+8*5din, and stores S4 in the third register module 110 connected to the output terminal of the third-stage adding module 120, where din=p4;

[0112] Then, the 4th stage adding module 120 calculates S5=S4-2*5din-din, and registers S5 in the 4th register module 110 connected to the output terminal of the 4th stage adding module 120, where din=p5;

[0113] Then, the fifth-stage adding module 120 calculates S6=S5+4din and registers S6 in the fifth register module 110 connected to the output terminal of the fifth-stage adding module 120, where din=p6;

[0114] Finally, the sixth-stage addition module 120 calculates S7=S6−din and stores S7 in the sixth register module 110 connected to the output terminal of the sixth-stage addition module 120 , ie, the dot product operation result of the first vector and the second vector.

[0115] In the technical solution disclosed herein, by converting a single multiplication-accumulation operation on multiple sets of data, performed by a single addition module in a dot product operation, into a hierarchical multiplication-accumulation operation, performed separately by multiple addition modules, where each addition module can be used to perform multiplication-accumulation operations on fewer sets of data, the logic for directly connecting registers in the arithmetic circuit used to perform the dot product operation can be reduced or even eliminated, thereby effectively reducing or even eliminating the risk of hold time violations in the arithmetic circuit. Furthermore, because each addition module performs fewer multiplication-accumulation operations or shift-and-addition operations, it can be formed from relatively simple addition units (e.g., a small number of adders), thereby reducing operation delays, improving the performance of the arithmetic circuit and the computing device containing it, and reducing the area and power consumption of the arithmetic circuit and the computing device containing it. In addition, because the number of stages of combinational logic is reduced, signal glitches can be effectively controlled, further optimizing the power consumption of the arithmetic circuit and the computing device. In some embodiments, preset multiples of certain elements involved in the vector dot product operation can also be pre-calculated, effectively reducing the number of shifts and / or additions required in subsequent calculations, thereby reducing the number of shifters and / or addition units required in the addition module, making the structure of the operation circuit simpler, reducing the circuit area, shortening the critical path, facilitating timing convergence, reducing circuit delays, and lowering circuit power consumption. In some examples, the operation circuit and computing device disclosed herein can be used in the field of image interpolation, thereby effectively improving the efficiency and effectiveness of image processing.

[0116] The terms "left," "right," "front," "back," "top," "bottom," "upper," "lower," "higher," "lower," and the like, if used in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein. For example, when the device in the drawings is turned over, a feature previously described as "above" other features could then be described as "below" the other features. The device can also be otherwise oriented (rotated 90 degrees or at other orientations), and relative spatial relationships would be interpreted accordingly.

[0117] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "in contact with," etc., another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly in contact with the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly" "on," "directly attached," "directly connected," "directly coupled," or "in direct contact with" another element, there will be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0118] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0119] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0120] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0121] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0122] In addition, when used in this application, the words "herein," "above," "below," "hereunder," "supra," and words of similar meaning shall refer to this application as a whole and not to any particular portion of this application. Furthermore, unless expressly stated otherwise or understood otherwise in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to express that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments in any way require features, elements, and / or states, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0123] In the present disclosure, the term "providing" is used in a broad sense to cover all ways of obtaining an object, so "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" an object, etc. In addition, in the present disclosure, the terms "circuit", "unit" and "module" can be used interchangeably.

[0124] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0125] Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed across additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all of the embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative rather than restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0126] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0127] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. An arithmetic circuit, characterized in that: The operation circuit is at least used to calculate the dot product of a first vector and a second vector, wherein the first vector is a pre-known coefficient vector, and the operation circuit includes: a multi-stage addition module, wherein an input terminal of a subsequent stage addition module is communicatively connected to an output terminal of a previous stage addition module adjacent to the stage addition module, the subsequent stage addition module being configured to at least calculate a sum of a first operand output by the previous stage addition module and a product obtained by multiplying at least one set of first coefficients and second operands, wherein the first coefficients are generated based on at least one element in a first vector and the second operands are generated based on at least one element in a second vector; a first data transmission line communicatively connected to at least one first adding module of the multi-stage adding module, and the first data transmission line is configured to transmit the second operand to the corresponding first adding module; and a second data transmission line communicatively connected to at least one second adding module in the multi-stage adding module, and the second data transmission line is configured to transmit a third operand to the corresponding second adding module, wherein the third operand is a preset multiple of the corresponding fourth operand, and the fourth operand is generated based on at least one element in the second vector, and the preset multiple is greater than 1; Wherein, in the case where the addition module is only the first addition module, the addition module is configured to use the product obtained by multiplying the first coefficient and the fifth operand as the product obtained by multiplying the corresponding set of first coefficients and the second operand, and the fifth operand is generated based on at least one element in the second vector other than the element used to generate the third operand, In a case where the addition module is only the second addition module, the addition module is configured to use a product obtained by multiplying the second coefficient and the third operand as a product obtained by multiplying a corresponding set of first coefficients and the second operand, wherein, for the fourth operand and the corresponding third operand, a product of the second coefficient and the preset multiple is equal to the first coefficient, In the case where the addition module is both the first addition module and the second addition module, the addition module is configured to use the sum of the following products as the products obtained by multiplying a corresponding set of first coefficients and the second operand: the product obtained by multiplying the second coefficient and the third operand and the product obtained by multiplying the third coefficient and the fourth operand corresponding to the third operand, wherein, for the fourth operand and the corresponding third operand, the sum of the product of the second coefficient and the preset multiple plus the third coefficient is equal to the first coefficient.

2. The arithmetic circuit according to claim 1, wherein: When the dimensions of the first vector and the second vector are each N, the operation circuit has an N-1-stage addition module, wherein: The 0th stage addition module is configured to calculate A0*B0+A1*B1, where A0 is a first coefficient generated based on the 0th element a0 in the first vector, A1 is a first coefficient generated based on the 1st element a1 in the first vector, B0 is a second operand generated based on the 0th element b0 in the second vector, and B1 is a second operand generated based on the 1st element b1 in the second vector; and The i-th stage addition module is configured to calculate S i +A i+1 *B i+1 , where S i is the first operand output by the i-1th level addition module, A i+1 It is based on the i+1th element a in the first vector i+1 The first coefficient generated, and B i+1 It is based on the i+1th element b in the second vector i+1 The second operand generated, where i is an integer and 0 <i<N-1。 3. The operation circuit according to claim 1, wherein: The operation circuit further includes: A multiple operation module is configured to calculate a preset multiple of the fourth operand to generate a corresponding third operand.

4. The operation circuit according to claim 3, wherein: The preset multiple is determined based on the first vector; or The preset magnification includes at least one of 3 times, 5 times, and 7 times.

5. The operation circuit according to claim 3, wherein: The multiple operation module includes one or more multiple calculation units, each of which includes: A first shifter is configured to shift the sixth operand to the left by p bits to generate a seventh operand, wherein the seventh operand is 2 p times the sixth operand, the sixth operand is a positive integer multiple of the second operand, and p is a positive integer; or A first adding unit is configured to add an eighth operand and a ninth operand to generate a tenth operand, wherein the eighth operand is a positive integer multiple of the second operand and the ninth operand is a positive integer multiple of the second operand.

6. The operation circuit according to claim 1, wherein: The addition module includes at least one of the following: A second shifter is configured to shift the eleventh operand left by q bits to generate a twelfth operand, wherein the twelfth operand is 2 q times an eleventh operand, the eleventh operand being generated based on the second operand, and q being a positive integer; and A second adding unit is configured to calculate the sum of at least two operands, wherein the at least two operands include a first operand output by a previous stage adding module, one or more operands output by a corresponding second shifter, or a preset constant.

7. The operation circuit according to claim 1, wherein: The operation circuit further includes: One or more register modules, wherein the register modules are communicatively connected to the input end or the output end of the corresponding first-stage adding module in the multi-stage adding module.

8. The operation circuit according to claim 7, wherein: In the case where the arithmetic circuit has M-stage addition modules, the arithmetic circuit includes at least M register modules, wherein the output end of the m-th stage addition module is communicatively connected to the input end of the m-th register module, and the m-th register module is configured to register the first operand output by the m-th stage addition module, wherein m is an integer and 0≤m <M。 9. The operation circuit according to claim 7, wherein: The one or more register modules include a primary register module, which is communicatively connected to the input end of the 0th stage addition module, and the primary register module is configured to store A0*B0, where A0 is a first coefficient generated based on the 0th element a0 in the first vector, and B0 is a second operand generated based on the 0th element b0 in the second vector.

10. The operation circuit according to claim 1, wherein: The operation circuit further includes: A bitwise inversion module is configured to, when an element in the first vector is a negative number, bitwise invert at least one operand generated by multiplying an element in the second vector by the element in the first vector.

11. The operation circuit according to claim 1, wherein: The operation circuit is configured to perform an image interpolation operation, the first vector is a coefficient vector for image interpolation, and at least two elements of the second vector are not provided to the operation circuit at the same time.

12. A computing device, characterized in that: The computing device includes one or more computing circuits, and the computing circuit is the computing circuit according to any one of claims 1 to 11.

13. The computing device according to claim 12, wherein: In the case where the computing device includes a plurality of arithmetic circuits, at least two arithmetic circuits operate in parallel.

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