Transistor device with gate cut and method of manufacturing the same

Abstract

Transistor devices, and related methods of forming transistor devices, are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor on top of the lower transistor. Further, the transistor device includes a gate cut-out on the substrate and adjacent to the transistor stack. The gate cut-out has a first sloped sidewall and a second sloped sidewall opposite the first sloped sidewall.

Description

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 597,287 filed on November 8, 2023 and U.S. Patent Application No. 18 / 678,183 filed on May 30, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to devices having gate cuts between transistor structures. Background Art

[0003] The size of transistors in integrated circuit devices has continued to decrease to scale down logic elements. This has led to the development of devices such as multi-bridge channel field effect transistors (MBCFETs). TM ) and the development of gate-all-around (GAA) structures for nanosheet FETs (NSFETs). In addition, as technology for increasing transistor density continues to advance, three-dimensional device structures (such as stacked transistors) are being considered. Summary of the invention

[0004] According to some embodiments herein, a transistor device may include a substrate and a transistor stack on the substrate. The transistor stack may include a lower transistor and an upper transistor on top of the lower transistor. In addition, the transistor device may include a gate cutout on the substrate and adjacent to the transistor stack. The gate cutout may have a first inclined sidewall and a second inclined sidewall opposite to the first inclined sidewall. An upper portion of the second inclined sidewall may be adjacent to the upper transistor and may be inclined toward the upper transistor.

[0005] According to some embodiments herein, a transistor device may include a substrate. The transistor device may include a first transistor stack and a second transistor stack spaced apart from each other in a lateral direction on the substrate. The first transistor stack and the second transistor stack each include a lower transistor and an upper transistor on top of the lower transistor. In addition, the transistor device may include a gate cut between the first transistor stack and the second transistor stack in a lateral direction. The upper transistor may include a plurality of semiconductor channel layers. The gate cut may extend in a vertical direction higher than the uppermost semiconductor channel layer of the plurality of semiconductor channel layers. The gate cut may include a concave first sidewall and a concave or convex second sidewall.

[0006] According to some embodiments herein, a method of forming a transistor device may include forming a polysilicon layer on a plurality of semiconductor channel layers of a transistor. The method may include forming a gate cut after forming the polysilicon layer. The step of forming the gate cut may include forming an insulating layer on the polysilicon layer. The polysilicon layer may be a sacrificial spacer, and the gate cut is separated from the plurality of semiconductor channel layers by the sacrificial spacer. In addition, the method may include forming a source / drain region on the sidewalls of the plurality of semiconductor channel layers after forming the gate cut. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic block diagram of a transistor stack of a transistor device according to some embodiments herein.

[0008] Figure 1B yes Figure 1A An example cross-sectional view of a transistor device.

[0009] Figure 1C yes Figure 1A Schematic block diagram of a gate cut between two transistor stacks of a transistor device.

[0010] Figure 1D , Figure 1F and Figure 1G yes Figure 1C Example cross-sectional view of a gate cutout.

[0011] Figure 1E yes Figure 1D Magnified view of the gate cutout.

[0012] FIG. 2A to FIG. 2AD It is shown that the formation Figure 1C A cross-sectional view of the operation of the transistor device.

[0013] Figure 3 is with FIG. 2A to FIG. 2AD The operations shown in FIG. DETAILED DESCRIPTION

[0014] According to embodiments herein, a transistor device is provided that includes a self-aligned gate cutout having an inclined sidewall. Each gate cutout may be formed on a sacrificial spacer that separates the gate cutout from an adjacent transistor. Because the gate cutouts are sufficiently spaced apart from adjacent transistors, they can solve problems with misalignment of transistors. In contrast, conventional gate cutouts may be misaligned so that the gate cutouts may damage adjacent transistors. For example, a misaligned conventional gate cutout may be so close to a transistor that the formation of the gate cutout (e.g., an etching operation / process for forming the gate cutout) may damage a channel layer or other layers of the transistor, or may affect the performance of the transistor.

[0015] In some embodiments, a transistor device may include a stacked transistor having a multi-bridge channel or nanosheet. As the pitch of the gate and the pitch of the nanosheet or multi-bridge channel continue to scale down, it may be difficult to implement a gate cut that separates adjacent stacked transistors. As an example, the space (e.g., lateral distance) between the gate cut and the stacked transistor (e.g., the bottom of the stacked transistor, such as, the active area of ​​the stacked transistor) may decrease as the pitch of the nanosheet or multi-bridge channel of the stacked transistor is scaled down, thereby increasing the risk of damaging (e.g., recessing) the stacked transistor during the formation of the gate cut. However, according to embodiments herein, self-alignment techniques may be implemented to form a gate cut that is sufficiently spaced from the stacked transistor to limit (e.g., prevent) damage to the stacked transistor.

[0016] Furthermore, although stacked transistors may be susceptible to gate cut misalignment and are described in the examples herein, the embodiments herein are not limited to stacked transistors. For example, the structures, features, and / or manufacturing operations disclosed herein may be applied to FinFETs or other non-stacked FETs.

[0017] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0018] Figure 1A 1 is a schematic block diagram of a transistor stack 101 of a transistor device 100 according to some embodiments herein. The transistor stack 101 includes a lower transistor Tb having a stacked plurality of lower semiconductor channel layers (or referred to as lower channel layers) 120b and an upper transistor Ta having a stacked plurality of upper semiconductor channel layers (or referred to as upper channel layers) 120a. The channel layers 120a, 120b may include, for example, silicon and may not contain germanium and carbon. The lower transistor Tb is between the upper transistor Ta and a substrate 110 (e.g., silicon or other semiconductor substrate) in the vertical direction Z. In addition, in some embodiments, an intermediate dielectric isolation layer (or referred to as an isolation layer) 130 may be used as a spacer between the upper transistor Ta and the lower transistor Tb.

[0019] The lower channel layer 120b of the lower transistor Tb is between a pair of lower source / drain (S / D) regions 140 electrically connected to the lower channel layer 120b in a first horizontal (i.e., lateral) direction X. The first horizontal direction X and the vertical direction Z may be perpendicular to each other, and the second horizontal (i.e., lateral) direction Y may be perpendicular to each of the first horizontal direction X and the vertical direction Z. Each lower channel layer 120b may be implemented by, for example, a nanosheet or a nanowire between the lower S / D regions 140. Similarly, the upper channel layer 120a of the upper transistor Ta may be between a pair of upper S / D regions 150 electrically connected to the upper channel layer 120a in the first horizontal direction X, and each upper channel layer 120a may be implemented by, for example, a nanosheet or a nanowire between the upper S / D regions 150.

[0020] In some embodiments, the upper S / D region 150 may include a semiconductor material different from the semiconductor material of the lower S / D region 140. As an example, the upper S / D region 150 may include silicon germanium and the lower S / D region 140 may include silicon carbide, or vice versa. In other embodiments, the upper S / D region 150 may include the same semiconductor material as the semiconductor material of the lower S / D region 140.

[0021] 1 for simplicity of illustration, only one semiconductor stack 101 is shown. However, according to some embodiments, the transistor device 100 may include two transistor stacks 101, three transistor stacks 101, four transistor stacks 101, or more transistor stacks 101.

[0022] Figure 1B yes Figure 1A An example cross-sectional view of a transistor device. Figure 1B As shown in FIG. 1 , a metal gate (or gate) 170 may be provided in the transistor stack 101 ( Figure 1A ) on the upper channel layer 120 a of the upper transistor Ta and on the lower transistor Tb ( Figure 1A ). The gate 170 may be spaced apart from the lower S / D region 140 in the first horizontal direction X by an insulating spacer (or referred to as a spacer) 172. The spacer 172 may be on the sidewall of the gate 170 and between the lower channel layers 120b in the vertical direction Z. Similarly, the gate 170 may be spaced apart from the upper S / D region 150 in the first horizontal direction X by the spacer 172, and the spacer 172 may be on the sidewall of the gate 170 and between the upper channel layers 120a in the vertical direction Z. In some embodiments, the spacer 172 may contact the sidewall of the gate 170, the lower S / D region 140, and the upper S / D region 150. The sidewall of the lower channel layer 120b may contact the lower S / D region 140, and the sidewall of the upper channel layer 120a may contact the upper S / D region 150.

[0023] Furthermore, the spacers 172 may include, for example, a nitride (eg, silicon nitride). Because the spacers 172 are located between nanosheet / nanowire channels within the transistor, the spacers 172 may also be referred to herein as "inter-spacers."

[0024] The upper transistor Ta and the lower transistor Tb may be different types of MOSFETs. For example, the upper transistor Ta and the lower transistor Tb may be a PMOS transistor and an NMOS transistor, respectively, or vice versa. As an example, the PMOS transistor and the NMOS transistor may be provided by S / D regions including silicon germanium and silicon carbide, respectively. In some embodiments, the isolation layer 130 may be a spacer separating the lower channel layer 120b of the lower transistor Tb from the upper channel layer 120a of the upper transistor Ta. The isolation layer 130 may include, for example, silicon boron carbon nitride (SiBCN).

[0025] For simplicity of illustration, Figure 1B The gate insulating layer is omitted from the view in FIG. However, it will be understood that the gate insulating layer may extend between each channel layer 120 a, 120 b and the metal gate 170 . The gate insulating layer may wrap each channel layer 120 a, 120 b and may be thinner than the isolation layer 130 .

[0026] According to some embodiments, the insulating layer 112 may be in the recess of the substrate 110. The insulating layer 114 may also be in the recess and may extend above the substrate 110 to, for example, the height of the uppermost surface of the gate 170. The insulating layer 152 may be between the lower S / D region 140 and the upper S / D region 150 in the vertical direction Z. In addition, the insulating layer 152 may be on the upper surface of each of the upper S / D regions 150. The insulating layer 132 may be between the sidewall of the insulating layer 114 and the gate 170, and the insulating layer 134 may be between the sidewall of the insulating layer 152 and the gate 170.

[0027] Insulating layers 132, 134 may include the same material as that of isolation layer 130 (e.g., SiBCN), and such insulating material may be different from the insulating material of insulating layer 112 and different from the insulating material of insulating layers 114, 152. In some embodiments, insulating layer 112 may include an insulating material different from the insulating material of insulating layers 114, 152. As an example, insulating layer 112 may include a nitride (e.g., silicon nitride), and insulating layers 114, 152 may each include an oxide (e.g., silicon oxide).

[0028] Figure 1C1 is a schematic block diagram of a gate cutout 160 between two transistor stacks 101a, 101b of a transistor device 100 in a second horizontal direction Y. The gate cutout 160 is on a substrate 110 and is adjacent to each of the transistor stacks 101a, 101b. As used herein with respect to the gate cutout 160 and the transistor stacks 101a, 101b on opposite sides of the gate cutout 160, the term "adjacent" means that no other transistor stack 101 is between the gate cutout 160 and the transistor stacks 101a, 101b. In addition, as used herein with respect to the sidewall of the gate cutout 160 and one of the transistor stacks 101a, 101b, the term "adjacent" means that the sidewall is closer to the other of the transistor stacks 101a, 101b than one of the transistor stacks 101a, 101b.

[0029] The transistor stack 101a is Figure 1A The transistor stack 101 is Figure 1C 101a to distinguish it from the transistor stack 101b. Figure 1C As shown in FIG. 1 , a first metal gate (or referred to as a first gate) 170a is on the transistor stack 101a and on the sidewall of the gate cutout 160, and a second metal gate (or referred to as a second gate) 170b is on the transistor stack 101b and on the sidewall of the gate cutout 160. The first gate 170a is Figure 1B The gate 170, and Figure 1C The gate cutout 160 is labeled as “170a” to distinguish it from the second gate 170b. The gate cutout 160 includes an insulating material (eg, silicon nitride) that electrically isolates the first gate 170a from the second gate 170b.

[0030] Figure 1D , Figure 1F and Figure 1G yes Figure 1C An example cross-sectional view of a gate cutout 160, and Figure 1E yes Figure 1D A magnified view of the gate cutout. Figure 1DAs shown in , the gate cutout 160 may be a gate cutout 160a that separates the first gate 170a from the second gate 170b, wherein the upper portion of the gate cutout 160a is closer to the transistor stack 101b than the transistor stack 101a in the second horizontal direction Y. For example, the uppermost upper channel layer 120a in the upper channel layer 120a in the transistor stack 101b is spaced apart from the upper portion of the gate cutout 160a (in the second horizontal direction Y) by a distance d1, and the distance d1 may be the shortest distance between the gate cutout 160a and any one of the transistor stacks 101a, 101b. The upper portion of the gate cutout 160a is angled (e.g., bent) toward the transistor stack 101b and away from the transistor stack 101a.

[0031] Transistor device 100 ( Figure 1C ) may include more than two transistor stacks 101. For example, transistor stack 101b may be between transistor stack 101a and transistor stack 101c. However, no other transistor stack 101 is between transistor stack 101a and transistor stack 101b. Therefore, no transistor stack 101 (in the second horizontal direction Y) is between gate cutout 160a and transistor stack 101a, or between gate cutout 160a and transistor stack 101b. In addition, although Figure 1D An example without a gate cut 160 between the transistor stack 101b and the transistor stack 101c is shown, but in some embodiments, the transistor device 100 may include a gate cut 160 between the transistor stack 101b and the transistor stack 101c. Figure 1C , Figure 1F and Figure 1G The transistor stack 101c is omitted from the illustration in FIG.

[0032] like Figure 1E As shown in FIG. 1 , the gate cutout 160a has a first inclined sidewall 166a and a second inclined sidewall 166b opposite to the first inclined sidewall 166a. The second inclined sidewall 166b is adjacent to the upper channel layer 120a ( Figure 1D ) is separated by a distance d1 ( Figure 1D ). Because the inclined sidewalls 166a, 166b are both inclined toward the uppermost upper channel layer 120a in the transistor stack 101b and away from the uppermost upper channel layer 120a in the transistor stack 101a ( Figure 1D ), so the gate cutout 160a is asymmetric with respect to the vertical axis.

[0033] In some embodiments, the inclined sidewalls 166a, 166b may be curved sidewalls having an upper portion that curves toward the transistor stack 101b and away from the transistor stack 101a as the height increases in the vertical direction Z. The first inclined sidewall 166a is a convex surface of the gate cutout 160a, and the second inclined sidewall 166b is a concave surface of the gate cutout 160a. In other embodiments, at least one of the inclined sidewalls 166a, 166b may be an inclined sidewall having an upper portion that is angled (e.g., inclined) toward the transistor stack 101b and away from the transistor stack 101a. The inclined sidewall has a constant slope and is neither parallel nor perpendicular to the vertical direction Z, but may form an acute angle (e.g., between 5 and 35 degrees) with the vertical direction Z. In contrast, the slope of the curved sidewall varies along a curve.

[0034] The upper portion of the gate cutout 160a is narrower than the lower portion of the gate cutout 160a. For example, the upper portion may include an uppermost surface 162 that is narrower than the lowermost surface 164 of the lower portion. The uppermost surface 162 may be coplanar with the uppermost surfaces of the gates 170a, 170b, and therefore may be higher (in the vertical direction Z) than the uppermost upper channel layer 120a in the transistor stack 101b. In some embodiments, the width w1 of the uppermost surface 162 (in the second horizontal direction Y) may be less than half of the width w2 of the lowermost surface 164 (in the second horizontal direction Y). In addition, the width of the gate cutout 160a may narrow monotonically as the height in the vertical direction Z increases. Therefore, the gate cutout 160a does not widen as the height increases from the lowermost surface 164 to the uppermost surface 162.

[0035] The opposite ends of the uppermost surface 162 may be defined by the uppermost point 168a of the first inclined sidewall 166a and the uppermost point 168b of the second inclined sidewall 166b. Since the upper portion of the gate cutout 160a is inclined toward the transistor stack 101b, the uppermost point 168b may not vertically overlap with the lower portion of the gate cutout 160a. Therefore, the vertical axis 182 passing through the uppermost point 168b does not pass through the lowermost surface 164, but passes through the gate 170b.

[0036] In some embodiments, the uppermost point 168a may vertically overlap the lower portion of the gate cutout 160a, as opposed to the uppermost point 168b, such that the vertical axis 180 passes through both the uppermost point 168a and the lowermost surface 164, but the vertical axis 180 may be closer (in the second horizontal direction Y) to the lowermost point of the second inclined sidewall 166b than to the lowermost point of the first inclined sidewall 166a. In other embodiments, both the uppermost points 168a, 168b may vertically overlap the gate 170b, but not the lower portion of the gate cutout 160a.

[0037] like Figure 1F As shown in FIG. , the gate cutout 160 is not limited to Figure 1E . In contrast, the gate cutout 160 may be a gate cutout 160b that is symmetrical with respect to a vertical axis (e.g., a vertical axis passing through a center point of an uppermost surface 162 of the gate cutout 160b and a center point of a lowermost surface 164 of the gate cutout 160b). In addition, the upper portion of the gate cutout 160b may be wider than the lower portion of the gate cutout 160b. For example, both the inclined sidewalls 166a, 166b of the gate cutout 160b may be concave surfaces of the gate cutout 160b. The inclined sidewalls 166a, 166b may be inclined away from each other as their height in the vertical direction Z increases. Therefore, as the first inclined sidewall 166a increases in height, the first inclined sidewall 166a may be bent toward the transistor stack 101a and away from the transistor stack 101b. Likewise, as the second sloped sidewall 166 b increases in height, the second sloped sidewall 166 b may curve toward the transistor stack 101 b and away from the transistor stack 101 a .

[0038] like Figure 1G As shown in , a plurality of gate cutouts 160 may be disposed between a pair of transistor stacks 101a, 101b. Figure 1D In addition to the gate cutout 160a shown in , another gate cutout 160c may be between the transistor stacks 101a and 101b in the second horizontal direction Y. The gate cutouts 160a and 160c are separated from each other (and therefore do not touch). The gate cutout 160c may be closer to the transistor stack 101a, and the gate cutout 160a may be closer to the transistor stack 101b. As with the gate cutout 160a, the upper portion of the gate cutout 160c (in the second horizontal direction Y) may be narrower than the lower portion of the gate cutout 160c. In addition, as the height increases in the vertical direction Z, the upper portion of the gate cutout 160c may be tilted away from the upper portion of the gate cutout 160a. Thus, the lower portion of the gate cutout 160 a and the lower portion of the gate cutout 160 c may be spaced apart from each other (in the second horizontal direction Y) by a distance d2 that is shorter than a distance d3 that the upper portion of the gate cutout 160 a and the upper portion of the gate cutout 160 c are spaced apart (in the second horizontal direction Y). In some embodiments, the gate cutouts 160 a, 160 c may be mirror images of each other with respect to the vertical axis.

[0039] FIG. 2A to FIG. 2AD It is shown that the formation Figure 1C A cross-sectional view of the operation of the transistor device 100. Figure 2A , Figure 2C , Figure 2E , Figure 2G , Fig.2I , Figure 2K , Figure 2M , Fig.2O , Figure 2Q , Figure 2S , Figure 2U , Figure 2W , Figure 2Y , Figure 2AA and Figure 2AC is a section in plane XZ, and Figure 2B , Figure 2D , Figure 2F , Figure 2H , Figure 2J , Figure 2L , Figure 2N , Figure 2P , Figure 2R , Figure 2T , Figure 2V , Figure 2X , Figure 2Z , Figure 2AB and Figure 2AD is a section in plane YZ. Figure 3 is with FIG. 2A to FIG. 2AD The operations shown in the flowchart correspond to the following.

[0040] like Figure 2A , Figure 2B and Figure 3 As shown, the operation may include forming a stack of semiconductor channel layers 120a, 120b on a substrate 110 (block 310). In some embodiments, the channel layers 120a, 120b may be nanosheets, and the stack may therefore be a nanosheet stack. The lower stack includes a lower channel layer 120b, and the upper stack includes an upper channel layer 120a. The lower stack is separated from the upper stack by a sacrificial isolation layer 272. In addition, sacrificial gate layers 270 and channel layers 120a, 120b may be alternately stacked on the substrate 110. The sacrificial isolation layer 272 may be between an upper one of the sacrificial gate layers 270 and a lower one of the sacrificial gate layers 270.

[0041] The upper stack and the lower stack each form a transistor stack 101 ( Figure 1A ) portion. The lower channel layer 120b forms the lower transistor Tb ( Figure 1A ) portion, and the upper channel layer 120 a forms an upper transistor Ta ( Figure 1A ) portion. A plurality of transistor stacks 101 may be spaced apart from each other on the substrate 110 and in the second horizontal direction Y. Therefore, Figure 2B It is shown that forming the transistor stack 101 may include forming a plurality of stacks of channel layers 120 a , 120 b spaced apart from each other in the second horizontal direction Y.

[0042] The channel layers 120a and 120b are semiconductor layers including, for example, silicon (eg, polysilicon). In subsequent processes / operations, the metal gate 170 ( Figure 1C ) to replace the sacrificial gate layer 270. In addition, the intermediate dielectric isolation layer 130 ( Figure 1B ) replaces the sacrificial isolation layer 272. The sacrificial gate layer 270 may include, for example, silicon germanium. Therefore, the sacrificial gate layer 270 may have an etching selectivity relative to the channel layers 120a, 120b. The sacrificial gate layer 270 may also have an etching selectivity relative to the sacrificial isolation layer 272. For example, the sacrificial isolation layer 272 and the sacrificial gate layer 270 may both include silicon germanium, but have different concentrations of germanium. As an example, the sacrificial isolation layer 272 may have a higher concentration of germanium (e.g., 55%) than the concentration of germanium of the sacrificial gate layer 270 (e.g., 25%).

[0043] In some embodiments, an insulating layer 214 may be formed on the sidewalls of the alternately stacked channel layers 120a, 120b and the sacrificial gate layer 270 and on the uppermost surface of the upper channel layer 120a. In addition, the insulating layer 112 may be formed in a recess of the substrate 110, and the insulating layer 114 may be formed in a recess on top of the insulating layer 112. The insulating layers 114, 214 may include the same insulating material (e.g., oxide), and in some embodiments, the insulating layers 114, 214 may be a single continuous layer without an interface or separation between the insulating layers 114, 214. In addition, the insulating material of the insulating layers 114, 214 may be different from the insulating material of the insulating layer 112, and the insulating material of the insulating layer 112 may include, for example, nitride (e.g., silicon nitride).

[0044] like Figure 2C , Figure 2D and Figure 3 As shown in FIG. 3 , a semiconductor layer 274 may be formed on the top and sidewalls of the stack of channel layers 120 a, 120 b (block 315 ). For example, semiconductor layer 274 may be a first polysilicon layer and may be conformally deposited on insulating layer 214 (and on insulating layer 114 ). In what will become transistor stack 101 b ( Figure 1D ) on the sidewalls of the stack of channel layers 120a, 120b, and at the same time as the gate cutout 160a is formed, a portion of the semiconductor layer 274 that will serve as a sacrificial spacer is formed. In subsequent processes / operations, the metal gate 170 ( Figure 1C ) replaces semiconductor layer 274.

[0045] like Figure 2E , Figure 2F and Figure 3As shown in FIG. 3 , a first insulating material 280 may be formed on the semiconductor layer 274 (block 320). For example, the first insulating material 280 may include an oxide that may fill gaps between adjacent vertical portions of the semiconductor layer 274. The oxide may then be planarized, such as by chemical mechanical planarization (CMP), after which the uppermost surface of the first insulating material 280 may be coplanar with the uppermost surface of the first semiconductor layer 274.

[0046] like Figure 2G , Figure 2H and Figure 3 As shown in , a second insulating material 282 may be formed on the uppermost surface of the semiconductor layer 274 and the uppermost surface of the first insulating material 280 (block 325). The second insulating material 282 may be patterned to expose a portion of the uppermost surface of the semiconductor layer 274 and a portion of the uppermost surface of the first insulating material 280, while a portion of the second insulating material 282 that remains vertically overlaps the channel layers 120a, 120b. In addition, the second insulating material 282 may have an etching selectivity relative to the first insulating material 280. For example, the second insulating material 282 may include a nitride, such as silicon nitride, and the first insulating material 280 may not contain nitrogen.

[0047] like Fig.2I , Figure 2J and Figure 3 As shown in FIG. 3 , the exposed portions of the first insulating material 280 may be removed (block 330) to form openings 284 that expose sidewalls and underlying horizontal portions of the semiconductor layer 274. As an example, the exposed portions of the first insulating material 280 may be removed by an oxidation recess operation / process.

[0048] like Figure 2K , Figure 2L and Figure 3 As shown in , the semiconductor layer 274 can be recessed (block 335). For example, a polysilicon recess operation / process can be performed on the exposed sidewalls of the semiconductor layer 274, thereby forming a recessed sidewall 276. The upper portion of the exposed sidewall can be more recessed than the lower portion of the exposed sidewall. In some embodiments, the recessed sidewall 276 can be an inclined surface that is inclined (e.g., curved) closer to the channel layer 120a, 120b as the vertical height increases. As an example, the recessed sidewall 276 can be a convex surface of the semiconductor layer 274. According to some embodiments, the second insulating material 282 can protect the unexposed portion of the semiconductor layer 274 during the recessing of the exposed sidewalls of the semiconductor layer 274. The second insulating material 282 can be removed after the recessed sidewall 276 of the semiconductor layer 274 is formed.

[0049] like Figure 2M , Figure 2N and Figure 3As shown in , a third insulating material 286 may be formed in the opening 284 on the recessed sidewall 276 of the semiconductor layer 274 and on the uppermost surface of the semiconductor layer 274 (block 340). As an example, the third insulating material 286 may be formed by conformal deposition and thus may have a first sidewall that is conformal to (and in contact with) the recessed sidewall 276 of the semiconductor layer 274. Thus, the first sidewall of the third insulating material 286 may be an inclined surface (e.g., a concave surface) of the third insulating material 286. A second sidewall 288 of the third insulating material 286, opposite to the first sidewall, may also be an inclined surface (e.g., a convex surface) of the third insulating material 286.

[0050] The third insulating material 286 may have an etch selectivity relative to the insulating layer 114. For example, the third insulating material 286 may include a nitride (eg, silicon nitride), and the insulating layer 114 may include an oxide and / or may not contain nitrogen. In some embodiments, the third insulating material 286 may include a nitride (eg, silicon nitride) and a second insulating material 282 ( Figure 2H ) same insulating material.

[0051] like Fig.2O , Figure 2P and Figure 3 As shown in FIG. 3 , the third insulating material 286 may be recessed (block 345 ). As a result, the uppermost surface of the semiconductor layer 274 may be exposed, and the second sidewall 288 of the third insulating material 286 may be thinned in the second horizontal direction Y. For example, after the second sidewall 288 is thinned, the upper portion of the third insulating material 286 may have a narrower width.

[0052] The third insulating material 286 having the thinned second sidewall 288 may be used as the gate cutout 160a ( Figure 1D ). Therefore, the gate cutout 160a may be formed after forming the semiconductor layer 274 (e.g., the first polysilicon layer). In addition, forming the gate cutout 160a may include forming a third insulating material 286 on the semiconductor layer 274, the semiconductor layer 274 including a sacrificial spacer, and the gate cutout 160a is separated from the stack of adjacent channel layers 120a and 120b by the sacrificial spacer. In order to ensure that the subsequently formed metal layer 218 ( Figure 2AC , Figure 2AD ) is completely separated into a plurality of metal gates, and after the thinned second sidewall 288 is formed, the gate cut 160 a extends higher than the uppermost upper channel layer 120 in the upper channel layers 120 a (in the vertical direction Z).

[0053] like Figure 2Q , Figure 2R and Figure 3As shown in FIG. 3 , the first insulating material 280 may be removed (block 350) to form an opening 290 adjacent to the vertical portion of the semiconductor layer 274 (e.g., between adjacent vertical portions of the semiconductor layer 274). For example, the first insulating material 280 may be removed by an oxide removal operation / process. To facilitate removal of the first insulating material 280, the first insulating material 280 may have an etch selectivity relative to the third insulating material 286 and the semiconductor layer 274.

[0054] like Figure 2S , Figure 2T and Figure 3 As shown in FIG. , the openings 284, 290 ( Figure 2Q and Figure 2R ) is formed in the semiconductor layer 292 (block 355). For example, the semiconductor layer 292 may be a second polysilicon layer and may be conformally deposited on the second sidewall 288 of the third insulating material 286 (e.g., on the gate cut 160a) and the uppermost surface of the semiconductor layer 274. In some embodiments, because the semiconductor layers 274 and 292 may include the same semiconductor material (e.g., polysilicon), there may be no interface between them. However, in order to simplify the illustration of the formation of the semiconductor layer 292, in Figure 2S and Figure 2T An interface is shown between semiconductor layers 274 , 292 .

[0055] like Figure 2U , Figure 2V and Figure 3 As shown in FIG. 3 , the semiconductor layers 274 , 292 may be etched (block 360 ). As an example, an etch mask 294 may be formed and patterned on the uppermost surface of the semiconductor layer 292 , and portions of the semiconductor layers 274 , 292 may be etched by reactive ion etching (RIE) to form an opening 296 that exposes a portion of the uppermost surface of the insulating layer 214 .

[0056] like Figure 2W , Figure 2X and Figure 3 As shown in FIG. 2 , additional etching may be performed through opening 296 to remove exposed portions of the uppermost surface of insulating layer 214 ( Figure 2U and Figure 2X ), and remove portions of the alternately stacked channel layers 120a, 120b and sacrificial gate layer 270. The sacrificial isolation layer 272 may be removed and replaced with the intermediate dielectric isolation layer 130 ( Figure 2A and Figure 2B). In addition, the lower S / D region 140 and the upper S / D region 150 may be formed on the sidewalls of the alternately stacked channel layers 120a, 120b and the sacrificial gate layer 270 (block 365). Therefore, the S / D regions 140, 150 may be formed after forming the gate cut 160a (e.g., after forming the third insulating material 286 having the thinned second sidewall 288).

[0057] In some embodiments, the S / D regions 140, 150 may be formed by epitaxial growth. For example, the lower S / D region 140 may be epitaxially grown from the lower channel layer 120b, and the upper S / D region 150 may be epitaxially grown from the upper channel layer 120a. According to some embodiments, the channel layers 120a, 120b may include silicon, and the lower S / D region 140 and / or the upper S / D region 150 may include silicon, silicon carbide, or silicon germanium.

[0058] In some embodiments, the insulating layer 132 may be formed on the exposed sidewalls of the semiconductor layers 274, 292, and the insulating layer 134 may be formed on the sidewalls of the insulating layer 214 at the same vertical height as the isolation layer 130. The insulating layer 152 may be formed between the lower S / D region 140 and the upper S / D region 150 and on the upper surface of each of the upper S / D regions 150 in the vertical direction Z.

[0059] According to some embodiments, a planarization operation / process (eg, CMP) may be performed after forming insulating layers 132, 152. In addition, insulating layers 132, 134 may include the same insulating material as that of isolation layer 130 (eg, SiBCN), and such insulating material may be different from the insulating material of insulating layers 152, 214.

[0060] In some embodiments, insulating spacers 172 may be formed on the sidewalls of the sacrificial gate layer 270 and between the channel layers 120a, 120b in the vertical direction Z. For example, the sacrificial gate layer 270 may be etched to form an opening in the sacrificial gate layer 270 between the channel layers 120a, 120b. The sidewalls of the sacrificial gate layer 270 may be exposed through the opening, and the spacers 172 may be formed in the opening. The spacers 172 may include the same insulating material (e.g., silicon nitride) as the third insulating material 286, which may be different from the insulating material of the insulating layers 152, 214, and different from the insulating material of the insulating layers 132, 134.

[0061] like Figure 2Y , Figure 2Z and Figure 3 As shown in FIG. , the semiconductor layers 274 and 292 ( Figure 2W and Figure 2X) (block 370), thereby forming an opening 298. Therefore, after forming the S / D regions 140, 150, portions of the semiconductor layer 274 that serve as sacrificial spacers between the sidewalls of the third insulating material 286 and the stack of adjacent channel layers 120a, 120b may be removed. In addition, the sidewalls of the third insulating material 286 may be exposed through the opening 298.

[0062] like Figure 2AA and Figure 2AB As shown in , because the sacrificial gate layer 270 may have an etch selectivity relative to the channel layers 120a, 120b, the sacrificial gate layer 270 may be removed from between the channel layers 120a, 120b. In addition, the insulating layer 214 ( ) may be removed from the top and sidewalls of the stack of channel layers 120a, 120b, such as by an additional gate (EG) oxide removal operation / process. Figure 2Y and Figure 2Z ).

[0063] like Figure 2AC and Figure 2AD As shown in FIG. 1 , a metal layer 218 may be formed on the stack of the third insulating material 286 and the channel layers 120 a and 120 b. Figure 2AC and Figure 2AD The gate insulating layer is omitted in the illustration in FIG. 2 , but according to some embodiments, a gate insulating layer may be formed between the metal layer 218 and the channel layers 120 a , 120 b . Figures 2AA to 2AD The operations shown in the figure may each be a replacement metal gate (RMG) process ( Figure 3 In addition, the metal layer 218 may also be filled through the semiconductor layer 274 ( Figure 2X ) to replace the space occupied by semiconductor layer 274.

[0064] In some embodiments, the metal layer 218 may extend higher than the uppermost point of the third insulating material 286 (in the vertical direction Z). Therefore, in order to ensure that the metal layer 218 is completely separated into a plurality of metal gates, the metal layer 218 may be planarized, such as by CMP, to provide Figure 1D For example, the planarized metal layer 218 may include two metal gates 170a, 170b electrically isolated from each other by a gate cut 160a.

[0065] According to some embodiments, after planarization, as Figure 1D As shown in FIG. 1 , the gate cutout 160 a may have a flat uppermost surface. The flat uppermost surface of the gate cutout 160 a may be Figure 2ADThe rounded tip portion of the third metal material 286 shown in FIG. 1 is wide. In other embodiments, the planarization may stop at the rounded tip portion of the third metal material 286, and the gate cut 160a may thus have a rounded tip portion, as long as the rounded tip portion is thick enough to electrically isolate the metal gate 170a from the metal gate 170b. Regardless of whether the gate cut 160a has a flat uppermost surface or a rounded tip portion, the uppermost (e.g., narrowest) point of the gate cut 160a may be coplanar with the uppermost surface of each of the metal gates 170a, 170b, and thus the metal gates 170a, 170b may be separated from each other.

[0066] although FIG. 2A to FIG. 2AD Shown for forming Figure 1D The gate cutout 160a operation shown in FIG. 1 is shown in FIG. 1 , but related operations may be used to form the gate cutout 160a. Figure 1F The gate cutout 160b shown in FIG. Figure 1G For example, a U-shaped semiconductor layer 274 ( Figure 2D ), and then recessing the opposing sidewalls of the U-shape to provide opposing recessed (eg, sloped / convex) sidewalls 276 of the semiconductor layer 274 ( Figure 2L ), to form Figure 1F In addition, the lower middle portion of the U-shape may be etched to expose the insulating layer 114 ( Figure 2D ) (thereby separating the sidewalls 276 from each other). A third insulating material 286 may then be conformally formed between the opposing recessed sidewalls 276 ( Figure 2N ), thereby providing a shape of gate cut 160b having two concave sidewalls 166a, 166b. Gate cut 160b may be referred to herein as a "combined" gate cut because it may combine (i) gate cut 160a and (ii) a mirror image of gate cut 160a into a single integrated gate cut 160b having a wide uppermost surface 162.

[0067] Reference Figure 1G , which can be modified FIG. 2A to FIG. 2AD The gate cutout 160c is formed adjacent to and spaced apart from the gate cutout 160a by operation of FIG. 2A to FIG. 2AD The operation is performed to form a semiconductor layer 274 ( Figure 2D ), and then the sidewall of the portion of the semiconductor layer 274 is recessed to set the semiconductor layer 274 facing the Figure 2LAnother recessed (eg, inclined / convex) sidewall 276 of the recessed sidewall 276 shown in FIG. A third insulating material 286 ( Figure 2N ), thereby setting the shapes of the gate cuts 160a, 160c each having a concave sidewall and a convex sidewall. The gate cuts 160a, 160c may be separated from each other by, for example, etching a portion of the third insulating material 286 that would otherwise link the gate cuts 160a, 160c, or forming the third insulating material 286 so that the portion of the third insulating material 286 that becomes the gate cut 160a is not integrated / continuous with the portion of the third insulating material 286 that becomes the gate cut 160c (for example, separated therefrom by a vertical insulating layer). In some embodiments, to facilitate the separation of the gate cuts 160a, 160c from each other, the distance between the stack of channel layers 120a, 120b that will become part of the transistor stack 101a and the stack of channel layers 120a, 120b that will become part of the transistor stack 101b may be comparable. Figure 1D and Figure 1F The corresponding distance (in the second horizontal direction Y) in the structure shown in is wider.

[0068] According to the transistor device 100 ( Figure 1A ) can provide many advantages. These advantages include by forming the S / D regions 140, 150 ( Figure 2W ) and before forming the metal gate 170 ( Figure 1D ) before forming a semiconductor layer 274 used as a sacrificial spacer for forming the gate cut 160 ( Figure 2L ), to reduce the gate cut 160 relative to the transistor stack 101 ( Figure 1C ). Therefore, the gate cutout 160 can be formed using a self-aligned technique that can help reduce the risk of misalignment. In addition, the self-aligned technique can help reduce the overall area of ​​the stacked FET device, because the stacked FET device would otherwise be prone to misalignment when scaled down (i.e., without using the self-aligned gate cutout 160).

[0069] The semiconductor layer 274 may be formed, for example, by depositing polysilicon. The thickness of polysilicon deposition may advantageously be more controllable than photolithography alignment. Thus, forming the semiconductor layer 274 before forming the gate cut 160 may reduce the risk of damaging the channel layers 120a, 120b or the sacrificial gate layer 270 ( FIG. 1 ) in the stack that will become the transistor stack 101 when forming the gate cut 160. Figure 2B). In addition, using the semiconductor layer 274 as a sacrificial spacer to form the gate cut 160 can result in inclined (e.g., concave, convex, or angled) sidewalls 166a, 166b. In contrast, conventional gate cuts are not formed using sacrificial semiconductor (e.g., polysilicon) spacers, lack convex sidewalls or concave sidewalls, and / or are not adjacent to a transistor stack (of a stacked FET device).

[0070] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure, and therefore the disclosure should not be construed as limited to the example embodiments set forth herein. Instead, these example embodiments are provided so that the present disclosure will be thorough and complete and will convey the scope of the invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals refer to the same elements throughout.

[0071] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic diagrams of intermediate structures between idealized and example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the embodiments disclosed herein should not be construed as limited to the specific shapes shown herein but are to include deviations in shapes that may result, for example, from manufacturing.

[0072] It should also be noted that, in some alternative embodiments, the function / action indicated in the flow chart frame here may not occur in the order indicated in the flow chart. For example, depending on the function / action involved, the two frames shown continuously may actually be performed substantially simultaneously, or the frame may sometimes be performed in reverse order. In addition, the function of a given frame of a flow chart and / or block diagram may be divided into a plurality of frames and / or the function of two or more frames of a flow chart and / or block diagram may be integrated at least in part. Finally, without departing from the scope of the present invention, other frames may be added / inserted between the frames shown, and / or frames / operations may be omitted.

[0073] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense, unless expressly defined as such herein.

[0074] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "one", and "the" are also intended to include the plural forms. It will be further understood that the terms "include" and / or "comprise" when used in this specification indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0075] It will be understood that when an element is referred to as being "in conjunction with," "connected to," or "responsive to," or "on" another element, the element may be directly engaged, connected to, or responsive to, or directly on, the other element, or there may be intermediate elements. Conversely, when an element is referred to as being "directly in conjunction with," "directly connected to," or "directly responsive to," or "directly on," another element, there are no intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In addition, the symbol " / " (e.g., when used in the term "source / drain") will be understood to be equivalent to the term "and / or."

[0076] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, a first element may be named a second element without departing from the teachings of the presented embodiments.

[0077] For ease of explanation, spatially relative terms such as "under", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It will be understood that spatially relative terms are intended to include different orientations of the device in use or in operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, the element described as "below" or "below" other elements or features will subsequently be oriented to be "above" the other elements or features. Therefore, the term "below" may include both above and below orientations. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0078] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that it would be unduly repetitive and obfuscating to describe and illustrate verbatim every combination and subcombination of these embodiments. Therefore, this specification including the accompanying drawings should be construed as constituting a complete written description of all combinations and subcombinations of the embodiments described herein, as well as the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0079] The subject matter disclosed above is considered to be illustrative and not restrictive, and the appended claims are intended to cover all such modifications, improvements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent allowed by law, the scope will be determined by the broadest permissible interpretation of the claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

Claims

1. A transistor device comprising: substrate; a transistor stack on the substrate, wherein the transistor stack includes a lower transistor and an upper transistor on top of the lower transistor; and a gate cutout on the substrate and adjacent to the transistor stack, wherein the gate cutout includes a first sloped sidewall and a second sloped sidewall opposite the first sloped sidewall, The upper portion of the second inclined sidewall is adjacent to the upper transistor and is inclined toward the upper transistor as the height increases.

2. The transistor device according to claim 1, in, The upper portion of the gate cutout is narrower than the lower portion of the gate cutout, and The gate cutout is asymmetric relative to the vertical axis.

3. The transistor device according to claim 2, wherein: The upper portion of the gate cutout includes an uppermost point that does not vertically overlap the lower portion of the gate cutout.

4. The transistor device according to claim 3, in, The uppermost point is the portion of the second inclined side wall, The first inclined sidewall includes an uppermost point vertically overlapping a lower portion of the gate cutout.

5. The transistor device according to claim 1, in, The upper portion of the gate cutout is wider than the lower portion of the gate cutout, and The gate cutout is symmetrical with respect to the vertical axis.

6. The transistor device according to claim 1, in, The gate cutout is the first gate cutout, wherein the transistor device further comprises a second gate cutout separated from the first gate cutout, wherein an upper portion of the first gate cutout is narrower than a lower portion of the first gate cutout, and The upper portion of the second gate cutout is narrower than the lower portion of the second gate cutout.

7. The transistor device according to claim 6, in, An upper portion of the second gate cutout is spaced apart from an upper portion of the first gate cutout by a first distance, and The lower portion of the second gate cutout is spaced apart from the lower portion of the first gate cutout by a second distance that is shorter than the first distance.

8. The transistor device according to claim 6, in, the transistor stack is a first transistor stack, The transistor device further comprises a second transistor stack on the substrate, There is no other transistor stack between the first transistor stack and the second transistor stack, and Wherein, both the first gate cut and the second gate cut are between the first transistor stack and the second transistor stack.

9. The transistor device according to claim 1, in, the transistor stack is a first transistor stack, The transistor device further comprises a second transistor stack on the substrate, There is no other transistor stack between the first transistor stack and the second transistor stack, and The gate cutout is between the first transistor stack and the second transistor stack.

10. The transistor device according to claim 1, in, The upper transistor includes a plurality of semiconductor channel layers, wherein the gate cutout extends higher than the uppermost semiconductor channel layer among the plurality of semiconductor channel layers, and Herein, the width of the gate cutout monotonically narrows from the lowermost surface of the gate cutout to the uppermost surface of the gate cutout.

11. The transistor device according to claim 1, wherein: The gate cutout includes silicon nitride.

12. The transistor device according to claim 1, in, The first inclined side wall is convex, and Wherein, the second inclined side wall is concave.

13. The transistor device according to claim 1, wherein: The first inclined sidewall and the second inclined sidewall are both concave.

14. A transistor device comprising: substrate; A first transistor stack and a second transistor stack spaced apart from each other in a lateral direction on a substrate, wherein the first transistor stack and the second transistor stack each include a lower transistor and an upper transistor on top of the lower transistor; and a gate cutout between the first transistor stack and the second transistor stack in a lateral direction, Wherein, the upper transistor includes a plurality of semiconductor channel layers, wherein the gate cutout extends in a vertical direction higher than an uppermost semiconductor channel layer among the plurality of semiconductor channel layers, and The gate cutout includes a concave first sidewall and a concave or convex second sidewall.

15. The transistor device according to claim 14, in, The gate cutout includes insulating material, and The transistor device further comprises: a first metal gate on the plurality of semiconductor channel layers of the first transistor stack and on a first sidewall of the gate cutout, A second metal gate is on the plurality of semiconductor channel layers of the second transistor stack and on a second sidewall of the gate cutout.

16. A method of forming a transistor device, the method comprising: forming a polysilicon layer on a plurality of semiconductor channel layers of the transistor; forming a gate cut after forming a polysilicon layer, wherein the step of forming the gate cut comprises forming an insulating layer on the polysilicon layer, and wherein the polysilicon layer comprises a sacrificial spacer, and the gate cut is spaced apart from the plurality of semiconductor channel layers by the sacrificial spacer; and After forming the gate cuts, source / drain regions are formed on sidewalls of the plurality of semiconductor channel layers.

17. The method according to claim 16, further comprising: removing the polysilicon layer after forming the source / drain regions; as well as Replace the polysilicon layer with a metal gate.

18. The method of claim 17, further comprising, before forming the source / drain regions, forming another polysilicon layer on the gate cutout, in, The step of replacing the polysilicon layer includes replacing both the polysilicon layer and another polysilicon layer with a metal gate after forming the source / drain regions.

19. The method according to claim 16, in, The step of forming the gate cutout further includes removing an upper portion of the insulating layer, wherein, after removing the upper portion of the insulating layer, the gate cut narrows monotonically with increasing height and extends higher than the uppermost semiconductor channel layer of the plurality of semiconductor channel layers, and Therein, the transistor is an upper transistor on top of a lower transistor in a transistor stack.

20. The method according to claim 16, further comprising, before forming the insulating layer, removing a portion of the polysilicon layer so that the polysilicon layer has an inclined sidewall, in, The step of forming an insulating layer includes conformally forming the insulating layer on the inclined sidewalls of the polysilicon layer.

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