Double-ended spin-orbit torque magnetoresistive random access memory and manufacturing method thereof

Abstract

A magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction and a spin-orbit torque material. The spin-orbit torque material produces spin polarization along one or more axes based on a current applied to the spin-orbit torque material. A magnetoresistive random access memory (MRAM) device includes an in-plane magnetic tunnel junction and a spin-orbit torque material, where the MRAM device is field-free switching between a parallel state and an anti-parallel state based on a current applied to the spin-orbit torque material.

Description

Technical Field

[0001] The present disclosure relates to a two terminal spin-orbit-torque (SOT) magnetoresistive random access memory (MRAM) and a method for manufacturing the same. Background Art

[0002] The benefits of artificial intelligence (AI) in modern society have enabled a wide range of transformative new applications in areas ranging from natural language processing to cancer diagnostics. State-of-the-art AI algorithms are trained in power-hungry cloud data centers, which place extreme demands on the underlying computing hardware. Today’s AI algorithms are highly memory-intensive; for example, GPT-3 includes ~175 billion trainable parameters, which corresponds to a memory footprint of over 700 gigabytes (assuming 32-bit data is used during training). Therefore, enhancing the performance of the memory subsystem will play a key role in improving the overall energy efficiency of future computing systems.

[0003] The rise of big data and artificial intelligence (AI) has enabled transformative new technologies with a wide range of potential applications. This rapid innovation imposes extreme demands on the underlying computing fabric, where significant advances in energy-efficient computing hardware will be needed to keep up with the demands of modern AI algorithms. In today’s computing systems, state-of-the-art AI algorithms are trained in cloud data centers, where heavy computational workloads require the use of expensive, power-hungry computing hardware. For example, the training process of the GPT-3 language model, the predecessor to the GPT-3.5 and GPT-4 models that serve as the basis for the ubiquitous ChatGPT AI engine, consumed an estimated 1,287 MWh of energy. According to the U.S. Energy Information Administration, this energy would be enough to power ~1,500 U.S. homes for one month.

[0004] Today’s mainstream AI applications rely heavily on application-specific architectures, which include high-throughput multiply-accumulate units fed by operands fetched from off-chip memory (typically DRAM today). For memory-intensive applications, studies have shown that a large portion of program execution time and energy consumption (>90% in some cases) is spent accessing off-chip memory. Therefore, enhancing memory performance in conjunction with computational logic is essential to improving the overall energy efficiency of future computing systems. Summary of the invention

[0005] Technical issues

[0006] One aspect is to provide a nonvolatile magnetoresistive random access memory device that achieves ultra-high speed, density, and energy efficiency.

[0007] Another aspect is to provide a non-volatile, high-speed and high-capacity magnetoresistive random access memory with computing logic co-located on the chip.

[0008] Solution to the problem

[0009] According to one aspect of one or more embodiments, a magnetoresistive random access memory (MRAM) device is provided, including: a magnetic tunnel junction; and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or more axes.

[0010] According to another aspect of one or more embodiments, a method of operating a magnetoresistive random access memory (MRAM) device is provided, the magnetoresistive random access memory (MRAM) device including: a magnetic tunnel junction; and a spin-orbit torque material, the method including applying a current to the spin-orbit torque material to generate spin polarization along one or more axes in the MRAM device.

[0011] According to yet another aspect of one or more embodiments, a method of operating a magnetoresistive random access memory (MRAM) device is provided, the magnetoresistive random access memory (MRAM) device including: a magnetic tunnel junction; and a spin-orbit torque material, the method including applying a current to the spin-orbit torque material to generate a field-free switch in the MRAM device.

[0012] According to another aspect of one or more embodiments, a magnetoresistive random access memory (MRAM) device is provided, comprising: an in-plane magnetic tunnel junction; and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the MRAM device switches between a parallel state and an anti-parallel state without a field.

[0013] According to another aspect of one or more embodiments, a magnetoresistive random access memory (MRAM) device is provided, comprising: an out-of-plane magnetic tunnel junction; and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the MRAM device switches between a parallel state and an anti-parallel state without a field.

[0014] According to yet another aspect of one or more embodiments, a method for manufacturing a two-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device is provided, the method comprising: depositing a spin-orbit torque (SOT) material on a substrate; depositing a magnetic tunnel junction (MTJ) stack on the SOT material; forming a SOT line from the SOT material; forming an MTJ column from the MTJ stack; and forming a first electrode on the MTJ column and forming a second electrode on a portion of the SOT line. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or other aspects will become apparent and more easily understood from the following description of various embodiments in conjunction with the accompanying drawings, in which:

[0016] Figure 1 shows a structural configuration of a y-type two-terminal SOT MRAM device using conventional SOT materials according to some embodiments;

[0017] Figure 2 shows spin-orbit torque (SOT) and spin-transfer torque (STT) in conventional SOT materials according to some embodiments;

[0018] Figure 3A and Figure 3B shows parallel and antiparallel states of an in-plane magnetic tunnel junction (MTJ) and an out-of-plane MTJ according to some embodiments;

[0019] Figure 4 shows the relationship between switching current and MTJ critical dimension (CD) for y-type and z-type two-terminal SOT MRAM devices with conventional SOT materials according to some embodiments;

[0020] Figure 5 shows the switching current versus MTJ critical dimension (CD) of a y-type two-terminal SOT MRAM device with conventional SOT materials according to some embodiments compared to a STT MRAM (z-type) device;

[0021] Figure 6 shows the relationship between write voltage and MTJ CD for a y-type two-terminal SOT MRAM device with conventional SOT materials according to some embodiments compared to a STT MRAM (z-type) device;

[0022] Figure 7 shows the bit cell area density of a y-type two-terminal SOT MRAM device with conventional SOT materials in two fabrication processes in accordance with some embodiments, compared to an STT MRAM (z-type) device and an SRAM device;

[0023] Figure 8 An example of a z-type two-terminal SOT MRAM device with conventional or non-conventional SOT materials according to some embodiments is shown;

[0024] Fig. 9shows spin-orbit torque (SOT) and tilt angle and spin transfer torque (STT) in unconventional SOT materials according to some embodiments;

[0025] Fig.10 shows simulation of non-deterministic operation in a z-type two-terminal SOT MRAM device with MTJ critical dimension (CD) of 30nm and conventional SOT materials;

[0026] Fig.11 shows simulations of deterministic field-free switching in a z-type two-terminal SOT MRAM device with MTJ critical dimension (CD) of 26nm and conventional SOT materials;

[0027] Fig.12 shows an example bit cell layout of a z-type two-terminal SOT MRAM with SOT material below a magnetic tunnel junction (MTJ) according to some embodiments;

[0028] Fig.13 shows an example of a bit cell layout of a z-type two-terminal SOT MRAM with SOT material above the MTJ according to some embodiments;

[0029] Fig.14 shows an example of a bit cell layout of a y-type two-terminal SOT MRAM with SOT material below the MTJ according to some embodiments;

[0030] Fig.15 shows an example of a bit cell layout of an x-type two-terminal SOT MRAM with SOT material below the MTJ according to some embodiments;

[0031] Fig.16A shows switching current in a z-type two-terminal SOT MRAM for various unconventional SOT tilt angles according to some embodiments, where the switching current of a pure STT MRAM (z-type) is shown as a reference, and Fig. 16B shows voltages in a z-type two-terminal SOT MRAM for various unconventional SOT tilt angles, according to some embodiments, where the voltage of a pure STT MRAM (z-type) is shown as a reference;

[0032] Fig.17 shows resistance-area (RA) targets in z-type two-terminal SOT MRAM for various unconventional SOT tilt angles according to some embodiments, where the RA target of pure STT MRAM (z-type) is shown as a reference;

[0033] Fig.18shows the change of magnetization trajectory along the z-axis over time of a z-type two-terminal SOT MRAM with unconventional SOT materials according to some embodiments;

[0034] Fig.19 A flow chart illustrating operations of a method of manufacturing a z-type two-terminal SOT MRAM device having a SOT material below an MTJ and perpendicular magnetic anisotropy according to some embodiments;

[0035] FIG. 20A to FIG. 20F A method of manufacturing a z-type two-terminal SOT MRAM device having a SOT material and perpendicular magnetic anisotropy below an MTJ according to some embodiments is shown;

[0036] Fig.21 shows a block diagram illustrating an electronic system according to an embodiment;

[0037] Fig. 22 The embodiment shown in FIG. Fig.21 A block diagram of a memory device of an electronic system;

[0038] Fig.23 According to some embodiments Fig. 22 A block diagram of a resistive memory device in a memory device;

[0039] Fig.24 According to some embodiments Fig.23 An example of a first memory bank array in a resistive memory device; and

[0040] Fig.25 A circuit diagram illustrating on-chip non-volatile memory according to an embodiment is shown. DETAILED DESCRIPTION

[0041] As used in this specification, the phrase "at least one of A, B, or C" includes within its scope "only A," "only B," "only C," "A and B," "B and C," "A and C," and "A, B, and C." Note that components in the drawings are not necessarily drawn to scale and some components may be exaggerated for clarity of description.

[0042] To date, various non-volatile memory technologies have been proposed to help solve the above memory bottleneck. For example, spin-orbit torque (SOT) memory is a non-volatile memory technology based on stacking a magnetic tunnel junction (MTJ) on a SOT switching layer. The SOT switching layer can include materials such as heavy metals, topological materials, etc.

[0043] SOT memory has desirable characteristics for high-performance memory applications. For example, the magnetization switching driven by SOT provides faster data operations in memory applications. A single write operation can be performed as fast as about 0.2ns. This speed is comparable to the semiconductor field effect transistor of the related art used in static random access memory (SRAM). SOT memory is non-volatile and significantly faster than competing memory technologies, such as spin transfer torque (STT) (having a switching speed of about 2ns to about 10ns), dynamic random access memory (DRAM) (having a switching speed of about 30ns to about 50ns), resistance random access memory (RRAM) (having a switching speed of about 100ns), phase change memory (PCM) (having a switching speed of about 150ns) and flash memory (having a switching speed of about 0.001 to about 1ms).

[0044] According to various embodiments, a two-terminal SOT memory cell provides high-density applications. According to various embodiments, SOT materials with unconventional spin polarization and the combination of SOT switching with other mechanisms such as spin transfer torque (STT) or voltage controlled magnetic anisotropy (VCMA) can achieve high speed and high density.

[0045] According to various embodiments, a nonvolatile magnetoresistive random access memory (MRAM) device may utilize a combination of spin-orbit torque (SOT) and spin transfer torque (STT) in a two-terminal device architecture and an unconventional spin-orbit torque polarization to achieve ultra-high speed, density, and energy efficiency. For example, a nonvolatile magnetoresistive random access memory (MRAM) device may utilize a combination of spin-orbit torque (SOT) and spin transfer torque (STT) in a two-terminal device architecture to achieve ultra-high speed, density, and energy efficiency. More specifically, a two-terminal SOT MRAM device may utilize the synergy between spin transfer torque (STT) and spin-orbit torque (SOT) to achieve field-free switching in a high-density bit cell layout.

[0046] As used in this specification, the terms "x-type", "y-type" and "z-type" refer to the easy axis anisotropy of a magnetic tunnel junction (MTJ), that is, the magnetization direction of the MTJ. Thus, for example, a z-type two-terminal SOT MRAM device refers to a two-terminal SOT MRAM, wherein its magnetic tunnel junction has an easy axis in the z-axis direction, which is perpendicular to the film deposition plane in an out-of-plane orientation, and thus has a perpendicular magnetic anisotropy (PMA) and magnetization in the z-axis. For another example, a y-type two-terminal SOT MRAM device refers to a two-terminal SOT MRAM, wherein its MTJ has an easy axis in the y-axis direction, and therefore has an in-plane magnetic anisotropy (IMA) and magnetization in the y-axis direction, which is orthogonal to the current flow direction in the SOT material and in the film deposition plane (e.g., xy plane). Similarly, an x-type two-terminal SOT MRAM device refers to a two-terminal SOT MRAM in which its MTJ has an easy axis in the x-axis direction, and therefore also has an in-plane anisotropy (IMA) and magnetization in the x-axis direction, which is parallel to the current flow direction in the SOT material and in the film deposition plane (e.g., zy plane).

[0047] In the following description, the IMA device will be described mainly with reference to the y-type two-terminal SOT MRAM device. However, the embodiments are not limited thereto, and those skilled in the art will appreciate that the description of the y-type two-terminal SOT MRAM device may also be applicable to the x-type two-terminal SOT MRAM device.

[0048] Emerging non-volatile memory technologies, such as SOT-based memories, pave a potential path to improving energy efficiency at the hardware level. SOT memories use current flowing through high-efficiency SOT materials to generate spin-orbit torque that can switch adjacent magnetic free layers, such as CoFeB. In SOT memories that use current flowing through SOT materials to generate spin-orbit torque to switch adjacent magnetic free layers, the switching direction within the adjacent magnetic free layers can be in an in-plane orientation (e.g., in the case of an x-type device or a y-type device) or in a perpendicular orientation (e.g., in the case of a z-type device), depending on the magnetic anisotropy of the device.

[0049] In the related art, in-plane MTJs have been considered unfavorable and impractical for two-terminal STT MRAM applications because the required switching current is very high. For example, with a current pulse time of 0.5 ns, for an in-plane STT MRAM (x-type or y-type) with a critical dimension (CD) of about 10 nm to about 30 nm, a switching current of 400 μA to about 1800 μA is required to achieve switching. In contrast, a vertical STT (z-type) with an MTJ CD of about 22 nm to about 43 nm only requires a switching current of about 200 μA to about 750 μA to achieve switching with the same current pulse time. Therefore, in the related art, in-plane MTJs are generally ignored for STT MRAM applications due to the high current required for switching applications.

[0050] However, the inventors have discovered that by adding SOT materials to in-plane STT MRAM, field-free switching operation becomes unexpectedly more favorable. Here, the term "field-free" is defined as a two-terminal SOT MRAM device that can achieve deterministic operation and switch between parallel and anti-parallel states without the assistance of an external magnetic field or bias field. The concept of "field-free" switching is further discussed below with reference to a z-type two-terminal SOT MRAM device.

[0051] Figure 1 A structural configuration of a y-type two-terminal SOT MRAM device using conventional SOT materials according to some embodiments is shown. Figure 2 Spin-orbit torque and spin transfer torque (STT) in a conventional SOT material according to some embodiments are shown. Figure 3A shows the parallel state and the antiparallel state of an in-plane magnetic tunnel junction (MTJ) according to some embodiments, and Figure 3B The parallel state and the anti-parallel state of an out-of-plane MTJ are shown according to some embodiments.

[0052] exist Figure 1 In the embodiment, the Y-type two-terminal SOT MRAM device 1 may include a magnetic tunnel junction (MTJ) 50 and a spin-orbit torque (SOT) layer 100. The MTJ 50 may be configured as follows: Figure 1The order from top to bottom in the SOT layer 100 includes a fixed magnetization layer 20, a tunnel barrier layer 30, and a magnetic free layer 40, so that the upper surface of the SOT layer 100 contacts the magnetic free layer 40. In an embodiment, the first end can be connected to the fixed magnetization layer 20 of the MTJ 50, and the second end can be connected to the SOT layer 100. The MTJ 50 has an easy axis anisotropy along the y-axis (in-plane in the xy plane) direction as described above. In other words, the MTJ 50 can be an in-plane magnetic tunnel junction, also known as a magnetic tunnel junction with in-plane magnetic anisotropy (IMA) or with in-plane anisotropy. In an embodiment, the magnetic free layer 40 can be, for example, CoFeB.

[0053] exist Figure 1 In the illustrated embodiment, the SOT layer 100 is a conventional SOT material. The term "conventional SOT material" defines a SOT material in which the spin-orbit torque is only along the y-axis. Figure 1 1 is shown as a single layer, but this is only an example, and in some embodiments, a plurality of layers may be provided. In other words, the SOT layer 100 may be formed of a plurality of layers.

[0054] In the y-type two-terminal SOT MRAM device 1, the switching current Iwrite flows along the x-axis. The y-axis enters and leaves the page. Therefore, in the y-type two-terminal SOT MRAM device 1, when the switching current Iwrite is applied to the SOT layer 100, the spin polarization directions of the spin-orbit torque (SOT) and the spin transfer torque (STT) are both along the y-axis. In other words, for the y-type two-terminal SOT MRAM device 1 using conventional SOT materials, the STT follows the easy-axis anisotropy of the MTJ 50, and the SOT in the SOT layer 100 is always along the y-axis direction, as shown in FIG. Figure 2 shown.

[0055] Compared to the STT MRAM technology of the related art, the y-type two-terminal SOT MRAM device 1 introduces a conventional SOT material adjacent to the magnetic free layer 40 of the MTJ 50 to achieve field-free switching, thereby improving the switching speed and reducing the write current of the y-type two-terminal SOT MRAM device 1 while maintaining a high-density bit cell layout. By injecting current through the MTJ 50 of the y-type two-terminal SOT MRAM device 1, the orientation of the magnetic free layer 40 can be field-free switched between a parallel state (P) and an anti-parallel state (AP), such as Figure 3A Here, the parallel state (P) represents a 0 degree angular separation between the magnetic orientations of the free and pinned layers, while the antiparallel state (AP) represents a 180 degree angular separation between the magnetic orientations of the free and pinned layers, as shown in Figure 3A As shown in Figure 3A As shown, the parallel state provides a parallel resistance RP that is lower than the antiparallel resistance RAP in the antiparallel state. For digital storage, 0 degrees of the parallel state (P) and 180 degrees of the antiparallel state (AP) provide the maximum resistance difference. Here, the tunneling magnetoresistive ratio (TMR) = (RAP-RP) / RP*100%. The direction of the current determines the final state (e.g., parallel state (P) or antiparallel state (AP)) of the y-type two-terminal SOT MRAM device 1.

[0056] Figure 4 The switching current versus MTJ critical dimension (CD) of a y-type two-terminal SOT MRAM device with conventional SOT materials according to some embodiments is shown.

[0057] like Figure 4 As shown, the y-type two-terminal SOT MRAM device with conventional SOT materials provides better switching current than the z-type two-terminal SOT MRAM device.

[0058] In a y-type two-terminal SOT MRAM device having a conventional SOT material, field-free switching occurs when the MTJ CD is about 10 nm to about 43 nm and the switching current is about 80 μA to about 160 μA. Therefore, compared with a z-type two-terminal SOT MRAM device having a conventional SOT material, a y-type two-terminal SOT MRAM device having a conventional SOT material uses a lower amount of switching current (e.g., ISW from about 80 μA to about 160 μA).

[0059] Figure 5 The switching current versus MTJ critical dimension (CD) of a y-type two-terminal SOT MRAM device with conventional SOT materials according to some embodiments is shown compared to a STT MRAM (z-type) device. Figure 6 The write voltage versus MTJ CD for a y-type two-terminal SOT MRAM device with conventional SOT materials according to some embodiments is shown compared to a STT MRAM (z-type) device.

[0060] like Figure 5As shown, a y-type two-terminal SOT MRAM device with conventional SOT materials requires 4.4 times less switching current ISW than an STT MRAM device. In a y-type two-terminal SOT MRAM device with conventional SOT materials, for a current pulse time tpulse of 0.5 ns, where Δ is 60@350k, a MTJ CD of about 10nm to about 43nm requires a switching current of about 80μA to about 160μA. In contrast, an STT MRAM with an MTJ CD of about 22nm to about 43nm requires a switching current of about 210μA to about 750μA, which is much higher.

[0061] In addition, the write voltage of the y-type two-terminal SOT MRAM device with conventional SOT materials is also lower than that of the STT MRAM (z-type) device. In the y-type two-terminal SOT MRAM device with conventional SOT materials, RA is 4Ω / μm 2 , MTJ CDs from about 22nm to about 42nm require voltages from about 0.5v to about 0.25v. In contrast, at RA of 4Ω / μm 2 In STT MRAM (z-type), the MTJ CD at about 22nm to about 42nm requires a voltage of about 2.3v.

[0062] Figure 7 The bit cell area density of a y-type two-terminal SOT MRAM device with conventional SOT materials in two manufacturing processes according to some embodiments is shown compared to an STT MRAM (z-type) device and an SRAM device.

[0063] Compared to SRAM devices, y-type two-terminal SOT MRAM devices with conventional SOT materials allow for approximately 4 times denser devices. Figure 7 The results show that the SRAM cell size (μm) with a contacted gate pitch (CGP) of 50nm, a minimum metal pitch (MMP) of 30nm, and a 2 ), 16nm MTJ CD (=0.5*MMP) and 0.5ns MTJ switching speed target of 4nm mode equivalent manufacturing process, and with 54nm contact gate pitch (CGP), 40nm minimum metal pitch (MMP), 0.0367 SRAM cell size (μm 2 ), 20nm MTJ CD (=0.5*MMP) and 0.5ns MTJ switching speed target in 7nm mode equivalent manufacturing process (μm 2 ).like Figure 7As shown in , depending on the process technology used, the bit cell area can be reduced by about 3.8 times to about 4.2 times that of a comparable SRAM device. For example, for a 4nm mode equivalent manufacturing process, the bit cell area can be reduced from 0.03μm 2 Reduced to less than 0.01μm 2 .

[0064] Z-type two-terminal SOT MRAM devices have been experimentally demonstrated in the related art. For z-type two-terminal SOT MRAM devices with conventional SOT materials, the field-free switching window is very limited. For example, in an experimentally demonstrated z-type two-terminal SOT MRAM device with its specific SOT material and geometry, field-free switching is only available for MTJ CDs of about 18nm to 26nm for switching currents of about 150μA to about 225μA. Above this MTJ CD range, the z-type two-terminal SOT MRAM device with conventional SOT materials is non-deterministic without applying an external magnetic field or bias field to assist in achieving deterministic operation. Below this MTJ CD range, the perpendicular magnetic anisotropy becomes insufficient, and it is difficult to maintain the thermal stability factor of the z-type two-terminal SOT MRAM device. That is, for large MTJ CDs, the switching characteristics of the z-type two-terminal SOT MRAM device become non-deterministic without applying an external magnetic field or bias field to assist in achieving deterministic operation. In contrast, it is difficult to maintain the thermal stability factor of a z-type two-terminal SOT MRAM device with conventional SOT materials when the MTJ CD becomes smaller.

[0065] In the related art, various terms are used for the external magnetic field - "dipole field", "external magnetic field", "bias magnetic field", etc. The external magnetic field is usually generated by an additional layer variously referred to as an "in-plane magnetized magnetic layer", "in-plane magnetized bias magnetic field providing layer", etc., and an additional magnetic layer and / or an additional current applied to the additional magnetic layer is required to generate the auxiliary external magnetic field required to achieve deterministic switching. For example, deterministic operation and state switching can be provided by introducing a tilt axis through the geometry of a z-type two-terminal SOTMRAM device with conventional SOT materials. In these cases, the high switching current is combined with the additional current required to generate the auxiliary external magnetic field, or the complex manufacturing method required to introduce the tilt axis into the device geometry, making the z-type two-terminal SOT MRAM device using conventional SOT materials impractical for highly integrated memories where lower current, higher density and scalable manufacturing are advantageous.

[0066] However, the inventors have discovered that by introducing unconventional SOT materials into a z-type two-terminal SOT MRAM device, the z-type two-terminal SOT MRAM device unexpectedly achieves field-free deterministic switching with a wider field-free switching window and reduced switching current. As used in this specification, the term "field-free switching" is defined as a deterministic operation that achieves state switching without the assistance of an external magnetic field or bias field. In addition, a "device that achieves field-free switching" is defined as a SOT MRAM device that is able to achieve deterministic operation and state switching by itself without the assistance of an external magnetic field and without the need for additional layers or additional currents required to generate an auxiliary external magnetic field.

[0067] By introducing unconventional SOT materials into a z-type two-terminal SOT MRAM device, the z-type two-terminal SOT MRAM device with the unconventional SOT materials unexpectedly achieves a greater than 2-fold reduction in switching current and an approximately 4-fold increase in switching speed compared to a z-type two-terminal SOT MRAM with conventional SOT materials.

[0068] Figure 8 An example of a z-type two-terminal SOT MRAM device with unconventional SOT materials is shown in accordance with some embodiments. Fig. 9 The spin-orbit torque (SOT) and tilt angle and spin transfer torque (STT) in unconventional SOT materials according to some embodiments are shown.

[0069] exist Figure 8 In the embodiment, the z-type two-terminal SOT MRAM device 200 may include a magnetic tunnel junction (MTJ) 250 and a spin-orbit torque (SOT) layer 300. The MTJ 250 is Figure 8 The order from top to bottom in the SOT layer 300 includes a fixed magnetization layer 220, a tunnel barrier layer 230, and a magnetic free layer 240, so that the upper surface of the SOT layer 300 contacts the magnetic free layer 240. In an embodiment, the first end can be connected to the fixed magnetization layer 220 of the MTJ 50, and the second end can be connected to the SOT layer 300. The MTJ 250 has an easy axis anisotropy along the z-axis (out-of-plane) direction, as described above. In other words, the MTJ 250 can be an out-of-plane magnetic tunnel junction, also known as a magnetic tunnel junction with out-of-plane or perpendicular magnetic anisotropy (PMA). In an embodiment, the magnetic free layer 240 can be, for example, CoFeB.

[0070] exist Figure 8In the illustrated embodiment, the SOT layer 300 is an unconventional SOT material. The term "unconventional SOT material" defines a SOT material in which the spin-orbit torque has a component along both the y-axis and another axis. "Unconventional SOT material" refers to a low-symmetry SOT material in which the spin polarization, spin current, and charge current are not forced to be orthogonal. In contrast to conventional SOT materials in which the spin-orbit torque is only along the y-axis, in unconventional SOT materials, the spin-orbit torque is tilted away from the y-axis toward the x-axis or the z-axis, so that the spin-orbit torque is in the y-axis and in the x-axis or the z-axis. Although the SOT layer 300 is Figure 8 3. Although shown as a single layer in FIG. 3, this is merely an example, and in some embodiments, a plurality of layers may be provided. In other words, the SOT layer 300 may be formed of a plurality of layers.

[0071] SOT materials with unconventional spin polarization in the in-plane x-orientation and / or out-of-plane z-orientation are an emerging class of SOT materials that enable field-free switching and further improve the energy efficiency of SOT MRAM devices. Although the origin of unconventional spin polarization is still under investigation, several mechanisms and accompanying experimental demonstrations and theoretical calculations have been performed. For example, out-of-plane unconventional spin polarization has been demonstrated in MnPd3, where density functional theory calculations show that the unconventional spin polarization is caused by the low crystal symmetry of the (114)-oriented MnPd3 film. In addition to MnPd3, unconventional spin polarization has been found in a wide range of SOT materials, including Mn3Sn, WTe2, IrMn, RuO2, L10-FePt / Cu / Py, CuPt, etc.

[0072] In the z-type two-terminal SOT MRAM device 200, the switching current Isw flows along the x-axis, and the y-axis enters and leaves the page. In the z-type two-terminal SOT MRAM device 200, when the switching current Isw is applied to the SOT layer 300, the spin polarization direction of the spin-orbit torque (SOT) is along the y-axis and another axis (x-axis or z-axis), and the spin transfer torque (STT) is along the z-axis. In other words, for unconventional SOT materials, there is a tilt angle away from the y-axis toward the x-axis or the z-axis. Fig. 9 The z tilt angle is shown in the example shown.

[0073] The use of unconventional SOT materials further reduces the switching current and extends the field-free switching window in z-type two-terminal SOT MRAM devices. Fig. 9 As shown in Figure 1, the net effect of the tilt angle is that the tilt angle allows the spin-orbit torque (SOT) to contribute more toward the z-axis direction in the z-type two-terminal SOT MRAM device, where the z-axis direction is the easy axis, which makes switching more efficient. Fig. 9 In the figure, θSHA represents the spin Hall angle.

[0074] In conventional SOT materials, only the spin transfer torque (STT) contributes to the z-axis spin orientation. In contrast, in unconventional SOT materials, both the spin-orbit torque (SOT) and the spin transfer torque (STT) contribute to the z-axis spin orientation.

[0075] The inventors have unexpectedly discovered that the non-conventional SOT material itself can change the tilt angle due to the crystal structure of the SOT material. Thus, changing from a conventional SOT material to a non-conventional SOT material introduces a tilt axis.

[0076] More specifically, the inventors found that the ratio of the in-plane current (JSOT) in the SOT material to the current (JSTT) perpendicular to the plane of the SOT material determines the switching behavior in the z-type two-terminal SOT MRAM device. Here, a high JSOT / JSTT ratio indicates that the spin contribution from the SOT material is dominant, while a low JSOT / JSTT ratio indicates that the spin contribution from the STT is dominant. This ratio explains why external magnetic field assistance is required at large tunnel junction sizes.

[0077] The JSOT / JSTT ratio depends on the device geometry. Figure 8 , Kirchhoff's current law requires ISOT=ISTT.

[0078] here, , assuming , where MTJCD is the critical dimension of the MTJ.

[0079] Fig.10 Figure 2 shows a simulation of non-deterministic operation in a z-type two-terminal SOT MRAM device with a MTJ critical dimension (CD) of 30 nm and conventional SOT materials. Fig.10 As shown, the JSOT / JSTT ratio is 4.7. Fig.10The left figure in shows the magnetization mx, my, and mz in the x-axis, y-axis, and z-axis directions, respectively, with time t in ns. The right figure shows the initial and final states of the magnetic components in a three-dimensional coordinate system. As shown in the left figure, a steady-state switching current is applied starting at time t=0 and maintained for 0.5 ns, at which time the switching current is turned off. In this case, as shown in the left figure, the in-plane spin-orbit torque (SOT) prevails over the out-of-plane spin transfer torque (STT). Therefore, as shown in the right figure, the initial position starts at the coordinates (0,0,0) at point t=0, and when the switching current is turned off, the final position at time t=0.5ns is not located on the z-axis, but the final position is located towards the middle and back of the sphere. Therefore, it is unclear whether the state of the material will fall back to the initial position, resulting in non-deterministic operation.

[0080] Fig.11 Simulations of deterministic field-free switching in a z-type two-terminal SOT MRAM device with an MTJ critical dimension (CD) of 26 nm and unconventional SOT materials are shown. Fig.11 As shown, the JSOT / JSTT ratio is 4.1. Fig.10 , Fig.11 The left figure in the figure shows the magnetization mx, my and mz in the x-axis, y-axis and z-axis directions respectively with time t in ns. The right figure shows the initial and final states of the magnetic components in the three-dimensional coordinate system. As shown in the left figure, a steady-state switching current is applied from time t=0 and maintained for 0.5 ns, at which time the switching current is turned off. In this case, Fig.10 In contrast, as shown in the left-hand figure, the out-of-plane spin transfer torque (SOT) overcomes the in-plane spin orbit torque (SOT), causing the magnetic free layer 240 to become deterministic. Therefore, as shown in the right-hand figure, the initial position starts at the coordinates (0, 0, 0) at point t = 0, and when the switching current is turned off, the final position at time t = 0.5ns is located close to the z-axis. Therefore, as time passes t = 0.5ns, the state of the material will not fall back to the initial state, but will end at the coordinates (0, 0, 1), resulting in non-deterministic operation. As described above, the direction of the switching current determines the final state of the z-type two-terminal SOT MRAM device with unconventional SOT materials (i.e., whether the final state is parallel (P) or anti-parallel (AP)).

[0081] Compare Fig.10 and Fig.11 Simulations of the 2018 NAND flashover circuit can be used to compare non-deterministic operation with deterministic switching. For deterministic field-free switching, the MTJ critical dimension (CD) is 26nm and the JSOT / JSTT ratio is 4.1. Therefore, field-free switching is naturally achieved as the MTJ CD decreases.

[0082] Therefore, when the device is larger, external magnetic field assistance is required to overcome the in-plane SOT. However, unexpectedly, the inventors found that as the size of the z-type two-terminal SOT MRAM device decreases (i.e., as the MTJ CD decreases), the z-type two-terminal SOT MRAM device can be field-free switched (i.e., without external magnetic field assistance).

[0083] Fig.12 An example bit cell layout of a z-type two-terminal SOT MRAM device with SOT material below a magnetic tunnel junction (MTJ) is shown in accordance with some embodiments.

[0084] like Fig.12 As shown, a bit cell layout 400 of a z-type two-terminal SOT MRAM device may include a substrate 401, a bit line 405, a source line 410, a word line 470, a magnetic tunnel junction (MTJ) 450, an SOT layer 460, metal layers 415 and 465, and a via 480. The metal layer 415 may be a contact for connecting the bit line 405 to the MTJ 450, and the metal layer 465 may be a contact for connecting the via 480 to the SOT layer 460.

[0085] The MTJ 450 may be top pinned and may include a fixed magnetic layer 420, a tunnel barrier layer 430, and a magnetic free layer 440. The MTJ 450 may have an easy axis anisotropy (perpendicular magnetic anisotropy (PMA)) in the z-axis direction. In an embodiment, a SOT layer 460 may be disposed below the MTJ 450, and an upper surface of the SOT layer 460 may contact the magnetic free layer 440. In an embodiment, the SOT layer 460 may be a non-conventional SOT material as described above. In an embodiment, the bit cell layout 400 may be as described above with respect to Figure 8 An example bit cell layout of the z-type two-terminal SOT MRAM device 200 is shown.

[0086] exist Fig.12 In the embodiment of the present invention, the plurality of metal layers may be about two layers. The minimum bit cell size may be 12F2.

[0087] Fig.13 An example of a bit cell layout of a z-type two-terminal SOT MRAM with SOT material above the MTJ is shown in accordance with some embodiments.

[0088] like Fig.13As shown, the bit cell layout 500 of the z-type dual-terminal SOT MRAM device may include a substrate 501, a bit line 505, a source line 510, a word line 570, a magnetic tunnel junction (MTJ) 550, a SOT layer 560, metal layers 515 and 590, and a via 580. The metal layer 515 may be a contact for connecting the bit line 505 to the SOT layer 560, and the metal layer 590 may be a contact for connecting the via 580 to the MTJ 550. The MTJ 550 may be bottom pinned and may include a fixed magnetic layer 520, a tunnel barrier layer 530, and a magnetic free layer 540. The MTJ 550 may have an easy axis anisotropy (perpendicular magnetic anisotropy (PMA)) in the z-axis direction. The SOT layer 560 may be a non-conventional SOT material as described above. In an embodiment, the SOT layer 560 may be disposed above the MTJ 550, and the lower surface of the SOT layer 560 may contact the magnetic free layer 440. In an embodiment, the bit cell layout 500 may be as described above with respect to Figure 8 An example bit cell layout of the z-type two-terminal SOT MRAM device 200 is shown.

[0089] exist Fig.13 In the example, the number of metal layers can be about three layers. For MTJ AR=2, the minimum bit cell size can be 12F2. For MTJ AR=3 (see Figure 7 ), the minimum bit unit size can be 16F2.

[0090] Fig.14 An example of a bit cell layout of a y-type two-terminal SOT MRAM with SOT material below the MTJ is shown in accordance with some embodiments.

[0091] like Fig.14 As shown, the bit cell layout 600 of the Y-type two-terminal SOT MRAM device may include a substrate 601, a bit line 605, a source line 610, a word line 670, a magnetic tunnel junction (MTJ) 650, a SOT layer 660, a metal layer 665, and a via 480. The metal layer 665 may be a contact for connecting the via 480 to the SOT layer 660.

[0092] The MTJ 650 may be top pinned and may include a fixed magnetic layer 620, a tunnel barrier layer 630, and a magnetic free layer 640. The MTJ 650 may have easy axis anisotropy (in-plane magnetic anisotropy (IMA)) in the y-axis direction. In an embodiment, a SOT layer 660 may be disposed below the MTJ 650, and an upper surface of the SOT layer 660 may contact the magnetic free layer 640. In an embodiment, the SOT layer 660 may be a conventional SOT material as described above. However, the embodiment is not limited thereto, and in an embodiment, the SOT layer 660 may be a non-conventional SOT material as described above. The bit cell layout 600 may be as described above with respect to Figure 1 An example bit cell layout of the Y-type two-terminal SOT MRAM device 1 is shown.

[0093] exist Fig.14 In the example, the number of metal layers can be about three layers. For MTJ AR=2, the minimum bit cell size can be 12F2. For MTJ AR=3 (see Figure 7 ), the minimum bit unit size can be 16F2. Fig.15 An example of a bit cell layout of an x-type two-terminal SOT MRAM with SOT material under the MTJ is shown in accordance with some embodiments.

[0094] like Fig.15 As shown, a bit cell layout 700 of an x-type two-terminal SOT MRAM device may include a substrate 701, a bit line 705, a source line 710, a word line 770, a magnetic tunnel junction (MTJ) 750, a SOT layer 760, a metal layer 765, and a via 780. The metal layer 765 may be a contact for connecting the via 780 to the SOT layer 760.

[0095] The MTJ 750 may be top pinned and may include a fixed magnetic layer 720, a tunnel barrier layer 730, and a magnetic free layer 740. The MTJ 750 may have an easy axis anisotropy (in-plane magnetic anisotropy (IMA)) in the x-axis direction. In an embodiment, a SOT layer 760 may be disposed below the MTJ 750, and an upper surface of the SOT layer 760 may contact the magnetic free layer 740. In an embodiment, the SOT layer 760 may be a conventional SOT material as described above. However, embodiments are not limited thereto, and in an embodiment, the SOT layer 760 may be a non-conventional SOT material as described above. The bit cell layout 700 may be similar to that described above with respect to Figure 1 The example bit cell layout of the bit cell layout of the y-type two-terminal SOT MRAM device 1 is different in that the in-plane magnetic anisotropy is in the x-axis direction.

[0096] exist Fig.15In the embodiment, the number of metal layers can be about two to four layers. For MTJ AR=2, the minimum bit cell size can be 12F2. For MTJ AR=3, the minimum bit cell size can be 12F2 (see Figure 7 ).

[0097] Z-type, Y-type, and X-type two-terminal SOT MRAM devices exploit the synergy between spin transfer torque (STT) and spin orbit torque (SOT) to achieve field-free switching in high-density, one transistor, one resistor per cell (1T1R) bit cell layouts, as described in detail in the paper. Figures 12 to 15 The example shown in the figure is described, where each bit cell contains a transistor and a resistive storage element. Compared with the STT MRAM technology of the related art, Figures 12 to 15 Each of the z-type, y-type, and x-type two-terminal SOT MRAM devices shown in Figure 1 introduces SOT material adjacent to the free layer of the magnetic tunnel junction (MTJ). The adjacent SOT material increases the switching speed and reduces the write current of the device while maintaining a high-density 1T1R bit cell layout.

[0098] and Figure 14 to Figure 15 The examples in FIG. 4 show y-type and x-type two-terminal SOT MRAM devices, in which SOT materials are integrated under MTJs 660 and 760, respectively. According to some embodiments, each of the y-type two-terminal SOT MRAM device and the x-type two-terminal SOT MRAM device may include a MTJ 660 and a SOT material integrated under MTJs 760 and 760, respectively. Fig.13 An example of a bit cell layout for a z-type two-terminal SOT MRAM device is shown in a similar manner with the SOT material integrated above the MTJ with appropriate modifications.

[0099] In an embodiment, the SOT material may be connected in series with the MTJ. In an embodiment, by injecting a current into the top electrode of the two-terminal SOT MRAM device through the bit line 405, 505, 605, or 705, the orientation of the free layer may be switched between a parallel (P) state and an antiparallel (AP) state. The current may be, for example, a charging current. In an embodiment, as described above, the direction of the current determines the final state of the two-terminal SOT MRAM device (i.e., parallel (P) or antiparallel (AP)).

[0100] When a charge current is injected into the top electrode of the two-terminal SOT MRAM device through the bit line 405, 505, 605 or 705, both a spin-orbit torque (SOT) and a spin transfer torque (STT) are generated. As described above, the spins generated by the SOT are polarized in the in-plane y orientation in conventional SOT materials. The spins generated by the STT are polarized coaxially with the easy axis anisotropy of the two-terminal SOT MRAM device. For example, when the x direction represents the direction in which the current flows through the SOT material, the z direction represents the direction in which the current flows through the MTJ.

[0101] In z-type two-terminal SOT MRAM devices with unconventional SOT materials (i.e., with perpendicular magnetic anisotropy (PMA)), the synergy between the spins generated by the SOT and those generated by the STT has several key benefits.

[0102] For example, the spin polarization angle of the spins generated by SOT is nominally orthogonal to the anisotropy of the two-terminal SOT MRAM device, so that when current is injected into the two-terminal SOT MRAM device, the maximum spin-orbit torque (SOT) is initially applied to the free layer. Therefore, switching can be initiated immediately. In contrast, the spin polarization angle of the spins generated by STT is coaxial with the easy axis anisotropy of the two-terminal SOT MRAM device. Therefore, the initial spin transfer torque (STT) is close to zero, so that a thermally activated incubation time is required to establish the initial angle before switching can begin. Therefore, the switching delay of the two-terminal SOT MRAM device is greatly improved (i.e., switching occurs much faster) compared to the switching delay of the spin transfer torque (STT) MRAM device of the related art. For example, the switching speed in the two-terminal SOT MRAM device can be about four times (4x) faster than the switching speed in the spin transfer torque (STT) MRAM device of the related art. This faster speed is because no thermal energy is required to initiate switching in the two-terminal SOT MRAM device. This benefit is more significant at lower temperatures because less thermal energy is available to establish the initial angle in the related art spin transfer torque (STT) MRAM device. In the case where the related art spin transfer torque (STT) MRAM device is subjected to high energy radiation, such as in space-related applications, the increased thermal energy from the high energy radiation may cause switching errors. In contrast, the two-terminal SOT MRAM device is naturally immune to such soft errors caused by high energy radiation because the data is magnetically stored in the free layer of the MTJ. Therefore, the two-terminal SOT MRAM device is particularly suitable for aerospace and space applications, where radiation hardness and ultra-low temperature operation are naturally achieved through the synergy between the SOT-generated spins and the STT-generated spins.

[0103] Fig.16AThe switching current in a z-type two-terminal SOT MRAM for various unconventional SOT tilt angles is shown, according to some embodiments, where the switching current of a pure STT MRAM (z-type) is shown as a reference. Fig. 16B The charging voltage in a z-type two-terminal SOT MRAM for various non-conventional SOT tilt angles is shown, according to some embodiments, where the write voltage of a pure STT MRAM (z-type) is shown as a reference. Fig.17 Resistance-area (RA) targets in a z-type two-terminal SOT MRAM for various unconventional SOT tilt angles are shown, according to some embodiments, where the RA target of a pure STT MRAM (z-type) is shown as a reference.

[0104] In a two-terminal SOT MRAM device with conventional SOT materials, the ratio of x-spin to y-spin or z-spin to y-spin is mainly determined by the device geometry. By introducing SOT materials with unconventional spin polarization, the ratio of x-spin to y-spin or z-spin to y-spin can be enhanced to further improve the switching performance.

[0105] like Fig.16A As shown, according to various embodiments, an unconventional tilt angle of 5° toward the z-axis reduces the switching current by more than two times (2x) compared to the switching current in the related art STT MRAM (z-type). For example, the switching current of the related art STT MRAM (z-type) is about 370 μA, while the switching current of the z-type two-terminal SOT MRAM with an unconventional SOT tilt angle of 5° toward the z-axis is about 180 μA. For example, for an unconventional tilt angle of 10°, the reduction in switching current is even higher, from about 370 μA to about 150 μA. The unconventional tilt angle is defined as the angular separation between the spin-orbit torque (SOT) spin polarization vector and the y-axis. A higher unconventional tilt angle corresponds to a higher ratio of x spin to y spin or a ratio of z spin to y spin. This significant reduction in switching current can be attributed to the z spin current density generated in the SOT material. The z spin current density reduces the spin transfer torque (STT) current density and the total write current required for switching.

[0106] like Fig. 16BAs shown, the z-type two-terminal SOT MRAM with an unconventional SOT tilt angle provides a 2.3 times reduction in write voltage Vc (V) compared to a pure STT MRAM (z-type) device with an RA of 4 Ω•µm2. Here, the contribution of the voltage from the SOT line is small compared to the contribution of the MTJ. For example, the pure STT MRAM (z-type) device has a write voltage of about 2.8 V, while the z-type two-terminal SOT MRAM with an unconventional SOT tilt angle of 10° toward the z-axis has a write voltage of about 1.25 V.

[0107] Compared to pure STT MRAM (z-type) devices, the reduction in spin transfer torque (STT) current density increases the available area resistance (RA) budget by more than two times (2x), as shown in Fig.17 As shown. For example, assuming a 0.75 V voltage budget, the RA target for the related art STTMRAM (z-type) is about 1.1 Ω•µm2. The RA target for the z-type two-terminal SOTMRAM with an unconventional SOT tilt angle of 5° toward the z-axis is about 2.0 Ω•µm2. Similar to the switching current performance, the increase in the RA target is even higher, from about 1.1 Ω•µm2 to about 2.6 Ω•µm2 for unconventional tilt angles up to 10°. This increased RA budget improves the manufacturability and scalability of the magnetic tunnel junction (MTJ) compared to the related art STT MRAM technology. Figures 16 and Fig.17 A trend is shown where greater benefit is achieved by increasing the non-conventional SOT tilt angle toward the z-axis.

[0108] Fig.18 The magnetization trajectory along the z-axis of a z-type two-terminal SOT MRAM with unconventional SOT materials is shown as a function of time, according to some embodiments.

[0109] According to various embodiments, the unconventional tilt angle of 10° reduces the switching delay by about four times (4x) compared to the switching delay of the related art STT MRAM technology. For example, the related art STT MRAM (z-type) requires about 0.65 ns to reach a magnetization of 1.0 for switching. In contrast, the z-type two-terminal SOT MRAM of the unconventional SOT material with a tilt angle of 10° reaches a magnetization of 1.0 for switching in about 0.17 ns.

[0110] The above embodiments are shown with respect to a perpendicularly polarized z-type magnetic tunnel junction (MTJ). According to various embodiments, unconventional tilt angles may also be applied to in-plane polarized magnetic tunnel junctions (MTJs) (eg, in-plane polarized x-type MTJs or in-plane polarized y-type MTJs).

[0111] Such significant increase in switching speed and reduction in write current resulting from two-terminal SOT MRAM including unconventional SOT materials shows great promise as a next-generation nonvolatile memory technology.

[0112] Fig.19 A flow chart illustrating operations of a method of fabricating a z-type two-terminal SOT MRAM device having a SOT material under an MTJ and perpendicular magnetic anisotropy, in accordance with some embodiments. FIG. 20A to FIG. 20F A method of fabricating a z-type two-terminal SOT MRAM device with SOT material under the MTJ and perpendicular magnetic anisotropy is shown in accordance with some embodiments.

[0113] According to an embodiment, a z-type two-terminal SOT MRAM device with perpendicular magnetic anisotropy can be FIG. 20A to FIG. 20F Note that similar fabrication processes can be used for MTJs with in-plane magnetic anisotropy. However, embodiments are not limited to FIG. 20A to FIG. 20F The manufacturing process shown, and according to some embodiments, other manufacturing processes can be used to manufacture the two-terminal SOT MRAM.

[0114] In the following description, the manufacturing of a z-type two-terminal SOT MRAM device will be explained. FIG. 20A to FIG. 20F The manufacturing process shown in FIG. 1 is a schematic diagram of an integrated SOT line below an MTJ. Fig.12 As shown, and reference Fig.19 The operation shown.

[0115] The manufacturing process begins by depositing a spin-orbit torque (SOT) material on a substrate (S10). In some embodiments, the SOT material may be an unconventional SOT material. In some embodiments, the SOT material may be a conventional SOT material. In some embodiments, the SOT material may include multiple layers. A magnetic tunnel junction (MTJ) stack may then be deposited on the SOT material (S20). For example, Fig. 20AAs shown, in some embodiments, the MTJ stack may include a free layer, a tunnel barrier layer, a reference layer, a spacer layer, a pinning layer, and a capping layer deposited in sequence on the SOT layer. However, this is only an example, and in some embodiments, the number of layers may be changed. In some embodiments, the MTJ stack may be a vertical MTJ stack. In some embodiments, the MTJ stack may be an in-plane MTJ stack. In some embodiments, for example, a low area resistance (RA) MTJ stack with a SOT film may be provided, such as SOT layer / CoFeB(1) / MgO(1.2) / CoFeB(1.3) / Ta(0.4) / Co(0.4) / Pd(0.6) / Co(0.4) / Ru(0.85) / Co(0.4) / [Pd(0.6) / Co(0.3)]3 / Ru(1.5), where the unit is nm. According to an embodiment, the MTJ stack may be deposited on a surface-passivated CMOS die via magnetron sputtering and vacuum annealed at 200° C. for 1 hour. A SOT line may be formed ( S30 ). For example, in some embodiments, a first mask (Mask 1 ) may be provided on the MTJ stack using a negative photoresist, such as Fig.19 As shown in B. Fig.19 As shown in C, the SOT line can be formed by electron beam lithography (EBL) based on the first mask, two-step ion beam etching and Al 2 O 3 In-situ passivation via Al 2 O 3 The SOT line can be patterned by using precise time control or endpoint detection via secondary ion mass spectrometry to stop at the surface of the passivation substrate and the SOT layer, respectively. In an embodiment, the minimum width of the SOT line can be about 30 nm or less (e.g., about 5 nm to about 30 nm), and the length of the SOT line can vary according to the embodiment. An MTJ column can be formed (S40). For example, in some embodiments, after the SOT line is patterned, a second mask (Mask 2) can be provided on the SOT line using a negative photoresist, such as Fig.19 D. Fig.19 As shown in E, the MTJ pillar can be fabricated by electron beam lithography (EBL) based on a second mask, by two-step ion beam etching, and Al 2 O 3Sputtering in-situ passivation, and photoresist stripping for patterning. The etching of the MTJ pillars can be stopped at the surface of the SOT lines and MTJ pillars, respectively, using precise time control or endpoint detection via secondary ion mass spectrometry, similar to the SOT lines.

[0116] A first electrode may be formed on the MTJ pillar, and a second electrode may be formed on a portion of the SOT line (S50). Fig.19 As shown in FIG. 5 , in some embodiments, an insulating material may be deposited on the SOT line and the MTJ column and then etched to expose the top layer of the MTJ column. A third mask (Mask 3) may be disposed on the insulating material using a positive photoresist. Fig.19 As shown in FIG. 4G , the top electrode (TE) material (e.g., Cu, Ti(10) / Au(80)) for the MTJ pillar top contact and the SOT line contact can be patterned via EBL, and then the positive photoresist can be evaporated and stripped to form the top electrodes of the MTJ pillar and the SOT line.

[0117] According to an embodiment, Figure 12-Figure 15 The bit cell architecture of the dual-terminal SOT MRAM device shown may use Manhattan wiring rules. Note that this bit cell architecture is almost identical to that of the related art STT MRAM (z-type), except that one of the metal layers is replaced by SOT material. The process complexity of such a bit cell architecture is therefore comparable to that of the related art STT MRAM, with additional process steps associated with depositing the SOT material.

[0118] Fig.21 A block diagram illustrating an electronic system according to an embodiment is shown.

[0119] refer to Fig.21 , the electronic system 1000 may include a host 1015 and a memory system 1020. The memory system 1020 may include a memory controller 1100 and a plurality of resistive memory devices 1200a to 1200k.

[0120] The host 1015 may communicate with the memory system 1020 through various interface protocols, such as Peripheral Component Interconnect-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). In an embodiment, the host 1015 may communicate with the memory system 1020 through an interface protocol, such as Universal Serial Bus (USB), MultiMediaCard (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0121] The memory controller 1100 may control the overall operation of the memory system 1020. The memory controller 1100 may control the overall data exchange between the host 1015 and the plurality of resistive memory devices 1200a to 1200k. For example, the memory controller 1100 may write data in the plurality of resistive memory devices 1200a to 1200k or read data from the plurality of resistive memory devices 1200a to 1200k in response to a request from the host 1015.

[0122] In an embodiment, the memory controller 1100 may issue an operation command to the plurality of resistive memory devices 1200 a to 1200 k for controlling the plurality of resistive memory devices 1200 a to 1200 k.

[0123] In some embodiments, each of the plurality of resistive memory devices 1200a to 1200k may include a Figures 1 to 18 A two-terminal SOT MRAM device among the two-terminal SOT MRAM devices of various embodiments are described.

[0124] Fig. 22 The description according to the embodiment is shown Fig.21 1 is a block diagram of a memory device 1020 of an electronic system 1000.

[0125] exist Fig. 22 , for convenience, only one resistance type memory device 1200a is shown communicating with the memory controller 1100. However, the details discussed herein with respect to the resistance type memory device 1200a may also be applicable to the other resistance type memory devices 1200b to 1200k.

[0126] refer to Fig. 22 , the memory system 1020 may include a memory controller 1100 and a resistance-type memory device 1200a. The memory controller 1100 may send a command CMD and an address ADDR to the resistance-type memory device 1200a. The memory controller 1100 may exchange data DQ with the resistance-type memory device 1200a.

[0127] refer to Fig.21 and Fig.12 , the memory controller 1100 may input data to the resistance-type memory device 1200 a or may output data from the resistance-type memory device 1200 a based on a request from the host 1015 .

[0128] Fig.23 According to some embodiments Fig. 22 1020 in a memory system 1020 of FIG. 100a.

[0129] 3 , the resistance-type memory device 1200 a may include a control logic 1210 , an address register 1220 , a memory body control logic 1230 , a row address multiplexer 1240 , a column address latch 1250 , a row decoder 1260 , a column decoder 1270 , a memory cell array 1300 , a sense amplifier circuit 1285 , an input / output (I / O) gating circuit 1290 , a data input / output (I / O) buffer 1295 , and a refresh counter 1245 .

[0130] The memory cell array 1300 may include first to eighth bank arrays 1310 to 1340. The row decoder 1260 may include first to fourth bank row decoders 1260a to 1260d respectively coupled to the first to fourth bank arrays 1310 to 1340, the column decoder 1270 may include first to fourth bank column decoders 1270a to 1270d respectively coupled to the first to fourth bank arrays 1310 to 1340, and the sense amplifier unit 1285 may include first to fourth bank sense amplifiers 1285a to 1285d respectively coupled to the first to fourth bank arrays 1310 to 1340. The first memory bank array 1310 to the fourth memory bank array 1340, the first memory bank row decoder 1260a to the fourth memory bank row decoder 1260d, the first memory bank column decoder 1270a to the fourth memory bank column decoder 1270d, and the first memory bank sense amplifier 1285a to the fourth memory bank sense amplifier 1285d may form the first memory bank to the fourth memory bank. Each of the first memory bank array 1310 to the fourth memory bank array 1340 may include a plurality of resistance-type memory cells RMC, and each of the resistance-type memory cells RMC is coupled to a corresponding word line and a corresponding bit line. Although the resistance-type memory device 1200a is Fig.23 1200a, but the resistance type memory device 1200a may include any number of memory banks. In some embodiments, different memory banks and row decoders and column decoders may be formed on a single semiconductor chip (e.g., a die formed from a wafer). In other embodiments, each group (or a set of different groups) of different memory banks, row decoders, and column decoders may be formed on a plurality of different corresponding semiconductor chips, such as a stack of semiconductor chips.

[0131] The address register 1220 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 1100. The address register 1220 may provide the received bank address BANK_ADDR to the bank control logic 1230, may provide the received row address ROW_ADDR to the row address multiplexer 1240, and may provide the received column address COL_ADDR to the column address latch 1250.

[0132] The bank control logic 1230 may generate a bank control signal in response to the bank address BANK_ADDR. One of the first bank row decoder 1260a to the fourth bank row decoder 1260d corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal, and one of the first column decoder 1270a to the fourth bank column decoder 1270d corresponding to the bank address BANK_ADDR may be activated in response to the bank control signal.

[0133] The row address multiplexer 1240 may receive a row address ROW_ADDR from the address register 11220 and may receive a refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 11240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to fourth bank row decoders 1260a to 1260d.

[0134] The activated one of the first to fourth bank row decoders 1260a to 1260d may decode the row address RA output from the row address multiplexer 1240 and may activate a word line corresponding to the row address RA. For example, the activated bank row decoder may apply a word line driving voltage to the word line corresponding to the row address RA.

[0135] The column address latch 1250 may receive the column address COL_ADDR from the address register 1220 and may temporarily store the received column address COL_ADDR. In some embodiments, in burst mode, the column address latch 1250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 1250 may apply the temporarily stored or generated column address to the first to fourth bank column decoders 1270a to 1270d.

[0136] An activated one of the first to fourth bank column decoders 1270 a to 1270 d may decode the column address COL_ADDR output from the column address latch 1250 and may control the input / output gating circuit 1290 to output data corresponding to the column address COL_ADDR.

[0137] The I / O gating circuit 1290 may include a circuit for gating input / output data. The I / O gating circuit 1290 may also include a read data latch for storing data output from the first memory array 1310 to the fourth memory array 1340, and a write driver for writing data into the first memory array 1310 to the fourth memory array 1340.

[0138] Data to be read from one of the first to fourth memory bank arrays 1310 to 1340 may be sensed by a sense amplifier coupled to the one of the memory bank arrays from which the data is to be read, and may be stored in a read data latch. The data DQ stored in the read data latch may be provided to the memory controller 1100 via the data I / O buffer 1295. The data DQ to be written into one of the first to fourth memory bank arrays 1310 to 1340 may be provided from the memory controller 100 to the data I / O buffer 11295. The write driver may write the data DQ into one of the first to fourth memory bank arrays 1310 to 1340.

[0139] The control logic 1210 may control the operation of the resistance type memory device 1200a. For example, the control logic 1210 may generate a control signal CTL for the resistance type memory device 1200a so as to perform a write operation or a read operation. The control logic 1210 may include, for example, a command decoder 1211 that decodes a command CMD received from the memory controller 1100 and a mode register 1212 that sets the operation mode of the resistance type memory device 1200a. The mode register 1212 may be programmed by a mode register set (MRS) command. The mode register 1212 may generate a mode signal according to the programmed operation mode.

[0140] For example, the command decoder 1211 may generate a control signal CTL corresponding to the command CMD by decoding a write enable signal ( / WE), a row address strobe signal ( / RAS), a column address strobe signal ( / CAS), a chip select signal ( / CS), etc. The control logic 1210 may provide the control signal CTL to the memory cell array 1300 .

[0141] Fig.24According to some embodiments Fig.23 An example of a first memory bank array in a resistance-type memory device.

[0142] Reference Fig.24 , the first memory bank array 1310 may include a plurality of word lines WL0 to WLn (where n is a natural number equal to or greater than 1), a plurality of bit lines BL0 to BLm (where M is a natural number equal to or greater than 1), a plurality of source lines SL0 to SLn, and a plurality of resistance-type memory cells RMC disposed at intersections between the word lines WL0 to WLn and the bit lines BL0 to BLm. Each of the resistance-type memory cells RMC may be a SOT MRAM cell. For example, the resistance-type memory cell RMC may include MTJ and SOT materials, as described above with reference to Figures 1 to 18 described.

[0143] In some embodiments, each of the resistance-type memory cells RMC may include a cell transistor CT and an MTJ and a SOT material. In one resistance-type memory cell RMC, the drain (first electrode) of the cell transistor CT may be connected to the fixed layer of the MTJ. The free layer of the MTJ may be connected to the SOT material, and the SOT material may be connected to the bit line BL0, and the source (second electrode) of the cell transistor CT may be connected to the source line SL0. The gate of the cell transistor CT may be connected to the word line WL0. Note that this configuration corresponds to the above reference Fig.12 The z-type two-terminal SOT MRAM device 400 is described. However, the embodiment is not limited thereto, and in some embodiments, the above reference Figure 13-Figure 15 The described y-type and / or x-type two-terminal SOTMRAM devices 500-700 may be based on Figure 13-Figure 15 The description is used with the modification.

[0144] The word line WL0 may be enabled by the row decoder 1260 and may be connected to the word line driver 1311 driving a word line selection voltage. The word line selection voltage activates the word line WL0 in order to read or write a logic state of the MTJ.

[0145] The source line SL0 is connected to a source line voltage generator 1294. The source line voltage generator 1294 may receive and decode address signals and read / write signals, and may generate a source line selection signal in the selected source line SL0. A ground reference voltage may be supplied to the unselected source lines SL1 to SLn.

[0146] The bit line BL0 is connected to a column selection circuit 1292 driven by column selection signals CSL0 to CSLm. The column selection signals CSL0 to CSLm are selected by a column decoder 1270a. For example, the selected column selection signal CSL0 turns on the column selection transistor in the column selection circuit 1292 and selects the bit line BL0. In an embodiment, the logic state of the MTJ can be read from the bit line BL0 by a sense amplifier 1285a. In an embodiment, a write current applied by a write driver 1291 can be transmitted to the selected bit line BL0 and written to the MTJ.

[0147] According to various embodiments, a z-type, y-type, or x-type two-terminal SOT MRAM having a SOT material may be implemented as an on-chip nonvolatile memory.

[0148] Fig.25 A circuit diagram is shown illustrating an example of an on-chip non-volatile memory according to an embodiment.

[0149] like Fig.25 The on-chip non-volatile memory 2000 shown may include a semiconductor chip 2000. The semiconductor chip 2000 may include a computing logic 2100 and one or more MRAM devices 2200. In some embodiments, the MRAM devices 2200 may each be a semiconductor device described above. Figure 1-Figure 18 One or more of the described z-type, y-type, or x-type two-terminal SOT MRAM devices.

[0150] The on-chip non-volatile memory 2000 can provide SRAM-like performance while providing significantly higher bit cell density and a dramatic improvement in system-level energy efficiency. In addition, in some embodiments, the on-chip non-volatile memory 2000 can be implemented on a satellite or other space-related device that is subject to high-energy radiation, and the on-chip non-volatile memory 2000 can prevent soft errors as described above.

[0151] Exemplary Embodiments

[0152] Various exemplary embodiments are described with reference to the following numerical terms.

[0153] 1. A magnetoresistive random access memory (MRAM) device, comprising: a magnetic tunnel junction; and a spin-orbit torque material, wherein the spin-orbit torque material generates spin polarization along one or more axes based on a current applied to the spin-orbit torque material.

[0154] 2. The MRAM device of clause 1, wherein the spin-orbit torque material is a low-symmetry spin-orbit torque material in which spin polarization, spin current, and charge current are not forced to be orthogonal.

[0155] 3. The MRAM device of clause 1 or 2, wherein the magnetic tunnel junction includes a free layer, and the free layer contacts an upper surface of the spin-orbit torque material.

[0156] 4. The MRAM device of clause 1 or 2, wherein the magnetic tunnel junction includes a free layer, and the free layer contacts a bottom surface of the spin-orbit torque material.

[0157] 5. The MRAM device of clauses 1-4, further comprising only two electrodes, a first electrode of the two electrodes coupled to the magnetic tunnel junction, and a second electrode of the two electrodes coupled to the spin-orbit torque material.

[0158] 6. The MRAM device of clause 5, further comprising one or more transistors connected to at least one of the first electrode or the second electrode.

[0159] 7. The MRAM device of clauses 1-6, wherein the current generates a spin-orbit torque and a spin-transfer torque.

[0160] 8. The MRAM device of clauses 1-7, wherein the direction of the current determines one of a parallel state or an antiparallel state as a final state of the MRAM device.

[0161] 9. The MRAM device of clauses 1-8, wherein the magnitude of the current determines a switching time of the MRAM device.

[0162] 10. The MRAM device of clauses 1-9, wherein the magnetic tunnel junction has an easy-axis anisotropy in an in-plane orientation relative to the plane of the spin-orbit torque material.

[0163] 11. An MRAM device according to clause 10, wherein current flows through the spin-orbit torque material and generates spins polarized coaxially with the current and / or spins polarized orthogonally to the current, and wherein current flows through the spin-orbit torque material and generates spins polarized coaxially with the current, generates spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or generates spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

[0164] 12. The MRAM device of clauses 1-9, wherein the magnetic tunnel junction has an easy-axis anisotropy in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

[0165] 13. An MRAM device according to clause 12, wherein current flows through the spin-orbit torque material and generates spins polarized coaxially with the current and / or spins polarized orthogonally to the current, and wherein current flows through the spin-orbit torque material and generates spins polarized coaxially with the current, generates spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or generates spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

[0166] 14. The MRAM device of clauses 1-13, wherein spins orthogonal to the current flow generated by the spin-orbit torque material in an in-plane orientation are larger than spins coaxial with the current flow and / or orthogonal to the current flow generated by the spin-orbit torque material in an out-of-plane orientation.

[0167] 15. The MRAM device of clauses 1-9 or 12-14, wherein the magnetic tunnel junction is an out-of-plane magnetic tunnel junction, and wherein the MRAM device switches between a parallel state and an antiparallel state without a field based on current being applied to the spin-orbit torque material.

[0168] 16. A method of operating a magnetoresistive random access memory (MRAM) device according to clauses 1-15, the method comprising: applying a current to a spin-orbit torque material to produce spin polarization along one or more axes in the MRAM device.

[0169] 17. A method of operating a magnetoresistive random access memory (MRAM) device according to clauses 1-15, the method comprising: applying a current to a spin-orbit torque material to produce field-free switching in the MRAM device.

[0170] 18. The method of clause 17, wherein applying the current switches the MRAM device between the parallel state and the antiparallel state in the absence of a magnetic bias field and / or an external magnetic field.

[0171] 19. A magnetoresistive random access memory (MRAM) device comprising: an in-plane magnetic tunnel junction; and a spin-orbit torque material, wherein the MRAM device switches between a parallel state and an anti-parallel state without a field based on a current applied to the spin-orbit torque material.

[0172] 20. The MRAM device of clause 19, wherein applying the current switches the MRAM device between the parallel state and the antiparallel state in the absence of a magnetic bias field and / or an external magnetic field.

[0173] 21. The MRAM device of clauses 19-20, wherein the spin-orbit torque material is a low symmetry spin-orbit torque material in which spin polarization, spin current and charge current are not forced to be orthogonal.

[0174] 22. The MRAM device of clauses 19-21, wherein the in-plane magnetic tunnel junction includes a free layer, and the free layer contacts an upper surface of the spin-orbit torque material.

[0175] 23. The MRAM device of clauses 19-21, wherein the in-plane magnetic tunnel junction includes a free layer, and the free layer contacts a bottom surface of the spin-orbit torque material.

[0176] 24. The MRAM device of clauses 19-23, further comprising only two electrodes, a first electrode of the two electrodes coupled to the in-plane magnetic tunnel junction, and a second electrode of the two electrodes coupled to the spin-orbit torque material.

[0177] 25. The MRAM device of clause 24, further comprising one or more transistors connected to at least one of the first electrode or the second electrode.

[0178] 26. The MRAM device of clauses 19-25, wherein the spin-orbit torque material is a conventional spin-orbit torque material that produces spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material.

[0179] 27. An MRAM device according to clauses 19-25, wherein the spin-orbit torque material is an unconventional spin-orbit torque material that produces spins polarized coaxially with the current, produces spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or produces spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

[0180] 28. The MRAM device of clause 19, wherein a critical dimension of the in-plane magnetic tunnel junction is from about 10 nm to about 43 nm, and the current is from about 80 μA to about 160 μA.

[0181] 29. A magnetoresistive random access memory (MRAM) device comprising: an out-of-plane magnetic tunnel junction; and a spin-orbit torque material, wherein the MRAM device switches between a parallel state and an anti-parallel state without a field based on a current applied to the spin-orbit torque material.

[0182] 30. The MRAM device of clause 29, wherein applying the current switches the MRAM device between the parallel state and the antiparallel state in the absence of a magnetic bias field and / or an external magnetic field.

[0183] 31. The MRAM device of clauses 29-30, wherein the spin-orbit torque material is a low symmetry spin-orbit torque material in which spin polarization, spin current and charge current are not forced to be orthogonal.

[0184] 32. The MRAM device of clauses 29-31, wherein the out-of-plane magnetic tunnel junction includes a free layer, and the free layer contacts an upper surface of the spin-orbit torque material.

[0185] 33. The MRAM device of clauses 29-31, wherein the out-of-plane magnetic tunnel junction includes a free layer, and the free layer contacts a bottom surface of the spin-orbit torque material.

[0186] 34. The MRAM device of clauses 29-33, further comprising only two electrodes, a first electrode of the two electrodes coupled to the out-of-plane magnetic tunnel junction, and a second electrode of the two electrodes coupled to the spin-orbit torque material.

[0187] 35. The MRAM device of clause 34, further comprising one or more transistors connected to at least one of the first electrode or the second electrode.

[0188] 36. The MRAM device of clauses 29-35, wherein the spin-orbit torque material is a conventional spin-orbit torque material that produces spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material.

[0189] 37. An MRAM device according to clauses 29-35, wherein the spin-orbit torque material is an unconventional spin-orbit torque material that produces spins polarized coaxially with the current, produces spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or produces spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

[0190] 38. A method for manufacturing a two-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device, the method comprising: depositing a spin-orbit torque (SOT) material on a substrate; depositing a magnetic tunnel junction (MTJ) stack on the SOT material; forming a SOT line from the SOT material; forming an MTJ column from the MTJ stack; and forming a first electrode on the MTJ column and forming a second electrode on a portion of the SOT line.

[0191] 39. A method according to clause 38, wherein the spin-orbit torque material is a low-symmetry spin-orbit torque material in which the spin polarization, spin current and charge current are not forced to be orthogonal.

[0192] 40. The method of clauses 38 to 39, wherein forming the SOT line comprises: depositing a mask on the MTJ stack; and patterning the SOT line based on the mask;

[0193] 41. A method according to clauses 38-40, wherein the SOT lines are patterned by two-step ion beam etching using mask-based electron beam lithography (EBL).

[0194] 42. The method of clauses 38-41, wherein forming the MTJ pillar comprises: depositing a mask on the SOT line; and patterning the MTJ pillar based on the mask.

[0195] 43. A method according to clauses 38 to 42, wherein the MTJ pillars are patterned with electron beam lithography (EBL) by two-step ion beam etching based on the mask.

[0196] 44. A method according to clauses 38-43, wherein forming the first electrode and the second electrode includes: depositing an insulating material on the SOT line and the MTJ column and etching the insulating material to expose the top layer of the MTJ column; depositing a mask on the insulating material; and patterning the top electrode material above the top layer of the MTJ column and above a portion of the top layer of the SOT line based on the mask to form a first electrode connected to the MTJ column and a second electrode connected to the SOT line.

[0197] 45. A method according to clauses 38-44, wherein the MTJ stack has a low resistance area product.

[0198] 46. ​​The method of clauses 38-45, wherein the MTJ stack is deposited via magnetron sputtering on a surface passivated CMOS die.

[0199] 47. The method of clauses 37-45, wherein the minimum width of the SOT line is from about 5 nm to about 30 nm.

[0200] 48. The method of clauses 38-47, wherein the top electrode material comprises at least one of Cu, Ti or Au.

[0201] Applications of the above technology include, but are not limited to, magnetoresistive random access memory (MRAM) (including SOT MRAM and STT MRAM), last level cache applications, edge computing applications and / or Internet of Things (IoT) applications.

[0202] Advantages provided by the two-terminal SOT MRAM device according to various embodiments described above include, but are not limited to: 1) write current reduction of >2 times compared to related art STT MRAM technology; 2) 4 times faster than related art STT MRAM technology; 3) ultra-high density physical layout (down to -12F^2 per magnetic tunnel junction (MTJ), where F represents the minimum half-pitch feature size of the chip layout), which is about 4 to 8 times denser than 6T SRAM technology due to the one transistor, one resistor (1T1R) bit cell layout; 4) write scheme supports all types of SOT switching, including x-type, y-type and z-type; 5) SRAM-like performance with nearly an order of magnitude improved bit cell density and ultra-low leakage current; 6) CMOS compatible - MRAM can be integrated for BEOL (back end of line) processing with a thermal budget below 400C; and / or 7) energy-efficient non-volatile data storage. However, embodiments are not limited to these advantages, and some embodiments may provide additional improvements not discussed above.

[0203] It should be understood that the embodiments are not limited to the various embodiments described above, but various other changes and modifications may be made therein without departing from the spirit and scope thereof as set forth in the appended claims.

Claims

1. A magnetoresistive random access memory (MRAM) device, comprising: Magnetic tunnel junction; and Spin-orbit torque materials, Wherein, based on the current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or more axes.

2. The MRAM device according to claim 1, wherein: The spin-orbit torque material is a low symmetry spin-orbit torque material in which the spin polarization, spin current and charge current are not forced to be orthogonal.

3. The MRAM device according to claim 1, wherein: The magnetic tunnel junction includes a free layer, and the free layer contacts an upper surface of the spin-orbit torque material.

4. The MRAM device according to claim 1, wherein: The magnetic tunnel junction includes a free layer, and the free layer contacts a bottom surface of the spin-orbit torque material. 5 . The MRAM device of claim 1 , further comprising only two electrodes, a first electrode of the two electrodes being coupled to the magnetic tunnel junction, and a second electrode of the two electrodes being coupled to the spin-orbit torque material.

6. The MRAM device according to claim 1, wherein: The current generates a spin-orbit torque and a spin-transfer torque.

7. The MRAM device according to claim 6, wherein: The direction of the current determines one of a parallel state or an antiparallel state as a final state of the MRAM device.

8. The MRAM device according to claim 6, wherein: The magnitude of the current determines the switching time of the MRAM device.

9. The MRAM device according to claim 1, wherein: The current flows through the spin-orbit torque material and generates spins polarized coaxially with the current and / or spins polarized orthogonally with the current, and wherein the current flows through the spin-orbit torque material and generates spins polarized coaxially with the current, generates spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or generates spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

10. The MRAM device according to claim 1, wherein: The magnetic tunnel junction is an out-of-plane magnetic tunnel junction, and Wherein, the MRAM device switches between a parallel state and an antiparallel state without a field based on a current applied to the spin-orbit torque material.

11. A magnetoresistive random access memory (MRAM) device, comprising: In-plane magnetic tunnel junction; and Spin-orbit torque materials, Wherein, the MRAM device switches between a parallel state and an antiparallel state without a field based on a current applied to the spin-orbit torque material.

12. The MRAM device according to claim 11, wherein: Applying the current causes the MRAM device to switch between the parallel state and the antiparallel state in the absence of a magnetic bias field and / or an external magnetic field.

13. The MRAM device according to claim 11, wherein: The spin-orbit torque material is a low-symmetry spin-orbit torque material in which the spin polarization, spin current and charge current are not forced to be orthogonal.

14. The MRAM device according to claim 11, wherein: The in-plane magnetic tunnel junction includes a free layer, and the free layer contacts an upper surface of the spin-orbit torque material.

15. The MRAM device according to claim 11, wherein: The in-plane magnetic tunnel junction includes a free layer, and the free layer contacts a bottom surface of the spin-orbit torque material.

16. The MRAM device of claim 11, further comprising only two electrodes, a first electrode of the two electrodes coupled to the in-plane magnetic tunnel junction, and a second electrode of the two electrodes coupled to the spin-orbit torque material. 17 . The MRAM device of claim 16 , further comprising one or more transistors connected to at least one of the first electrode or the second electrode.

18. The MRAM device according to claim 11, wherein: The spin-orbit torque material is a conventional spin-orbit torque material that produces spins polarized orthogonally to the current in an in-plane orientation relative to a plane of the spin-orbit torque material.

19. The MRAM device according to claim 11, wherein: The spin-orbit torque material is an unconventional spin-orbit torque material, which generates spins polarized coaxially with the current, generates spins polarized orthogonally to the current in an in-plane orientation relative to the plane of the spin-orbit torque material, and / or generates spins polarized orthogonally to the current in an out-of-plane orientation relative to the plane of the spin-orbit torque material.

20. A magnetoresistive random access memory (MRAM) device, comprising: Out-of-plane magnetic tunnel junction; and Spin-orbit torque materials, Wherein, the MRAM device switches between a parallel state and an antiparallel state without a field based on a current applied to the spin-orbit torque material.

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