Transistor device with semiconductor spacer and method of manufacturing same

Abstract

Transistor devices and methods of forming transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor on top of the lower transistor. Further, the transistor device includes a semiconductor spacer between the upper transistor and the lower transistor.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, and more particularly, to three-dimensional transistor structures. Background Art

[0002] The size of transistors in integrated circuit (IC) devices continues to decrease to allow for scaling of logic elements. This has led to the development of gate-all-around (GAA) structures such as multi-bridge channel field effect transistors (MBCFETs). TM ) and nanosheet FET (NSFET). In addition, as technology to increase transistor density continues to advance, three-dimensional device structures, such as stacked transistors, are being considered.

[0003] The stacked transistor may include a first transistor and a second transistor. The first transistor may be a transistor of a first type (e.g., an n-type metal oxide semiconductor (NMOS) transistor), and the second transistor may be a transistor of a second type (e.g., a p-type metal oxide semiconductor (PMOS) transistor). The first type of transistor and the second type of transistor may be complementary to each other and may therefore be part of a complementary metal oxide semiconductor (CMOS) IC. The first transistor and the second transistor may be stacked in any order (e.g., the first transistor on top of the second transistor, or the second transistor on top of the first transistor), thereby producing a stack including a top / upper device and a bottom / lower device. Summary of the invention

[0004] According to some embodiments herein, a transistor device may include a substrate and a transistor stack on the substrate. The transistor stack may include a lower transistor and an upper transistor on top of the lower transistor. In addition, the transistor device may include a semiconductor spacer between the upper transistor and the lower transistor.

[0005] According to some embodiments herein, a transistor device may include a substrate and a transistor stack on the substrate. The transistor stack may include a lower transistor and an upper transistor on top of the lower transistor. The upper transistor and the lower transistor may each include a semiconductor channel layer. The transistor device may include a silicon spacer separating the upper transistor from the lower transistor. The silicon spacer may not contain nitrogen. In addition, the transistor device may include a bottom isolation region between the substrate and the semiconductor channel layer of the lower transistor.

[0006] According to some embodiments herein, a method of forming a transistor device may include forming a stack of semiconductor layers alternating with sacrificial gate layers on a substrate. Another sacrificial layer may be between the substrate and the lowest sacrificial gate layer in the sacrificial gate layers. In addition, the method may include replacing another sacrificial layer with a bottom isolation region. An upper semiconductor layer in the semiconductor layer may include an upper channel layer of an upper transistor. A lower semiconductor layer in the semiconductor layer may include a lower channel layer of a lower transistor. An intermediate semiconductor layer in the semiconductor layer may separate the upper channel layer from the lower channel layer. The intermediate semiconductor layer in the semiconductor layer may be thicker in a vertical direction than each upper channel layer and each lower channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1A is a schematic block diagram of a transistor stack of a transistor device according to some embodiments herein.

[0008] Figure 1B It is shown Figure 1A A schematic block diagram of further details of the transistor stack.

[0009] Figure 2A-2P It is shown that the formation Figure 1B A cross-sectional view of the operation of a transistor stack.

[0010] Figure 3 is corresponding to Figure 2A-2P Flowchart of the operations shown in . DETAILED DESCRIPTION

[0011] According to embodiments herein, a transistor device is provided that includes a transistor stack in which an upper transistor and a lower transistor are separated from each other by a semiconductor spacer. The semiconductor spacer may occupy a space that would otherwise be occupied by a middle dielectric isolation (MDI) comprising an insulating material.

[0012] An MDI including an insulating material may be interposed between an upper transistor and a lower transistor of a transistor stack to separate and electrically isolate the upper transistor and the lower transistor from each other. However, for a replacement metal gate (RMG) process that may be performed on a transistor stack, the MDI may be undesirably thin. The thickness of the MDI may be limited by, for example, voids and residues (e.g., silicon germanium residues) that may be generated when a sacrificial layer (e.g., silicon germanium) is replaced with an insulating material (e.g., silicon nitride) of the MDI.

[0013] In addition, the critical thickness of the sacrificial layer may make it difficult, if not impossible, to form a bottom dielectric isolation (BDI) for the transistor stack. For example, the sacrificial layer may have a higher concentration of germanium (e.g., 50-55% germanium) than the sacrificial gate layer (e.g., 20-25% germanium), and the higher concentration sacrificial layer may be more difficult to form, more difficult to remove (e.g., more likely to leave residue), and / or more likely to have defects than the lower concentration sacrificial gate layer. As a result, it may be difficult to replace the higher concentration sacrificial layer with sufficiently thick MDI and BDI regions.

[0014] However, according to embodiments herein, the transistor stack may include a semiconductor (rather than a dielectric / insulating) spacer between the upper transistor and the lower transistor. The semiconductor spacer may include, for example, silicon, and may be free of nitrogen, carbon, oxygen, and germanium. The semiconductor spacer may be formed when forming a semiconductor channel layer for a transistor stack, rather than being formed as a substitute for a sacrificial layer. Therefore, the semiconductor spacer may be thicker than an MDI including an insulating material that replaces the sacrificial layer. Therefore, when a semiconductor spacer is formed instead of an MDI including an insulating material, voids and residues may be reduced or prevented. In addition, the absence of a sacrificial layer before the semiconductor spacer may facilitate the formation of a BDI for a transistor stack.

[0015] Example embodiments will be described in more detail with reference to the accompanying drawings.

[0016] Figure 1A 1 is a schematic block diagram of a transistor stack 101 of a transistor device 100 according to some embodiments herein. The transistor stack 101 includes a stacked lower transistor Tb having a plurality of lower semiconductor channel layers 120b and a stacked upper transistor Ta having a plurality of upper semiconductor channel layers 120a. The channel layers 120a, 120b may include, for example, silicon, and may not contain germanium and carbon. The lower transistor Tb is located between the upper transistor Ta and a substrate 110 (e.g., a silicon substrate or other semiconductor substrate) in a vertical direction Z. The semiconductor spacer 130 may be located between the upper transistor Ta and the lower transistor Tb in a vertical direction Z. In addition, a bottom isolation region (e.g., BDI) 170 may be located between the lower transistor Tb and the substrate 110 in a vertical direction Z.

[0017] The lower channel layer 120b of the lower transistor Tb is located between a pair of lower source / drain (S / D) regions 140 electrically connected to the lower channel layer 120b in the first horizontal (i.e., lateral) direction X. The first horizontal direction X and the vertical direction Z may be perpendicular to each other, and the second horizontal (i.e., lateral) direction Y may be perpendicular to each of the first horizontal direction X and the vertical direction Z. Each lower channel layer 120b may be implemented by, for example, a nanosheet or nanowire between the lower S / D regions 140. Similarly, the upper channel layer 120a of the upper transistor Ta may be located between a pair of upper S / D regions 150 electrically connected to the upper channel layer 120a in the first horizontal direction X, and each upper channel layer 120a may be implemented by, for example, a nanosheet or nanowire between the upper S / D regions 150.

[0018] In some embodiments, the upper S / D region 150 may include a semiconductor material different from that of the lower S / D region 140. As an example, the upper S / D region 150 may include silicon germanium and the lower S / D region 140 may include silicon carbide, or vice versa. In other embodiments, the upper S / D region 150 may include the same semiconductor material as the lower S / D region 140.

[0019] The S / D isolation region 160 may be located between the upper S / D region 150 and the lower S / D region 140 in the vertical direction Z. The S / D isolation region 160 includes an insulating material (e.g., oxide) that electrically isolates and physically separates the upper S / D region 150 from the lower S / D region 140. The S / D isolation region 160 may also be referred to herein as “blocking spacers” because they are spacers between the S / D regions 140, 150 and can block the S / D regions 140, 150 from contacting the spacer 130.

[0020] To simplify the diagram, Figure 1A Only one transistor stack 101 is shown in FIG. 1 . However, according to some embodiments, the device 100 may include two, three, four or more transistor stacks 101 .

[0021] Figure 1B is a schematic block diagram showing further details of the transistor stack 101. Figure 1B As shown, the upper transistor Ta of the transistor stack 101 may include an upper metal gate 180a (also referred to as gate 180a, upper gate 180a) on the upper channel layer 120a. For example, the gate 180a may be between the channel layers 120a. Similarly, the lower transistor Tb of the transistor stack 101 may include a lower metal gate 180b (also referred to as gate 180b, lower gate 180b) on the lower channel layer 120b (for example, between the lower channel layers 120b).

[0022] The gate 180b may be spaced apart from the lower S / D region 140 in the direction X by an insulating spacer 190. The spacer 190 may be on the sidewall of the gate 180b and between the lower channel layers 120b in the vertical direction Z. Similarly, the gate 180a may be spaced apart from the upper S / D region 150 in the direction X by an insulating spacer 190, and the insulating spacer 190 may be on the sidewall of the gate 180a and between the upper channel layers 120a in the vertical direction Z. In some embodiments, the spacer 190 may contact the sidewalls of the lower S / D region 140, the upper S / D region 150, and the gates 180a, 180b. The sidewall of the lower channel layer 120b may contact the lower S / D region 140, and the sidewall of the upper channel layer 120a may contact the upper S / D region 150.

[0023] The bottom isolation region 170 may be located between the substrate 110 and the channel layer 120 b in the vertical direction Z. In some embodiments, the bottom isolation region 170 may be located between the substrate 110 and the gate 180 b in the vertical direction Z. The bottom isolation region 170 includes an insulating material such as silicon nitride.

[0024] Furthermore, the spacers 190 may include, for example, nitrogen (eg, silicon nitride). The spacers 190 may also be referred to herein as "internal spacers" because they may be located between nanosheet / nanowire channels within a transistor.

[0025] In some embodiments, the uppermost surface of the spacer 130 may contact the lowermost surface of the spacer 190 on the sidewall of the gate 180a, and the lowermost surface of the spacer 130 may contact the uppermost surface of the spacer 190 on the sidewall of the gate 180b. In addition, the S / D isolation region 160 may overlap a portion of the sidewall of the gate 180a (and a portion of the spacer 190 thereon) and a portion of the sidewall of the gate 180b (and a portion of the spacer 190 thereon) in the lateral direction X. Therefore, the uppermost surface of the S / D isolation region 160 may be at a higher level than the uppermost surface of the spacer 130 in the vertical direction Z, and the lowermost surface of the S / D isolation region 160 may be at a lower level than the lowermost surface of the spacer 130 in the vertical direction Z. Therefore, the S / D isolation region 160 may be thicker than the spacer 130 in the vertical direction Z, and thus the S / D regions 140, 150 may be blocked / prevented from contacting the spacer 130.

[0026] Some of the spacers 190 may have a thickness t1 in the vertical direction Z that is thinner than a thickness t2 of other spacers in the spacers 190. For example, a spacer 190 in the spacers 190 that is adjacent to the spacer 130 (e.g., in contact with the spacer 130) may have a thicker thickness t2. As used herein with respect to the spacers 190 and the spacers 130, the term "adjacent" means that there are no other spacers 190 between the spacers 190 and the spacers 130. In some embodiments, the thickness t2 may be more than 50% thicker than the thickness t1. As an example, the thickness t1 may be about 8 nanometers (nm) and the thickness t2 may be about 15 nm. In addition, the portions / layers of the gates 180a and 180b having the spacers 190 thereon may share the thickness of the spacer 190. Thus, a lower (eg, lowermost) portion / layer of upper gate 180a and an upper (eg, uppermost) portion / layer of lower gate 180b may have a thickness t2, and remaining portions / layers of gates 180a, 180b may have a thickness t1.

[0027] The spacer 130 has a thickness t3 that is thicker than each of the thicknesses t1 and t2 in the vertical direction Z. For example, the thickness t3 may be greater than 12 nm (or greater than 12.5 nm), greater than 15 nm, greater than 20 nm, or even greater than 30 nm. In some embodiments, the thickness t3 may be in the range of 20-40 nm. In contrast, a conventional MDI including an insulating material that replaces a sacrificial layer may have a thickness of 10-12 nm. The spacer 130 may be thicker than a conventional MDI because the spacer 130 includes a semiconductor material that may be formed when forming the channel layer 120, rather than being formed as a substitute for a sacrificial layer.

[0028] The bottom isolation region 170 has a thickness t4, which may be thinner than the spacer 130 in the vertical direction Z. For example, the thickness t4 may be in the range of 10-12 nm. According to some embodiments, the thickness t4 may be thicker than the thickness t1.

[0029] Each S / D isolation region 160 may be on a corresponding sidewall of the spacer 130, and may have a thickness t5 that is thicker than the thickness t3 of the spacer 130 in the vertical direction Z. As a result, the S / D isolation region 160 may prevent the S / D regions 140, 150 from contacting the spacer 130. In addition, the channel layers 120a, 120b may have a thickness t6 that is thinner than the thickness t3 in the vertical direction Z. Therefore, the spacer 130 may be thicker than each channel layer 120a, 120b. For example, the thickness t6 of each channel layer 120a, 120b may be about 7 nm, and thus may be thinner than the thickness t1 and less than half (or even less than one-third, less than one-quarter, or less than one-fifth) of the thickness t3.

[0030] The width w of the spacer 130 in the lateral direction X can be equal to the width of each channel layer 120a, 120b. The width w can be, for example, about 20nm. The width w can be wider than the width of the gates 180a and 180b because the spacer 190 can be on the sidewalls of the gates 180a and 180b. In some embodiments, the outer sidewalls of the spacer 190 can be collinear with the sidewalls of the spacer 130 and the sidewalls of the channel layers 120a, 120b in the vertical direction Z.

[0031] The upper transistor Ta and the lower transistor Tb can be different types of MOSFETs. For example, the upper transistor Ta and the lower transistor Tb can be a PMOS transistor and an NMOS transistor, respectively, and vice versa. As an example, the PMOS and NMOS transistors can be provided by S / D regions containing silicon germanium and silicon carbide, respectively. The spacer 130 separates the lower channel layer 120b of the lower transistor Tb from the upper channel layer 120a of the upper transistor Ta. The spacer 130 can include, for example, silicon, and can be free of nitrogen and germanium. In some embodiments, the channel layers 120a, 120b can include the same semiconductor material as the spacer 130. For example, the semiconductor material can include crystalline (e.g., single crystal) silicon, and can be free of germanium, free of nitrogen (e.g., free of nitride), free of carbon and free of oxygen (e.g., free of oxide).

[0032] The spacer 130 and the channel layers 120a, 120b are all semiconductor layers in the same transistor stack 101. Therefore, the lower channel layer 120b may be referred to herein as a "lower channel layer" in the semiconductor layer, the upper channel layer 120a may be referred to herein as an "upper channel layer" in the semiconductor layer, and the spacer 130 may be referred to herein as an "intermediate channel layer" in the semiconductor layer.

[0033] To simplify the diagram, Figure 1A The lower S / D region 140, the upper S / D region 150 and the S / D isolation region 160 shown on the left are Figure 1B is omitted from the view, and Figure 1A The lower S / D region 140, the upper S / D region 150, and the S / D isolation region 160 shown on the right are also Figure 1B Shown in.

[0034] To further simplify the diagram, Figure 1B The gate insulating layer is omitted in the view of FIG. However, it will be understood that the gate insulating layer may extend between each channel layer 120 a, 120 b and the metal gates 180 a and 180 b. The gate insulating layer may surround each channel layer 120 a, 120 b and may be thinner than the spacer 190 .

[0035] In some embodiments, the channel layers 120a, 120b of the upper transistor Ta and the lower transistor Tb may have the same width w. In other embodiments, the lower transistor Tb may be wider than the upper transistor Ta in the direction X. Therefore, Figure 1B The spacers 130 , bottom isolation regions 170 , S / D isolation regions 160 , and / or other features shown in FIG. 1 may be implemented in transistor stacks having various shapes.

[0036] Figure 2A-2P It is shown that the formation Figure 1B A cross-sectional view of the operation of transistor stack 101. Figure 3 is corresponding to Figure 2A-2P To simplify the illustration, Figure 2A-2P The elements formed on the left side of the channel layers 120a, 120b (eg, Figure 1A The lower S / D region 140, upper S / D region 150 and S / D isolation region 160 are shown on the left side). However, it will be understood that Figure 2A-2P The operations performed on the right side of the channel layers 120a, 120b may be simultaneously performed on the left side of the channel layers 120a, 120b.

[0037] like Figure 2A and Figure 3 As shown, the operation may include forming (block 310) a stack of semiconductor channel layers 120 on a substrate 110. In some embodiments, the channel layers 120a, 120b may be nanosheets, and the stack may therefore be a stack of nanosheets. The lower stack includes the channel layer 120b, and the upper stack includes the channel layer 120a. The lower stack is separated from the upper stack by a semiconductor spacer 130, which may be formed simultaneously with the channel layers 120a, 120b and formed of the same semiconductor material as the channel layers 120a, 120b. Thus, the spacer 130 may be formed without replacing a sacrificial layer having a high concentration of germanium.

[0038] The lower stack, the upper stack, and the spacer 130 may together provide a single stack of semiconductor layers alternating with sacrificial gate layers 280a and 280b. The sacrificial gate layers 280a and 280b include upper sacrificial gate layers 280a and lower sacrificial gate layers 280b. The upper sacrificial gate layers 280a may be stacked alternately with the channel layers 120a on the substrate 110, and the lower sacrificial gate layers 280b may be stacked alternately with the channel layers 120b on the substrate 110. The spacer 130 may be located in the vertical direction Z between the uppermost lower sacrificial gate layer 280b in the lower sacrificial gate layers 280b and the lowermost upper sacrificial gate layer 280a in the upper sacrificial gate layers 280a.

[0039] Another sacrificial layer 282 may be located between the substrate 110 and the lowermost of the lower sacrificial gate layers 280b in the vertical direction Z. Another sacrificial layer 282 may have a higher germanium concentration than the sacrificial gate layers 280a and 280b. For example, the sacrificial gate layers 280a and 280b may include silicon germanium epitaxially grown from the channel layers 120a, 120b and having a germanium concentration of 20-25%, and another sacrificial layer 282 may include silicon germanium epitaxially grown from the substrate 110 and having a higher germanium concentration (e.g., 50-55% germanium).

[0040] According to some embodiments, the lowest lower sacrificial gate layer 280b among the lower sacrificial gate layers 280b may be epitaxially grown from the lowest channel layer 120b among the channel layers 120b or from another sacrificial layer 282. In addition, another sacrificial layer 282 may have a thickness t4 that is thicker than a thickness t1 of some of the sacrificial gate layers 280a and 280b. For example, another sacrificial layer 282 may be thicker than the lowest lower sacrificial gate layer 280b among the lower sacrificial gate layers 280b. In some embodiments, the lowest surface of another sacrificial layer 282 may contact the highest surface of the substrate 110, and the highest surface of another sacrificial layer 282 may contact the lowest surface of the lowest lower sacrificial gate layer 280b among the lower sacrificial gate layers 280b.

[0041] The upper stack and the lower stack each form a portion of the transistor stack 101. The lower channel layer 120b forms the lower transistor Tb ( Figure 1A ), the upper channel layer 120a forms an upper transistor Ta ( Figure 1A ). A plurality of transistor stacks 101 may be spaced apart from each other on the substrate 110 and in the direction Y (and / or in the direction X). Therefore, the operation of forming the transistor stack 101 may include forming a plurality of stacks of channel layers 120a, 120b spaced apart from each other in the direction Y (and / or in the direction X).

[0042] The channel layers 120a, 120b and the spacer 130 are semiconductor layers including, for example, silicon (eg, crystalline silicon). In subsequent processes / operations, the sacrificial gate layers 280a and 280b may be replaced with metal gates 180a and 180b ( Figure 1B ) is replaced. In addition, in subsequent processes / operations, another sacrificial layer 282 may be replaced with a bottom isolation (eg, BDI) region 170 ( Figure 1B) is replaced. Because the germanium concentration of the sacrificial gate layers 280a and 280b may be different from the germanium concentration of the other sacrificial layer 282, the sacrificial gate layers 280a and 280b may have an etching selectivity relative to the other sacrificial layer 282. In addition, the sacrificial gate layers 280a and 280b and the other sacrificial layer 282 may have an etching selectivity relative to the channel layers 120a, 120b and the spacer 130.

[0043] like Figure 2B and Figure 3 As shown, the other sacrificial layer 282 can be removed and replaced with a bottom isolation region 170 (block 315), the bottom isolation region 170 comprising an insulating material, such as silicon nitride. For example, the other sacrificial layer 282 can be removed by selectively etching the other sacrificial layer 282 relative to the sacrificial gate layers 280a and 280b, the channel layers 120a, 120b, and the spacers 130. Thus, the bottom isolation region 170 can be formed between the substrate 110 and (and in contact with) the lowermost of the lower sacrificial gate layers 280b, while the spacers 130 separate the upper channel layer 120a from the lower channel layer 120b (and while the sacrificial gate layers 280a and 280b remain between the channel layers 120a, 120b). Since the bottom isolation region 170 can completely (or at least substantially) replace the other sacrificial layer 282, the bottom isolation region 170 can have a thickness t4 ( Figure 2A ).

[0044] like Figure 2C As shown, the sacrificial gate layers 280a and 280b may be narrowed in direction X to form an opening 284 between the channel layers 120a and 120b. As an example, the sidewalls of the sacrificial gate layers 280a and 280b may be selectively etched relative to the sidewalls of the bottom isolation region 170, the channel layers 120a and 120b, and the spacer 130.

[0045] like Figure 2D As shown, an insulating layer 290 may be formed in the opening 284, on the substrate 110, and on the sidewalls of the channel layers 120a, 120b. In some embodiments, the insulating layer 290 and the bottom isolation region 170 may include the same insulating material (eg, silicon nitride).

[0046] like Figure 2E and Figure 3 As shown, the insulating inner spacer 190 can be formed by selectively removing a portion of the insulating layer 290 outside the opening 284 (block 320). Thus, the selective removal can expose the sidewalls of the channel layers 120a, 120b and a portion of the uppermost surface of the substrate 110. In some embodiments, the selective removal can include etching the insulating layer 290 vertically but not laterally.

[0047] like Figure 2F As shown, the sacrificial region 240 may be formed on the exposed portion of the substrate 110, on the exposed sidewalls of the channel layer 120, and on the exposed sidewalls of the spacer 190. The sacrificial region 240 may include an insulating material different from the insulating material of the bottom isolation region 170 and the spacer 190. For example, the sacrificial region 240 may include an oxide (e.g., silicon oxide).

[0048] like Figure 2G As shown, the sacrificial region 240 may be vertically thinned. As an example, the sacrificial region 240 may be etched until its uppermost surface is at a vertical level lower than the lowermost surface of the spacer 130. The sacrificial region 240 may have an etch selectivity relative to the bottom isolation region 170 and the spacer 190. The vertical thinning exposes the sidewalls of the upper channel layer 120a, the sidewalls of the upper spacers in the spacers 190, and the sidewalls of the spacers 130. In some embodiments, the uppermost surface of the sacrificial region 240 may be at a vertical level of the lower portion of the spacer 190, which is located on the sidewall of the uppermost lower sacrificial gate layer 280b in the lower sacrificial gate layer 280b. Therefore, a majority (e.g., greater than 50% or even greater than 75%) of the sidewalls of the spacer 190 may be exposed.

[0049] like Figure 2H As shown, the insulating layer 242 and the insulating layer 244 may be formed on the uppermost surface of the sacrificial region 240 and on the exposed sidewalls of the upper spacer in the spacer 190 (and the exposed sidewalls of the spacer 130) and the exposed sidewalls of the upper channel layer 120a. The insulating layer 242 may be between the sacrificial region 240 and the insulating layer 244, and between the sidewalls of the upper spacer in the spacer 190 and the insulating layer 244. In addition, the insulating layer 242 may have an etching selectivity relative to the spacer 190, the insulating layer 244, and the sacrificial region 240. As an example, the insulating layer 242 may include an oxide that is denser than the oxide of the sacrificial region 240. On the other hand, the insulating layer 244 may include the same insulating material as the spacer 190 (e.g., silicon nitride). Therefore, when the vertical portion of the insulating layer 244 is removed in a subsequent operation, the insulating layer 242 may protect the spacer 190.

[0050] like Fig.2I As shown, lower lateral portions of the insulating layers 242 , 244 may be removed to expose an uppermost surface of the sacrificial region 240 . Fig.2IAlso shown is an upper portion P1 of the sacrificial region 240, which laterally overlaps a lower portion of a sidewall of a spacer 190 located on a sidewall of the uppermost of the lower sacrificial gate layers 280b. The upper portion P1 has a vertical thickness that is thinner than a thickness t2 of the uppermost of the lower sacrificial gate layers 280b (and the spacers 190 thereon). The lowest point of the upper portion P1 may be at the same vertical level as the lowermost surface of the uppermost of the lower sacrificial gate layers 280b, and the uppermost surface of the upper portion P1 may be lower in the vertical direction Z than the uppermost surface of the uppermost of the lower sacrificial gate layers 280b.

[0051] like Figure 2J As shown, the sacrificial region 240 may be removed to form an opening 246 that exposes a portion of the uppermost surface of the substrate 110 and exposes the sidewall of the lower channel layer 120b. In some embodiments, the sacrificial region 240 may be removed by selective etching relative to the spacer 190, the bottom isolation region 170, and the insulating layers 242, 244.

[0052] like Figure 2K and Figure 3 As shown, a lower S / D region 140 is formed in the opening 246 (block 325). For example, the lower S / D region 140 may be epitaxially grown from the substrate 110 and / or the lower channel layer 120b. The lower S / D region 140 may be on the sidewalls of the bottom isolation region 170 and on the sidewalls of the lower channel layer 120b. Figure 2K Only one lower S / D region 140 is shown in FIG. However, it will be understood that a pair of lower S / D regions 140 may be formed on opposite sides of the lower channel layer 120 b.

[0053] like Figure 2L As shown, a thin insulating liner 248 may be formed on the uppermost surface of the lower S / D region 140. The liner 248 may include, for example, the same insulating material as the spacer 190 and the insulating layer 244. As an example, the liner 248 may include silicon nitride.

[0054] like Figure 2M and Figure 3As shown, the S / D isolation region 160 can be formed (block 330) on top of the liner 248 to laterally overlap the sidewalls of the spacer 130 (and be vertically thicker than the sidewalls of the spacer 130). The S / D isolation region 160 can include, for example, an oxide that is less dense than the oxide of the insulating layer 242 (e.g., silicon oxide). The uppermost surface of the S / D isolation region 160 can be at a vertical level above the vertical level of the uppermost surface of the spacer 130. In addition, the lowermost surface of the S / D isolation region 160 can be at a vertical level below the vertical level of the lowermost surface of the spacer 130. Therefore, the S / D isolation region 160 can be thicker than the spacer 130 in the vertical direction Z.

[0055] As an example of the thickness of the S / D isolation region 160, Figure 2M It is shown that the S / D isolation region 160 can have an upper portion P2 that laterally overlaps at least a portion of a sidewall of a spacer 190, the sidewall of which is on the sidewall of the lowest upper sacrificial gate layer 280a in the upper sacrificial gate layers 280a. In some embodiments, the upper portion P2 can have a vertical thickness that is thinner than the thickness t2 of the lowest upper sacrificial gate layer 280a in the upper sacrificial gate layers 280a (and the spacers 190 thereon). The lowest point of the upper portion P2 can be at the same vertical level as the lowest surface of the lowest upper sacrificial gate layer 280a in the upper sacrificial gate layers 280a, and the uppermost surface of the upper portion P2 can be lower than the uppermost surface of the lowest upper sacrificial gate layer 280a in the vertical direction Z. Therefore, the upper portion P2 does not laterally overlap with the lowest upper channel layer 120a in the upper channel layers 120a in the direction X.

[0056] To simplify the diagram, Figure 2M Only one S / D isolation region 160 is shown in FIG. 1 . However, it will be understood that a pair of S / D isolation regions 160 may be formed on opposite sides of the spacer 130 .

[0057] like Figure 2N As shown, the vertical portions of the insulating layers 242, 244 that protrude upward beyond the uppermost surface of the upper portion P2 of the S / D isolation region 160 may be removed. For example, the vertical portions of the insulating layer 244 may be etched, and then the vertical portions of the insulating layer 242 may be etched. The vertical portions of the insulating layer 242 may protect the upper spacers in the spacers 190 during the etching of the vertical portions of the insulating layer 244. After removing the vertical portions of the insulating layers 242, 244, the uppermost surfaces of the insulating layers 242, 244 may be coplanar with the uppermost surface of the S / D isolation region 160.

[0058] like Fig.2O and Figure 3As shown, an upper source / drain region 150 may be formed (block 335) on top of the S / D isolation region 160. As an example, the upper S / D region 150 may be epitaxially grown from the upper channel layer 120a. Fig.2O Only one upper S / D region 150 is shown in FIG. 2 . However, it will be understood that a pair of upper S / D regions 150 may be formed on opposite sides of the upper channel layer 120 a.

[0059] According to some embodiments, the channel layer 120 may include silicon, and the lower S / D region 140 and / or the upper S / D region 150 may include silicon, silicon carbide, or silicon germanium. In addition, the upper S / D region 150 may include a material different from that of the lower S / D region 140. For example, the upper S / D region 150 may include silicon germanium, and the lower S / D region 140 may include silicon (without germanium) or silicon carbide.

[0060] like Figure 2P As shown, a thin insulating liner 252 may be formed on the lowermost and uppermost surfaces of the upper S / D region 150. The liner 252 may include, for example, the same insulating material as the spacer 190 and the insulating layer 244. As an example, the liner 252 may include silicon nitride. Figure 2M ) does not laterally overlap with the lowermost upper channel layer 120a of the upper channel layers 120a, so after the upper S / D region 150 is formed on the sidewall of the upper channel layer 120a (for example, the upper S / D region 150 is epitaxially grown from the sidewall of the upper channel layer 120a), a small gap may exist between the lowermost surface of the upper S / D region 150 and the uppermost surface of the S / D isolation region 160. The liner 252 may be formed on the lowermost surface of the upper S / D region 150 through the small gap. In addition, the liner 252 may be a protective liner that blocks / prevents contact from penetrating the S / D regions 140, 150.

[0061] Reference Figure 1B and Figure 3 , an RMG process (block 340) may be performed after forming the S / D regions 140, 150. The RMG process includes removing the sacrificial gate layers 280a and 280b and replacing them with metals, thereby forming metal gates 180a, 180b. The sacrificial gate layers 280a and 280b may be removed from between the channel layers 120a, 120b because the sacrificial gate layers 280a and 280b may have an etching selectivity relative to the channel layers 120a, 120b. A metal layer may then be formed on the upper and lower stacks of the channel layers 120a, 120b. According to some embodiments, a gate insulating layer may be formed between the metal layer and the channel layers 120a, 120b.

[0062] In some embodiments, the metal layer may be a first work function metal (WFM) layer, which may be removed from between the upper channel layer 120a and replaced with a second WFM layer including a WFM different from the first WFM layer. Therefore, the RMG process may include a dual WFM (DWFM) process because the upper transistor Ta and the lower transistor Tb may include different WFMs, respectively. For example, the first WFM layer of the lower transistor Tb may include aluminum because the lower transistor Tb may be an NMOS transistor, and the second WFM layer of the upper transistor Ta may include titanium nitride because the upper transistor Ta may be a PMOS transistor. In addition, tungsten (or another metal) may be formed on the first WFM layer and then may be formed on the second WFM layer. Accordingly, the lower metal gate 180b may include a first WFM layer and tungsten (or another metal), and the upper metal gate 180a may include a second WFM layer and tungsten (or another metal).

[0063] According to the embodiments herein, the transistor device 100 ( Figure 1A ) can provide many advantages. These advantages include eliminating the need for a silicon nitride MDI formation process. Instead of forming a silicon nitride MDI, the channel layers 120a, 120b ( Figure 1B ) is formed when a semiconductor spacer 130 is formed. The spacer 130 separates the upper transistor Ta and the lower transistor Tb ( Figure 1A ) separation. By using the spacer 130 instead of the silicon nitride MDI, problems such as silicon germanium residues (remaining from the sacrificial layer replaced by the silicon nitride MDI) and voids in the MDI can be avoided / mitigated.

[0064] Since the spacer 130 is a silicon (eg, crystalline silicon) layer formed in the process of forming the channel layers 120a, 120b, the spacer 130 may have a thickness t3 (t2) greater than that of the silicon nitride MDI. Figure 1B ), the silicon nitride MDI replaces the sacrificial layer (e.g., a high germanium concentration sacrificial layer that may make it difficult to form a thick MDI). This larger thickness t3 can help to better separate the upper transistor Ta and the lower transistor Tb from each other. However, if the spacer 130 is too thick (e.g., thicker than 40nm or thicker than 50nm), it may be difficult to use the metal gates 180a and 180b ( Figure 1B ) replaces sacrificial gates 280a and 280b ( Figure 2A ). Therefore, the thickness t3 of the spacer 130 may be in the range of, for example, 20-40 nm. In some embodiments, the thickness t3 may be selected in consideration of the process window of the DWFM process used to form the metal gates 180a and 180b.

[0065] The spacer 130 may also facilitate the formation of the bottom isolation region 170 ( Figure 1A), otherwise if the silicon nitride MDI is formed by replacing the sacrificial layer, it may be difficult to form the bottom isolation region 170. This is because the critical thickness of the sacrificial layer may make it difficult (if not impossible) to form the BDI. In addition, it may be desirable that the bottom isolation region 170 is relatively thick. For example, the thickness t4 ( Figure 1B ) can be in the range of 10-12nm.

[0066] Example embodiments are described herein with reference to the accompanying drawings. Without departing from the teachings of the present disclosure, many different forms and embodiments are possible, and therefore the present disclosure should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure will be thorough and complete, and the scope of the present invention will be conveyed to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals always refer to the same elements.

[0067] Example embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments and intermediate structures of example embodiments. As such, variations from the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments herein should not be construed as limited to the particular shapes shown herein, but may include deviations in shapes that may result, for example, from manufacturing.

[0068] It should also be noted that in some alternative implementations, the function / action indicated in the flow chart frame here may not occur in the order indicated in the flow chart. For example, two frames shown in succession can actually be performed substantially simultaneously, or frames can sometimes be performed in reverse order, depending on the function / action involved. In addition, the function of a given frame of a flow chart and / or block diagram can be divided into a plurality of frames and / or the function of two or more frames of a flow chart and / or block diagram can be integrated at least in part. Finally, without departing from the scope of the present invention, other frames can be added / inserted between the frames shown, and / or frames / operations can be omitted.

[0069] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0070] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "one", "an" and "the" are intended to also include plural forms, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "comprising", "comprising ... ", "including" and / or "comprising ... " indicate the presence of the features, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts and / or their groups.

[0071] It will be understood that when an element is referred to as being "coupled" to another element, "connected" to another element, or "responsive to" another element, or "on" another element, it may be directly coupled to another element, directly connected to another element, or directly responsive to another element, or directly on another element, or there may be an intermediate element. In contrast, when an element is referred to as being "directly coupled" to another element, "directly connected" to another element, or "directly responsive to" another element, or "directly on" another element, there is no intermediate element. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items. In addition, the symbol " / " (e.g., when used in the term "source / drain") will be understood to be equivalent to the term "and / or".

[0072] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of this embodiment, the first element may be referred to as the second element.

[0073] For ease of description, spatial relational terms such as "under", "below", "below", "above", "on", etc. may be used here to describe the relationship between an element or feature and another element or feature as shown in the figure. It will be understood that in addition to the orientation depicted in the figure, the spatial relational terms are intended to cover different orientations of the device in use or operation. For example, if the device in the accompanying drawings is turned over, the elements described as "under" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the term "under" can cover both above and below orientations. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relational descriptors used here can be interpreted accordingly.

[0074] Many different embodiments have been disclosed herein in conjunction with the above description and accompanying drawings. It will be understood that literally describing and illustrating every combination and subcombination of these embodiments would be unduly repetitive and confusing. Therefore, this specification (including the accompanying drawings) should be interpreted as constituting a complete written description of all combinations and subcombinations of the embodiments described herein and the manner and process of making and using them, and should support claims to any such combination or subcombination.

[0075] The above disclosure is to be considered illustrative rather than restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the scope of the invention. Therefore, to the maximum extent permitted by law, the scope shall be determined by the broadest permissible interpretation of the appended claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.

[0076] Related Applications

[0077] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 602,010, filed on November 22, 2023, entitled “STACKED TRANSISTOR INLUDING MIDDLE DIELECTRIC INSULATOR AND METHODS OF FORMING THE SAME,” the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A transistor device, comprising: substrate; a transistor stack on the substrate, wherein the transistor stack includes a lower transistor and an upper transistor on top of the lower transistor; as well as A semiconductor spacer is between the upper transistor and the lower transistor.

2. The transistor device according to claim 1, wherein the upper transistor and the lower transistor each include a semiconductor channel layer, and The semiconductor spacer is thicker than each of the semiconductor channel layers in a vertical direction. 3 . The transistor device of claim 2 , further comprising a bottom isolation region between the substrate and the semiconductor channel layer of the lower transistor. The transistor device of claim 3 , wherein the bottom isolation region is thinner than the semiconductor spacer in the vertical direction. The transistor device of claim 3 , wherein the bottom isolation region comprises silicon nitride. 6 . The transistor device according to claim 2 , wherein the semiconductor spacer has a width in a lateral direction equal to a width of each of the semiconductor channel layers. 7 . The transistor device of claim 2 , wherein the semiconductor spacer and the semiconductor channel layer comprise the same semiconductor material. The transistor device of claim 7 , wherein the semiconductor material comprises crystalline silicon.

9. The transistor device of claim 7, wherein the semiconductor material is free of germanium, free of carbon, free of nitrogen, and free of oxygen.

10. The transistor device according to claim 2, further comprising: a source / drain isolation region on a sidewall of the semiconductor spacer; as well as an upper source / drain region on the source / drain isolation region and electrically connected to the semiconductor channel layer of the upper transistor, The source / drain isolation region is thicker than the semiconductor spacer in the vertical direction.

11. The transistor device according to claim 10, further comprising a lower source / drain region electrically connected to the semiconductor channel layer of the lower transistor, The source / drain isolation region separates the lower source / drain region from the upper source / drain region.

12. The transistor device according to claim 11, further comprising: a gate, between the semiconductor channel layers of the upper transistor; as well as an insulating spacer, on a sidewall of the gate, wherein the uppermost surface of the semiconductor spacer contacts the lowermost surface of the insulating spacer, and An upper portion of the source / drain isolation region overlaps with a sidewall of the gate and a sidewall of the insulating spacer in a lateral direction.

13. The transistor device according to claim 12, wherein the insulating spacer comprises silicon nitride, and The semiconductor channel layer comprises nanosheets.

14. A transistor device comprising: substrate; a transistor stack on the substrate, wherein the transistor stack includes a lower transistor and an upper transistor on top of the lower transistor, and wherein the upper transistor and the lower transistor each include a semiconductor channel layer; a silicon spacer separating the upper transistor from the lower transistor, wherein the silicon spacer does not contain nitrogen; as well as A bottom isolation region is between the substrate and the semiconductor channel layer of the lower transistor.

15. The transistor device according to claim 14, further comprising: a source / drain isolation region on a sidewall of the silicon spacer; an upper source / drain region on the source / drain isolation region and electrically connected to the semiconductor channel layer of the upper transistor; as well as a lower source / drain region electrically connected to the semiconductor channel layer of the lower transistor, wherein the source / drain isolation region separates the lower source / drain region from the upper source / drain region, and The source / drain isolation region is thicker than the silicon spacer in a vertical direction.

16. The transistor device according to claim 15, in, The source / drain isolation regions include oxide, and The bottom isolation region comprises silicon nitride and is thinner than the silicon spacer in the vertical direction.

17. A method of forming a transistor device, the method comprising: forming a stack of semiconductor layers alternating with sacrificial gate layers on a substrate, wherein another sacrificial layer is between the substrate and a lowermost of the sacrificial gate layers; as well as replacing the further sacrificial layer with a bottom isolation region, Wherein, the upper semiconductor layer in the semiconductor layer includes an upper channel layer of an upper transistor, Wherein, the lower semiconductor layer in the semiconductor layer includes a lower channel layer of a lower transistor, and The middle semiconductor layer in the semiconductor layer separates the upper channel layer from the lower channel layer and is thicker than each of the upper channel layers and each of the lower channel layers in a vertical direction.

18. The method according to claim 17, further comprising: forming a lower source / drain region on the sidewalls of the lower channel layer; forming a source / drain isolation region on the lower source / drain region and on a sidewall of the middle semiconductor layer in the semiconductor layer; as well as An upper source / drain region is formed on the source / drain isolation region and on a sidewall of the upper channel layer.

19. The method according to claim 18, wherein: Forming the lower source / drain region includes forming the lower source / drain region on a sidewall of the bottom isolation region.

20. The method according to claim 18, wherein: Forming the source / drain isolation region includes forming an uppermost surface of the source / drain isolation region at a level higher than an uppermost surface of the middle semiconductor layer among the semiconductor layers in the vertical direction.

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