Three-dimensional stacked chip and test method

Abstract

The invention discloses a three-dimensional stacked chip and a test method. The three-dimensional stacked chip comprises at least two wafers to be tested; the at least two to-be-tested wafers comprise a first to-be-tested wafer and a second to-be-tested wafer, and the first to-be-tested wafer and the second to-be-tested wafer are stacked and connected through a connecting layer; the first to-be-tested wafer is provided with a first test circuit, and the second to-be-tested wafer is provided with a second test circuit and a comparison circuit. The first test circuit is used for writing test data into the first wafer to be tested; the second test circuit is used for copying the test data to the second wafer to be tested through the connecting layer; and the comparison circuit is used for comparing the copied test data with to-be-compared data in the second to-be-tested wafer and outputting comparison information for judging whether the connection layer is abnormal or not. The test of the connection layer can be realized, and the test coverage rate and the simultaneous test number are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a three-dimensional stacked chip and a testing method. Background Art

[0002] High Bandwidth Memory (HBM) uses a 3D stacking process, and the logic chips and memory chips, as well as the memory chips, are interconnected using a 3D connection layer. That is, a large number of TSVs (Through-Silicon Via, vertical electrical interconnection through the silicon substrate) and HBs (Hybrid Bonding) are required to meet the requirements of high-bandwidth data paths. Therefore, the reliability of TSVs and HBs has a great impact on the performance of HBM, so the connection layer needs to be tested during the HBM wafer testing phase.

[0003] Since the read and write operation paths of the HBM task mode can cover the TSV and HB of the connection layer, the traditional testing method only needs to lead out the instruction interface and data interface of the task mode to the pad through the redistribution layer (RDL), directly connect the pad and the test machine through a probe card during testing, and then send the HBM standard read and write operations through the test machine to meet the requirements of testing the 3D connection layer.

[0004] However, due to the characteristics of HBM wide IO (Input / Output) and multiple channels, taking a single channel as an example, if the traditional test method is used, 20 instruction pads and 192 data pads need to be brought out, and a total of 1696 pads are needed for 8 channels. Such a large number of pads is almost impossible to achieve for RDL design, probe card design, and test needle machine testing capabilities.

[0005] Therefore, the traditional test method can only bring out part of the IO for testing, but this will result in low test coverage, a large number of pads, and difficulty in increasing the number of simultaneous tests. Summary of the invention

[0006] In view of the above problems, the present invention is proposed to provide a three-dimensional stacked chip and a testing method. By setting test circuits on the wafer to be tested, only a small number of test pads need to be brought out to improve the test coverage and the number of simultaneous tests.

[0007] According to a first aspect of the present invention, there is provided a three-dimensional stacked chip, comprising: at least two wafers to be tested;

[0008] The at least two wafers to be tested include a first wafer to be tested and a second wafer to be tested, wherein the first wafer to be tested and the second wafer to be tested are stacked and connected via a connection layer;

[0009] The first wafer to be tested is provided with a first test circuit, and the second wafer to be tested is provided with a second test circuit and a comparison circuit;

[0010] Among them, the first test circuit is used to write test data into the first wafer to be tested; the second test circuit is used to copy the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

[0011] Optionally, before copying the test data to the second wafer to be tested, the second test circuit of the second wafer to be tested is also used to write background data to the second wafer to be tested, and the second test circuit copies the test data to the second wafer to be tested through the connection layer to cover the background data.

[0012] Optionally, the background data is bitwise inverted data of the test data.

[0013] Optionally, the connection layer includes a plurality of connection keys, the first wafer to be tested includes a plurality of storage units to be tested for storing the test data, and the second wafer to be tested includes a plurality of storage submodules;

[0014] Each of the register units to be tested is connected to each of the storage submodules via n connection keys, where n is equal to the bit length of the data to be compared;

[0015] The first test circuit is used for writing the test data into each of the register units to be tested of the first wafer to be tested; and the second test circuit is used for copying the test data to each of the storage submodules of the second wafer to be tested through the connection key.

[0016] Optionally, the three-dimensional stacked chip further includes a first shielding module; the second wafer to be tested includes a plurality of storage bins, each of the storage bins includes a plurality of storage sub-modules;

[0017] The first shielding module is used to shield the comparison results of any one or more storage submodules in the storage repository; wherein the comparison information of the storage repository is obtained by compressing the comparison results of each storage submodule in the storage repository.

[0018] Optionally, the three-dimensional stacked chip further includes a second shielding module;

[0019] The second masking module is used to mask any one or more bits of the data to be compared.

[0020] Optionally, the first test circuit and the second test circuit are in a test mode based on a received test stimulus, and in the test mode, the first test circuit receives test data sent by the test machine and writes it into the first wafer to be tested; the comparison circuit receives the data to be compared sent by the test machine and writes it into the second wafer to be tested; the second test circuit copies the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

[0021] According to a second aspect of the present invention, a testing method is provided, the method being applicable to the above-mentioned three-dimensional stacked chip; the method comprising:

[0022] Writing the test data into the first wafer to be tested;

[0023] Writing the data to be compared into the second wafer to be tested;

[0024] Copying the test data to the second wafer to be tested through the connection layer;

[0025] The copied test data is compared with the data to be compared in the second wafer to be tested and comparison information is output to determine whether the connection layer is abnormal.

[0026] Optionally, copying the test data to the second wafer to be tested through the connection layer includes:

[0027] Writing the background data into the second wafer to be tested;

[0028] The test data is copied to the second wafer to be tested to cover the background data.

[0029] Optionally, the background data is bitwise inverted data of the test data.

[0030] According to a third aspect of the present invention, a testing method is provided, the method being applicable to a testing machine; the method comprising:

[0031] Sending a test stimulus to the three-dimensional stacked chip to test a connection layer of the three-dimensional stacked chip;

[0032] The comparison information sent by the three-dimensional stacked chip is received, and based on the comparison information, it is determined whether a connection layer of the three-dimensional stacked chip is abnormal.

[0033] According to a fourth aspect of the present invention, a test machine is provided, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the aforementioned test method when executed by the processor.

[0034] The above one or more technical solutions in the embodiments of this specification have at least the following technical effects:

[0035] A three-dimensional stacked chip and testing method provided in the embodiments of this specification are different from the prior art. The three-dimensional stacked chip does not need to be rewired, and the test data is stored in a register unit connected to the connection layer in the first wafer to be tested. The second test circuit of the second wafer to be tested can directly move the test data in the first wafer to be tested to the second wafer to be tested through the connection layer. By comparing the test data with the data to be compared, it can be determined whether the connection layer is abnormal, which can be achieved by bringing out a small number of test pads, while improving the test coverage and the number of same tests.

[0036] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Also, throughout the accompanying drawings, the same reference figures are used to represent the same components. In the drawings:

[0038] Figure 1 A schematic diagram of the structure of an HBM in an embodiment of the present invention is shown.

[0039] Figure 2 A schematic diagram of a three-dimensional stacked chip in an embodiment of the present invention is shown.

[0040] Figure 3 A flow chart of a testing method in an embodiment of the present invention is shown.

[0041] Figure 4 A flow chart of another testing method in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0045] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0046] Combination Figure 1 As shown, Figure 1 The HBM in the Figure 1 logic1) and two storage wafers (i.e. Figure 1 dram1 and dram2 in the prior art). In the prior art, due to the characteristics of wide IO and multiple channels of HBM, taking a single channel as an example, if the traditional test method is used, 20 instruction pads and 192 data pads need to be brought out, and a total of 1696 pads need to be brought out for 8 channels. Such a large number of pads is almost impossible to achieve for RDL design, probe card design, and the test capabilities of the test needle machine. Therefore, the traditional test method can only bring out part of the IO for testing, but this will result in low test coverage. Even so, the number of pads is still large, and it is difficult to increase the number of simultaneous tests.

[0047] Based on the above situation, combined with Figure 2 As shown, an embodiment of the present invention provides a three-dimensional stacked chip, including: at least two wafers to be tested.

[0048] In one embodiment, the wafer to be tested includes a first wafer to be tested and a second wafer to be tested. The first wafer to be tested and the second wafer to be tested are stacked, and the first wafer to be tested and the second wafer to be tested are connected by a connection layer. For example, the first wafer to be tested can be a logic wafer to be tested, and the second wafer to be tested can be a memory wafer to be tested, for example, the memory wafer to be tested is a DRAM (Dynamic Random Access Memory).

[0049] In one embodiment, the at least two wafers to be tested include a first wafer to be tested, a second wafer to be tested, and a third wafer to be tested. The first wafer to be tested is connected to the second wafer to be tested via a connection layer, and the second wafer to be tested is connected to the third wafer to be tested via a connection layer. For example, the first wafer to be tested may be a logic wafer to be tested, the second wafer to be tested is a memory wafer to be tested, and the third wafer to be tested is a memory wafer to be tested, wherein the memory wafer to be tested may be a DRAM.

[0050] It should be noted that the above examples are for illustration only, and the specific number of the second wafers to be tested can be determined according to actual conditions, and this embodiment does not limit this.

[0051] In this embodiment, a first test circuit is disposed on the first wafer to be tested, and a second test circuit and a comparison circuit are disposed on the second wafer to be tested.

[0052] Among them, the first test circuit is used to write test data into the first wafer to be tested; the second test circuit is used to copy the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

[0053] In this embodiment, the test data in the first wafer to be tested and the data to be compared in the second wafer to be tested are known data sent by the test machine. The test data in the first wafer to be tested is moved and copied to the second wafer to be tested through the connection layer, and then compared with the data to be compared in the second wafer to be tested. It should be noted that when the test data is compared with the data to be compared, the two may be the same or opposite. In either case, there is a regularity between the test data and the data to be compared. This embodiment is explained by taking the example that the test data is the same as the data to be compared.

[0054] The comparison circuit will compare the test data copied to the second wafer to be tested with the data to be compared. If the two are the same, it means that the connection layer is normal. If the two are different, it means that there is an abnormality in the connection layer.

[0055] Different from the prior art, when performing the connection layer test, the present embodiment does not need to design a rewiring layer. It is only necessary to design a plurality of pads for testing on the first wafer to be tested, and these pads are used to connect the first test circuit and the second test circuit and the comparison circuit through the connection layer. The number of pads is related to the number of wafers to be tested, and is also related to the bit length of the test data and the test results, and can be expanded accordingly.

[0056] The pad is connected to the first test circuit, and the test machine sends test excitation to the first wafer to be tested and the second wafer to be tested through the pad. After receiving the test excitation, the first wafer to be tested and the second wafer to be tested are in test mode. In the test mode, the first test circuit receives the test data sent by the test machine and writes it into the first wafer to be tested; the comparison circuit receives the data to be compared sent by the test machine and writes it into the second wafer to be tested; the second test circuit copies the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

[0057] The test stimulus includes two types: an enable signal and a data signal. The test stimulus sent to the first test circuit includes a test enable signal, a clock signal, a test instruction address, a first test circuit enable signal, and test data.

[0058] After receiving the test stimulus sent by the test machine, the second test circuit on the second wafer to be tested is in the test mode, and after being parsed by the second test circuit of the second wafer to be tested, the test data in the first wafer to be tested is moved and copied to the second wafer to be tested through the connection layer. The test stimulus received by the second test circuit includes a test enable signal, a clock signal, a test instruction address, a second test circuit enable signal, and data to be compared.

[0059] It should be noted that when moving and copying test data, it is necessary to pass through the connection layer, and the test data is moved and copied from the first wafer to the second wafer to be tested through the connection layer. If there is a problem with the connection layer, the test data moved to the second wafer to be tested will have at least some errors. In this way, when comparing with the data to be compared later, the comparison information obtained can reflect the abnormality of the connection layer.

[0060] However, it should be noted that in actual testing, the location where the test data is stored in the second wafer to be tested may have data preset. This may cause some of the preset data to be the same as the test data of the first wafer to be tested. Then when the test data of the first wafer to be tested is moved and copied, if there is an abnormality in the connection layer, the test data moved and copied in the second wafer to be tested should have some errors. However, since the preset data in the second wafer to be tested may be the same as the test data, the abnormality of the connection layer cannot be displayed in the subsequent comparative test, thereby affecting the accuracy of the connection layer test.

[0061] In order to solve the above problem, in this embodiment, before copying the test data to the second wafer to be tested, the second test circuit of the second wafer to be tested is also used to write background data to the second wafer to be tested, and the second test circuit copies the test data to the second wafer to be tested through the connection layer to cover the background data. The background data is the bitwise inverted data of the test data, that is, the background data is the data topology opposite to the test data.

[0062] For example, if the test data is 8-bit binary data 10101010, the background data is 01010101. The background data has the same length as the test data, but the data stored in each storage bit of the background data is opposite to the data stored in each storage bit of the test data. The first wafer to be tested writes the test data 10101010 through the first test circuit, and the second wafer to be tested writes the background data 01010101 through the second test circuit. The second wafer to be tested then moves and copies the test data to the second wafer to be tested through the connection layer through the second test circuit to overwrite the background data, thereby preventing the original preset data in the second wafer to be tested from being the same as the test data of the first wafer to be tested, so as to ensure the accuracy of the comparison results between the moved and copied test data and the data to be compared.

[0063] Since the data in each storage bit of the background data in the second wafer to be tested is opposite to the test data, if the connection layer is abnormal, at least part of the test data moved and copied in the second wafer to be tested is different from the test data in the first wafer to be tested. If the connection layer is normal, the test data moved and copied in the second wafer to be tested is the same as the test data in the first wafer to be tested.

[0064] In this embodiment, the first wafer to be tested includes a plurality of register units to be tested for storing the test data, the second wafer to be tested includes a plurality of storage submodules, the connection layer includes a plurality of connection keys, each register unit to be tested is connected to each storage submodule via n connection keys, and n is equal to the bit length of the data to be compared. It is not difficult to understand that the bit length of the test data and the data to be compared depends on the number of connection keys in each storage submodule.

[0065] For example, the second wafer to be tested includes 8 storage arrays, each storage array includes 8 storage banks (also called banks), if each storage bank is provided with 128 connection keys, then one storage bank can be divided into 16 storage submodules, each storage submodule includes 8 connection keys, and accordingly, the bit length of the test data and the data to be compared is 8. Thus, the comparison result in each storage submodule corresponds to a connection key.

[0066] In this embodiment, a plurality of second test circuits are arranged in the second wafer to be tested, and the number of the second test circuits on the second wafer to be tested is the same as the number of the storage submodules, that is, each storage submodule is connected to a second test circuit.

[0067] The first test circuit is used for writing test data into each of the register units to be tested of the first wafer to be tested; and the second test circuit is used for copying the test data to each of the storage submodules of the second wafer to be tested through the connection key.

[0068] In this embodiment, the first test circuit and the second test circuit are in a test mode based on the received test stimulus. In the test mode, the first wafer to be tested receives test data sent by the test machine, and the second wafer to be tested receives data to be compared sent by the test machine.

[0069] In this embodiment, the test machine is connected to the first wafer to be tested through the corresponding pads, and is used to send test stimuli to the first wafer to be tested and the second wafer to be tested. Among them, the data to be compared is determined according to the comparison mode and the test data. For example, the data to be compared is the same as the test data, and the comparison mode is an XOR operation. During the test comparison, the test data copied and moved from the second wafer to be tested is subjected to an XOR operation with the data to be compared. If the comparison information is all 1, that is, 11111111, it means that the connection layer is normal. If the comparison information is not all 1, for example, 11111101, it means that a part of the connection layer is abnormal. After the comparison is completed, an AND operation is performed to compress the operation result. For example, 1 bank will compress the comparison result into 1 bit, that is, 1 or 0, 1 represents that the bank comparison passes, and 0 represents that the bank comparison fails.

[0070] In order to facilitate understanding and implementation by those skilled in the art, this embodiment is described by way of example:

[0071] Taking 8G HBM (composed of 1 layer of logic wafer to be tested and 2 layers of memory wafer to be tested, where the logic wafer to be tested is hereinafter referred to as logic die and the memory wafer to be tested is hereinafter referred to as dram die) as an example, 8G HBM requires a total of 27 test pads. The definition of the test pads (hereinafter referred to as pads) is shown in Table 1:

[0072]

[0073] Table 1

[0074] 8G HBM includes two dram dies, each of which includes eight 512M storage arrays. Each storage array includes eight banks, and each bank is divided into 16 storage submodules. There can be multiple dram dies, and the number of logic dies is 1. Each dram die is tested separately with the logic die on the connection layer, while all storage submodules in the same dram die are tested simultaneously.

[0075] In this example, there are two dram dies, namely dram die1 and dram die2. Dram die1 and dram die2 respectively test the connection layer with the logic die. Therefore, Vcs_dram can realize the gating of the second test circuit in dram die1 and dram die2 by 1 bit (also called 1bit). For example, Vcs_dram inputs a low level, which means that the second test circuit in dramdie1 is gated, and Vcs_dram inputs a high level, which means that the second test circuit in dram die2 is gated. If there are multiple dram dies in this example, the number of bits of Vcs_dram can be expanded according to the number of dram dies.

[0076] As shown in Table 1, for the 8G HBM in this example, 6 pads need to be set for Vca<5:0> and 16 pads need to be set for Vtmdq_dram<15:0>. Therefore, a total of 27 test pads need to be set for the HBM in this example. It is not difficult to see that the number of pads required for testing can be expanded according to the capacity of the HBM.

[0077] In this example, Vclk, Vca<5:0> and Vxbist_n are shared by logic die and dram die, Vcs_dram controls the gating of the second test circuit, and Vcs_logic controls the gating of the first test circuit. Vtmdq_logic is used to input the test data of logicdie and output the comparison information; vtmdq_dram<15:0> is used to input the data to be compared and output the comparison information of dram die, and the comparison information of each 512M storage array is compressed into 8 bits. For example, when all 8 bits of comparison information are 1, it means that the test result of the storage array is passed, and when not all are 1, it means that the test result of the storage array is failed.

[0078] This example uses the dram die1 test as an example. The test machine inputs test stimulus to dram die1 through Vclk, Vca<5:0>, Vxbist_n, Vcs_dram, and Vtmdq_dram<15:0>. Specifically, the test stimulus includes two types of enable signals and data signals. The signals input through Vclk, Vxbist_n, and Vcs_dram are enable signals. The signals input through Vca<5:0> and Vtmdq_dram<15:0> are data signals, such as background data. After being parsed by the second test circuit of dram die1, it can now support the input of write data from vtmdq_dram<15:0>, that is, background data is written to all storage sub-modules in dram die1.

[0079] The test machine inputs test stimulus to the logicdie through Vclk, Vca<5:0>, Vxbist_n, Vcs_logic, and Vtmdq_logic. Similarly, the test stimulus includes two types of enable signals and data signals. The input through Vclk, Vxbist_n, and Vcs_logic belongs to the enable signal. The input through Vca<5:0> and Vtmdq_dram<15:0> belongs to the data signal, for example, the input test data. After being parsed by the first test circuit of the logic die, the test data is written to the connection key of the connection layer, and the test data is stored in the register unit to be tested of the logic die.

[0080] The test machine inputs the enable signal to dram die1 through Vclk, Vxbist_n, and Vcs_dram, and inputs the data to be compared through Vca<5:0> and Vtmdq_dram<15:0>. After being analyzed by the second test circuit of dram die1, it can support writing data at this time, and the test data in the register unit to be tested of the logic die is moved and copied to all the storage submodules in dram die1 through the connection key to cover the background data.

[0081] In this example, the test machine inputs test stimulus to dram die1 through Vclk, vca<5:0>, vxbist_n, vcs_dram, and vtmdq_dram<15:0>. After being analyzed by the second test circuit, the data to be compared can be written to the comparison circuit and the comparison mode can be configured. At this time, the data to be compared is input from vtmdq_dram<15:0>. At the same time, the comparison information can also be output through vtmdq_dram<15:0>.

[0082] Among them, the comparison method configured in dram die1 can be as follows:

[0083] Each 512M storage array has 8 banks, and each bank is divided into 16 storage submodules (also called segments). Each storage submodule has 8 bits of test data. After the 8 bits of test data and the 8 bits of data to be compared in the comparison circuit are compared bit by bit, a comparison information is output to indicate whether the connection key of the corresponding connection layer is normal. If it is normal, it is indicated by pass, and if it is abnormal, it is indicated by fail. Among them, the comparison information output by the 16 storage submodules in a bank will be compressed together (that is, the test results of the 16 storage submodules are all passed to be considered passed, and the test result of any storage submodule is fail, which is considered to be failed). Then a bank will output 1 bit of pass / fail comparison information, and each 512M array outputs 8 bits of comparison information, which is serially output through the corresponding vtmdq_dram pad.

[0084] In addition, it should be noted that this embodiment also shields the designated channel, storage library or bit by configuring the shielding module to implement partial comparison, so as to locate which specific connection key in the connection layer is abnormal.

[0085] For example, the three-dimensional stacked chip also includes a first shielding module. The first shielding module is used to shield the comparison results of any one or more storage submodules in the storage repository. In other words, the first shielding module can be used to choose to ignore the comparison results of any one or more storage submodules, that is, to force the comparison result of the storage submodule to pass. The comparison information of the storage repository is obtained by compressing the comparison results of each storage submodule in the storage repository.

[0086] Take the second wafer to be tested including 8 storage arrays, each storage array including 8 storage banks, and each storage bank including 16 storage submodules as an example for explanation. If the data to be compared is 8 bits, each storage submodule has 8 corresponding connection keys, and one storage array has 1024 corresponding connection keys.

[0087] If the comparison information output by the storage array is 10111111, it means that a connection key in the storage library corresponding to the second output information is abnormal, which means that the abnormal connection key has been located in a specific storage library. In order to determine the specific location of the storage submodule where the connection key is located, this embodiment chooses to ignore the comparison results of the storage submodules one by one (i.e., force the comparison results of the storage submodules to be pass), and finally screens out the storage submodule where the abnormal connection key is located.

[0088] In order to further locate the specific position of the abnormal connection key in this embodiment, the three-dimensional stacked chip in this embodiment further includes a second shielding module.

[0089] The second masking module is used to mask any one or more bits of the data to be compared.

[0090] The use of the second masking module belongs to the configuration bit masking mode, which can force the comparison result of the bit to pass by choosing to ignore any one or more bits of the 8 bits of the data to be compared. Because the number of bits of the data to be compared is equal to the number of connection keys in each storage submodule. By masking each bit of the data to be compared one by one, the position of the abnormal connection key can be further located in the storage submodule.

[0091] In summary, the three-dimensional stacked chip provided in the embodiment of this specification is different from the prior art. The three-dimensional stacked chip does not need to be rewired. The test data is stored in the register unit connected to the connection layer in the first wafer to be tested. The second test circuit of the second wafer to be tested can directly move the test data in the first wafer to be tested to the second wafer to be tested through the connection layer. By comparing the test data with the data to be compared, it can be determined whether the connection layer is abnormal. This can be achieved by only bringing out a small number of test pads, while improving the test coverage and the number of same tests. And by configuring the shielding module, the abnormal connection key can also be accurately located, which is convenient for the connection layer to locate and troubleshoot faults.

[0092] Based on the same inventive concept, Figure 3 As shown, an embodiment of the present invention further provides a testing method, which is based on any one of the three-dimensional stacked chips mentioned above; the testing method includes steps 101 to 104:

[0093] Step 101: writing test data into a first wafer to be tested;

[0094] Step 102: writing the data to be compared into the second wafer to be tested;

[0095] Step 103: copying the test data to the second wafer to be tested through the connection layer;

[0096] Step 104: Compare the copied test data with the data to be compared in the second wafer to be tested and output a relatively fresh one to determine whether the connection layer is abnormal.

[0097] Optionally, copying the test data to the second wafer to be tested through the connection layer includes:

[0098] Writing the background data into the second wafer to be tested;

[0099] The test data is copied to the second wafer to be tested to cover the background data.

[0100] Optionally, the background data is bitwise inverted data of the test data.

[0101] To sum up, the testing method provided in the embodiments of this specification is different from the prior art. The three-dimensional stacked chip does not need to be rewired, and the test data is stored in a register unit connected to the connection layer in the first wafer to be tested. The second test circuit of the second wafer to be tested can directly move the test data in the first wafer to be tested to the second wafer to be tested through the connection layer. By comparing the test data with the data to be compared, it can be determined whether the connection layer is abnormal. This can be achieved by bringing out a small number of test pads, while improving the test coverage and the number of identical tests.

[0102] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific steps of the testing method described above can refer to the corresponding process in the aforementioned three-dimensional stacked chip, and will not be described in detail here.

[0103] Based on the same inventive concept, an embodiment of the present invention further provides a testing method, which is based on a testing machine; Figure 4 As shown in the flowchart, the test method includes steps 201 to 202:

[0104] Step 201: Sending a test stimulus to the three-dimensional stacked chip;

[0105] Step 202: receiving comparison information sent by the three-dimensional stacked chip, and determining whether a connection layer of the three-dimensional stacked chip is abnormal based on the comparison information.

[0106] To sum up, the testing method provided in the embodiments of this specification is different from the prior art. The three-dimensional stacked chip does not need to be rewired, and the test data is stored in a register unit connected to the connection layer in the first wafer to be tested. The second test circuit of the second wafer to be tested can directly move the test data in the first wafer to be tested to the second wafer to be tested through the connection layer. By comparing the test data with the data to be compared, it can be determined whether the connection layer is abnormal. This can be achieved by bringing out a small number of test pads, while improving the test coverage and the number of identical tests.

[0107] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific steps of the testing method described above can refer to the corresponding process in the aforementioned three-dimensional stacked chip, and will not be described in detail here.

[0108] Based on the same inventive concept, an embodiment of the present invention further provides a testing machine, including a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program implements the steps of the aforementioned testing method when executed by the processor.

[0109] The memory stores machine-readable instructions executable by the processor. When the test machine is running, the processor and the memory communicate via a bus, the processor executes the machine-readable instructions, and performs the test method in the aforementioned embodiment.

[0110] The memory, processor and communication unit components are electrically connected to each other directly or indirectly to achieve signal transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines. The test machine includes at least one software function module that can be stored in the memory in the form of software or firmware. The processor is used to execute the executable module stored in the memory.

[0111] In some embodiments, the processor is used to perform one or more functions described in this embodiment. In some embodiments, the processor may include one or more processing cores (eg, a single-core processor (S) or a multi-core processor (S)).

[0112] In this embodiment, the memory is used to store the program, and the processor is used to execute the program after receiving the execution instruction. The process definition method disclosed in any implementation of this embodiment can be applied to the processor, or implemented by the processor.

[0113] The communication unit is used to establish a communication connection between the controller and other devices through the network, and to send and receive data through the network.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the controller described above can refer to the corresponding process in the aforementioned method, and will not be elaborated here.

[0115] To sum up, the test machine provided in the embodiment of the present specification is different from the prior art. The three-dimensional stacked chip does not need to be rewired, and the test data is stored in a register unit connected to the connection layer in the first wafer to be tested. The second test circuit of the second wafer to be tested can directly move the test data in the first wafer to be tested to the second wafer to be tested through the connection layer. By comparing the test data with the data to be compared, it can be determined whether the connection layer is abnormal. This can be achieved by bringing out a small number of test pads, while improving the test coverage and the number of same tests.

[0116] The above are only various embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional stacked chip, characterized in that: include: At least two wafers to be tested; The at least two wafers to be tested include a first wafer to be tested and a second wafer to be tested, wherein the first wafer to be tested and the second wafer to be tested are stacked and connected via a connection layer; The first wafer to be tested is provided with a first test circuit, and the second wafer to be tested is provided with a second test circuit and a comparison circuit; Among them, the first test circuit is used to write test data into the first wafer to be tested; the second test circuit is used to copy the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

2. The three-dimensional stacked chip according to claim 1, characterized in that: Before copying the test data to the second wafer to be tested, the second test circuit of the second wafer to be tested is also used to write background data into the second wafer to be tested, and the second test circuit copies the test data to the second wafer to be tested through the connection layer to cover the background data.

3. The three-dimensional stacked chip according to claim 2, characterized in that: The background data is bitwise inverted data of the test data.

4. The three-dimensional stacked chip according to claim 1, characterized in that: The connection layer includes a plurality of connection keys, the first wafer to be tested includes a plurality of storage units to be tested for storing the test data, and the second wafer to be tested includes a plurality of storage submodules; Each of the register units to be tested is connected to each of the storage submodules via n connection keys, where n is equal to the bit length of the data to be compared; The first test circuit is used for writing the test data into each of the register units to be tested of the first wafer to be tested; and the second test circuit is used for copying the test data to each of the storage submodules of the second wafer to be tested through the connection key.

5. The three-dimensional stacked chip according to claim 1, characterized in that: The three-dimensional stacked chip further includes a first shielding module; the second wafer to be tested includes a plurality of storage bins, each of which includes a plurality of storage sub-modules; The first shielding module is used to shield the comparison results of any one or more storage submodules in the storage repository; wherein the comparison information of the storage repository is obtained by compressing the comparison results of each storage submodule in the storage repository.

6. The three-dimensional stacked chip according to claim 5, characterized in that: The three-dimensional stacked chip also includes a second shielding module; The second masking module is used to mask any one or more bits of the data to be compared.

7. The three-dimensional stacked chip according to claim 1, characterized in that: The first test circuit and the second test circuit are in a test mode based on the received test stimulus, and in the test mode, the first test circuit receives the test data sent by the test machine and writes it into the first wafer to be tested; the comparison circuit receives the data to be compared sent by the test machine and writes it into the second wafer to be tested; the second test circuit copies the test data to the second wafer to be tested through the connection layer; the comparison circuit is used to compare the copied test data with the data to be compared in the second wafer to be tested and output comparison information to determine whether the connection layer is abnormal.

8. A testing method, characterized in that: The method is applicable to the three-dimensional stacked chip according to any one of claims 1 to 7; the method comprises: Writing the test data into the first wafer to be tested; Writing the data to be compared into the second wafer to be tested; Copying the test data to the second wafer to be tested through the connection layer; The copied test data is compared with the data to be compared in the second wafer to be tested and comparison information is output to determine whether the connection layer is abnormal.

9. The method according to claim 8, characterized in that The step of copying the test data to the second wafer to be tested through the connection layer includes: Writing the background data into the second wafer to be tested; The test data is copied to the second wafer to be tested to cover the background data.

10. The method according to claim 9, characterized in that The background data is bitwise inverted data of the test data.

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