Gate-first GaN HEMT vertical structure chip and preparation method thereof

Abstract

The invention discloses a gate-first GaN HEMT vertical structure chip and a preparation method thereof, and belongs to the technical field of gate-first preparation, and the method comprises the steps: sequentially growing a GaN drift region, an AlN insertion layer, an AlXGa (1-X) N barrier layer and a SiN dielectric cap layer on a pretreatment substrate, and forming an epitaxial wafer; sequentially forming a gate electrode and a source electrode through the process steps of photoetching, evaporation, etching and the like; after growing a passivation layer, etching a conductive channel to obtain a field plate; performing deep etching trepanning and ion implantation to form a chip isolation region; and finally, forming a drain electrode at the bottom, growing a passivation layer, and photoetching an electrode leading-out region. According to the invention, the gate resistance is reduced by optimizing the selection and processing of the gate material; electric field distribution is improved through accurate grid shape design and manufacturing; the high performance and the stability of the chip are ensured by the close integration with the subsequent process steps, higher switching speed and better device performance are realized, and the key technical problems in the preparation of the gate-first GaN HEMT vertical structure chip are effectively solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of pre-gate preparation, and specifically relates to a pre-gate GaN HEMT vertical structure chip and a preparation method thereof. Background Art

[0002] With the continuous development of semiconductor technology, GaN HEMT devices are increasingly widely used in fields such as power electronics and microwave communication. In order to improve the performance and stability of devices, researchers have continuously explored new preparation methods and structural designs. As an important method among them, the pre-gate preparation technology can achieve more precise device control and optimized performance by first forming the gate structure during the preparation process and then performing subsequent process steps.

[0003] The pre-gate preparation technology has been widely applied in the research of GaN HEMT devices. By optimizing parameters such as gate material, shape, and size, lower gate resistance, higher switching speed, and better device performance can be achieved. At present, certain progress has been made in the research on pre-gate GaN HEMT vertical structure chips, including the selection and optimization of gate materials, the design and manufacturing of gate shapes, and the integration technology between the gate and subsequent layers.

[0004] Although certain achievements have been made in the research on pre-gate GaN HEMT vertical structure chips, there are still some challenges. First, the selection and optimization of gate materials are one of the key technologies, and factors such as the conductive performance, thermal stability, and compatibility with GaN of the materials need to be considered. Second, the design and manufacturing of gate shapes are also one of the difficulties, and the size and shape of the gate need to be precisely controlled to ensure the performance and stability of the device. In addition, the pre-gate preparation technology also needs to be well integrated and coordinated with subsequent process steps to achieve efficient device preparation and performance optimization. Summary of the Invention

[0005] In order to overcome the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a pre-gate GaN HEMT vertical structure chip and a preparation method thereof, so as to solve the technical problem of how to achieve lower gate resistance, higher switching speed, and better device performance in the selection and optimization of gate materials, the design and manufacturing of gate shapes, and the integration with subsequent process steps of the pre-gate GaN HEMT vertical structure chip.

[0006] In order to achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a preparation method of a pre-gate GaN HEMT vertical structure chip, including the following steps: 1) Sequentially grow a GaN drift region, an AlN insertion layer, and Al X Ga(1-X) An N-barrier layer and a SiN dielectric capping layer are obtained to get a GaN HEMT vertical structure epitaxial wafer, which is then cleaned, dried, and marked for positioning; 2) The electrode contact area of the gate is lithographed on the top. After evaporating TiAlNi, lithography, and metal etching, the gate electrode is formed; 3) The window area of the source is lithographed on the top, and the SiN dielectric capping layer in the window area is etched away; 4) The electrode contact area of the source is lithographed on the top, and electrode metal is evaporated. After stripping, the source electrode is formed; Rapid thermal annealing is carried out at 400 - 500 °C to form an alloy; 5) A passivation layer is grown on the top, the conductive channels of the source and the gate are etched out, and after evaporation, the field plate is obtained; 6) Deep etching and opening holes are carried out on the GaN HEMT vertical structure epitaxial wafer; 7) Chip isolation areas are formed on the top through lithography and ion implantation; 8) The electrode contact area of the drain is lithographed on the bottom, and electrode metal is evaporated. After stripping, the drain electrode is formed; 9) A passivation layer is grown on the bottom, and the drain electrode lead-out area is lithographed; The gate electrode and source electrode lead-out areas are lithographed on the top to obtain a pre-gate GaN HEMT vertical structure chip.

[0007] Preferably, in step 1), the pretreatment conditions of the substrate include: pretreating the substrate at 1000 - 1150 °C, and simultaneously, introducing N2 at a rate of 0 - 100 L / min, H2 at a rate of 50 - 200 L / min, and NH3 at a rate of 1 - 100 L / min.

[0008] Preferably, in step 1), the growth conditions of the GaN drift region include: at a growth pressure of 200 torr and a growth temperature of 1000 - 1150 °C, by controlling the flow rates of trimethylgallium, N2, H2, NH3, and the first silane, a GaN drift region with a thickness of 0.5 - 50 μm is grown, and the growth rotation speed is 800 - 1200 rpm; Among them, the flow rate of trimethylgallium is 200 - 1000 sccm / min, the flow rate of N2 is 0 - 100 L / min, the flow rate of H2 is 50 - 200 L / min, the flow rate of NH3 is 1 - 100 L / min, the concentration of the first silane is 200 ppm, and the flow rate is 0 - 500 sccm / min; In step 1), the carrier blocking layer region is defined by photolithography on the GaN drift region, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000 - 1150 °C, the rotation speed is 800 - 1200 rpm, the growth pressure is 200 torr, and trimethylgallium, N2, H2, and NH3 are introduced simultaneously to grow undoped GaN with a thickness of 150 - 400 nm. Among them, the introduction rate of trimethylgallium is 200 - 1000 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 0 - 200 L / min, and the introduction rate of NH3 is 0 - 100 L / min.

[0009] Preferably, in step 1), the growth conditions of the AlN insertion layer include: growing an extremely thin AlN insertion layer with a thickness of 0 - 2 nm by simultaneously introducing trimethylaluminum, H2, and NH3 at a growth temperature of 800 - 1100 °C and a growth pressure of 75 torr; among them, the introduction rate of trimethylaluminum is 0 - 500 sccm / min, the introduction rate of H2 is 50 - 200 L / min, and the introduction rate of NH3 is 1 - 100 L / min; In step 1), Al X Ga (1-X) The growth conditions of the N barrier layer include: growing an Al X Ga (1-X) N barrier layer with a thickness of 15 - 35 nm at a growth temperature of 800 - 1100 °C, a rotation speed of 800 - 1200 rpm, and a growth pressure of 100 torr by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2, and NH3; among them, the molar percentage of X is 15% - 50%, the introduction rate of trimethylgallium is 0 - 500 sccm / min, the introduction rate of trimethylaluminum is 50 - 500 sccm / min, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 50 - 200 L / min, and the introduction rate of NH3 is 1 - 100 L / min.

[0010] Preferably, in step 1), the growth conditions of the SiN dielectric capping layer include: growing a SiN dielectric capping layer with a thickness of 0.1 - 100 nm at a growth temperature of 700 - 1100 °C and a growth pressure of 200 torr by adjusting the flow rates of N2, H2, and NH3 and introducing disilane; among them, the introduction rate of N2 is 0 - 100 L / min, the introduction rate of H2 is 50 - 200 L / min, the introduction rate of NH3 is 1 - 100 L / min, the concentration of disilane is 2%, and the introduction rate of disilane is 0 - 500 sccm / min.

[0011] Preferably, in step 2), the gate electrode is a Ti / Al / Ti electrode metal; In step 3), the depth of the window region of the source electrode is below the two-dimensional electron gas, and the lithography angle is 60°; inductively coupled plasma etching is used to remove the SiN dielectric capping layer in the window region.

[0012] Preferably, in step 4), after soaking in a strong oxidation solution tank before evaporation coating, then soak in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi; In step 5), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0013] Preferably, in step 7), the elements for ion implantation include at least one of F, Ar, B, and N; the depth of ion implantation is 0.1 - 20 μm.

[0014] Preferably, in step 8), the depth of the electrode contact region of the drain electrode is below the two-dimensional electron gas, and the lithography angle is 60°; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN, and AlSi; In step 9), the passivation layer is composed of at least one of SiN, SiO2, and Al2O3.

[0015] The present invention also discloses a gate-first GaN HEMT vertical structure chip, prepared by the above preparation method, including: a substrate; A GaN drift region, an AlN insertion layer, and an Al X Ga (1-X) N barrier layer and a SiN dielectric capping layer stacked on the substrate in sequence; in the Al X Ga (1-X) N barrier layer, 0.15 ≤ X ≤ 0.5; A gate electrode located on the top of the SiN dielectric capping layer, the gate electrode is composed of a TiAlN stack and forms a Schottky contact with the Al X Ga (1-X) N barrier layer; A source window penetrating the SiN dielectric capping layer, and a source electrode located in the source window, the source electrode forms an ohmic contact with the GaN drift layer through the etched Al X Ga (1-X) N barrier layer; A top passivation layer covering the gate electrode and the source electrode, a conductive channel communicating with the gate electrode and the source electrode respectively is provided in the top passivation layer, and a field plate structure is formed on the surface of the conductive channel; A drain electrode located at the bottom of the substrate, the drain electrode forms an ohmic contact with the GaN drift region; An isolation region penetrating the substrate and the GaN drift region, the isolation region is formed by ion implantation and is used to define the chip boundary; A first passivation layer disposed on the top, and a first opening and a second opening are provided in the first passivation layer, exposing the metal connection portions of the gate electrode and the source electrode respectively; And a second passivation layer disposed at the bottom of the substrate, and a third opening is provided in the second passivation layer to expose the metal connection portion of the drain electrode.

[0016] Compared with the prior art, the present invention has the following beneficial effects: The present invention discloses a preparation method for a vertical structure chip of a front-gate GaN HEMT. Through precise pretreatment conditions and chemical vapor deposition processes, the high-quality growth of the GaN drift region, AlN insertion layer, AlXGa(1-X)N barrier layer, and SiN dielectric capping layer is ensured, providing a stable substrate for the formation of the gate and source-drain electrodes and helping to reduce the gate resistance. Using TiAlNi as the gate electrode material and forming the gate electrode through photolithography and metal etching processes helps to reduce the gate resistance and improve the switching speed. Removing the SiN dielectric capping layer in the window area through precise photolithography and etching processes, then evaporating the electrode metal to form the source electrode and performing rapid thermal annealing to form an alloy helps to optimize the contact between the source and the two-dimensional electron gas and improve the device performance. Growing a passivation layer and etching out the conductive channels of the source and gate, and then evaporating to obtain a field plate helps to protect the device from the external environment, while optimizing the electric field distribution and improving the breakdown voltage and stability of the device. Deep etching and opening holes in the GaN HEMT vertical structure epitaxial wafer facilitates subsequent ion implantation and electrode formation, helping to achieve better device isolation and performance. Forming a chip isolation region through photolithography and ion implantation helps to prevent mutual interference between different devices and improve the integration and performance of the device. Photolithographing the electrode contact area of the drain at the bottom and evaporating the electrode metal to form the drain electrode helps to optimize the contact between the drain and the two-dimensional electron gas, reduce the drain resistance, and improve the device performance. Growing passivation layers at the bottom and top and photolithographing the drain electrode and the lead-out areas of the gate and source electrodes helps to protect the device from the external environment, while providing a convenient electrode lead-out method for device packaging and testing. By selecting TiAlNi as the gate electrode material and combining with the rapid thermal annealing process, low gate resistance and good contact between the gate and the semiconductor layer are achieved, improving the switching speed. TiAlNi as the gate electrode material has good conductivity and compatibility with the GaN semiconductor material, helping to form a low-resistance gate contact, enabling the gate to respond more quickly to signal changes during the switching process. Through evaporation and subsequent heat treatment (such as rapid thermal annealing), the contact between the gate metal and the semiconductor layer can be further optimized, reducing the contact resistance. Low gate resistance helps to reduce the gate charge and discharge time, thereby improving the switching speed of the device. Using photolithography and metal etching processes to form the gate electrode has high precision and good controllability, ensuring the accuracy and consistency of the gate shape. By controlling the angle of photolithography and the depth of etching, the contact between the face gate and the two-dimensional electron gas is further optimized, improving the device performance. The optimized gate shape helps to improve the electric field distribution, reduce the leakage current, and increase the breakdown voltage and efficiency of the device. The uniform electric field distribution helps to reduce the performance degradation of the device during long-term operation and enhance the stability of the device. The formation of the gate electrode is coordinated with subsequent processes such as the formation of the source and drain electrodes and the growth of the passivation layer, ensuring the efficiency and consistency of the entire preparation process.

[0017] The present invention also discloses a front-gate GaN HEMT vertical structure chip prepared by the above preparation method. By carefully selecting the gate material, optimizing the gate shape design, and closely integrating with subsequent process steps, the gate resistance is effectively reduced, the switching speed is significantly improved, and the performance of the device is comprehensively enhanced. It not only solves the problems in the selection and optimization of the gate material for the front-gate GaN HEMT vertical structure chip, but also ensures the accuracy and reliability of the gate shape design and manufacturing. At the same time, seamless integration with subsequent process steps is achieved, realizing lower gate resistance, higher switching speed, and better device performance, providing strong technical support for the development of high-performance power electronic devices. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of the GaN HEMT vertical structure epitaxy disclosed by the present invention; Figure 2 It is a schematic structural diagram of the GaN HEMT vertical structure power chip disclosed by the present invention; Figure 3 It is a flowchart of the preparation method of the front-gate GaN HEMT vertical structure chip disclosed by the present invention. Detailed Embodiments

[0019] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0021] The following further describes the present invention in detail with reference to the accompanying drawings: A preparation method for vertical structure epitaxy of GaN HEMT disclosed by the present invention includes the following steps: GaN substrate preparation: Select an n-type doped GaN substrate with a thickness of 300 - 1000 μm as the growth basis. Selecting a GaN substrate with an appropriate thickness can ensure the uniformity and stability of the epitaxial layer. A thicker substrate usually has better thermal stability and mechanical strength, which is beneficial to the subsequent epitaxial growth process.

[0022] GaN substrate treatment: Pretreat the GaN substrate at a temperature of 1000 - 1150 °C (preferably 1100 °C). Meanwhile, introduce nitrogen (N2) at a rate of 0 - 100 L / min (preferably 0 L / min), hydrogen (H2) at a rate of 50 - 200 L / min (preferably 120 L / min), and ammonia (NH3) at a rate of 1 - 100 L / min (preferably 50 L / min) to prepare for the subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for the subsequent epitaxial growth.

[0023] GaN drift region growth: In the temperature range of 1000 - 1150 °C (preferably 1100 °C) and at a growth pressure of 200 torr, grow a GaN drift region with a thickness of 0.5 - 50 μm (preferably 7 μm) by precisely controlling the flow rates of trimethylgallium (TMGA), N2, H2, NH3, and the first silane (SiH4). This layer is crucial for the chip performance. Among them, the introduction rate of TMGA is 200 - 1000 sccm / min (preferably 600 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 10 L / min), the introduction rate of H2 is 50 - 200 L / min (preferably 90 L / min), the introduction rate of NH3 is 1 - 100 L / min (preferably 45 L / min), the concentration of the first SIH4 is 200 ppm, and the introduction rate is 0 - 500 sccm / min (preferably 10 sccm / min). The growth temperature is 1000 - 1150 °C (preferably 1100 °C), and the growth rotation speed is 800 - 1200 rpm (preferably 1200 rpm). The drift region is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the chip performance. By precisely controlling the growth parameters, a high-quality drift region can be obtained, thereby improving the current transmission ability and breakdown voltage of the chip.

[0024] Ion implantation: The carrier blocking layer region is defined by lithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. The implantation depth of the N ions is 0.1 - 20 μm (preferably 3 μm).

[0025] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1000 - 1150 °C (preferably 1080 °C), the rotation speed is 800 - 1200 rpm (preferably 1200 rpm), the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN, and its thickness is controlled at 150 - 400 nm (preferably 300 nm). The introduction rate of TMGa is 200 - 1000 sccm / min (preferably 500 sccm / min), the introduction rate of N2 is 0 - 100 L / min (preferably 64 L / min), the introduction rate of H2 is 0 - 200 L / min (preferably 120 L / min), and the introduction rate of NH3 is 0 - 100 L / min (preferably 50 L / min). The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0026] AlN insertion layer growth: Subsequently, at a temperature of 800 - 1100 °C (preferably 1000 °C) and a growth pressure of 75 torr, trimethylaluminum (TMAL), H2, and NH3 are simultaneously introduced to grow an extremely thin AlN insertion layer, and the thickness is controlled at 0 - 2 nm (preferably 0.8 nm) to optimize the chip performance. Among them, the introduction rate of TMAL is 0 - 500 sccm / min (preferably 200 sccm / min), the introduction rate of H2 is 50 - 200 L / min (preferably 190 L / min), and the introduction rate of NH3 is 1 - 100 L / min (preferably 5 L / min). The introduction of the insertion layer can optimize the interface characteristics of the chip, reduce interface scattering and defects, thereby improving the carrier mobility and current density of the chip. By precisely controlling the thickness and growth conditions of the insertion layer, the chip performance can be further optimized.

[0027] Al X Ga (1-X) AlGaN barrier layer growth: Then, in the temperature range of 800 - 1100 °C (preferably 1020 °C), at a rotation speed of 800 - 1200 rpm (preferably 1000 rpm) and a growth pressure of 100 torr, by adjusting the flow rates of TMGa, TMAL, N2, H2, and NH3 gases, an AlGaN layer with a thickness of 15 - 35 nm (preferably 22 nm) is grownX Ga (1-X) N barrier layer, where the Al component X ranges from 15% to 50% (preferably 20 - 25%). This layer plays a crucial role in controlling the current magnitude and reliability. Among them, the feeding rate of TMGA is 0 - 500 sccm / min (preferably 80 sccm / min), the feeding rate of TMAL is 50 - 500 sccm / min (preferably 300 sccm / min), the feeding rate of N2 is 0 - 100 L / min (preferably 64 L / min), the feeding rate of H2 is 50 - 200 L / min (preferably 120 L / min), and the feeding rate of NH3 is 1 - 100 L / min (preferably 50 L / min). The barrier layer is a key part of the HEMT chip, and its thickness and growth conditions have an important impact on the current transmission characteristics of the chip. By precisely controlling the growth parameters of the barrier layer, a high-quality barrier layer can be obtained, thereby improving the switching speed and current control ability of the chip.

[0028] Growth of SiN dielectric capping layer: Finally, at a temperature of 700 - 1100 °C (preferably 1000 °C) and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SiH4 gas, a SiN dielectric capping layer with a thickness of 0.1 - 100 nm (preferably 2 nm) is grown to protect and optimize the chip surface. Among them, the feeding rate of N2 is 0 - 100 L / min (preferably 64 L / min), the feeding rate of H2 is 50 - 200 L / min (preferably 120 L / min), the feeding rate of NH3 is 1 - 100 L / min (preferably 50 L / min), the concentration of the second SiH4 is 2%, and the feeding rate is 0 - 500 sccm / min (preferably 40 sccm / min). The above gases are fed simultaneously. The introduction of the SiN dielectric capping layer can protect the chip surface from the influence of the external environment, improving the stability and reliability of the chip. At the same time, by precisely controlling the growth parameters of the capping layer and introducing an appropriate amount of the second SiH4, the electrical characteristics of the chip surface can be further optimized.

[0029] Finally, a GaN HEMT vertical structure epitaxy is obtained.

[0030] During the entire preparation process, the growth of each layer needs to be carried out under strictly controlled temperature, gas flow rate, and doping conditions to ensure the high-quality growth of the GaN HEMT vertical structure epitaxy.

[0031] A preparation method for a gate-first GaN HEMT vertical structure chip disclosed by the present invention includes the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; grow a GaN drift region, an AlN insertion layer, an Al X Ga (1-X) N barrier layer, and a SiN dielectric cap layer on the substrate in sequence by metalorganic chemical vapor deposition.

[0032] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out of the pure water tank, transfer it to a spin dryer. The spin dryer needs to purge N2 at all times, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water having a water resistance of more than 8. The rotation speed changes as 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0033] 3. Alignment preparation: Prepare marks by photolithography and evaporation processes to achieve the purpose of alignment. First, use a 1-μm negative photoresist and coat it evenly on the surface. Expose the pattern using a lithography machine, bake it at 100 °C, and remove the excess photoresist using a positive photoresist developer. Before metal evaporation, bombard the surface of the GaN HEMT vertical structure epitaxial wafer with an ion source for 2 min. Evaporate the metal using CrTiNi. After evaporation, perform stripping using a stripper. The stripper is first immersed in a degluing tank for 10 min, and finally, high-pressure rinsing with pure water is performed. During the rinsing process, add a rotation of 1000 rpm for 2 min.

[0034] 4. Gate preparation: Lithographically pattern the electrode contact area of the gate on the top, and fabricate the gate of the device using a metal sputtering machine, photolithography, and metal etching. First, use a metal sputtering machine. Deposit a layer of TiAlNi, and then use a 1-3-μm positive photoresist as a mask for photolithography. Develop the pattern through exposure. Etch the pattern using a metal etching machine.

[0035] 5. Source opening: Perform opening on the top using photolithography and etching processes. Lithographically pattern the window area of the source, and remove the SiN dielectric cap layer in the window area by inductively coupled plasma etching (ICP). Use a 3-μm positive photoresist for photolithography, and develop a pattern after exposure as a mask before etching. For etching, use an ICP etching machine. First, etch the dielectric with an F - radical, and then etch GaN with a Cl - radical.

[0036] Note: The depth after etching should be below the two-dimensional electron gas, and the photolithography angle should be about 60° to make the etched trench smooth.

[0037] 6. Source electrode preparation: The source electrode of the device is fabricated by photolithography and evaporation. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal is composed of at least one of Ti, Al, Ni, TiN, and AlSi. The source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (RTA) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Photolithography uses a negative photoresist with a thickness of 1 - 3 μm for lift-off. The pattern is developed through exposure. TiAlTi is evaporated using a metal evaporator and annealed using a rapid thermal annealing furnace to form an alloy.

[0038] Note: The metal coating should be smooth and continuous. After evaporation, alloying is carried out at a high temperature of 400 - 500 °C. The purpose is to make the gold-coated metal penetrate downward into the two-dimensional electron layer to achieve the effect of conductivity.

[0039] 7. Field plate preparation: First, a passivation layer is grown on the top by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is composed of at least one of SiN, SiO2, and Al2O3. After photolithography, the conductive channels of the source and gate are etched. A negative photoresist with a thickness of 1 - 3 μm is used for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0040] 8. Deep etching and opening holes: Deep etching is carried out by photolithography and etching. A photoresist with a thickness of 7 - 9 μm is used as a mask. Deep holes are made at specific positions through exposure and development. Then, a Cl-based etchant is used to perform deep etching on the GaN HEMT vertical structure epitaxial wafer, and the etching depth is about 3 - 5 μm. - The etching depth is about 3 - 5 μm.

[0041] 9. Electron isolation: Electron isolation is performed on the top by photolithography and ion implantation to form a chip isolation region and achieve electrical isolation of the active region. The implanted element is at least one of F, Ar, B, and N. Photolithography uses a positive photoresist with a thickness of 3 μm, and a layer of pattern is developed through exposure as a mask before ion implantation. Boron ions are used for ion implantation to dope the areas without a photolithography mask to achieve the purpose of electron isolation.

[0042] 10. Drain Preparation: Lithographically pattern the electrode contact area of the drain at the bottom, and grow the electrode metal by electron beam evaporation or magnetron sputtering. The metal consists of at least one of Ti, Al, Ni, TiN, and AlSi. Form the drain electrode through a lift-off process, and perform rapid thermal annealing on the drain electrode metal in a nitrogen atmosphere to form an ohmic contact in the drain region. Use photolithography, etching, and evaporation to fabricate the drain of the device. Use a positive photoresist with a thickness of 1 - 3 μm as a mask, and use an etching machine to etch out the drain channel at a specific position. For photolithography, use a negative photoresist with a thickness of 1 - 3 μm for lift-off. Develop the pattern through exposure. Evaporate TiAlNiAu on the drain channel using a metal evaporator, and anneal it with RTA to form an alloy.

[0043] Note: The depth after etching should be below the two-dimensional electron gas, and the photolithography angle should be about 60 degrees to make the etched trenches smooth.

[0044] 11. Bonding Metal Preparation: Grow a passivation layer by plasma-enhanced chemical vapor deposition at the bottom. The passivation layer consists of at least one of SiN, SiO2, and Al2O3, and lithographically pattern the drain electrode lead-out area. Lithographically pattern the gate electrode and source electrode lead-out areas on the top to obtain the chip. Use photolithography and evaporation to fabricate the required bonding metal. For photolithography, use a negative photoresist with a thickness of 7 - 9 μm for lift-off. Develop the pattern through exposure. Evaporate TiAlNi using a metal evaporator. Use a bonder, and before bonding, align with an infrared laser to align the bonding metal with the deep etched holes, and bond the two chips A and B together in a vacuum manner.

[0045] See Figure 1 For the structural schematic diagram of the GaN HEMT vertical structure epitaxy disclosed in the present invention; as can be seen from the figure, when preparing the GaN HEMT vertical structure epitaxy disclosed in the present invention, first, select high-quality GaN as the substrate material, which provides mechanical support and thermal conductivity for the entire epitaxial structure, and at the same time avoids the epitaxial layer defects introduced during the heteroepitaxial process. Epitaxially grow the GaN drift region and the GaN channel layer on the GaN substrate successively. This region is the key part of the chip to withstand the off-state voltage and has a direct impact on the on-resistance of the chip. Subsequently, deposit a layer of AlN (aluminum nitride) insertion layer on the GaN channel layer. This AlN insertion layer is used to adjust the height and distribution of the electron barrier to further optimize the chip performance. Immediately afterwards, epitaxially grow a barrier layer on the AlN insertion layer. This layer and the GaN channel layer form a heterojunction to induce a two-dimensional electron gas with high concentration and high mobility, which is the key to forming an efficient electron transport channel. Finally, in-situ deposit a dielectric capping layer on the barrier layer. This dielectric capping layer not only plays a protective role to prevent damage to the underlying structure during subsequent processes, but also serves as an etch stop layer to ensure the accuracy of subsequent processes.

[0046] See Figure 2Schematic diagram of the vertical structure AlGaN / GaN power chip disclosed by the present invention; It can be seen from the figure that the AlGaN / GaN heterojunction provides a two-dimensional electron gas participating in the operation of the chip, serving as the carrier source for the chip to conduct electricity. The chip gate is located between the source electrodes, and the on-off of the current is controlled by applying a voltage. When the gate voltage is lower than the turn-on voltage (also known as the threshold voltage) of the chip, the two-dimensional electron gas in the channel layer region under the gate is depleted, and the chip is in the off state. The breakdown voltage of the chip depends on the thickness of the channel layer, drift region, and substrate. When the gate voltage is higher than the threshold voltage, the two-dimensional electron gas in the channel layer region under the gate is restored and flows vertically through the channel layer, drift region, and substrate to the drain under the action of the electric field. The dielectric layer in the gate region can effectively reduce gate leakage and lower the operating loss of the chip. The drift region and substrate are doped with n-type to reduce the bulk resistance, achieving a low on-resistance of the chip. The carrier blocking layers on both sides of the drift region are used to regulate the current direction to ensure that the current does not flow to other regions of the chip. The entire structure shows a complete path of injecting current from the source electrode, efficiently conducting through the GaN epitaxial layer and substrate, and finally flowing out through the drain. This vertical structure design optimizes the current path, weakens the influence of the interface states between the passivation layer / barrier layer on carrier transport, and improves the efficiency and reliability of the chip.

[0047] See Figure 3 Flowchart of the preparation method of the gate-first GaN HEMT vertical structure chip disclosed by the present invention; It can be seen from the figure that the processing flow of incoming material A includes cleaning to remove surface impurities and ensure the purity of the material; positioning preparation to precisely set the positions of each layer, laying the foundation for subsequent steps; electrical isolation to achieve effective isolation between components and ensure electrical performance; gate preparation to construct the key structure for controlling current; source opening and preparation to prepare for source connection and deposit source material; low-temperature alloying to improve the electrical contact performance through low-temperature treatment; field plate preparation and deep etching opening to optimize the electric field distribution and form a vertical structure; the processing flow of incoming material B includes cleaning and positioning preparation, similar to incoming material A, to ensure the correct preparation of the material; drain opening and preparation to prepare for drain connection and deposit drain material; electrical isolation to emphasize again the effective isolation between components; bonding metal preparation and AB wafer bonding to achieve the tight combination of wafers A and B and form a complete chip. The vertical structure design makes the chip more compact, facilitating integration and application, and at the same time reducing the weight. Through deep etching opening and field plate preparation technologies, it is ensured that the chip can operate stably in various environments, enhancing its long-term reliability.

[0048] Example 1 A preparation method of a gate-first GaN HEMT vertical structure chip, comprising the following steps: 1. Prepare a GaN HEMT vertical structure epitaxial wafer; grow a GaN drift region, an AlN insertion layer, and Al on the substrate in sequence by metalorganic chemical vapor depositionX Ga (1-X) N barrier layer and SiN dielectric capping layer.

[0049] 2. Cleaning: Immerse the GaN HEMT vertical structure epitaxial wafer in a 511 strong oxidation solution tank at 90 °C for 10 min in a cleaning machine, then transfer it to an IPA solution tank at 60 °C for 10 min to remove the residual solution on the surface. Finally, transfer it to a pure water tank at room temperature for 10 min. After the GaN HEMT vertical structure epitaxial wafer is taken out of the pure water tank, transfer it to a spin dryer. The spin dryer needs to blow N2 all the time, and the temperature is controlled at 60 °C. First, rinse the GaN HEMT vertical structure epitaxial wafer with pure water with a water resistance of more than 8. The rotation speed changes to 500 rpm for 5 min, 2000 rpm for 10 min, 1000 rpm for 5 min, and finally to 0 rpm.

[0050] 3. Alignment preparation: Prepare marks by photolithography and evaporation processes to achieve the purpose of alignment. First, use 1 μm negative photoresist and coat it evenly on the surface. Expose the pattern using a mask aligner, bake it at 100 °C, and remove the excess photoresist with a positive photoresist developer. Before metal evaporation, bombard the surface of the GaN HEMT vertical structure epitaxial wafer with an ion source for 2 min. Evaporate metal using CrTiNi. After evaporation, perform stripping with a stripper. The stripper is first immersed in a degluing tank for 10 min, and finally rinsed with high-pressure pure water. During the rinsing process, add a rotation of 1000 rpm for 2 min.

[0051] 4. Gate preparation: Lithograph the electrode contact area of the gate on the top, and use a metal sputtering machine, photolithography, and metal etching to make the gate of the device. First, use a metal sputtering machine. Deposit a layer of TiAlNi, and then use 2 μm positive photoresist for photolithography as a mask. Develop the pattern through exposure. Etch the pattern with a metal etcher.

[0052] 5. Source opening: Make an opening on the top by photolithography and etching processes. Lithograph the window area of the source, and use inductively coupled plasma etching (ICP) to remove the SiN dielectric capping layer in the window area. Use 3 μm positive photoresist for photolithography, and make a layer of pattern through exposure and development as a mask before etching. Use an ICP etcher for etching with F - -based to etch the dielectric first, and then use Cl - -based to etch GaN.

[0053] Note: The depth after etching should be below the two-dimensional electron gas, and the photolithography angle should be 60° to make the etched groove smooth.

[0054] 6. Source Electrode Preparation: Lithography and evaporation are used to fabricate the source electrode of the device. The electrode contact area of the source electrode is lithographed on the top, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti; the source electrode is formed through a lift-off process, and the source electrode metal is subjected to rapid thermal annealing (RTA) treatment in a nitrogen atmosphere to form an ohmic contact in the source region. Lithography uses a 2-μm negative photoresist for lift-off. The pattern is developed through exposure. TiAlTi is evaporated using a metal evaporator and annealed using a rapid thermal annealing furnace to form an alloy.

[0055] Note: The metal coating should be smooth and continuous. After evaporation, alloying is performed at a high temperature of 450 °C to allow the gold to penetrate downward and wrap the metal into the two-dimensional electron layer to achieve the conductivity effect.

[0056] 7. Field Plate Preparation: First, a passivation layer is grown on the top by plasma enhanced chemical vapor deposition (PECVD). The passivation layer is SiN. After lithography, the conductive channels of the source and gate are etched. A 2-μm negative photoresist is used for lift-off. The pattern is developed through exposure. TiAlNi is evaporated using a metal evaporator to complete the fabrication of the field plate.

[0057] 8. Deep Etching and Opening Holes: Lithography and etching are used for deep etching. An 8-μm photoresist is used as a mask. Deep holes are made at specific positions through exposure and development. Then, a Cl-based etcher is used to perform deep etching on the GaN HEMT vertical structure epitaxial wafer, and the etching depth is about 3 - 5 μm. - The etching depth is about 3 - 5 μm.

[0058] 9. Electron Isolation: Lithography and ion implantation are used on the top to achieve electron isolation, forming a chip isolation region to realize the electrical isolation of the active region. The implanted element is F. Lithography uses a 3-μm positive photoresist, and a pattern is made through exposure and development as a mask before ion implantation. Boron ions are used for ion implantation to dope the areas without a lithography mask to achieve the purpose of electron isolation.

[0059] 10. Drain Electrode Preparation: The electrode contact area of the drain electrode is lithographed on the bottom, and the electrode metal is grown by electron beam evaporation or magnetron sputtering. The metal consists of Ti; the drain electrode is formed through a lift-off process, and the drain electrode metal is subjected to rapid thermal annealing treatment in a nitrogen atmosphere to form an ohmic contact in the drain region. Lithography, etching, and evaporation are used to fabricate the drain electrode of the device. A 2-μm positive photoresist is used as a mask, and a drain channel is etched at a specific position using an etcher. Lithography uses a 2-μm negative photoresist for lift-off. The pattern is developed through exposure. TiAlNiAu is evaporated on the drain channel using a metal evaporator and annealed using RTA to form an alloy.

[0060] Note: The depth after etching should be below the two-dimensional electron gas, and the lithography angle should be 60° to make the etched grooves smooth.

[0061] 11. Preparation of bonding metal: A passivation layer is grown on the bottom by plasma-enhanced chemical vapor deposition. The passivation layer is composed of SiN, and the drain electrode lead-out area is lithographed. The gate electrode and source electrode lead-out areas are lithographed on the top to obtain the chip. Lithography and evaporation are used to make the required bonding metal. A negative photoresist with a thickness of 8 μm is used for lift-off in lithography. The pattern is developed by exposure. TiAlNi is evaporated using a metal evaporator. A bonding machine is used. Before bonding, infrared laser alignment is performed to align the bonding metal with the deep etched holes, and the two wafers A and B are bonded together in a vacuum manner.

[0062] Among them, the preparation method of the vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: A 1000-μm GaN substrate is selected as the growth basis.

[0063] Substrate treatment: The GaN substrate is pretreated at a temperature of 1150 °C. At the same time, N2 is introduced at a rate of 100 L / min, H2 is introduced at a rate of 200 L / min, and NH3 is introduced at a rate of 100 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0064] Drift region growth: In the temperature range of 1150 °C and a growth pressure of 200 torr, by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4, a drift region with a thickness of 50 μm is grown. This layer is crucial for device performance. Among them, the flow rate of TMGA is 1000 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, the flow rate of NH3 is 100 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 500 sccm / min. The growth temperature is 1100 °C, and the growth rotation speed is 1200 rpm.

[0065] Ion implantation: The carrier blocking layer region is defined by lithography on the epitaxial drift region grown in the previous step, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 3 μm.

[0066] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1080 °C, the rotation speed is 1200 rpm, the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled at 300 nm. The flow rate of TMGa is 500 scmm / min, the flow rate of N2 is 64 L / min, the flow rate of H2 is 120 L / min, and the flow rate of NH3 is 50 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0067] Insertion layer growth: Subsequently, at a temperature of 1100 °C and a growth pressure of 75 torr, the flow rates of gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 1 nm to optimize device performance. Among them, the flow rate of TMAL is 500 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min.

[0068] Barrier layer growth: Then, in the temperature range of 1100 °C, at 1000 rpm and a growth pressure of 100 torr, by adjusting the flow rates of gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 35 nm is grown, where the Al component X ranges from 20%. This layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 500 sccm / min, the flow rate of TMAL is 500 sccm / min, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, and the flow rate of NH3 is 100 L / min.

[0069] SIN dielectric cap layer growth: Finally, at a temperature of 1100 °C and a growth pressure of 200 torr, by adjusting the flow rates of gases N2, H2, and NH3 and introducing the second SiH4 gas, a SIN dielectric cap layer with a thickness of 100 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 100 L / min, the flow rate of H2 is 200 L / min, the flow rate of NH3 is 100 L / min, and the concentration of the second SiH4 is 2%, with a flow rate of 500 sccm / min.

[0070] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0071] Example 2 A preparation method for a vertical structure chip of a front-gate GaN HEMT, comprising the following steps: The difference from Example 1 is: 4. Gate preparation: Lithography uses 1μm positive photoresist as a mask.

[0072] 5. Source opening: The lithography angle should be 55°, so that the etched groove can be gentle.

[0073] 6. Source preparation: The metal is composed of Ti and Al. Lithography uses 1μm negative photoresist for lift-off. After evaporation, alloying is carried out at a high temperature of 400°C.

[0074] 7. Field plate preparation: The passivation layer is SiN and SiO2. 1μm negative photoresist is used for lift-off.

[0075] 8. Deep etching opening: 7μm photoresist is used as a mask. The etching depth is 3μm.

[0076] 9. Electron isolation: The implanted elements are F and Ar.

[0077] 10. Drain preparation: The metal is composed of Ti and Al. 1μm positive photoresist is used as a mask. Lithography uses 1μm negative photoresist for lift-off. The lithography angle should be 55°, so that the etched groove can be gentle.

[0078] 11. Bonding metal preparation: The passivation layer is composed of SiN and SiO2. Lithography uses 7μm negative photoresist for lift-off.

[0079] Among them, the preparation method for the epitaxy of the vertical structure of GaN HEMT comprises the following steps: Substrate preparation: Select a 900μm GaN substrate as the growth basis.

[0080] Substrate treatment: At a temperature of 1140°C, the GaN substrate is pre-treated, and at the same time, N2 is introduced at a rate of 90 L / min, H2 is introduced at a rate of 140 L / min, and NH3 is introduced at a rate of 90 L / min to prepare for subsequent epitaxial growth. High-temperature pre-treatment helps to remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pre-treatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0081] Drift region growth: In the temperature range of 1130 °C, under a growth pressure of 200 torr, a drift region with a thickness of 40 μm is grown by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 800 sccm / min, the flow rate of N2 is 70 L / min, the flow rate of H2 is 170 L / min, the flow rate of NH3 is 70 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 200 sccm / min. The growth temperature is 1000 °C, and the growth rotation speed is 800 rpm.

[0082] Ion implantation: On the epitaxial drift region grown in the previous step, the carrier blocking layer region is defined by photolithography, and ion implantation is performed on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region, achieving high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 0.1 μm.

[0083] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. Among them, the growth temperature is 1000 °C, the rotation speed is 800 rpm, the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are simultaneously introduced to grow undoped GaN, and its thickness is controlled at 150 nm. Among them, the flow rate of TMGa is 200 scmm / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0084] Insertion layer growth: Subsequently, at a temperature of 1020 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 2 nm to optimize device performance. Among them, the flow rate of TMAL is 250 sccm / min, the flow rate of N2 is 60 L / min, the flow rate of H2 is 160 L / min, and the flow rate of NH3 is 70 L / min.

[0085] Barrier layer growth: Then, in the temperature range of 1010 °C, at 800 rpm, under a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X)N barrier layer, where the Al component X ranges from 15%, and this layer plays a key role in controlling current transmission. Among them, the flow rate of TMGA is 300 sccm / min, the flow rate of TMAL is 250 sccm / min, the flow rate of N2 is 80 L / min, the flow rate of H2 is 140 L / min, and the flow rate of NH3 is 80 L / min.

[0086] Growth of SIN dielectric capping layer: Finally, at a temperature of 950 °C and a growth pressure of 200 torr, by adjusting the flow rates of N2, H2, and NH3 gases and introducing a second SIH4 gas, a SIN dielectric capping layer with a thickness of 20 nm is grown to protect and optimize the device surface. Among them, the flow rate of N2 is 80 L / min, the flow rate of H2 is 140 L / min, the flow rate of NH3 is 80 L / min, the concentration of the second SIH4 is 2%, and the flow rate is 200 sccm / min.

[0087] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0088] Example 3 A preparation method for a gate-first GaN HEMT vertical structure chip includes the following steps: The difference from Example 1 is: 4. Gate preparation: Photolithography uses 3 μm positive photoresist as a mask.

[0089] 5. Source opening: The photolithography angle should be 65° to make the etched trench smooth.

[0090] 6. Source preparation: The metal consists of Ni and TiN. Photolithography uses 3 μm negative photoresist for lift-off. After evaporation, alloying is carried out at a high temperature of 460 °C.

[0091] 7. Field plate preparation: The passivation layer is SiO2. 3 μm negative photoresist is used for lift-off.

[0092] 8. Deep etching opening: 9 μm photoresist is used as a mask. The etching depth is 3 μm.

[0093] 9. Electron isolation: The implanted element is B.

[0094] 10. Drain preparation: The metal consists of Ni and TiN. 3 μm positive photoresist is used as a mask. Photolithography uses 3 μm negative photoresist for lift-off. The photolithography angle should be 65° to make the etched trench smooth.

[0095] 11. Bonding metal preparation: The passivation layer is composed of SiO2. Photolithography uses 9 μm negative photoresist for lift-off.

[0096] Among them, the preparation method of the vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: Select a 500-μm GaN substrate as the growth basis.

[0097] Substrate treatment: Pretreat the GaN substrate at a temperature of 1100 °C. Meanwhile, introduce N2 at a rate of 0.1 L / min, H2 at a rate of 120 L / min, and NH3 at a rate of 50 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0098] Drift region growth: In the temperature range of 1100 °C and at a growth pressure of 200 torr, grow a drift region with a thickness of 7 μm by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the introduction rate of TMGA is 600 sccm / min, the introduction rate of N2 is 10 L / min, the introduction rate of H2 is 90 L / min, the introduction rate of NH3 is 45 L / min, the concentration of the first SIH4 is 200 ppm, and the introduction rate is 5 sccm / min. The growth temperature is 1050 °C, and the growth rotation speed is 900 rpm.

[0099] Ion implantation: Define the carrier blocking layer region on the epitaxial drift region grown in the previous step by photolithography, and perform ion implantation on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 5 μm.

[0100] Channel layer growth: Perform secondary epitaxy on the epitaxial wafer after ion implantation. Among them, the growth temperature is 1100 °C, the rotation speed is 1000 rpm, the growth pressure is 200 torr, and TMGa, N2, H2, and NH3 are introduced simultaneously to grow undoped GaN, and its thickness is controlled within 200 nm. Among them, the introduction rate of TMGa is 600 scmm / min, the introduction rate of N2 is 80 L / min, the introduction rate of H2 is 100 L / min, and the introduction rate of NH3 is 80 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved, and the scattering of the two-dimensional electron gas can be reduced.

[0101] Insertion layer growth: Subsequently, at a temperature of 1000 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 were adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 0.8 nm to optimize device performance. Among them, the introduction rate of TMAL was 200 sccm / min, the introduction rate of N2 was 0.1 L / min, the introduction rate of H2 was 190 L / min, and the introduction rate of NH3 was 5 L / min.

[0102] Barrier layer growth: Then, in the temperature range of 1020 °C, at 1100 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 22 nm was grown, where the Al component X ranged from 25%, and this layer played a key role in controlling current transmission. Among them, the introduction rate of TMGA was 80 sccm / min, the introduction rate of TMAL was 300 sccm / min, the introduction rate of N2 was 64 L / min, the introduction rate of H2 was 120 L / min, and the introduction rate of NH3 was 50 L / min.

[0103] SIN dielectric capping layer growth: Finally, at a temperature of 1000 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric capping layer with a thickness of 2 nm was grown to protect and optimize the device surface. Among them, the introduction rate of N2 was 64 L / min, the introduction rate of H2 was 120 L / min, the introduction rate of NH3 was 50 L / min, the concentration of the second SIH4 was 2%, and the introduction rate was 40 sccm / min.

[0104] Finally, a vertical structure epitaxy of GaN HEMT was obtained.

[0105] Example 4 A preparation method for a pre-gate GaN HEMT vertical structure chip, comprising the following steps: The difference from Example 1 is: 5. Source opening: The lithography angle should be 65° to make the etched trench smooth.

[0106] 6. Source preparation: The metal is composed of AlSi. Lithography uses a 1-μm negative photoresist for lift-off. After evaporation, alloying is performed at a high temperature of 500 °C.

[0107] 7. Field plate preparation: The passivation layer is Al2O3.

[0108] 9. Electron isolation: The implanted element is N.

[0109] 10. Drain preparation: The metal is composed of AlSi. The lithography angle should be 65° to make the etched trench smooth.

[0110] 11. Bonding metal preparation: The passivation layer is composed of Al2O3. The preparation method of the vertical structure epitaxy of GaN HEMT includes the following steps: Substrate preparation: Select a 300-μm GaN substrate as the growth basis.

[0111] Substrate treatment: Pretreat the GaN substrate at a temperature of 1000°C. At the same time, introduce N2 at a rate of 20 L / min, H2 at a rate of 50 L / min, and NH3 at a rate of 1 L / min to prepare for subsequent epitaxial growth. High-temperature pretreatment helps remove impurities and defects on the substrate surface and improve the growth quality of the epitaxial layer. By precisely controlling the gas flow rate, the pretreatment environment can be optimized to provide favorable conditions for subsequent epitaxial growth.

[0112] Drift region growth: In the temperature range of 1000°C and at a growth pressure of 200 torr, grow a drift region with a thickness of 0.5 μm by precisely controlling the flow rates of TMGA, N2, H2, NH3, and the first SIH4. This layer is crucial for device performance. Among them, the flow rate of TMGA is 200 sccm / min, the flow rate of N2 is 0.1 L / min, the flow rate of H2 is 50 L / min, the flow rate of NH3 is 1 L / min, the concentration of the first SIH4 is 200 ppm, and the flow rate is 0.1 sccm / min. The growth temperature is 1150°C, and the growth rotation speed is 1150 rpm.

[0113] Ion implantation: Define the carrier blocking layer region on the epitaxial drift region grown in the previous step by lithography, and perform ion implantation on the carrier blocking layer region. The high-energy ions implanted are N ions. The implanted ions damage the lattice of the implanted region to achieve high resistance in the implanted region, thereby restricting the current direction. Among them, the implantation depth of N ions is 20 μm.

[0114] Channel layer growth: On the epitaxial wafer after ion implantation, secondary epitaxy is carried out. The growth temperature is 1150 °C, the rotation speed is 1150 rpm, and the growth pressure is 200 torr. At the same time, TMGa, N2, H2, and NH3 are introduced to grow undoped GaN, and its thickness is controlled at 400 nm. The introduction rate of TMGa is 1000 sccm / min, the introduction rate of H2 is 200 L / min, and the introduction rate of NH3 is 100 L / min. The quality of this layer determines the mobility and electron concentration of the two-dimensional electron gas. By adjusting the temperature and growth rate, the flatness of the interface can be improved and the scattering of the two-dimensional electron gas can be reduced.

[0115] Insertion layer growth: Subsequently, at a temperature of 800 °C and a growth pressure of 75 torr, the flow rates of the gases TMAL, N2, H2, and NH3 are adjusted, especially reducing the N2 flow rate to almost zero, to grow an extremely thin insertion layer with a thickness controlled at 0.1 nm to optimize device performance. Among them, the introduction rate of TMAL is 0..1 sccm / min, the introduction rate of N2 is 0.1 L / min, the introduction rate of H2 is 50 L / min, and the introduction rate of NH3 is 1 L / min.

[0116] Barrier layer growth: Then, within a temperature range of 800 °C, at 1200 rpm and a growth pressure of 100 torr, by adjusting the flow rates of the gases TMGA, TMAL, N2, H2, and NH3, an Al X Ga (1-X) N barrier layer with a thickness of 15 nm is grown, where the Al component X ranges from 50%. This layer plays a key role in controlling current transmission. Among them, the introduction rate of TMGA is 0.1 sccm / min, the introduction rate of TMAL is 50 sccm / min, the introduction rate of N2 is 0.1 L / min, the introduction rate of H2 is 50 L / min, and the introduction rate of NH3 is 1 L / min.

[0117] SIN dielectric cap layer growth: Finally, at a temperature of 700 °C and a growth pressure of 200 torr, by adjusting the flow rates of the gases N2, H2, and NH3 and introducing the second SIH4 gas, a SIN dielectric cap layer with a thickness of 0.1 nm is grown to protect and optimize the device surface. Among them, the introduction rate of N2 is 0.1 L / min, the introduction rate of H2 is 50 L / min, the introduction rate of NH3 is 1 L / min, and the concentration of the second SIH4 is 2%, and the introduction rate is 0.1 sccm / min.

[0118] Finally, a vertical structure epitaxy of GaN HEMT is obtained.

[0119] The above content is only for explaining the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution in accordance with the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A method for preparing a gate-first GaN HEMT vertical structure chip, characterized in that: The following steps are involved: 1) Chemical vapor deposition is used to sequentially grow GaN drift region, AlN insertion layer, Al X Ga (1-X) N barrier layer and SiN dielectric cap layer, obtain GaN HEMT vertical structure epitaxial wafer, and then clean, dry and position mark; the Al X Ga (1-X) In the N barrier layer, 0.15≤X≤0.5; 2) The electrode contact area of ​​the gate is photolithographically formed on the top, and the gate electrode is formed after TiAlNi evaporation, photolithography and metal etching; 3) Photolithography a source window area on the top, and etching away the SiN dielectric cap layer in the window area; 4) Photolithography the source electrode contact area on the top, and evaporate the electrode metal. After stripping, the source electrode is formed; Rapid thermal annealing at 400-500°C to form the alloy; 5) Grow a passivation layer on the top, etch out the conductive channels of the source and gate, and obtain the field plate after evaporation; 6) Deeply etch and open holes in the GaN HEMT vertical structure epitaxial wafer; 7) Form a chip isolation area on the top through photolithography and ion implantation; 8) Photolithography the drain electrode contact area at the bottom, and evaporate the electrode metal. After stripping, the drain electrode is formed; 9) Grow a passivation layer at the bottom and photolithograph the drain electrode lead-out region; photolithograph the gate electrode and source electrode lead-out regions at the top to obtain a gate-first GaN HEMT vertical structure chip.

2. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the pretreatment conditions of the substrate include: pretreating the substrate at 1000-1150° C., while introducing N2 at a rate of 0-100 L / min, H2 at a rate of 50-200 L / min, and NH3 at a rate of 1-100 L / min.

3. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for the growth of the GaN drift region include: at 1000-1150° C. and a growth pressure of 200 torr, by controlling the flow rates of trimethylgallium, N2, H2, NH3 and the first monosilane, a GaN drift region with a thickness of 0.5-50 μm is grown, the growth temperature is 1000-1150° C., and the growth speed is 800-1200 rpm; wherein the introduction rate of trimethylgallium is 200-1000 sccm / min, the introduction rate of N2 is 0-100 L / min, the introduction rate of H2 is 50-200 L / min, the introduction rate of NH3 is 1-100 L / min, the concentration of the first monosilane is 200 ppm, and the introduction rate is 0-500 sccm / min; In step 1), a carrier blocking layer region is defined on the GaN drift region by photolithography, and ion implantation and secondary epitaxy are performed on the carrier blocking layer region; the growth temperature of the secondary epitaxy is 1000-1150°C, the rotation speed is 800-1200rpm, the growth pressure is 200torr, and trimethylgallium, N2, H2 and NH3 are introduced at the same time to grow undoped GaN, and the thickness of GaN is 150-400nm, wherein the introduction rate of trimethylgallium is 200-1000sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 0-200L / min, and the introduction rate of NH3 is 0-100L / min.

4. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the growth conditions of the AlN insertion layer include: at 800-1100° C. and a growth pressure of 75 torr, trimethylaluminum, H2 and NH3 are introduced simultaneously to grow an extremely thin AlN insertion layer, and the thickness of the AlN insertion layer is 0-2 nm; wherein the introduction rate of trimethylaluminum is 0-500 sccm / min, the introduction rate of H2 is 50-200 L / min, and the introduction rate of NH3 is 1-100 L / min; In step 1), Al X Ga (1-X) The growth conditions of the N barrier layer include: growing an Al layer with a thickness of 15-35 nm by adjusting the flow rates of trimethylgallium, trimethylaluminum, N2, H2 and NH3 at 800-1100°C, 800-1200rpm, and a growth pressure of 100 torr. X Ga (1-X) N barrier layer; wherein the molar percentage of X is 15%-50%, the introduction rate of trimethylgallium is 0-500sccm / min, the introduction rate of trimethylaluminum is 50-500sccm / min, the introduction rate of N2 is 0-100L / min, the introduction rate of H2 is 50-200L / min, and the introduction rate of NH3 is 1-100L / min.

5. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 1), the conditions for growing the SiN dielectric cap layer include: growing a SiN dielectric cap layer with a thickness of 0.1-100 nm at 700-1100° C. and a growth pressure of 200 torr by adjusting the flow rates of N2, H2 and NH3 and introducing a second monosilane; wherein the N2 introduction rate is 0-100 L / min, the H2 introduction rate is 50-200 L / min, the NH3 introduction rate is 1-100 L / min, the concentration of the second monosilane is 2%, and the second monosilane introduction rate is 0-500 sccm / min.

6. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 2), the gate electrode is a Ti / Al / Ti electrode metal; In step 3), the depth of the window region of the source electrode is below the two-dimensional electron gas, and the photolithography angle is 60°; the SiN dielectric cap layer in the window region is removed by inductively coupled plasma etching.

7. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 4), before evaporation, the substrate is immersed in a strong oxidizing solution tank and then immersed in dilute hydrochloric acid; the source electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 5), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

8. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 7), the ion implanted element includes at least one of F, Ar, B and N; and the depth of the ion implantation is 0.1-20 μm.

9. The method for preparing a gate-first GaN HEMT vertical structure chip according to claim 1, characterized in that: In step 8), the depth of the electrode contact region of the drain electrode is below the two-dimensional electron gas, and the photolithography angle is 60°; the drain electrode is an electrode metal composed of at least one of Ti, Al, Ni, TiN and AlSi; In step 9), the passivation layer is composed of at least one of SiN, SiO2 and Al2O3.

10. A gate-first GaN HEMT vertical structure chip, characterized in that: The method according to any one of claims 1 to 9 is used to prepare the substrate, comprising: a substrate; The GaN drift region, the AlN insertion layer, and the Al X Ga (1-X) N barrier layer and SiN dielectric cap layer; the Al X Ga (1-X) In the N barrier layer, 0.15≤X≤0.5; A gate electrode is located on top of the SiN dielectric cap layer, the gate electrode is composed of a TiAlN stack and is connected to the Al X Ga (1-X) The N barrier layer forms a Schottky contact; A source window penetrating the SiN dielectric cap layer and a source electrode located in the source window, wherein the source electrode is exposed by etching the Al X Ga (1-X) The N barrier layer forms an ohmic contact with the GaN drift layer; A top passivation layer covering the gate electrode and the source electrode, wherein the top passivation layer is provided with a conductive channel connected to the gate electrode and the source electrode respectively, and a field plate structure is formed on the surface of the conductive channel; A drain electrode located at the bottom of the substrate, wherein the drain electrode forms an ohmic contact with the GaN drift region; An isolation region penetrating the substrate and the GaN drift region, wherein the isolation region is formed by ion implantation and is used to define a chip boundary; A first passivation layer is disposed on the top, wherein a first opening and a second opening are disposed in the first passivation layer, respectively exposing metal connection portions of the gate electrode and the source electrode; and a second passivation layer disposed at the bottom of the substrate, wherein a third opening is disposed in the second passivation layer to expose the metal connection portion of the drain electrode.

Images