Wafer alignment method and wafer bonding method

Abstract

The present application relates to a wafer alignment method and a wafer bonding method, comprising: using a first wafer and a second wafer as target wafers respectively. Selecting at least two first target marks on the target wafer located on one side of a first reference line; at least two second target marks located on the other side of the first reference line; at least two first target marks and at least two second target marks are located on both sides of the second reference line respectively. Obtaining first angle data of each first target mark and second angle data of each second target mark. Determining a first angle offset based on the first angle data, and determining a second angle offset based on the second angle data. Determining an average angle offset of the corresponding target wafer based on the first angle offset and the second angle offset. Performing wafer angle alignment based on the average angle offset of the first wafer and the average angle offset of the second wafer. The present application can match the central symmetry effect of the wafer process and improve the accuracy of angle offset measurement.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a wafer alignment method and a wafer bonding method. Background Art

[0002] With the advent of the post-Moore era, the development of multi-wafer-on-wafer hybrid bonding (MWHB) structures in semiconductor manufacturing is becoming increasingly important. These structures can break through the von Neumann architecture, shrinking interconnect sizes to approximately 1μm and increasing the number of interconnects per square millimeter on the wafer to millions, significantly improving wafer integration and effectively reducing power consumption.

[0003] As the size of hybrid bonding interconnect structures (such as bonding pads) in multi-layer wafer bonding structures continues to shrink, the requirements for the alignment accuracy between wafers during wafer bonding in related technologies are becoming increasingly higher. Summary of the Invention

[0004] Based on this, the embodiments of the present application provide a wafer alignment method and a wafer bonding method, which can match the central symmetry effect in the wafer production process, improve the accuracy of angle offset measurement, and thus improve the wafer alignment accuracy.

[0005] To achieve the above objectives, in one aspect, some embodiments of the present application provide a wafer alignment method for aligning a first wafer and a second wafer, and the wafer alignment method includes the following steps.

[0006] The first wafer and the second wafer are respectively used as target wafers.

[0007] At least two wafer alignment marks on the target wafer located on one side of a first reference line are selected as first target marks, and at least two wafer alignment marks on the target wafer located on the other side of the first reference line are selected as second target marks; wherein, at least two first target marks are respectively located on both sides of the second reference line, and at least two second target marks are respectively located on both sides of the second reference line; the second reference line is orthogonal to the first reference line.

[0008] First angle data of at least two first target marks and second angle data of at least two second target marks are acquired respectively.

[0009] A first angular offset of the first target mark is determined based on the first angular data, and a second angular offset of the second target mark is determined based on the second angular data.

[0010] An average angular offset of the corresponding target wafer relative to the wafer machine is determined according to the first angular offset and the second angular offset.

[0011] An angular alignment between the first wafer and the second wafer is performed based on an average angular offset of the first wafer and an average angular offset of the second wafer.

[0012] In some embodiments, respectively acquiring first angle data of at least two first target marks and second angle data of at least two second target marks includes the following steps.

[0013] The intersection of the first reference line and the second reference line is determined as the reference point.

[0014] The first angle data is determined based on the angle between the straight line connecting the geometric centers and the reference points of at least two first target marks and the first reference line, and the second angle data is determined based on the angle between the straight line connecting the geometric centers and the reference points of at least two second target marks and the first reference line.

[0015] In some embodiments, the fiducial is located at the geometric center of the target wafer.

[0016] In some embodiments, the first wafer and the second wafer both include a plurality of chips arranged in an array, each chip having a wafer alignment mark; selecting at least two wafer alignment marks on the target wafer located on one side of the first reference line as the first target mark, and selecting at least two wafer alignment marks on the target wafer located on the other side of the first reference line as the second target mark, including the following steps.

[0017] A first chip and a second chip located on both sides of a first reference line on a target wafer are selected, and the wafer alignment mark on the first chip is used as a first target mark, and the wafer alignment mark on the second chip is used as a second target mark; wherein, the number of chips between the first chip and the second chip in a direction parallel to the second reference line and the first reference line is equal, and the number of chips between the first chip and the second chip in a direction parallel to the first reference line and the second reference line is equal.

[0018] In some embodiments, the first chips of the first wafer and the first chips of the second wafer are located in the same number of rows and columns in the chip array, and the second chips of the first wafer and the second chips are located in the same number of rows and columns in the chip array.

[0019] In some embodiments, after selecting at least two wafer alignment marks on the target wafer located on one side of the first reference line as first target marks, and selecting at least two wafer alignment marks on the target wafer located on the other side of the first reference line as second target marks, the wafer alignment method also includes the following steps.

[0020] First position data of at least two first target marks and second position data of at least two second target marks are acquired respectively.

[0021] A first position offset of the first target mark is determined according to the first position data, and a second position offset of the second target mark is determined according to the second position data.

[0022] An average position offset of the corresponding target wafer relative to the wafer machine is determined according to the first position offset and the second position offset.

[0023] Position alignment between the first wafer and the second wafer is performed based on the average position offset of the first wafer and the average position offset of the second wafer.

[0024] In some embodiments, the first position offset includes a first lateral position offset in a direction parallel to the first reference line and a first longitudinal position offset in a direction parallel to the second reference line; the second position offset includes a second lateral position offset in a direction parallel to the first reference line and a second longitudinal position offset in a direction parallel to the second reference line.

[0025] In some embodiments, the first angle data of at least two first target marks are measured and acquired synchronously with the first position data, and the second angle data of at least two second target marks are measured and acquired synchronously with the second position data.

[0026] In some embodiments, the wafer alignment method further includes the following steps.

[0027] According to the process sequence, the angular alignment of the first wafer and the second wafer of the current group is compensated according to the average angular offset of the first wafer and the average angular offset of the second wafer of the previous group.

[0028] On the other hand, the present application also provides a wafer bonding method according to some embodiments; the wafer bonding method includes: providing a first wafer and a second wafer; aligning the second wafer and the first wafer using the wafer alignment method described in some of the aforementioned embodiments of the present application; and bonding the aligned second wafer and the first wafer.

[0029] The embodiments of the present application may or at least have the following advantages:

[0030] In an embodiment of the present application, at least two first target marks are selected on one side of a first reference line, respectively located on either side of a second reference line, and at least two second target marks are selected on the other side of the first reference line, respectively located on either side of the second reference line, to sample angle data at different locations on either side of the first reference line and the second reference line, and the angle offset at different locations is measured multiple times. By determining the average angle offset of the corresponding target wafer relative to the wafer tool based on the first angle offset of the first target mark and the second angle offset of the second target mark, the determined average angle offset is globally representative for the corresponding target wafer and can eliminate the adverse effects of environmental factors at local locations on the wafer (such as optical signal interference, measurement noise interference, transient environmental fluctuations, etc.) on the angle data measurement, thereby improving the accuracy of the angle offset measurement. Angle alignment between the first wafer and the second wafer is performed based on the average angle offset of the first wafer and the average angle offset of the second wafer, which can match the centrosymmetric effect in the wafer production process. Alignment between wafers based on global deviations effectively improves wafer alignment accuracy and is conducive to improving the product yield of the wafer bonding process. In summary, under the joint action of the above technical features, the embodiment of the present application performs global measurement of the angle data of the wafer to match the central symmetry effect in the wafer production process, determines the globally representative average angle offset, and improves the accuracy of the angle offset measurement, which is beneficial to improving the wafer alignment accuracy.

[0031] The details of one or more embodiments of the present application are set forth in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0033] Figure 1 is a flow chart of a wafer alignment method provided in some embodiments;

[0034] Figure 2 A flowchart of another wafer alignment method provided in some embodiments;

[0035] Figure 3 A flowchart of another wafer alignment method provided in some embodiments;

[0036] Figure 4A flowchart of another wafer alignment method provided in some embodiments;

[0037] Figure 5 Schematic diagram of the structure of a wafer provided in some embodiments; wherein, Figure 5 Figure (a) is a schematic diagram of the structure of a first wafer. Figure 5 Figure (b) is a schematic structural diagram of a second wafer;

[0038] Figure 6 A schematic structural diagram of a combined pattern consisting of a first wafer alignment mark and a second wafer alignment mark provided in some embodiments;

[0039] Figure 7 A schematic structural diagram of a target wafer provided in some embodiments.

[0040] Description of reference numerals:

[0041] w1-first wafer, w2-second wafer, W-target wafer, S1-first wafer alignment mark, S2-second wafer alignment mark, A1-first target mark, A2-second target mark, o-reference point, C-chip, C1-first chip, C2-second chip. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0044] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, a first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion without departing from the teachings of the present application.

[0045] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] While embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, variations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Embodiments of the present invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to represent the actual shapes of regions of a device and are not intended to limit the scope of the present invention.

[0047] In the field of semiconductor manufacturing, the manufacturing processes in the wafer production process (such as wafer spin cleaning process, photoresist spin coating process, etc.) and the characteristics of the wafer itself (such as wafer orientation, wafer warpage, etc.) usually have a central symmetry effect.

[0048] Based on this, the embodiments of the present application provide a wafer alignment method and a wafer bonding method, which can match the central symmetry effect in the wafer production process, improve the accuracy of angle offset measurement, and thus improve the wafer alignment accuracy.

[0049] In some embodiments, see Figure 1 The wafer alignment method is used to align a first wafer and a second wafer; the wafer alignment method includes the following steps S100~S600.

[0050] S100 , taking a first wafer and a second wafer as target wafers respectively.

[0051] S200, select at least two wafer alignment marks on the target wafer located on one side of a first reference line as first target marks, and select at least two wafer alignment marks on the target wafer located on the other side of the first reference line as second target marks; wherein, at least two first target marks are respectively located on both sides of the second reference line, and at least two second target marks are respectively located on both sides of the second reference line; the second reference line is orthogonal to the first reference line.

[0052] S300 , respectively acquiring first angle data of at least two first target marks and second angle data of at least two second target marks.

[0053] S400 , determining a first angle offset of a first target mark according to the first angle data, and determining a second angle offset of a second target mark according to the second angle data.

[0054] S500 , determining an average angular offset of the corresponding target wafer relative to the wafer machine according to the first angular offset and the second angular offset.

[0055] S600 , performing angular alignment between the first wafer and the second wafer according to an average angular offset of the first wafer and an average angular offset of the second wafer.

[0056] In an embodiment of the present application, at least two first target marks are selected on one side of a first reference line, respectively located on either side of a second reference line, and at least two second target marks are selected on the other side of the first reference line, respectively located on either side of the second reference line, to sample angle data at different locations on either side of the first reference line and the second reference line, and the angle offset at different locations is measured multiple times. By determining the average angle offset of the corresponding target wafer relative to the wafer tool based on the first angle offset of the first target mark and the second angle offset of the second target mark, the determined average angle offset is globally representative for the corresponding target wafer and can eliminate the adverse effects of environmental factors at local locations on the wafer (such as optical signal interference, measurement noise interference, transient environmental fluctuations, etc.) on the angle data measurement, thereby improving the accuracy of the angle offset measurement. Angle alignment between the first wafer and the second wafer is performed based on the average angle offset of the first wafer and the average angle offset of the second wafer, which can match the centrosymmetric effect in the wafer production process. Alignment between wafers based on global deviations effectively improves wafer alignment accuracy and is conducive to improving the product yield of the wafer bonding process. In summary, under the joint action of the above technical features, the embodiment of the present application performs global measurement of the angle data of the wafer to match the central symmetry effect in the wafer production process, determines the globally representative average angle offset, and improves the accuracy of the angle offset measurement, which is beneficial to improving the wafer alignment accuracy.

[0057] In some embodiments, see Figure 2 , step S300 includes the following steps S310~S320.

[0058] S310: Determine the intersection of the first reference line and the second reference line as a reference point.

[0059] S320, determine the first angle data based on the angle between the straight line connecting the geometric centers and the reference points of at least two first target marks and the first reference line, and determine the second angle data based on the angle between the straight line connecting the geometric centers and the reference points of at least two second target marks and the first reference line.

[0060] In an embodiment of the present application, by determining the intersection of the first baseline and the second baseline as the reference point, and making the first angle data and the second angle data both determined based on the reference point, all angle data are determined with reference to the same fixed position, thereby enhancing the uniformity of the determined angle data to facilitate subsequent data processing steps, and at the same time improving data acquisition efficiency.

[0061] In some embodiments, the fiducial is located at the geometric center of the target wafer.

[0062] In the embodiment of the present application, the reference point is located at the geometric center of the target wafer, that is, the first reference line and the second reference line are orthogonal to the geometric center of the target wafer, which can match the central symmetry effect in the wafer production process, so that the first reference line and the second reference line evenly divide the target wafer into multiple wafer regions of equal area. In this way, the first angle data and the second angle data are located in different wafer regions, which can match the central symmetry effect in the wafer production process, improve the sampling uniformity of the angle data, and make the obtained average angle offset globally representative, thereby improving the accuracy of the angle offset measurement.

[0063] In some embodiments, the first wafer and the second wafer each include a plurality of chips arranged in an array, and each chip has a wafer alignment mark. Figure 3 , step S200 includes the following step S210.

[0064] S210, select the first chip and the second chip located on both sides of the first baseline on the target wafer, use the wafer alignment mark on the first chip as the first target mark, and use the wafer alignment mark on the second chip as the second target mark; wherein, the number of chips between the first chip and the second chip in a direction parallel to the second baseline and the first baseline is equal, and the number of chips between the first chip and the second chip in a direction parallel to the first baseline and the second baseline is equal.

[0065] In an embodiment of the present application, wafer alignment marks on the first chip and the second chip that are symmetrically positioned on both sides of the first reference line are respectively selected as the first target mark and the second target mark, which can match the central symmetry effect in the wafer production process, so that the positions of the first target mark and the second target mark on the target wafer also have a certain degree of symmetry, thereby improving the sampling uniformity of the angle data and making the angle offset globally representative, thereby improving the accuracy of the angle offset measurement.

[0066] In some embodiments, the first chips of the first wafer and the first chips of the second wafer are located in the same number of rows and columns in the chip array, and the second chips of the first wafer and the second chips are located in the same number of rows and columns in the chip array.

[0067] In the embodiment of the present application, measurement is performed based on the alignment marks on the chips at the same position on the first wafer and the second wafer, so that the data acquisition between the first wafer and the second wafer can be consistent, which is conducive to improving the accuracy of offset determination.

[0068] In some embodiments, see Figure 4 After step S200 , the wafer alignment method further includes the following steps S710 to S740 .

[0069] S710 , respectively acquiring first position data of at least two first target marks and second position data of at least two second target marks.

[0070] S720: Determine a first position offset of the first target mark according to the first position data, and determine a second position offset of the second target mark according to the second position data.

[0071] S730 , determining an average position offset of the corresponding target wafer relative to the wafer machine according to the first position offset and the second position offset.

[0072] S740 , aligning the first wafer and the second wafer according to the average position offset of the first wafer and the average position offset of the second wafer.

[0073] In some embodiments, the first angle data of at least two first target marks are measured and acquired synchronously with the first position data, and the second angle data of at least two second target marks are measured and acquired synchronously with the second position data.

[0074] In the embodiments of the present application, the adverse effects of environmental factors at local locations of the wafer (such as optical signal interference, measurement noise interference, instantaneous environmental fluctuations, etc.) on position data measurement can be eliminated, and the determined average position offset can be globally representative on the corresponding target wafer to match the central symmetry effect in the wafer production process, thereby improving the accuracy of position offset measurement and thus facilitating the improvement of wafer alignment accuracy.

[0075] In some embodiments, the first position offset includes a first lateral position offset in a direction parallel to the first reference line (e.g., the X direction) and a first longitudinal position offset in a direction parallel to the second reference line (e.g., the Y direction); the second position offset includes a second lateral position offset in a direction parallel to the first reference line (e.g., the X direction) and a second longitudinal position offset in a direction parallel to the second reference line (e.g., the Y direction).

[0076] In the embodiment of the present application, respectively obtaining the position offset in two directions (for example, including the X direction and the Y direction) can improve the accuracy and comprehensiveness of the position offset measurement, which is beneficial to improving the wafer alignment accuracy.

[0077] In some embodiments, the wafer alignment method further includes the following step S800 .

[0078] S800 , compensating for angular alignment of the first wafer and the second wafer in the current group according to the average angular offset of the first wafer and the average angular offset of the second wafer in the previous group in accordance with the process sequence.

[0079] In some embodiments, the wafer alignment method further includes the following step S900 .

[0080] S900 , compensating for the position alignment of the first wafer and the second wafer of the current group according to the average position offset of the first wafer and the average position offset of the second wafer of the previous group in accordance with the process sequence.

[0081] In an embodiment of the present application, performing alignment compensation for the current group based on the globally representative average offset determined in the previous group of wafer alignment steps can effectively improve the wafer alignment accuracy in the entire process, thereby improving the wafer product yield.

[0082] It should be understood that although Figures 1 to 4 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figures 1 to 4 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The order of execution of these steps or stages is not necessarily one by one, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0083] In order to more clearly illustrate the wafer alignment method in some of the above embodiments, the following embodiments are combined with Figures 5 to 7 Understand.

[0084] In some embodiments, a wafer alignment method is used to align a first wafer w1 and a second wafer w2 .

[0085] For some examples, see Figure 5 In FIG. 1 , a plurality of first wafer alignment marks S1 are provided on the first wafer w1; see FIG. Figure 5 In FIG. 5( b ), the second wafer w2 has a plurality of second wafer alignment marks S2 .

[0086] Please note that Figure 6 During the alignment process of the first wafer w1 and the second wafer w2, it is necessary to make the first wafer alignment mark S1 and the second wafer alignment mark S2 form a combined pattern, and measure the alignment offset between the first wafer w1 and the second wafer w2 based on the combined pattern.

[0087] For example, the alignment offset includes, but is not limited to, an angle offset and a position offset.

[0088] In some embodiments, a wafer alignment method is used to align a first wafer w1 and a second wafer w2 ; the wafer alignment method includes the following steps S100 - S600 .

[0089] In step S100 , a first wafer w1 and a second wafer w2 are respectively used as target wafers W.

[0090] It should be noted that, in some of the following embodiments, the first wafer w1 and the second wafer w2 need to be used as target wafers W, and steps S200 to S500 need to be performed on the target wafers W, respectively. Figure 7 In the embodiment, the first wafer w1 is used as the target wafer W and the wafer alignment mark is the first wafer alignment mark S1. However, it can be understood that when the second wafer w2 is used as the target wafer W and the wafer alignment mark is the second wafer alignment mark S2, the following embodiments need to be performed. Figure 7 The steps for performing the example are not described here in detail.

[0091] In step S200, at least two wafer alignment marks on the target wafer W located on one side of a first reference line (e.g., the x-axis) are selected as first target marks A1, and at least two wafer alignment marks on the target wafer W located on the other side of the first reference line (e.g., the x-axis) are selected as second target marks A2; wherein, the at least two first target marks A1 are respectively located on both sides of the second reference line (e.g., the y-axis), and the at least two second target marks A2 are respectively located on both sides of the second reference line (e.g., the y-axis); the second reference line (e.g., the y-axis) is orthogonal to the first reference line (e.g., the x-axis).

[0092] In some embodiments, see Figure 5 The first wafer w1 and the second wafer w2 each include a plurality of chips C arranged in an array, and each chip C has a wafer alignment mark. Step S200 includes the following step S210.

[0093] In step S210, the first chip C1 and the second chip C2 located on both sides of a first reference line (e.g., the x-axis) on the target wafer W are selected, and the wafer alignment mark on the first chip C1 is used as the first target mark A1, and the wafer alignment mark on the second chip C2 is used as the second target mark A2; wherein, the number of chips spaced between the first chip C1 and the second chip C2 in a direction parallel to the second reference line (e.g., the y-axis) and the first reference line (e.g., the x-axis) is equal to or as close as possible, and the number of chips spaced between the first chip C1 and the second chip C2 in a direction parallel to the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) is equal to or as close as possible.

[0094] It should be explained that the “number of separated chips” refers to the number of complete chips C in the separation distance between the target mark and the reference line.

[0095] It should be noted that Figure 7 In the example, the number of chips C spaced between the first chip C1 and the second chip C2 in the direction parallel to the second reference line (for example, the y-axis) and the first reference line (for example, the x-axis) is 1, and the number of chips C spaced between the first chip C1 and the second chip C2 in the direction parallel to the first reference line (for example, the x-axis) and the second reference line (for example, the y-axis) is 1; however, it can be understood that the number of spaced chips C can also be other values, and this application does not limit this.

[0096] Please refer to Figure 7 , the number of the first chips C1 may be at least two, and the number of the second chips C2 may be at least two.

[0097] It should be added that in some examples, please continue to refer to Figure 7 , at least two first target marks A1 located on the same side of a first reference line (for example, the x-axis) and respectively on both sides of a second reference line (for example, the y-axis) meet the following conditions: the number of chips C between the at least two first target marks A1 and the first reference line (for example, the x-axis) in a direction parallel to the second reference line (for example, the y-axis) is equal to or as close as possible; the number of chips C between the at least two first target marks A1 and the second reference line (for example, the y-axis) in a direction parallel to the first reference line (for example, the x-axis) is equal to or as close as possible.

[0098] For some examples, see Figure 7 , at least two second target marks A2 located on the same side of the first reference line (for example, the x-axis) and respectively on both sides of the second reference line (for example, the y-axis) meet the following conditions: the number of chips C between the at least two second target marks A2 and the first reference line (for example, the x-axis) in a direction parallel to the second reference line (for example, the y-axis) is equal to or as close as possible; the number of chips C between the at least two second target marks A2 and the second reference line (for example, the y-axis) in a direction parallel to the first reference line (for example, the x-axis) is equal to or as close as possible.

[0099] In some embodiments, the number of rows and columns of each first chip C1 in the first wafer w1 and each first chip C1 in the second wafer w2 in the chip array are the same or as close as possible, and the number of rows and columns of each second chip C2 in the first wafer w1 and each second chip C2 in the second wafer w2 in the chip array are the same or as close as possible.

[0100] In step S300 , first angle data of at least two first target marks A1 and second angle data of at least two second target marks A2 are acquired respectively.

[0101] In some embodiments, step S300 includes the following steps S310 to S320.

[0102] In step S310 , an intersection point of a first reference line (eg, the x-axis) and a second reference line (eg, the y-axis) is determined as a reference point o.

[0103] In step S320, the first angle data is determined based on the angle between the straight line connecting the geometric centers of at least two first target marks A1 and the reference point o and the first reference line (for example, the x-axis), and the second angle data is determined based on the angle between the straight line connecting the geometric centers of at least two second target marks A2 and the reference point o and the first reference line (for example, the x-axis).

[0104] For example, the first angle data can be the angle between the straight line connecting the geometric center of the first target mark A1 and the reference point o and the positive direction of the first reference line (for example, the positive direction of the x-axis), or the angle between the straight line connecting the geometric center of the first target mark A1 and the reference point o and the negative direction of the first reference line (for example, the negative direction of the x-axis). This application does not impose any restrictions on this.

[0105] For example, the second angle data can be the angle between the straight line connecting the geometric center of the second target mark A2 and the reference point o and the positive direction of the first reference line (for example, the positive direction of the x-axis), or the angle between the straight line connecting the geometric center of the second target mark A2 and the reference point o and the negative direction of the first reference line (for example, the negative direction of the x-axis). This application does not impose any restrictions on this.

[0106] It should be noted that the first angle data is the angle between the straight line connecting the geometric centers of at least two first target markers A1 and the reference point o and the first reference line (e.g., the x-axis) in the same direction. The second angle data is the angle between the straight line connecting the geometric centers of at least two second target markers A2 and the reference point o and the first reference line (e.g., the x-axis) in the same direction.

[0107] In some embodiments, the reference point o is located at the geometric center of the target wafer W.

[0108] It should be noted that, in the above embodiment, the first reference line and the second reference line are orthogonal to the reference point o, and the reference point o is located at the geometric center of the target wafer W; the first reference line (e.g., the x-axis) and the second reference line (e.g., the y-axis) can evenly divide the target wafer W into a plurality of sector-shaped areas of equal area. Figure 7 Each first target mark A1 and each second target mark A2 may be located in different sector-shaped areas evenly divided by a first reference line (eg, the x-axis) and a second reference line (eg, the y-axis).

[0109] In step S400 , a first angle offset of the first target mark A1 is determined according to the first angle data, and a second angle offset of the second target mark A2 is determined according to the second angle data.

[0110] In step S500 , an average angular offset of the corresponding target wafer W relative to the wafer tool is determined according to the first angular offset and the second angular offset.

[0111] For example, the average angular offset may be an arithmetic mean between the first angular offset and the second angular offset.

[0112] In step S600 , the first wafer w1 and the second wafer w2 are angularly aligned according to the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 .

[0113] It should be noted that the relationship between the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 can be used to characterize the rotational deviation caused by the relative rotation between the second wafer w2 and the first wafer w1. A specific method for performing angular alignment in step S600 can be: maintaining the angle of the first wafer w1 fixed, and relatively rotating the second wafer w2 based on the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 to compensate for the angular deviation.

[0114] For example, when the average angular offset of the first wafer w1 is equal to the average angular offset of the second wafer w2 , the first wafer w1 and the second wafer w2 are angularly aligned.

[0115] In some embodiments, after step S200 , the wafer alignment method further includes the following steps S710 - S740 .

[0116] It should be noted that in some of the following embodiments, the first wafer w1 and the second wafer w2 are respectively used as the target wafer W, and steps S710 to S740 are respectively performed on the target wafer W. Furthermore, the first target mark A1 and the second target mark A2 in the process of determining the position offset can be selected in step S200 in some of the above embodiments, and are not further described here.

[0117] In step S710 , first position data of at least two first target marks A1 and second position data of at least two second target marks A2 are acquired respectively.

[0118] It should be noted that the first position data and the second position data can be determined based on a rectangular coordinate system established with the first reference line as the x-axis, the second reference line as the y-axis, and the reference point o as the origin.

[0119] For example, the first position data includes a horizontal coordinate value of the first target mark A1 on the x-axis and a vertical coordinate value on the y-axis. The first position data may be (Tx1, Ty1), for example.

[0120] For example, the second position data includes the abscissa value of the second target mark A2 on the x-axis and the ordinate value on the y-axis. The second position data may be (Tx2, Ty2), for example.

[0121] In some embodiments, the first angle data of at least two first target marks A1 are measured and acquired synchronously with the first position data, and the second angle data of at least two second target marks A2 are measured and acquired synchronously with the second position data.

[0122] In step S720 , a first position offset of the first target mark A1 is determined according to the first position data, and a second position offset of the second target mark A2 is determined according to the second position data.

[0123] In some embodiments, the first position offset includes a first lateral position offset in a direction (e.g., X direction) parallel to a first reference line (e.g., x-axis) and a first longitudinal position offset in a direction (e.g., Y direction) parallel to a second reference line (e.g., y-axis); the second position offset includes a second lateral position offset in a direction (e.g., X direction) parallel to the first reference line (e.g., x-axis) and a second longitudinal position offset in a direction (e.g., Y direction) parallel to the second reference line (e.g., y-axis).

[0124] In step S730 , an average position offset of the corresponding target wafer W relative to the wafer tool is determined according to the first position offset and the second position offset.

[0125] For example, the average position offset may be an arithmetic mean between the first position offset and the second position offset.

[0126] For example, the average position offset includes an average transverse position offset and an average longitudinal position offset, wherein the average transverse position offset may be the arithmetic average of the first transverse position offset and the second transverse position offset; and the average longitudinal position offset may be the arithmetic average of the first longitudinal position offset and the second longitudinal position offset.

[0127] In step S740 , the first wafer w1 and the second wafer w2 are aligned according to the average position offset of the first wafer w1 and the average position offset of the second wafer w2 .

[0128] It should be noted that the relationship between the average position offset of the first wafer w1 and the average position offset of the second wafer w2 can be used to characterize the displacement deviation caused by the relative displacement between the second wafer w2 and the first wafer w1. The specific method of performing position alignment in step S740 can be: keeping the position of the first wafer w1 fixed, and relatively shifting the second wafer w2 based on the average position offset of the first wafer w1 and the average position offset of the second wafer w2 to compensate for the position deviation.

[0129] For example, when the average position offset of the first wafer w1 is equal to the average position offset of the second wafer w2 , the first wafer w1 and the second wafer w2 are aligned.

[0130] In some embodiments, the wafer alignment method further includes the following step S800 .

[0131] In step S800 , according to the process sequence, the angular alignment of the first wafer w1 and the second wafer w2 of the current group is compensated based on the average angular offset of the first wafer w1 and the average angular offset of the second wafer w2 of the previous group.

[0132] In some embodiments, the wafer alignment method further includes the following step S900 .

[0133] In step S900 , according to the process sequence, the position alignment of the first wafer w1 and the second wafer w2 of the current group is compensated based on the average position offset of the first wafer w1 and the average position offset of the second wafer w2 of the previous group.

[0134] In some examples, the compensation processes in step S800 and step S900 can both be performed by feeding back the offset to an advanced process control (APC) system, and the APC system can perform wafer alignment compensation based on the offset.

[0135] The present application also provides a wafer bonding method according to some embodiments, which includes the wafer alignment method in some of the above embodiments. The wafer bonding method also has the technical advantages of the above wafer alignment method. It should be noted that for the parts that are the same or corresponding to the above embodiments, reference can be made to the corresponding description of the above embodiments, and will not be described in detail below.

[0136] In some embodiments, the wafer bonding method includes the following steps S001 to S003 .

[0137] S001, providing a first wafer and a second wafer.

[0138] In some examples, step S001 includes: fixing a first wafer on a first chuck of a wafer bonding machine; fixing a second wafer on a second chuck of the wafer bonding machine; wherein the front side of the first wafer and the front side of the second wafer are relatively close.

[0139] Illustratively, the front side of the first wafer faces vertically upward, and the front side of the second wafer faces vertically downward.

[0140] S002 , aligning the second wafer and the first wafer using the wafer alignment method described in some of the aforementioned embodiments of the present application.

[0141] S003, bonding the aligned second wafer to the first wafer.

[0142] The wafer bonding method in the embodiment of the present application can match the central symmetry effect in the wafer production process during wafer alignment, determine at least two sets of offsets that are globally representative, which is beneficial to improving the wafer alignment accuracy, thereby facilitating high-precision bonding of wafers and effectively improving the product yield of the wafer bonding process.

[0143] In the description of this specification, reference to the terms "some embodiments," "some examples," "exemplarily," etc., means that a specific feature, structure, material, or characteristic described in conjunction with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0144] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art may make various modifications and improvements without departing from the scope of the present application, and such modifications and improvements are all within the scope of protection of the present application.

Claims

1. A wafer alignment method, characterized in that: Used to align the first wafer and the second wafer; The wafer alignment method comprises: taking the first wafer and the second wafer as target wafers respectively; At least two wafer alignment marks on the target wafer located on one side of a first reference line are selected as first target marks, and at least two wafer alignment marks on the target wafer located on the other side of the first reference line are selected as second target marks; wherein at least two of the first target marks are respectively located on either side of a second reference line, and at least two of the second target marks are respectively located on either side of the second reference line; and the second reference line is orthogonal to the first reference line; Determine an intersection of the first reference line and the second reference line as a reference point; Determine first angle data of the first target mark based on an angle between a straight line connecting the geometric centers of at least two of the first target marks and the reference point and the first reference line, and determine second angle data of the second target mark based on an angle between a straight line connecting the geometric centers of at least two of the second target marks and the reference point and the first reference line; determining a first angular offset of the first target mark according to the first angular data, and determining a second angular offset of the second target mark according to the second angular data; Determine an average angular offset of the corresponding target wafer relative to the wafer machine according to the first angular offset and the second angular offset; Angle alignment between the first wafer and the second wafer is performed according to an average angular offset of the first wafer and an average angular offset of the second wafer.

2. The wafer alignment method according to claim 1, wherein: The first angle data is the angle between the straight line connecting the geometric centers of at least two of the first target marks and the reference point and the first reference line in the same direction; the second angle data is the angle between the straight line connecting the geometric centers of at least two of the second target marks and the reference point and the first reference line in the same direction.

3. The wafer alignment method according to claim 1, wherein: The reference point is located at the geometric center of the target wafer.

4. The wafer alignment method according to claim 1, wherein: The first wafer and the second wafer each include a plurality of chips arranged in an array, each of the chips having the wafer alignment mark; the step of selecting at least two wafer alignment marks on one side of a first reference line on the target wafer as first target marks, and selecting at least two wafer alignment marks on the other side of the first reference line on the target wafer as second target marks, comprises: Select the first chip and the second chip on the target wafer, which are respectively located on both sides of the first reference line, and use the wafer alignment mark on the first chip as the first target mark, and use the wafer alignment mark on the second chip as the second target mark; wherein, the number of chips between the first chip and the second chip in a direction parallel to the second reference line and the first reference line is equal, and the number of chips between the first chip and the second chip in a direction parallel to the first reference line and the second reference line is equal.

5. The wafer alignment method according to claim 4, wherein: The first chips of the first wafer and the first chips of the second wafer are located in the same number of rows and columns in the chip array, and the second chips of the first wafer and the second chips are located in the same number of rows and columns in the chip array.

6. The wafer alignment method according to claim 1, wherein: After selecting at least two wafer alignment marks on the target wafer located on one side of the first reference line as first target marks, and selecting at least two wafer alignment marks on the target wafer located on the other side of the first reference line as second target marks, the wafer alignment method further includes: respectively acquiring first position data of at least two of the first target marks and second position data of at least two of the second target marks; determining a first position offset of the first target mark according to the first position data, and determining a second position offset of the second target mark according to the second position data; Determine an average position offset of the corresponding target wafer relative to the wafer machine according to the first position offset and the second position offset; Position alignment between the first wafer and the second wafer is performed based on an average position shift of the first wafer and the average position shift of the second wafer.

7. The wafer alignment method according to claim 6, wherein: The first position offset includes a first lateral position offset in a direction parallel to the first reference line and a first longitudinal position offset in a direction parallel to the second reference line; the second position offset includes a second lateral position offset in a direction parallel to the first reference line and a second longitudinal position offset in a direction parallel to the second reference line.

8. The wafer alignment method according to claim 6, wherein: The first angle data of at least two of the first target marks are measured and acquired synchronously with the first position data, and the second angle data of at least two of the second target marks are measured and acquired synchronously with the second position data.

9. The wafer alignment method according to claim 1, wherein: Also includes: According to the process sequence, the angular alignment of the first wafer and the second wafer of the current group is compensated based on the average angular offset of the first wafer and the average angular offset of the second wafer of the previous group.

10. A wafer bonding method, characterized in that: include: providing a first wafer and a second wafer; Aligning the second wafer with the first wafer using the wafer alignment method according to any one of claims 1 to 9; The aligned second wafer and the first wafer are bonded together.

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