ADC Circuit and Its Control Method

Abstract

The present application provides an ADC circuit and a control method thereof. The ADC circuit includes a multi-stage SAR analog-to-digital converter and a multi-stage residual processing circuit. Each stage of the residual processing circuit is located between two adjacent stages of the SAR analog-to-digital converter and includes a residual sampling circuit and a residual amplification circuit. The residual sampling circuit and the residual amplification circuit are both single-channel circuits. The residual sampling circuit is implemented using a passive charge sharing method, and the residual amplification circuit is implemented using an active operational amplifier. In each sampling and conversion cycle of the ADC circuit, the residual sampling circuit and the residual amplification circuit perform residual sampling and residual amplification on the residual signal output by the previous stage SAR analog-to-digital converter. While the residual amplification circuit amplifies the residual signal output by the previous stage SAR analog-to-digital converter and the next stage SAR analog-to-digital converter performs sampling, the previous stage SAR analog-to-digital converter is used to perform the next sampling. The present application can improve the ADC conversion rate.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to an ADC circuit and a control method thereof. Background Art

[0002] A SAR ADC (Successive Approximation Register Analog to Digital Converter) is a circuit that converts analog signals into digital signals. It uses a binary search algorithm to obtain N bits of data corresponding to the analog signal. Typically, an N-bit SAR ADC requires at least N comparisons to obtain a complete digital output. Therefore, the conversion speed of a SAR ADC is limited by its successive approximation algorithm, making it unsuitable for high-speed applications. However, SAR ADCs offer the advantages of low power consumption, simple algorithms, and small size. To achieve higher speeds, one solution combines the SAR ADC with the architecture of a pipeline ADC, creating a pipeline SAR ADC (pipeline successive approximation register analog-to-digital converter). This achieves high speed and high accuracy while maintaining the advantages of low power consumption, simple algorithms, and small size. Since the Pipeline SAR ADC replaces the flash sub-stage ADC in the Pipeline ADC with a SAR ADC, and the SAR ADC used can have a higher bit number, the number of cascades is much smaller than that of the Pipeline ADC, usually two to four stages.

[0003] However, because Pipeline SAR ADCs require inter-stage operational amplifiers, in existing Pipeline SAR ADCs, the first-stage SAR ADC must wait for the completion of the residual amplification and second-stage SAR ADC sampling phases before it can sample the next input signal. As a result, the conversion rate of the Pipeline SAR ADC is limited, resulting in a slow conversion rate. Summary of the Invention

[0004] The purpose of this application is to provide an ADC circuit and a control method thereof, which can solve at least one technical problem mentioned in the above-mentioned prior art.

[0005] One aspect of the present application provides an ADC circuit. The ADC circuit includes a multi-stage SAR analog-to-digital converter and a multi-stage residual processing circuit. Each stage of the residual processing circuit is located between two adjacent stages of the SAR analog-to-digital converter; each stage of the residual processing circuit includes a residual sampling circuit and a residual amplification circuit connected to the output end of the residual sampling circuit. The residual sampling circuit and the residual amplification circuit are both single-channel circuits. The residual sampling circuit is implemented using a passive charge sharing method, and the residual amplification circuit is implemented using an active operational amplifier. During each sampling and conversion cycle of the ADC circuit, the residual sampling circuit and the residual amplification circuit perform residual sampling and residual amplification on the residual signal output by the previous stage of the SAR analog-to-digital converter. While the residual amplification circuit amplifies the residual signal output by the previous stage of the SAR analog-to-digital converter and the next stage of the SAR analog-to-digital converter performs sampling, the previous stage of the SAR analog-to-digital converter is used to perform the next sampling.

[0006] Furthermore, the residue sampling circuit includes a first sampling capacitor and a second sampling capacitor, and the residue signal includes a positive residue signal and a negative residue signal. In the residue sampling phase, the first plate and the second plate of the first sampling capacitor are connected to the positive residue signal and the negative residue signal, respectively; the first plate and the second plate of the second sampling capacitor are also connected to the positive residue signal and the negative residue signal, respectively.

[0007] Furthermore, the residue sampling circuit includes a first positive-end switch, a second positive-end switch, a first negative-end switch, and a second negative-end switch, wherein the first plate of the first sampling capacitor is connected to the positive residue signal through the first positive-end switch; the second plate of the first sampling capacitor is connected to the negative residue signal through the second positive-end switch; the first plate of the second sampling capacitor is connected to the positive residue signal through the first negative-end switch; and the second plate of the second sampling capacitor is connected to the negative residue signal through the second negative-end switch.

[0008] Furthermore, when entering the residual sampling stage, the first positive end switch, the second positive end switch, the first negative end switch and the second negative end switch are switched from the open state to the closed state; after completing the charge sharing process, the first positive end switch, the second positive end switch, the first negative end switch and the second negative end switch are switched from the closed state to the open state.

[0009] Furthermore, the residual sampling circuit further includes a third positive switch, a fourth positive switch, a fifth positive switch, a third negative switch, a fourth negative switch, and a fifth negative switch, wherein a first end of the third positive switch is connected to a reference voltage, a second end of the third positive switch is connected to the second plate of the first sampling capacitor and is connected to the first plate of the first sampling capacitor through the fifth positive switch; two ends of the fourth positive switch are respectively connected to the first plate of the first sampling capacitor and the positive output end of the residual sampling circuit; a first end of the third negative switch is connected to the reference voltage, a second end of the third negative switch is connected to the first plate of the second sampling capacitor and is connected to the second plate of the second sampling capacitor through the fifth negative switch; and two ends of the fourth negative switch are respectively connected to the second plate of the second sampling capacitor and the negative output end of the residual sampling circuit.

[0010] Furthermore, when entering the residual sampling phase, the fifth positive-end switch and the fifth negative-end switch are switched from a closed state to an open state.

[0011] Furthermore, the residue amplification circuit includes an operational amplifier, a first feedback capacitor, a second feedback capacitor, a sixth positive terminal switch and a sixth negative terminal switch, wherein the operational amplifier has a positive input terminal, a negative input terminal, a positive amplification output terminal and a negative amplification output terminal, the positive input terminal of the operational amplifier is connected to the positive output terminal of the residue sampling circuit, and the negative input terminal of the operational amplifier is connected to the negative output terminal of the residue sampling circuit; the first feedback capacitor and the sixth positive terminal switch are both connected in parallel between the positive input terminal and the negative amplification output terminal of the operational amplifier; the second feedback capacitor and the sixth negative terminal switch are both connected in parallel between the negative input terminal and the positive amplification output terminal of the operational amplifier.

[0012] Furthermore, when entering the residual amplification stage, the third positive end switch, the fourth positive end switch, the third negative end switch and the fourth negative end switch are switched from the open state to the closed state, and the sixth positive end switch and the sixth negative end switch are switched from the closed state to the open state.

[0013] Furthermore, when the SAR analog-to-digital converter at the next stage completes sampling of the residual amplified signal, the third positive-end switch, the fourth positive-end switch, the third negative-end switch, and the fourth negative-end switch are disconnected, and the fifth positive-end switch, the fifth negative-end switch, the sixth positive-end switch, and the sixth negative-end switch are switched from an open state to a closed state.

[0014] Furthermore, each stage of the SAR analog-to-digital converter includes a positive-end switch array, a negative-end switch array, a positive-end capacitor array, a negative-end capacitor array, a positive-end top plate switch, a negative-end top plate switch, a comparator, and a SAR control module, wherein the first plate of the positive-end capacitor array is connected to the positive input of the comparator and is connected to the reference voltage through the positive-end top plate switch; the second plate of the positive-end capacitor array is selectively connected to the positive differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the positive-end switch array; the first plate of the negative-end capacitor array is connected to the negative input of the comparator and is connected to the reference voltage through the negative-end top plate switch; the second plate of the negative-end capacitor array is selectively connected to the negative differential input signal, the reference voltage, the positive reference voltage, and the negative reference voltage through the negative-end switch array; the output of the comparator is connected to the SAR control module; the SAR control module is used to control the positive-end switch array and the negative-end switch array, and output a conversion end signal and a digital code of the corresponding stage.

[0015] Furthermore, when the SAR analog-to-digital converter of a certain level enters the sampling phase, the positive-end upper plate switch and the negative-end upper plate switch in the SAR analog-to-digital converter of this level are closed, and at the same time, the second plate of the positive-end capacitor array in the SAR analog-to-digital converter of this level is connected to the positive input signal through the positive-end switch array in the SAR analog-to-digital converter of this level, and the second plate of the negative-end capacitor array in the SAR analog-to-digital converter of this level is connected to the negative input signal through the negative-end switch array in the SAR analog-to-digital converter of this level, wherein, for the first-level SAR analog-to-digital converter, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal; for all levels except the first level, For the SAR analog-to-digital converters at other stages, the positive input signal includes the positive residual amplified signal output by the residual amplification circuit at the previous stage, and the negative input signal includes the negative residual amplified signal output by the residual amplification circuit at the previous stage; after a predetermined sampling stabilization time, the positive-end upper plate switch and the negative-end upper plate switch in the SAR analog-to-digital converter at this stage are switched from a closed state to an open state, and the second plate of the positive-end capacitor array in the SAR analog-to-digital converter at this stage is connected to the reference voltage through the positive-end switch array in the SAR analog-to-digital converter at this stage, and the second plate of the negative-end capacitor array in the SAR analog-to-digital converter at this stage is connected to the reference voltage through the negative-end switch array in the SAR analog-to-digital converter at this stage.

[0016] Furthermore, the ADC circuit also includes a redundant calibration and data processing circuit, wherein the output end of each level of the SAR analog-to-digital converter is connected to the redundant calibration and data processing circuit, and the redundant calibration and data processing circuit is used to ultimately output the digital code of the ADC circuit.

[0017] Another aspect of the present application provides a control method for an ADC circuit. The ADC circuit includes a multi-stage SAR analog-to-digital converter and a multi-stage residual processing circuit, wherein each stage of the residual processing circuit is located between two adjacent stages of the SAR analog-to-digital converter. Each stage of the residual processing circuit includes a residual sampling circuit and a residual amplification circuit connected to the output end of the residual sampling circuit. Both the residual sampling circuit and the residual amplification circuit are single-channel circuits. The method includes: during each sampling and conversion cycle of the ADC circuit, controlling the residual sampling circuit and the residual amplification circuit to perform residual sampling and residual amplification on the residual signal output by the previous stage of the SAR analog-to-digital converter, respectively; and controlling the previous stage of the SAR analog-to-digital converter to perform the next sampling while the residual amplification circuit amplifies the residual signal output by the previous stage of the SAR analog-to-digital converter and the next stage of the SAR analog-to-digital converter is sampling.

[0018] Furthermore, the residue sampling circuit includes a first sampling capacitor and a second sampling capacitor, and the residue signal includes a positive residue signal and a negative residue signal. The method further includes: when entering the residue sampling phase, controlling the first plate and the second plate of the first sampling capacitor to be connected to the positive residue signal and the negative residue signal output by the previous-stage SAR analog-to-digital converter, respectively; and controlling the first plate and the second plate of the second sampling capacitor to be connected to the positive residue signal and the negative residue signal output by the previous-stage SAR analog-to-digital converter, respectively.

[0019] Furthermore, the residual amplification circuit includes an operational amplifier, a first feedback capacitor, and a second feedback capacitor. The method further includes: when entering the residual amplification stage, controlling the second plate of the first sampling capacitor and the first plate of the second sampling capacitor to be connected to a reference voltage; connecting the first plate of the first sampling capacitor and the second plate of the second sampling capacitor to the positive input terminal and the negative input terminal of the operational amplifier, respectively; and controlling the positive input terminal of the operational amplifier to be connected to the negative amplification output terminal of the operational amplifier through the first feedback capacitor; and connecting the negative input terminal of the operational amplifier to the positive amplification output terminal of the operational amplifier through the second feedback capacitor.

[0020] Furthermore, the method further includes: when the SAR analog-to-digital converter at the next stage completes sampling of the residue amplification signal output by the residue amplification circuit, controlling to short-circuit both ends of the first sampling capacitor, both ends of the second sampling capacitor, both ends of the first feedback capacitor, and both ends of the second feedback capacitor.

[0021] Furthermore, each stage of the SAR analog-to-digital converter includes a positive-end switch array, a negative-end switch array, a positive-end capacitor array, and a negative-end capacitor array. The method further includes: when the SAR analog-to-digital converter of a certain stage enters a sampling phase, by controlling the positive-end switch array and the negative-end switch array in the SAR analog-to-digital converter of the stage, the positive input signal and the negative input signal are connected to the second plate of the positive-end capacitor array and the second plate of the negative-end capacitor array in the SAR analog-to-digital converter of the stage, respectively; and controlling the first plate of the positive-end capacitor array and the first plate of the negative-end capacitor array in the SAR analog-to-digital converter of the stage to be connected to a reference voltage, wherein, for the first stage of the SAR analog-to-digital converter, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal. input signal; for the SAR analog-to-digital converters of other stages except the first stage, the positive input signal includes the positive residual amplified signal output by the residual amplification circuit of the previous stage, and the negative input signal includes the negative residual amplified signal output by the residual amplification circuit of the previous stage; after a predetermined sampling stabilization time, controlling the first plate of the positive terminal capacitor array and the first plate of the negative terminal capacitor array in the SAR analog-to-digital converter of the stage to be disconnected from the reference voltage; and controlling the positive input signal and the negative input signal to be disconnected from the second plate of the positive terminal capacitor array and the second plate of the negative terminal capacitor array in the SAR analog-to-digital converter of the stage, and connecting the second plate of the positive terminal capacitor array and the second plate of the negative terminal capacitor array in the SAR analog-to-digital converter of the stage to the reference voltage.

[0022] By introducing a residual sampling circuit, the ADC circuit and control method thereof in one or more embodiments of the present application can simultaneously perform the next sampling of the input signal by the preceding SAR ADC during the residual amplification and subsequent SAR ADC sampling phases. This fully utilizes the advantages of pipeline operation and significantly improves the conversion rate of the ADC circuit. Furthermore, for the same conversion rate requirement, the ADC circuit structure of the present application can appropriately increase the time required for the residual amplification and sampling phases, thereby reducing the requirements for the switch size and bandwidth of the operational amplifier in the circuit, thereby reducing design difficulty and cost.

[0023] In addition, the ADC circuit and control method thereof in one or more embodiments of the present application introduce a residual sampling circuit, so that the input common-mode voltage of the operational amplifier is always equal to the reference voltage during residual amplification, and does not depend on the residual signal output by the previous-stage SAR ADC. Therefore, the previous-stage SAR ADC can flexibly adopt other timing architectures. Even if a VCM-based timing architecture is not adopted, such as a monotonic timing architecture with a smaller area and lower power consumption, it can still be ensured that the common-mode input voltage input to the operational amplifier in the residual amplification circuit is constant at the reference voltage, thereby reducing the design difficulty of the operational amplifier and improving the flexibility of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The figure is a block diagram of the overall structure of a two-stage pipeline SAR ADC in the related art.

[0025] Figure 2 for Figure 1 An implementation circuit diagram of a two-stage Pipeline SAR ADC is shown in FIG.

[0026] Figure 3 for Figure 2 The working timing diagram of the two-stage Pipeline SAR ADC is shown in FIG.

[0027] Figure 4 This is an overall structural block diagram of a two-stage Pipeline SAR ADC according to an embodiment of the present application.

[0028] Figure 5 for Figure 4 An implementation circuit diagram of a two-stage Pipeline SAR ADC is shown in FIG.

[0029] Figure 6 for Figure 5 The working timing diagram of the two-stage Pipeline SAR ADC is shown in FIG.

[0030] Figure 7 This is a flow chart of a method for controlling an ADC circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0031] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of devices consistent with certain aspects of the present application, as detailed in the appended claims.

[0032] Figure 1 The overall structural block diagram of a two-stage Pipeline SAR ADC 100 in the related art is disclosed. Figure 1 As shown, the two-stage Pipeline SAR ADC 100 includes a first-stage M-bit SAR ADC (referred to as the first-stage SAR ADC 111), a residual amplifier circuit 130, a second-stage L-bit SAR ADC (referred to as the second-stage SAR ADC 112), and a redundancy calibration and data processing circuit 140. The first-stage M-bit SAR ADC samples and quantizes the input signal (VINP-VINN) to generate a first-stage M-bit digital code D1. <m-1:0>The residual amplifier circuit 130 amplifies the residual signal (VP1-VN1) output by the first-stage M-bit SAR ADC to generate an amplified signal, namely the residual amplified signal (VOP-VON). The second-stage L-bit SAR ADC samples and quantizes the residual amplified signal (VOP-VON) output by the residual amplifier circuit 130 to generate the second-stage L-bit digital code D2. <l-1:0>Finally, the final N-bit quantized data Dout is generated through the redundancy calibration and data processing circuit 140. <n-1:0>Usually, 1 bit of redundancy is required in the design, that is, M+L=N+1, and the amplification factor of the residual amplifier circuit 130 is designed to be For example, for a 14-bit two-stage Pipeline SAR ADC 100, the first-stage SAR ADC 111 can be designed to be 7-bit, the second-stage SAR ADC 112 can be designed to be 8-bit, and the amplification factor of the residual amplifier circuit 130 can be .

[0033] Figure 2 Revealed Figure 1 An implementation circuit diagram of a two-stage Pipeline SAR ADC 100 is shown, in which both the first-stage and the second-stage SAR ADC 112 adopt a VCM-Based timing architecture as an example; Figure 3 Revealed Figure 2 The working timing diagram of the two-stage Pipeline SAR ADC 100 is shown in FIG. Figure 2 and Figure 3 The working principle of the two-stage Pipeline SAR ADC 100 is described in detail using a fully differential form as an example.

[0034] The first-stage SAR ADC 111 sampling phase (duration t1): by controlling the first-stage positive terminal (P-terminal) switch array and the first-stage negative terminal (N-terminal) switch array, the positive differential input signal VINP and the negative differential input signal VINN are connected to the second plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N, respectively. At the same time, the first plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N are connected to the reference voltage by controlling the first-stage positive terminal upper plate switch SW1P and the first-stage negative terminal upper plate switch SW1N. VCM is used to sample the input signal. After a certain sampling stabilization time, the first-stage positive-end upper plate switch SW1P and the first-stage negative-end upper plate switch SW1N are controlled to be disconnected, and the positive differential input signal VINP and the negative differential input signal VINN are disconnected from the second plates of the first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N, respectively. At this time, the sampling of the input signal is completed (the information of the input signal V1 is sampled into the first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N).

[0035] First-stage SAR ADC 111 conversion phase (duration t2): The conversion end signal EOC_1 output by the first-stage SAR control (SAR CTRL1) module changes from high to low, indicating that the first-stage SAR ADC 111 enters the conversion phase. According to the binary search algorithm, the SAR CTRL1 module controls the switching of the first-stage positive switch array and the first-stage negative switch array, and controls the signal connected to the second electrode plate of the first-stage positive switch array CDAC1_P and the first-stage negative switch array CDAC1_N, thereby quantizing the sampled signal in a successive approximation manner. Finally, the conversion end signal EOC_1 changes from low to high, indicating that the conversion of the first-stage SAR ADC 111 is completed. At this time, the residual signal (VP1-VN1) will be generated, and the first-stage digital code D1_1 will be generated and output. <m-1:0>.

[0036] Residual amplification and second-stage SAR ADC 112 sampling phase (duration t3): By controlling the first positive-end switch SW11P and the first negative-end switch SW11N to be closed, and the sixth positive-end switch SW41P and the sixth negative-end switch SW41N to be open, the operational amplifier AMP amplifies the residual signal (VP1-VN1) to generate a residual amplified signal (VOP-VON). Simultaneously, by controlling the second-stage positive-end switch array and the second-stage negative-end switch array, the positive residual amplified signal VOP and the negative residual amplified signal VON are connected to the second plates of the second-stage positive-end capacitor array CDAC2_P and the second-stage negative-end capacitor array CDAC2_N, respectively. The first plates of the second-stage positive-end capacitor array CDAC2_P and the second-stage negative-end capacitor array CDAC2_N are connected to the reference voltage VCM by controlling the second-stage positive-end top plate switch SW2P and the second-stage negative-end top plate switch SW2N, thereby implementing the second-stage SAR ADC. After a certain period of amplification and sampling stabilization time, the second-stage positive-end top plate switch SW2P, the second-stage negative-end top plate switch SW2N, the first positive-end switch SW11P, and the first negative-end switch SW11N are disconnected. The positive-end amplified residual signal VOP and the negative-end amplified residual signal VON are disconnected from the second plates of the second-stage positive-end capacitor array CDAC2_P and the second-stage negative-end capacitor array CDAC2_N, respectively. At this point, the residual amplification and the sampling of the residual amplified signal by the second-stage SAR ADC 112 are completed.

[0037] Second-stage SAR ADC 112 conversion phase (duration t4): The conversion end signal EOC_2 output by the second-stage SAR control (SAR CTRL2) module changes from high to low, indicating that the second-stage SAR ADC 112 enters the conversion phase. According to the binary search algorithm, the second-stage SAR ADC 112 controls the switching of the second-stage positive-end switch array and the second-stage negative-end switch array through the SAR CTRL2 module to achieve quantization of the sampled signal in a successive approximation manner. Finally, the conversion end signal EOC_2 changes from low to high, indicating that the second-stage SAR ADC 112 conversion is completed. At this time, the second-stage digital code D2_1 is generated and output. <l-1:0>.

[0038] N-bit quantized data Dout <n-1:0>Generation stage: The redundancy calibration and data processing circuit 140 processes the first-level digital code D1_1 <m-1:0>and the second-level digital code D2_1 <l-1:0>After alignment addition and correction of fixed offset, the final N-bit quantized data (i.e., N-bit digital code) Dout1 is output. <n-1:0>, this N-bit quantized data corresponds to the input signal V1.

[0039] from Figure 3 It can also be seen from the timing diagram that, while the second-stage SAR ADC 112 is performing the conversion phase described above, the first-stage SAR ADC 111 can perform the next sampling of the input signal (sampling the input signal V2), reflecting the characteristics of pipeline operation. Figure 3 The digital code Dout2 <n-1:0>The first level digital code D1_2 <m-1:0>and the second-level digital code D2_2 <l-1:0>The N-bit quantized data corresponding to the input signal V2 is obtained after performing aligned addition and correcting the fixed offset.

[0040] Typically, the number of bits of the first-stage SAR ADC 111 and the second-stage SAR ADC 112 are designed to be approximately equal. For example, for a 14-bit two-stage Pipeline SAR ADC 100, the first-stage SAR ADC 111 can be designed to be 7 bits and the second-stage SAR ADC 112 can be designed to be 8 bits. Figure 3 The time t2 is approximately equal to the time t4. At the same time, since the residual amplification needs to be performed by the active operational amplifier AMP to amplify the small signal, a longer time is required to achieve the required accuracy. Figure 3 Based on the above analysis, it can be seen that the maximum conversion rate (i.e., Dout) of the two-stage Pipeline SAR ADC 100 is <n-1:0>Data update speed) ,See Figure 3 Tconv is determined by time t1+t3+t4, .

[0041] The two-stage Pipeline SAR ADC 100 of the related art has the following two main disadvantages:

[0042] First, the first-stage SAR ADC 111 must wait for the residual amplification and the second-stage SAR ADC 112 sampling phase to complete before sampling the next input signal. Figure 3 As shown, when the first-stage SAR ADC 111 samples the input voltage V2, it must do so after the operational amplifier AMP completes amplification of the previous residual signal (the residual signal generated after quantizing the input voltage V1). This is because the operational amplifier AMP requires the charge stored on the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N (including the residual voltage VP1-VN1) for amplification. Only after the amplification is completed and the second-stage SAR ADC 112 sampling phase is completed, the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N of the first-stage SAR ADC 111 can be released for sampling the new input signal. This will cause the two-stage Pipeline SAR ADC 100 in the related art to have a limited conversion rate. Maximum conversion rate , determined by the time t1+t3+t4, where t1 is the sampling phase of the first-stage SAR ADC 111, t3 is the residual amplification and sampling phase of the second-stage SAR ADC 112, and t4 is the conversion phase of the second-stage SAR ADC 112. To achieve a certain conversion rate, these three times must be compressed, resulting in larger switches in the circuit and higher bandwidth requirements for the operational amplifier AMP, increasing design difficulty and cost.

[0043] Second, during the residual amplification, the first positive-side switch SW11P and the first negative-side switch SW11N are closed, while the sixth positive-side switch SW41P and the sixth negative-side switch SW41N are opened. The operational amplifier AMP amplifies the residual signal (VP1-VN1) to generate the amplified residual signal (VOP-VON). At this time, the positive residual signal VP1 and the negative residual signal VN1 are connected to the positive input and negative input of the operational amplifier AMP, respectively. This places high demands on the common-mode input voltage range of the operational amplifier AMP. If the first-stage SAR ADC 111 does not adopt a VCM-based timing architecture, such as a monotonic timing architecture with a smaller area and lower power consumption, the common-mode voltage of the positive residual signal VP1 and the negative residual signal VN1 will vary from VCM to 0V, thereby increasing the design difficulty of the operational amplifier AMP.

[0044] In view of this, the present application proposes an improved ADC circuit, which can solve at least one of the technical problems mentioned in the above related technologies.

[0045] The ADC circuit and control method of the present application will be described in detail below with reference to the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0046] The present application provides an ADC circuit. The ADC circuit includes a multi-stage SAR analog-to-digital converter (SAR ADC) and a multi-stage residual processing circuit. Each stage of the residual processing circuit is located between two adjacent stages of the SAR ADC; each stage of the residual processing circuit includes a residual sampling circuit 220 and a residual amplification circuit 230 connected to the output end of the residual sampling circuit 220. The residual sampling circuit 220 and the residual amplification circuit 230 are both single-channel circuits. The residual sampling circuit 220 is implemented using a passive charge sharing method, while the residual amplification circuit 230 is implemented using an active operational amplifier. During each sampling and conversion cycle of the ADC circuit, the single-channel residual sampling circuit 220 and the single-channel residual amplification circuit 230 perform residual sampling and residual amplification on the residual signal output by the previous stage of the SAR ADC.

[0047] In some embodiments, the ADC circuit of the present application further includes a redundant calibration and data processing circuit 240. The output of each stage of the SAR analog-to-digital converter is connected to the redundant calibration and data processing circuit 240, which is used to ultimately output the digital code of the ADC circuit.

[0048] The following description will be made by taking the ADC circuit of the present application including a two-stage Pipeline SAR ADC 200 and a fully differential form as an example.

[0049] Figure 4 The overall structural block diagram of the two-stage Pipeline SAR ADC 200 of an embodiment of the present application is disclosed. Figure 4 As shown, a two-stage pipeline SAR ADC 200 according to an embodiment of the present application includes a first-stage M-bit SAR ADC (referred to as the first-stage SAR ADC 211), a residual sampling circuit 220, a residual amplification circuit 230, a second-stage L-bit SAR ADC (referred to as the second-stage SAR ADC 212), and a redundancy calibration and data processing circuit 240. The first-stage M-bit SAR ADC samples and quantizes the differential input signal (VINP-VINN) to generate a first-stage M-bit digital code D1. <m-1:0>The residual sampling circuit 220 samples the residual signals VP1-VN1 and stores the information in the sampling capacitor. The residual amplifier circuit 230 amplifies the residual signals stored in the sampling capacitor to generate the amplified residual signals (VOP-VON). The second-stage L-bit SAR ADC samples and quantizes the amplified residual signals (VOP-VON) output by the residual amplifier circuit 230 to generate the second-stage L-bit digital code D2. <l-1:0>Finally, the redundancy calibration and data processing circuit 240 generates the final N-bit quantized data Dout. <n-1:0>.

[0050] Figure 5 Revealed Figure 4 The circuit diagram of a two-stage pipeline SAR ADC 200 is shown, in which a first-stage SAR ADC 211 and a second-stage SAR ADC 212 are both implemented using a VCM-based sequential architecture as an example. It is understood that the first-stage SAR ADC 211 and the second-stage SAR ADC 212 of the present application can also be implemented using other SAR ADC architectures, such as a monotonic sequential architecture with a smaller area and lower power consumption. This application is not limited to this.

[0051] like Figure 5 As shown, the residue sampling circuit 220 of the present application includes a first sampling capacitor CSP and a second sampling capacitor CSN, and the residue signal includes a positive residue signal VP1 and a negative residue signal VN1.

[0052] During the residual sampling phase, the first plate and the second plate of the first sampling capacitor CSP are connected to the positive residual signal VP1 and the negative residual signal VN1 respectively; the first plate and the second plate of the second sampling capacitor CSN are also connected to the positive residual signal VP1 and the negative residual signal VN1 respectively.

[0053] In some embodiments, the residual sampling circuit 220 of the present application includes a first positive-side switch S11P, a second positive-side switch S12P, a first negative-side switch S11N, and a second negative-side switch S12N. The first plate of the first sampling capacitor CSP is connected to the positive residual signal VP1 via the first positive-side switch S11P; the second plate of the first sampling capacitor CSP is connected to the negative residual signal VN1 via the second positive-side switch S12P; the first plate of the second sampling capacitor CSN is connected to the positive residual signal VP1 via the first negative-side switch S11N; and the second plate of the second sampling capacitor CSN is connected to the negative residual signal VN1 via the second negative-side switch S12N.

[0054] When entering the residual sampling stage, the first positive-end switch S11P, the second positive-end switch S12P, the first negative-end switch S11N and the second negative-end switch S12N are switched from the open state to the closed state; after completing the charge sharing process, the first positive-end switch S11P, the second positive-end switch S12P, the first negative-end switch S11N and the second negative-end switch S12N are switched from the closed state to the open state.

[0055] In some embodiments, the residual sampling circuit 220 of the present application further includes a third positive switch S21P, a fourth positive switch S22P, a fifth positive switch R31P, a third negative switch S21N, a fourth negative switch S22N, and a fifth negative switch R31N. A first end of the third positive-end switch S21P is connected to the reference voltage VCM, a second end of the third positive-end switch S21P is connected to the second plate of the first sampling capacitor CSP and is connected to the first plate of the first sampling capacitor CSP through a fifth positive-end switch R31P; two ends of the fourth positive-end switch S22P are connected to the first plate of the first sampling capacitor CSP and the positive output terminal of the residual sampling circuit 220, respectively; a first end of the third negative-end switch S21N is connected to the reference voltage VCM, a second end of the third negative-end switch S21N is connected to the first plate of the second sampling capacitor CSN and is connected to the second plate of the second sampling capacitor CSN through a fifth negative-end switch R31N; and two ends of the fourth negative-end switch S22N are connected to the second plate of the second sampling capacitor CSN and the negative output terminal of the residual sampling circuit 220, respectively.

[0056] When entering the residual sampling phase, the fifth positive-end switch R31P and the fifth negative-end switch R31N are switched from a closed state to an open state.

[0057] In some embodiments, the residue amplifier circuit 230 of the present application includes an operational amplifier AMP, a first feedback capacitor CFP, a second feedback capacitor CFN, a sixth positive-end switch SW41P, and a sixth negative-end switch SW41N. The operational amplifier AMP has a positive input terminal, a negative input terminal, a positive amplified output terminal, and a negative amplified output terminal. The positive input terminal of the operational amplifier AMP is connected to the positive output terminal of the residue sampling circuit 220, and the negative input terminal of the operational amplifier AMP is connected to the negative output terminal of the residue sampling circuit 220. The first feedback capacitor CFP and the sixth positive-end switch SW41P are both connected in parallel between the positive input terminal and the negative amplified output terminal of the operational amplifier AMP. The second feedback capacitor CFN and the sixth negative-end switch SW41N are both connected in parallel between the negative input terminal and the positive amplified output terminal of the operational amplifier AMP.

[0058] When entering the residual amplification stage, the third positive switch S21P, the fourth positive switch S22P, the third negative switch S21N and the fourth negative switch S22N are switched from the open state to the closed state, and the sixth positive switch SW41P and the sixth negative switch SW41N are switched from the closed state to the open state.

[0059] When the next-stage SAR analog-to-digital converter completes sampling of the residue amplified signal, the third positive-end switch S21P, the fourth positive-end switch S22P, the third negative-end switch S21N, and the fourth negative-end switch S22N are disconnected, and the fifth positive-end switch R31P, the fifth negative-end switch R31N, the sixth positive-end switch SW41P, and the sixth negative-end switch SW41N are switched from an open state to a closed state.

[0060] In some embodiments, each stage of a SAR analog-to-digital converter (SAR ADC) includes a positive-side switch array, a negative-side switch array, a positive-side capacitor array, a negative-side capacitor array, a positive-side top plate switch, a negative-side top plate switch, a comparator, and a SAR control module. The first plate of the positive-side capacitor array is connected to the positive input of the comparator and is connected to a reference voltage VCM via the positive-side top plate switch; the second plate of the positive-side capacitor array selectively connects to a positive differential input signal, a reference voltage VCM, a positive reference voltage VREF, and a negative reference voltage VSS via the positive-side switch array. Typically, the reference voltage VCM is equal to half the sum of the positive reference voltage VREF and the negative reference voltage VSS, i.e., ; The first plate of the negative-end capacitor array is connected to the negative input terminal of the comparator and is connected to the reference voltage VCM through the negative-end upper plate switch; the second plate of the negative-end capacitor array is selectively connected to the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF and the negative reference voltage VSS through the negative-end switch array; the output terminal of the comparator is connected to the SAR control module; the SAR control module is used to control the positive-end switch array and the negative-end switch array, and output the conversion end signal and the digital code of the corresponding level.

[0061] For example, for the first-stage SAR ADC, the first plate of the first-stage positive capacitor array CDAC1_P is connected to the positive input terminal of the first-stage comparator COMP1 and is connected to the reference voltage VCM through the first-stage positive upper plate switch; the second plate of the first-stage positive capacitor array CDAC1_P is selectively connected to the positive differential input signal VINP, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the first-stage positive switch array; the first plate of the first-stage negative capacitor array CDAC1_N is connected to the negative input terminal of the first-stage comparator COMP1 and is connected to the reference voltage VCM through the first-stage negative upper plate switch; the second plate of the first-stage negative capacitor array CDAC1_N is selectively connected to the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF, and the negative reference voltage VSS through the first-stage negative switch array; the output terminal of the first-stage comparator COMP1 is connected to the first-stage SAR control (SAR CTRL1) module; the first-stage SAR control (SAR The CTRL1 module is used to control the first-stage positive switch array and the first-stage negative switch array, and output the conversion end signal EOC_1 and the first-stage digital code D1_1 <m-1:0>.

[0062] For the second-stage SAR ADC, the first plate of the second-stage positive capacitor array CDAC2_P is connected to the positive input terminal of the second-stage comparator COMP2 and is connected to the reference voltage VCM through the second-stage positive upper plate switch; the second plate of the second-stage positive capacitor array CDAC2_P is selectively connected to the positive differential input signal VINP, the reference voltage VCM, the positive reference voltage VREF and the negative reference voltage VSS through the second-stage positive switch array; the first plate of the second-stage negative capacitor array CDAC2_N is connected to the negative input terminal of the second-stage comparator COMP2 and is connected to the reference voltage VCM through the second-stage negative upper plate switch; the second plate of the second-stage negative capacitor array CDAC2_N is selectively connected to the negative differential input signal VINN, the reference voltage VCM, the positive reference voltage VREF and the negative reference voltage VSS through the second-stage negative switch array; the output terminal of the second-stage comparator COMP2 is connected to the second-stage SAR control (SAR CTRL2) module; the second-stage SAR control (SAR The CTRL2 module is used to control the second-stage positive terminal switch array and the second-stage negative terminal switch array, and output the conversion end signal EOC_2 and the second-stage digital code D2_1. <m-1:0>When a certain stage of SAR analog-to-digital converter enters the sampling phase, the positive upper plate switch and the negative upper plate switch in the SAR analog-to-digital converter of this stage are closed, and at the same time, the second plate of the positive capacitor array of this stage is connected to the positive input signal through the positive switch array of this stage, and the second plate of the negative capacitor array of this stage is connected to the negative input signal through the negative switch array of this stage. Among them, for the first-stage SAR analog-to-digital converter, the positive input signal includes the positive differential input signal VINP, and the negative input signal includes the negative differential input signal VINN; for SAR analog-to-digital converters of other stages except the first stage, the positive input signal includes the positive residual amplified signal VOP output by the residual amplifier circuit of the previous stage, and the negative input signal includes the negative residual amplified signal VON output by the residual amplifier circuit of the previous stage; after a predetermined sampling stabilization time, the positive end upper plate switch and the negative end upper plate switch in the SAR analog-to-digital converter of this stage are switched from a closed state to an open state, and the second plate of the positive end capacitor array of this stage is connected to the reference voltage VCM through the positive end switch array of this stage, and the second plate of the negative end capacitor array of this stage is connected to the reference voltage VCM through the negative end switch array of this stage.

[0063] Figure 6 Revealed Figure 5 The working timing diagram of the two-stage Pipeline SAR ADC 200 is shown in FIG. Figure 5 and Figure 6 , taking the two-stage Pipeline SAR ADC 200 as an example to illustrate the working principle of the ADC circuit of the present application.

[0064] The first-stage SAR ADC 211 sampling phase (duration t1): By controlling the first-stage positive terminal (P-terminal) switch array and the first-stage negative terminal (N-terminal) switch array, the positive differential input signal VINP and the negative differential input signal VINN are connected to the second plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N, respectively. At the same time, the first plates of the first-stage positive terminal capacitor array CDAC1_P and the first-stage negative terminal capacitor array CDAC1_N are connected to the reference circuit by controlling the first-stage positive terminal upper plate switch SW1P and the first-stage negative terminal upper plate switch SW1N. The voltage VCM is applied to sample the input signal. After a certain sampling stabilization time, the first-stage positive-end top plate switch SW1P and the first-stage negative-end top plate switch SW1N are disconnected, and the positive differential input signal VINP and the negative differential input signal VINN are disconnected from the second plates of the first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N. At this point, the sampling of the input signal is completed (the information of the input signal V1 is sampled into the first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N).

[0065] First-stage SAR ADC 211 conversion phase (duration t2): The conversion end signal EOC_1 output by the first-stage SAR control (SAR CTRL1) module changes from high to low, indicating that the first-stage SAR ADC 211 enters the conversion phase. According to the binary search algorithm, the SAR CTRL1 module controls the switching of the first-stage positive-end switch array and the first-stage negative-end switch array, and controls the signals connected to the second plates of the first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N, thereby quantizing the sampled signal in a successive approximation manner. Finally, the conversion end signal EOC_1 changes from low to high, indicating that the conversion of the first-stage SAR ADC 211 is completed. At this time, a residual signal (VP1-VN1) will be generated, and the first-stage digital code D1_1 will be output at the same time. <m-1:0>.

[0066] Residual sampling phase (duration ts): The residual sampling circuit 220 samples the residual signal as follows: the fifth positive switch R31P and the fifth negative switch R31N are switched from a closed state to an open state, and the first positive switch S11P, the second positive switch S12P, the first negative switch S11N, and the second negative switch S12N are switched from an open state to a closed state, thereby connecting the first plate and the second plate of the first sampling capacitor CSP and the second sampling capacitor CSN to the positive residual signal VP1 and the negative residual signal VN1, respectively. After the duration ts, the charge sharing process is completed, and the first positive switch S11P, the second positive switch S12P, the first negative switch S11N, and the second negative switch S12N are switched from a closed state to an open state. At this point, the residual signal is sampled and the charge information is stored on the first sampling capacitor CSP and the second sampling capacitor CSN.

[0067] Residual amplification and second-stage SAR ADC 212 sampling phase (duration t3): Residual amplification is achieved by controlling the third positive-end switch S21P, the fourth positive-end switch S22P, the third negative-end switch S21N, and the fourth negative-end switch S22N to switch from an open state to a closed state. Simultaneously, the sixth positive-end switch SW41P and the sixth negative-end switch SW41N are switched from a closed state to an open state, thereby generating a residual amplified signal (VOP-VON). Simultaneously, the second-stage positive-end switch array CDAC2_P and the second-stage negative-end switch array CDAC2_N are controlled to connect the positive residual amplified signal VOP and the negative residual amplified signal VON to the second plates of the second-stage positive-end switch array CDAC2_P and the second-stage negative-end switch array CDAC2_N, respectively. The first plates of the second-stage positive-end switch array CDAC2_P and the second-stage negative-end switch array CDAC2_N are connected to the reference voltage VCM by controlling the second-stage positive-end top plate switch SW2P and the second-stage negative-end top plate switch SW2N, thereby achieving the second-stage SAR ADC. After sampling the amplified residual signal (VOP-VON) by the second-stage SAR ADC 212, after a certain period of amplification stabilization and sampling stabilization, the second-stage positive-end top plate switch SW2P, the second-stage negative-end top plate switch SW2N, the third positive-end switch S21P, the fourth positive-end switch S22P, the third negative-end switch S21N, and the fourth negative-end switch S22N are disconnected. Furthermore, the positive-side amplified residual signal VOP and the negative-side amplified residual signal VON are disconnected from the second plates of the second-stage positive-end switch array CDAC2_P and the second-stage negative-end switch array CDAC2_N. At this point, the sampling of the amplified residual signal by the second-stage SAR ADC 212 is completed. At this point, the fifth positive-end switch R31P, the fifth negative-end switch R31N, the sixth positive-end switch SW41P, and the sixth negative-end switch SW41N need to be switched from an open state to a closed state to reset the charges of the first sampling capacitor CSP, the second sampling capacitor CSN, the first feedback capacitor CFP, and the second feedback capacitor CFN, so that the next sampling and amplification process can be performed.

[0068] Second-stage SAR ADC 212 conversion phase (duration t4): The conversion end signal EOC_2 output by the second-stage SAR control (SAR CTRL2) module changes from high to low, indicating that the second-stage SAR ADC 212 enters the conversion phase. According to the binary search algorithm, the second-stage SAR ADC 212 controls the switching of the second-stage positive-end switch array and the second-stage negative-end switch array through the SAR CTRL2 module, and quantizes the sampled signal in a successive approximation manner. Finally, the conversion end signal EOC_2 changes from low to high, indicating that the second-stage SAR ADC 212 conversion is completed. At this time, the second-stage digital code D2_1 is generated and output. <l-1:0>.

[0069] N-bit quantized data Dout <n-1:0>Generation stage: Redundancy calibration and data processing circuit 240 processes the first-level digital code D1_1 <m-1:0>and the second-level digital code D2_1 <l-1:0>After alignment addition and correction of fixed offset, the final N-bit quantized data (i.e., N-bit digital code) Dout1 is output. <n-1:0>, this N-bit quantized data corresponds to the input signal V1.

[0070] from Figure 6 The timing diagram also shows that during the residual amplification and second-stage SAR ADC 212 sampling stages described above, the first-stage SAR ADC 211 can perform the next sampling of the input signal (sampling the input voltage V2). This is mainly because the positive residual signal VP1 and the negative residual signal VN1 are no longer needed at this stage. The first-stage positive-end capacitor array CDAC1_P and the first-stage negative-end capacitor array CDAC1_N can be used to sample the new input signal, making fuller use of the advantages of pipeline operation. Figure 6 The digital code Dout2 <n-1:0>The first level digital code D1_2 <m-1:0>and the second-level digital code D2_2 <l-1:0>The N-bit quantized data corresponding to the input signal V2 is obtained after performing aligned addition and correcting the fixed offset.

[0071] Based on the above analysis, it can be seen that the two-stage Pipeline SAR ADC 200 of the present application, although the residual sampling stage (duration ts) is introduced, the time ts is much shorter than other stages, because the residual sampling stage is actually a process of shared charge transfer between capacitors, and this type of passive shared transfer process can be completed very quickly. Since the residual signal (VP1-VN1) on the first-stage positive capacitor array CDAC1_P and the first-stage negative capacitor array CDAC1_N has been sampled and stored in the first sampling capacitor CSP and the second sampling capacitor CSN during the residual sampling stage, the first-stage SAR ADC 211 can perform the next sampling of the input signal at the same time as the subsequent residual amplification and second-stage SAR ADC 212 sampling stages. Figure 6 As shown, the maximum conversion rate (ie, digital code Dout) of the two-stage Pipeline SAR ADC 200 of the present application is <n-1:0>Data update speed) , compared with the above related technologies , with a significant speed increase.

[0072] In addition, during the residual amplification and second-stage SAR ADC 212 sampling phase, the third positive-end switch S21P, the fourth positive-end switch S22P, the third negative-end switch S21N, and the fourth negative-end switch S22N are controlled to switch from an open state to a closed state, and at the same time, the sixth positive-end switch SW41P and the sixth negative-end switch SW41N are switched from a closed state to an open state, thereby achieving residual amplification and generating a residual amplification signal (VOP-VON). At this time, the reference voltage VCM is connected to the second plate of the first sampling capacitor CSP and the first plate of the second sampling capacitor CSN respectively through the third positive-end switch S21P and the third negative-end switch S21N. A plate, and after the residual sampling phase ends, the charges stored on the first sampling capacitor CSP and the second sampling capacitor CSN are the same. Therefore, it can be seen that at this time, the common-mode levels of the positive signal VISP and the negative signal VISN output by the residual sampling circuit 220 are always VCM. At this time, the positive input terminal and the negative input terminal of the operational amplifier AMP are respectively connected to the positive signal VISP and the negative signal VISN output by the residual sampling circuit 220. It can be seen that the common-mode input voltage of the operational amplifier AMP is always guaranteed to be the reference voltage VCM, and is not dependent on the positive residual signal VP1 and the negative residual signal VN1 output by the first-stage SAR ADC 211. This greatly simplifies the design difficulty of the operational amplifier AMP and improves the flexibility of circuit design.

[0073] The two-stage Pipeline SAR ADC 200 of the present application can realize the next sampling of the input signal by the first-stage SAR ADC 211 by introducing the residual sampling circuit 220 during the residual amplification and sampling stage of the second-stage SAR ADC 212, making full use of the advantages of pipeline operation. The maximum conversion rate of the ADC circuit is reduced by Upgrade to , significantly improving the conversion rate of the ADC circuit. For the same conversion rate requirement, the two-stage Pipeline SAR ADC 200 circuit structure of the present application can appropriately increase the time of the residual error amplification and sampling stages, thereby reducing the requirements for the switch size and bandwidth of the operational amplifier AMP in the circuit, thereby reducing design difficulty and cost.

[0074] In addition, the two-stage Pipeline SAR ADC 200 of the present application introduces the residual sampling circuit 220, so that the input common-mode voltage of the operational amplifier AMP is always equal to the reference voltage VCM during residual amplification, and is not dependent on the positive residual signal VP1 and the negative residual signal VN1 output by the first-stage SAR ADC 211. Therefore, the first-stage SAR ADC 211 can flexibly adopt other timing architectures. Even if a VCM-based timing architecture is not adopted, such as a monotonic timing architecture with a smaller area and lower power consumption, the common-mode input voltage input to the operational amplifier AMP in the residual amplification circuit 230 can still be ensured to be constant at the reference voltage VCM, thereby reducing the design difficulty of the operational amplifier AMP and improving the flexibility of circuit design.

[0075] The above uses a two-stage Pipeline SAR ADC 200 as an example to illustrate the structure, working principle and beneficial effects of the ADC circuit of the present application. It can be similarly extended to more-stage Pipeline SAR ADCs, which will not be described in detail here.

[0076] The present application also provides a control method for an ADC circuit. The ADC circuit includes a multi-stage SAR analog-to-digital converter (SAR) and a multi-stage residual processing circuit. Each stage of the residual processing circuit is located between two adjacent SAR ADC stages. Each stage of the residual processing circuit includes a residual sampling circuit 220 and a residual amplification circuit 230 connected to the output of the residual sampling circuit 220. Both the residual sampling circuit 220 and the residual amplification circuit 230 are single-channel circuits.

[0077] Figure 7 A flow chart of a control method of an ADC circuit according to an embodiment of the present application is disclosed. Figure 7 and combined Figure 5 As shown, the control method of the ADC circuit in one embodiment of the present application may include step S71 and step S72.

[0078] In step S71 , in each sampling conversion cycle of the ADC circuit, the residual sampling circuit 220 and the residual amplifying circuit 230 are controlled to perform residual sampling and residual amplification on the residual signal output by the previous stage SAR analog-to-digital converter, respectively.

[0079] In step S72 , while the residual amplifier circuit 230 is amplifying the residual signal output by the previous stage SAR ADC and the next stage SAR ADC is sampling, the previous stage SAR ADC is controlled to perform the next sampling.

[0080] The above steps S71 and S72 may be controlled and executed by one or more controllers.

[0081] The residual sampling circuit 220 includes a first sampling capacitor CSP and a second sampling capacitor CSN, and the residual signal includes a positive residual signal VP1 and a negative residual signal VN1. In some embodiments, the control method of the ADC circuit of the present application may further include step S73.

[0082] In step S73, when entering the residual sampling phase, the first plate and the second plate of the first sampling capacitor CSP are controlled to be connected to the positive residual signal VP1 and the negative residual signal VN1 output by the previous stage SAR analog-to-digital converter, respectively; and the first plate and the second plate of the second sampling capacitor CSN are controlled to be connected to the positive residual signal VP1 and the negative residual signal VN1 output by the previous stage SAR analog-to-digital converter, respectively.

[0083] The residual amplifying circuit 230 includes an operational amplifier AMP, a first feedback capacitor CFP, and a second feedback capacitor CFN. In some embodiments, the control method of the ADC circuit of the present application may further include step S74.

[0084] In step S74, when entering the residual amplification stage, the second plate of the first sampling capacitor CSP and the first plate of the second sampling capacitor CSN are controlled to be connected to the reference voltage VCM; the first plate of the first sampling capacitor CSP and the second plate of the second sampling capacitor CSN are respectively connected to the positive input terminal and the negative input terminal of the operational amplifier AMP; and the positive input terminal of the operational amplifier AMP is controlled to be connected to the negative amplified output terminal of the operational amplifier AMP through the first feedback capacitor CFP; and the negative input terminal of the operational amplifier AMP is controlled to be connected to the positive amplified output terminal of the operational amplifier AMP through the second feedback capacitor CFN.

[0085] In some embodiments, the control method of the ADC circuit of the present application may further include step S75.

[0086] In step S75, when the next-stage SAR analog-to-digital converter completes sampling of the amplified residual signal output by the residual amplifier circuit 230, the terminals of the first sampling capacitor CSP, the terminals of the second sampling capacitor CSN, the terminals of the first feedback capacitor CFP, and the terminals of the second feedback capacitor CFN are controlled to be short-circuited.

[0087] Each stage of the SAR analog-to-digital converter includes a positive-end switch array, a negative-end switch array, a positive-end capacitor array, and a negative-end capacitor array. In some embodiments, the control method of the ADC circuit of the present application may further include steps S76 and S77.

[0088] In step S76, when a SAR analog-to-digital converter of a certain stage enters the sampling phase, the positive input signal and the negative input signal are connected to the second plate of the positive capacitor array and the second plate of the negative capacitor array of the stage, respectively, by controlling the positive switch array and the negative switch array of the stage; and the first plate of the positive capacitor array and the first plate of the negative capacitor array of the stage are controlled to be connected to the reference voltage VCM. For the first-stage SAR analog-to-digital converter, the positive input signal includes the positive differential input signal VINP, and the negative input signal includes the negative differential input signal VINN. For SAR analog-to-digital converters of other stages except the first stage, the positive input signal includes the positive residual amplified signal VOP output by the residual amplifier circuit of the previous stage, and the negative input signal includes the negative residual amplified signal VON output by the residual amplifier circuit of the previous stage.

[0089] In step S77, after a predetermined sampling stabilization time, the first plate of the positive-end capacitor array of the stage and the first plate of the negative-end capacitor array of the stage are controlled to be disconnected from the reference voltage VCM; and the positive input signal and the negative input signal are controlled to be disconnected from the second plate of the positive-end capacitor array of the stage and the second plate of the negative-end capacitor array of the stage, and the second plate of the positive-end capacitor array of the stage and the second plate of the negative-end capacitor array of the stage are connected to the reference voltage VCM.

[0090] It should be understood that the above steps are distinguished for ease of description only. In practice, depending on the operating principle of the ADC circuit, the above steps or certain operations within each step may be combined or performed in different steps. These minor changes do not alter the basic principles of the ADC circuit control method of the present application and are intended to be within the scope of protection of the present application.

[0091] In the control method of the ADC circuit of the present application, the controller may execute corresponding steps by controlling the corresponding switch array and / or the corresponding switch.

[0092] The control method of the ADC circuit of the present application has similar beneficial technical effects as those described above for the ADC circuit, and therefore, it will not be described in detail here.

[0093] The ADC circuit and control method thereof provided in the embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the ADC circuit and control method thereof in the embodiments of the present application. The description of the above embodiments is only used to help understand the core idea of the present application and is not intended to limit the present application. It should be pointed out that for those skilled in the art, without departing from the spirit and principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications should also fall within the scope of protection of the claims attached to the present application.

Claims

1. An ADC circuit, characterized in that: It includes a multi-stage SAR analog-to-digital converter and a multi-stage residual processing circuit, wherein: The residual processing circuit of each stage is located between the SAR analog-to-digital converters of two adjacent stages; Each level of the residual processing circuit includes a residual sampling circuit and a residual amplification circuit connected to the output end of the residual sampling circuit. The residual sampling circuit and the residual amplification circuit are both single-channel circuits. The residual sampling circuit is implemented in a passive charge sharing manner, and the residual amplification circuit is implemented in an active operational amplifier. In each sampling and conversion cycle of the ADC circuit, the residue sampling circuit and the residue amplifying circuit perform residue sampling and residue amplification on the residue signal output by the previous stage SAR analog-to-digital converter. During the period when the residue amplifying circuit amplifies the residue signal output by the previous stage SAR analog-to-digital converter and the next stage SAR analog-to-digital converter performs sampling, the previous stage SAR analog-to-digital converter is used to perform the next sampling.

2. The ADC circuit according to claim 1, wherein: The residual sampling circuit includes a first sampling capacitor and a second sampling capacitor, and the residual signal includes a positive residual signal and a negative residual signal, wherein: During the residual sampling phase, the first plate and the second plate of the first sampling capacitor are connected to the positive residual signal and the negative residual signal, respectively; the first plate and the second plate of the second sampling capacitor are also connected to the positive residual signal and the negative residual signal, respectively.

3. The ADC circuit according to claim 2, wherein: The residual sampling circuit includes a first positive end switch, a second positive end switch, a first negative end switch and a second negative end switch, wherein: The first plate of the first sampling capacitor is connected to the positive residual signal through the first positive terminal switch; the second plate of the first sampling capacitor is connected to the negative residual signal through the second positive terminal switch; The first plate of the second sampling capacitor is connected to the positive residual signal through the first negative terminal switch; the second plate of the second sampling capacitor is connected to the negative residual signal through the second negative terminal switch.

4. The ADC circuit according to claim 3, wherein: When entering the residual sampling phase, the first positive end switch, the second positive end switch, the first negative end switch and the second negative end switch are switched from an open state to a closed state; After the charge sharing process is completed, the first positive end switch, the second positive end switch, the first negative end switch, and the second negative end switch are switched from a closed state to an open state.

5. The ADC circuit according to claim 3, wherein: The residual sampling circuit further includes a third positive end switch, a fourth positive end switch, a fifth positive end switch, a third negative end switch, a fourth negative end switch and a fifth negative end switch, wherein: A first end of the third positive end switch is connected to a reference voltage, a second end of the third positive end switch is connected to the second plate of the first sampling capacitor and connected to the first plate of the first sampling capacitor via the fifth positive end switch; Two ends of the fourth positive-end switch are respectively connected to the first plate of the first sampling capacitor and the positive output end of the residual sampling circuit; A first end of the third negative terminal switch is connected to the reference voltage, a second end of the third negative terminal switch is connected to the first plate of the second sampling capacitor and connected to the second plate of the second sampling capacitor through the fifth negative terminal switch; Two ends of the fourth negative-end switch are respectively connected to the second plate of the second sampling capacitor and the negative output end of the residual sampling circuit.

6. The ADC circuit according to claim 5, wherein: When entering the residual sampling phase, the fifth positive-end switch and the fifth negative-end switch are switched from a closed state to an open state.

7. The ADC circuit according to claim 5, wherein: The residual amplification circuit includes an operational amplifier, a first feedback capacitor, a second feedback capacitor, a sixth positive terminal switch and a sixth negative terminal switch, wherein: The operational amplifier has a positive input terminal, a negative input terminal, a positive amplified output terminal and a negative amplified output terminal, the positive input terminal of the operational amplifier is connected to the positive output terminal of the residual sampling circuit, and the negative input terminal of the operational amplifier is connected to the negative output terminal of the residual sampling circuit; The first feedback capacitor and the sixth positive-end switch are both connected in parallel between the positive input terminal of the operational amplifier and the negative amplification output terminal; The second feedback capacitor and the sixth negative-end switch are both connected in parallel between the negative input terminal of the operational amplifier and the positive amplification output terminal.

8. The ADC circuit according to claim 7, wherein: When entering the residual amplification stage, the third positive end switch, the fourth positive end switch, the third negative end switch and the fourth negative end switch are switched from an open state to a closed state, and the sixth positive end switch and the sixth negative end switch are switched from a closed state to an open state.

9. The ADC circuit according to claim 7, wherein: When the SAR analog-to-digital converter at the next stage completes sampling of the residual amplified signal, the third positive-end switch, the fourth positive-end switch, the third negative-end switch, and the fourth negative-end switch are disconnected, and the fifth positive-end switch, the fifth negative-end switch, the sixth positive-end switch, and the sixth negative-end switch are switched from an open state to a closed state.

10. The ADC circuit according to any one of claims 1 to 9, wherein: Each level of the SAR analog-to-digital converter includes a positive terminal switch array, a negative terminal switch array, a positive terminal capacitor array, a negative terminal capacitor array, a positive terminal upper plate switch, a negative terminal upper plate switch, a comparator and a SAR control module, wherein: The first plate of the positive-end capacitor array is connected to the positive input terminal of the comparator and is connected to the reference voltage through the positive-end upper plate switch; the second plate of the positive-end capacitor array is selectively connected to the positive differential input signal, the reference voltage, the positive reference voltage and the negative reference voltage through the positive-end switch array; The first plate of the negative-end capacitor array is connected to the negative input terminal of the comparator and is connected to the reference voltage through the negative-end upper plate switch; the second plate of the negative-end capacitor array is selectively connected to the negative differential input signal, the reference voltage, the positive reference voltage and the negative reference voltage through the negative-end switch array; The output end of the comparator is connected to the SAR control module; The SAR control module is used to control the positive-end switch array and the negative-end switch array, and output a conversion end signal and a digital code of a corresponding level.

11. The ADC circuit according to claim 10, wherein: When the SAR analog-to-digital converter of a certain level enters the sampling phase, the positive upper plate switch and the negative upper plate switch in the SAR analog-to-digital converter of this level are closed, and at the same time, the second plate of the positive capacitor array in the SAR analog-to-digital converter of this level is connected to the positive input signal through the positive switch array in the SAR analog-to-digital converter of this level, and the second plate of the negative capacitor array in the SAR analog-to-digital converter of this level is connected to the negative input signal through the negative switch array in the SAR analog-to-digital converter of this level, wherein, for the first-level SAR analog-to-digital converter, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal; for the SAR analog-to-digital converters of other levels except the first level, For the analog-to-digital converter, the positive input signal includes the positive residual amplified signal output by the residual amplification circuit of the previous stage, and the negative input signal includes the negative residual amplified signal output by the residual amplification circuit of the previous stage; after a predetermined sampling stabilization time, the positive-end upper plate switch and the negative-end upper plate switch in the SAR analog-to-digital converter of this stage are switched from a closed state to an open state, and the second plate of the positive-end capacitor array in the SAR analog-to-digital converter of this stage is connected to the reference voltage through the positive-end switch array in the SAR analog-to-digital converter of this stage, and the second plate of the negative-end capacitor array in the SAR analog-to-digital converter of this stage is connected to the reference voltage through the negative-end switch array in the SAR analog-to-digital converter of this stage.

12. The ADC circuit according to claim 10, wherein: Also included are redundant calibration and data processing circuits, wherein: The output end of each stage of the SAR analog-to-digital converter is connected to the redundant calibration and data processing circuit, and the redundant calibration and data processing circuit is used to ultimately output the digital code of the ADC circuit.

13. A control method for an ADC circuit, wherein the ADC circuit comprises a multi-stage SAR analog-to-digital converter and a multi-stage residual processing circuit, wherein each stage of the residual processing circuit is located between two adjacent stages of the SAR analog-to-digital converter, characterized in that: Each stage of the residual processing circuit includes a residual sampling circuit and a residual amplification circuit connected to the output end of the residual sampling circuit, wherein the residual sampling circuit and the residual amplification circuit are both single-channel circuits, and the method includes: In each sampling conversion cycle of the ADC circuit, controlling the residual sampling circuit and the residual amplification circuit to perform residual sampling and residual amplification on the residual signal output by the SAR analog-to-digital converter of the previous stage respectively; During the period when the residual amplification circuit amplifies the residual signal output by the previous stage SAR analog-to-digital converter and the next stage SAR analog-to-digital converter performs sampling, the previous stage SAR analog-to-digital converter is controlled to perform the next sampling.

14. The control method according to claim 13, wherein: The residual sampling circuit includes a first sampling capacitor and a second sampling capacitor, the residual signal includes a positive residual signal and a negative residual signal, and the method further includes: When entering the residual sampling stage, the first plate and the second plate of the first sampling capacitor are controlled to be connected to the positive residual signal and the negative residual signal output by the previous stage SAR analog-to-digital converter, respectively; and the first plate and the second plate of the second sampling capacitor are controlled to be connected to the positive residual signal and the negative residual signal output by the previous stage SAR analog-to-digital converter, respectively.

15. The control method according to claim 14, wherein: The residual amplification circuit includes an operational amplifier, a first feedback capacitor, and a second feedback capacitor. The method further includes: When entering the residual amplification stage, the second plate of the first sampling capacitor and the first plate of the second sampling capacitor are controlled to be connected to a reference voltage; the first plate of the first sampling capacitor and the second plate of the second sampling capacitor are connected to the positive input terminal and the negative input terminal of the operational amplifier, respectively; the positive input terminal of the operational amplifier is controlled to be connected to the negative amplification output terminal of the operational amplifier through the first feedback capacitor; and the negative input terminal of the operational amplifier is controlled to be connected to the positive amplification output terminal of the operational amplifier through the second feedback capacitor.

16. The control method according to claim 15, wherein: Also includes: When the SAR analog-to-digital converter at the next stage completes sampling of the residual amplified signal output by the residual amplification circuit, the two ends of the first sampling capacitor, the two ends of the second sampling capacitor, the two ends of the first feedback capacitor, and the two ends of the second feedback capacitor are controlled to be short-circuited.

17. The control method according to claim 13, wherein: Each stage of the SAR analog-to-digital converter includes a positive-end switch array, a negative-end switch array, a positive-end capacitor array, and a negative-end capacitor array. The method further includes: When the SAR analog-to-digital converter of a certain stage enters the sampling phase, the positive input signal and the negative input signal are connected to the second plate of the positive capacitor array and the second plate of the negative capacitor array of the SAR analog-to-digital converter of the stage, respectively, by controlling the positive switch array and the negative switch array of the SAR analog-to-digital converter of the stage; and the first plate of the positive capacitor array and the first plate of the negative capacitor array of the SAR analog-to-digital converter of the stage are controlled to be connected to a reference voltage, wherein, for the SAR analog-to-digital converter of the first stage, the positive input signal includes a positive differential input signal, and the negative input signal includes a negative differential input signal; for the SAR analog-to-digital converters of the other stages except the first stage, the positive input signal includes a positive residual amplified signal output by the residual amplification circuit of the previous stage, and the negative input signal includes a negative residual amplified signal output by the residual amplification circuit of the previous stage; After a predetermined sampling stabilization time, the first plate of the positive capacitor array and the first plate of the negative capacitor array in the SAR analog-to-digital converter of this level are controlled to be disconnected from the reference voltage; and the positive input signal and the negative input signal are controlled to be disconnected from the second plate of the positive capacitor array and the second plate of the negative capacitor array in the SAR analog-to-digital converter of this level, and the second plate of the positive capacitor array and the second plate of the negative capacitor array in the SAR analog-to-digital converter of this level are connected to the reference voltage.

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