Power supply detection circuit and detection method thereof

Abstract

The invention discloses a power supply detection circuit and a detection method thereof, one end of a switch SW0 is connected with a VCOMP signal, the other end of the switch SW0 is connected with the output end of a voltage clamping circuit CLAMP, the input end of a power supply detection module is connected with a signal VIN, the first output end of the power supply detection module generates a signal STATE1, the second output end of the power supply detection module generates a signal STATE2, and the first output end of the power supply detection module generates a signal STATE3. An OR gate G2 of the power supply control circuit adopts a three-input OR gate, a second input end of the OR gate G2 is connected with a signal STATE2, and a third input end of the OR gate G2 is connected with a signal STATE1. The state of the input voltage source of the power supply system and the state of connection with the input voltage source can be completely and reliably detected, so that the power supply can adaptively work in a preset working state.

Description

Technical Field

[0001] The present invention relates to a detection circuit and a detection method thereof, in particular to a power supply detection circuit and a detection method thereof, and belongs to the technical field of semiconductor integrated circuits. Background Art

[0002] With the continuous enrichment of the application scenarios of DC / DC power converters, the operating conditions and connection states of the input voltage (i.e., the power supply) of DC / DC power converters are also increasing. Therefore, it is necessary for DC / DC power converters to pre-detect and identify their input operating conditions and connection states, so as to enter the working state predetermined by the application scenario. In addition, the performance requirements for DC / DC power converters are also continuously improving, and requirements such as power consumption, stability, safety, and reliability need to be taken into account.

[0003] As Figure 6 As shown, the existing DC / DC power conversion system includes a capacitor C1, a capacitor C2, a capacitor C3, a freewheeling diode D1, an inductor L1, a resistor RO, a resistor RS, a power switch M1, and a power supply controller U1. One end of the capacitor C1 is connected to the VIN pin of the power supply controller U1, the cathode of the freewheeling diode D1, one end of the capacitor C2, and one end of the resistor R0. The other end of the capacitor C1 is grounded. The VCC pin of the power supply controller U1 is connected to one end of the capacitor C2. The other end of the capacitor C2 and the GND pin of the power supply controller U1 are grounded. The GATE pin of the power supply controller U1 is connected to the gate of the power switch M1. The CS pin of the power supply controller U1 is connected to one end of the power switch M1 and one end of the resistor RS and generates a signal VCS. The other end of the resistor RS is grounded. The other end of the power switch M1 is connected to the anode of the freewheeling diode D1 and one end of the inductor L1 and generates a signal VDRAIN. The other end of the inductor L1 is connected to the other end of the capacitor C2 and the other end of the resistor R0.

[0004] As Figure 7As shown in the figure, the power control circuit of the prior art is arranged in the power controller U1. The power control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1, and a drive circuit module Driver. The input end of the sample and hold module Sample&Hold is connected to the signal VCS. The output end of the sample and hold module Sample&Hold is connected to the inverting input end of the error amplifier module EA. The non-inverting input end of the error amplifier module EA is connected to the reference voltage Reference1. The output end of the error amplifier module EA is connected to the inverting input end of the comparator CMP1 and generates the signal VCOMP. The output end of the ramp generation circuit Ramp Generator is connected to the non-inverting input end of the comparator CMP1. The output end of the comparator CMP1 is connected to the R end of the RS flip-flop G1. The non-inverting input end of the comparator CMP2 is grounded. The output end of the comparator CMP2 is connected to the S end of the RS flip-flop G1. The Q end of the RS flip-flop G1 is connected to the input end of the drive circuit module Driver and generates the signal PWM. The output end of the drive circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates the signal GATE.

[0005] The existing DC / DC power converter cannot detect and identify the state of its input power supply (such as power supply capacity) and its connection state (such as good connection or weak connection, etc.) completely and accurately, and cannot adaptively enter the working state predetermined by the application scenario. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a power supply detection circuit and its detection method, which can detect the state of the input power supply and the connection state, so that the power supply can work adaptively in the predetermined working state.

[0007] To solve the above technical problems, the technical solution adopted by the present invention is: A power supply detection circuit includes a power control circuit, a switch SW0, a voltage clamping circuit CLAMP, and a power supply detection module Input State Detection. One end of the switch SW0 is connected to the VCOMP signal of the power control circuit, the other end of the switch SW0 is connected to the output end of the voltage clamping circuit CLAMP, the input end of the power supply detection module Input State Detection is connected to the signal VIN, the first output end of the power supply detection module Input State Detection generates a signal STATE1, the second output end of the power supply detection module Input State Detection generates a signal STATE2, the OR gate G2 of the power control circuit is a three-input OR gate, the second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1.

[0008] Further, the power control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit RampGenerator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS flip-flop G1, and a driver circuit module Driver. The input end of the sample and hold module Sample&Hold is connected to the signal VCS, the output end of the sample and hold module Sample&Hold is connected to the inverting input end of the error amplifier module EA, the non-inverting input end of the error amplifier module EA is connected to a reference voltage Reference1, the output end of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input end of the comparator CMP1 and generates a signal VCOMP, the output end of the ramp generation circuit Ramp Generator is connected to the non-inverting input end of the comparator CMP1, the output end of the comparator CMP1 is connected to the first input end of the OR gate G2, the second input end of the OR gate G2 is connected to the signal STATE2, the third input end of the OR gate G2 is connected to the signal STATE1, the output end of the OR gate G2 is connected to the R end of the RS flip-flop G1, the non-inverting input end of the comparator CMP2 is grounded, the output end of the comparator CMP2 is connected to the S end of the RS flip-flop G1, the Q end of the RS flip-flop G1 is connected to the input end of the driver circuit module Driver, and the output end of the driver circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates a signal GATE.

[0009] Further, the power supply detection module Input State Detection includes an input voltage divider and filter circuit Divider&Filter, a comparator CMP3, a comparator CMP4, a comparator CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample&Hold, a subtractor Subtractor1, a subtractor Subtractor2, an RS flip-flop G3, an RS flip-flop G4, a D flip-flop G5, a D flip-flop G6, an AND gate G7, a NOT gate G8, an AND gate G9, a switch SW1, a switch SW2, a current source Isource1, and a current source Isource2. The input end of the input voltage divider and filter circuit Divider&Filter is connected to the signal VIN. The output end of the input voltage divider and filter circuit Divider&Filter is connected to the positive input end of the comparator CMP3 and generates a signal VIN_DET. The negative input end of the comparator CMP3 is connected to a reference voltage Reference2. The output end of the comparator CMP3 is connected to the EN end of the timer Counter. The output end of the clock generator OSC is connected to the CK end of the timer Counter and generates a clock signal CLK. The T1 end of the timer Counter is connected to the S end of the RS flip-flop G3. The T2 end of the timer Counter is connected to the CK end of the D flip-flop G5. The T3 end of the timer Counter is connected to the R end of the RS flip-flop G3. The T4 end of the timer Counter is connected to the S end of the RS flip-flop G4. The T5 end of the timer Counter is connected to the CK end of the D flip-flop G6. The T6 end of the timer Counter is connected to the R end of the RS flip-flop G4. The Q end of the RS flip-flop G3 is connected to the control end of the switch SW1 and generates a control signal CTRL_{1}. The Q end of the RS flip-flop G4 is connected to the first input end of the AND gate G7. The output end of the AND gate G7 is connected to the control end of the switch SW2 and generates a control signal CTRL_{2}. One end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN. The other end of the switch SW1 is connected to one end of the current source Isource1. The other end of the switch SW2 is connected to one end of the current source Isource2. The other ends of the current source Isource1 and the current source Isource2 are grounded. The input end of the sample and hold module Sample&Hold is connected to the signal VIN_DET. The output end of the sample and hold module Sample&Hold is connected to the positive input ends of the subtractor Subtractor1 and the subtractor Subtractor2. The negative input end of the subtractor Subtractor1 is connected to a reference voltage Reference3. The output end of the subtractor Subtractor1 is connected to the negative input end of the comparator CMP4. The positive input end of the comparator CMP_{4} is connected to the signal VIN_DET.The output terminal of comparator CMP4 is connected to the D terminal of D flip-flop G5. The negative input terminal of subtractor Subtractor2 is connected to reference voltage Reference4. The output terminal of subtractor Subtractor2 is connected to the inverting input terminal of comparator CMP5. The non-inverting input terminal of comparator CMP5 is connected to signal VIN_DET. The output terminal of comparator CMP5 is connected to the D terminal of D flip-flop G6. The Q terminal of D flip-flop G5 is connected to the second input terminal of AND gate G7 and the input terminal of NOT gate G8. The output terminal of NOT gate G8 is connected to the first input terminal of AND gate G9 and generates signal STATE1. The Q terminal of comparator G6 is connected to the second input terminal of AND gate G9. The output terminal of AND gate G9 generates signal STATE2.,

[0010] Further, the waiting times for the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter to flip from logic low level to logic high level increase sequentially.,

[0011] Further, the conduction time of switch SW1 is before the conduction time of switch SW2.,

[0012] Further, both the current source Isource1 and the current source Isource2 are turned on in a manner that gradually increases to the set value with a rising slope, and both the current source Isource1 and the current source Isource2 are turned off in a manner that gradually decreases to zero with a falling slope.,

[0013] A power supply detection method for a power supply detection circuit includes the following steps: First Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW1, causing the current IVIN flowing into the VIN pin of the power controller U1 to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a weak voltage source, the signal VIN begins to be significantly pulled down by the current IVIN and the drop amplitude exceeds Reference3*K, where K is the voltage division ratio of the voltage divider and filter circuit Divider&Filter. At time T2, the T2 terminal of the timer Counter changes from logic low level to logic high level. At this time, it is detected that the drop amplitude of the signal VIN exceeds Reference3*K, causing the signal STATE1 to change from logic low level to logic high level, enabling the power control circuit and sending a switching waveform to the GATE pin of the power controller U1, and turning on the switch SW0 to enable the voltage clamping of the signal VCOMP output by the error amplifier module EA, causing the power control loop to operate in a set limited state. At time T3, the T3 terminal of the timer Counter changes from logic level to logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm2. Because the signal STATE1 flips to logic high level at time T2, the detection circuit for the signal STATE2 is not enabled, thereby causing the signal STATE2 to be constantly logic low level; Second Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts working. By time T1, the T1 terminal of the timer Counter transitions from a logic low level to a logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a high-capacity voltage source, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter transitions from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at a logic low level, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter transitions from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm2. At time T4, the T4 terminal of the timer Counter transitions from a logic low level to a logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource2, with a rise time of tm3. At this time, since the signal VIN is in a weakly connected state when connected to the input voltage source and there is a large connection impedance on the connection path, the voltage of the signal VIN starts to be significantly pulled down by the current IVIN, and the drop amplitude exceeds Reference4*K. At time T5, the T5 terminal of the timer Counter transitions from a logic low level to a logic high level. It is detected that the drop amplitude of the signal VIN exceeds Reference4*K, causing the signal STATE2 to remain at a logic low level, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T6, the T6 terminal of the timer Counter transitions from a logic low level to a logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm4; Third Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts working. By time T1, the T1 terminal of the timer Counter transitions from logic low to logic high, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a high-capability voltage source, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter transitions from logic low to logic high. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at logic low, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter transitions from logic level to logic high, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm2. At time T4, the T4 terminal of the timer Counter transitions from logic low to logic high, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource2, with a rise time of tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance in the connection path, the voltage of the signal VIN starts to be slightly pulled down by IVIN, and the drop amplitude does not exceed Reference4*K. At time T5, the T5 terminal of the timer Counter transitions from logic low to logic high. It is detected that the drop amplitude of the signal VIN does not exceed Reference4*K, causing the signal STATE2 to transition from logic low to logic high, thereby enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at logic low, it does not enable the voltage clamping of the signal VCOMPD output by the error amplifier module EA, and the power control loop is not restricted by clamping. At time T6, the T6 terminal of the timer Counter transitions from logic low to logic high, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm4; The input voltage divider and filter circuit Divider&Filter divides the signal VIN and filters out high-frequency disturbances through filtering, and outputs a signal VIN_DET that can be processed; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 conducts and / or before the switch SW2 conducts, and holds the sampled value VHOLD after the switch SW1 conducts and / or after the switch SW2 conducts; the held sampled value VHOLD generates reference voltages for detecting the state through the subtractors Subtractor1 and Subtractor2 respectively, and serves as the reference voltages for the comparators CMP4 and CMP5 respectively; the time waited for the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter to flip from logic low level to logic high level becomes longer in sequence; the moment when the switch SW1 conducts is before the moment when the switch SW2 conducts, and the current sources Isource1 and Isource2 are enabled respectively to pull down the current to detect the power supply state and the connection state of the VIN pin of the power supply controller U1 externally connected. The detection duration is set by the timer Counter. The current sources Isource1 and Isource2 are both turned on in an ascending slope manner to gradually reach the set value, and the current sources Isource1 and Isource2 are both turned off in a descending slope manner to gradually reach zero; when the signal STATE1 is at a high logic level, the conduction of the switch SW2 and the detection of the external connection state of the VIN pin of the power supply controller U1 by the current source Isource2 pulling down the current are not enabled.

[0014] Compared with the prior art, the present invention has the following advantages and effects: 1. The present invention can completely and reliably detect the state of the input voltage source of the power supply system and its connection state, enabling the power supply to adaptively operate in a predetermined working state; 2. The present invention does not add external detection components to the system, saves system costs, and does not increase the power consumption of the chip, keeping the total power consumption of the chip at a very low level; 3. For the detection current of the power supply state and connection state detection of the present invention, when enabled, it gradually reaches the set value in an ascending slope manner, and when turned off, it gradually reaches zero in a descending slope manner, which can reduce the downward ringing and / or upward ringing caused by parasitic inductance and capacitance, improve the detection accuracy while reducing the stress of power devices. Description of the Drawings

[0015] Figure 1 is a schematic diagram of a power supply detection circuit of the present invention.

[0016] Figure 2 is a circuit diagram of the power supply detection module Input State Detection of the present invention.

[0017] Figure 3 It is the first schematic waveform diagram of a power supply detection circuit of the present invention.

[0018] Figure 4 It is the second schematic waveform diagram of a power supply detection circuit of the present invention.

[0019] Figure 5 It is the third schematic waveform diagram of a power supply detection circuit of the present invention.

[0020] Figure 6 It is a schematic diagram of a DC / DC power conversion system of the prior art.

[0021] Figure 7 It is a schematic diagram of a power control circuit of the prior art. Detailed implementation manners

[0022] In order to elaborate in detail the technical solutions adopted by the present invention to achieve the predetermined technical purposes, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0023] As Figure 1 shown, a power supply detection circuit of the present invention includes a power control circuit, a switch SW0, a voltage clamping circuit CLAMP, and a power supply detection module Input State Detection, one end of the switch SW0 is connected to the VCOMP signal of the power control circuit, the other end of the switch SW0 is connected to the output end of the voltage clamping circuit CLAMP, the input end of the power supply detection module Input State Detection is connected to the signal VIN, the first output end of the power supply detection module Input State Detection generates a signal STATE1, the second output end of the power supply detection module Input State Detection generates a signal STATE2, the OR gate G2 of the power control circuit is a three-input OR gate, the second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1.

[0024] The power control circuit includes a sample and hold module Sample&Hold, a ramp generator circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS flip-flop G1, and a driver circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier module EA. The non-inverting input terminal of the error amplifier module EA is connected to the reference voltage Reference1. The output terminal of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input terminal of the comparator CMP1 and generates the signal VCOMP. The output terminal of the ramp generator circuit Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the first input terminal of the OR gate G2. The second input terminal of the OR gate G2 is connected to the signal STATE2. The third input terminal of the OR gate G2 is connected to the signal STATE1. The output terminal of the OR gate G2 is connected to the R terminal of the RS flip-flop G1. The non-inverting input terminal of the comparator CMP2 is grounded. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the driver circuit module Driver. The output terminal of the driver circuit module Driver is connected to the inverting input terminal of the comparator CMP2 and generates the signal GATE.

[0025] Such as Figure 2As shown, the power supply detection module Input State Detection includes an input voltage divider and filter circuit Divider&Filter, a comparator CMP3, a comparator CMP4, a comparator CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample&Hold, a subtractor Subtractor1, a subtractor Subtractor2, an RS flip-flop G3, an RS flip-flop G4, a D flip-flop G5, a D flip-flop G6, an AND gate G7, a NOT gate G8, an AND gate G9, a switch SW1, a switch SW2, a current source Isource1, and a current source Isource2. The input terminal of the input voltage divider and filter circuit Divider&Filter is connected to the signal VIN. The output terminal of the input voltage divider and filter circuit Divider&Filter is connected to the non-inverting input terminal of the comparator CMP3 and generates the signal VIN_DET. The inverting input terminal of the comparator CMP3 is connected to the reference voltage Reference2. The output terminal of the comparator CMP3 is connected to the EN terminal of the timer Counter. The output terminal of the clock generator OSC is connected to the CK terminal of the timer Counter and generates the clock signal CLK. The T1 terminal of the timer Counter is connected to the S terminal of the RS flip-flop G3. The T2 terminal of the timer Counter is connected to the CK terminal of the D flip-flop G5. The T3 terminal of the timer Counter is connected to the R terminal of the RS flip-flop G3. The T4 terminal of the timer Counter is connected to the S terminal of the RS flip-flop G4. The T5 terminal of the timer Counter is connected to the CK terminal of the D flip-flop G6. The T6 terminal of the timer Counter is connected to the R terminal of the RS flip-flop G4. The Q terminal of the RS flip-flop G3 is connected to the control terminal of the switch SW1 and generates the control signal CTRL1. The Q terminal of the RS flip-flop G4 is connected to the first input terminal of the AND gate G7. The output terminal of the AND gate G7 is connected to the control terminal of the switch SW2 and generates the control signal CTRL2. One end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN. The other end of the switch SW1 is connected to one end of the current source Isource1. The other end of the switch SW2 is connected to one end of the current source Isource2. The other end of the current source Isource1 and the other end of the current source Isource2 are grounded. The input terminal of the sample and hold module Sample&Hold is connected to the signal VIN_DET. The output terminal of the sample and hold module Sample&Hold is connected to the non-inverting input terminal of the subtractor Subtractor1 and the non-inverting input terminal of the subtractor Subtractor2. The inverting input terminal of the subtractor Subtractor1 is connected to the reference voltage Reference3. The output terminal of the subtractor Subtractor1 is connected to the inverting input terminal of the comparator CMP4. The non-inverting input terminal of the comparator CMP4 is connected to the signal VIN_DET,The output terminal of comparator CMP4 is connected to the D terminal of D flip-flop G5. The negative input terminal of subtractor Subtractor2 is connected to reference voltage Reference4. The output terminal of subtractor Subtractor2 is connected to the inverting input terminal of comparator CMP5. The non-inverting input terminal of comparator CMP5 is connected to signal VIN_DET. The output terminal of comparator CMP5 is connected to the D terminal of D flip-flop G6. The Q terminal of D flip-flop G5 is connected to the second input terminal of AND gate G7 and the input terminal of NOT gate G8. The output terminal of NOT gate G8 is connected to the first input terminal of AND gate G9 and generates signal STATE1. The Q terminal of comparator G6 is connected to the second input terminal of AND gate G9. The output terminal of AND gate G9 generates signal STATE2.,

[0026] Among them, the waiting times for the signals T1 to T6 generated by the T1 to T6 terminals of timer Counter to flip from logic low level to logic high level gradually increase in sequence.

[0027] The conduction time of switch SW1 is before the conduction time of switch SW2. Current sources Isource1 and Isource2 are enabled respectively to pull down the current to detect the power supply state and the connection state of the VIN pin of power supply controller U1. The detection duration is set by timer Counter.

[0028] Current sources Isource1 and Isource2 are both turned on in an ascending slope manner to gradually reach the set value, and are both turned off in a descending slope manner to gradually reach zero.

[0029] A power supply detection method for a power supply detection circuit, comprising the following steps: Such as Figure 3As shown, the first schematic waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts working. By time T1, the T1 terminal of the timer Counter transitions from a logic low level to a logic high level, thereby turning on the switch SW1, causing the current IVIN flowing into the VIN pin of the power supply controller U1 to gradually increase with a rising slope until it equals the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a weak voltage source, the signal VIN starts to be significantly pulled down by the current IVIN and the drop amplitude exceeds Reference3*K, where K is the voltage division ratio of the voltage divider and filter circuit Divider&Filter. At time T2, the T2 terminal of the timer Counter transitions from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN exceeds Reference3*K, causing the signal STATE1 to transition from a logic low level to a logic high level, enabling the power control circuit and delivering a switching waveform to the GATE pin of the power supply controller U1, and turning on the switch SW0, enabling the voltage clamping of the signal VCOMP output by the error amplifier module EA, causing the power control loop to operate in a set limited state. At time T3, the T3 terminal of the timer Counter transitions from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm2. Because the signal STATE1 flips to a logic high level at time T2, the detection circuit for the signal STATE2 is not enabled, thereby causing the signal STATE2 to remain constantly at a logic low level.

[0030] Among them, the signal VIN is the voltage on the VIN pin of the power supply controller U1, the current IVIN is the current flowing into the VIN pin of the power supply controller U1, the signal STATE1 is the logic level at the first output terminal of the power supply detection circuit, the signal STATE2 is the logic level at the second output terminal of the power supply detection circuit, and the signal GATE is the voltage on the GATE pin of the power supply controller U1.

[0031] As Figure 4As shown, the second schematic waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter changes from logical low level to logical high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase to the same value as the current of the current source Isource1 with a rising slope, and the rising time is tm1. At this time, since the source connected to the power supply system is a high-capability voltage source, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from logical low level to logical high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at logical low level, still not enabling the power control circuit and sending a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from logical level to logical high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, and the falling time is tm2. At time T4, the T4 terminal of the timer Counter changes from logical low level to logical high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase to the same value as the current of the current source Isource2 with a rising slope, and the rising time is tm3. At this time, since the signal VIN is in a weak connection state when connected to the input voltage source and there is a large connection impedance on the connection path, the voltage of the signal VIN starts to be significantly pulled down by the current IVIN, and the drop amplitude exceeds Reference4*K. At time T5, the T5 terminal of the timer Counter changes from logical low level to logical high level. It is detected that the drop amplitude of the signal VIN exceeds Reference4*K, causing the signal STATE2 to remain at logical low level, still not enabling the power control circuit and sending a switching waveform to the GATE pin of the power controller U1. At time T6, the T6 terminal of the timer Counter changes from logical low level to logical high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, and the falling time is tm4.

[0032] As Figure 5As shown, the third schematic waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource1, with a rising time of tm1. At this time, since the source connected to the power supply system is a voltage source with strong capabilities, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from logic low level to logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at logic low level, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from logic level to logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, and the falling time is tm2. At time T4, the T4 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource2, and the rising time is tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance in the connection path, the voltage of the signal VIN starts to be slightly pulled down by IVIN, and the drop amplitude does not exceed Reference4*K. At time T5, the T5 terminal of the timer Counter changes from logic low level to logic high level. It is detected that the drop amplitude of the signal VIN does not exceed Reference4*K, causing the signal STATE2 to change from logic low level to logic high level, thereby enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at logic low level, it does not enable the voltage clamping of the signal VCOMPD output by the error amplifier module EA, and the power control loop is not restricted by clamping. At time T6, the T6 terminal of the timer Counter changes from logic low level to logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, and the falling time is tm4.

[0033] The input voltage divider and filter circuit Divider&Filter divides the signal VIN and filters out high-frequency disturbances through filtering, and outputs a processable signal VIN_DET; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 conducts and / or before the switch SW2 conducts, and holds the sampled value VHOLD after the switch SW1 conducts and / or after the switch SW2 conducts; the held sampled value VHOLD generates a reference voltage for the detection state through the subtractors Subtractor1 and Subtractor2 respectively, and is used as the reference voltage for the comparators CMP4 and CMP5 respectively; the time waited for the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter to flip from logic low level to logic high level increases sequentially; the conduction time of the switch SW1 is before the conduction time of the switch SW2, and enables the current sources Isource1 and Isource2 to pull down the current to detect the power supply state and connection state of the VIN pin of the power supply controller U1 respectively. The detection duration is set by the timer Counter. The current sources Isource1 and Isource2 are both turned on in an ascending slope manner to the set value, and the current sources Isource1 and Isource2 are both turned off in a descending slope manner to zero; when the signal STATE1 is at a high logic level, the conduction of the switch SW2 and the detection of the external state of the VIN pin of the power supply controller U1 by the current source Isource2 pulling down the current are not enabled.

[0034] The present invention can completely and reliably detect the state of the input voltage source of the power supply system and its connection state, enabling the power supply to adaptively operate in a predetermined working state; the present invention does not add external detection components to the system, saves system costs, and does not increase the power consumption of the chip, keeping the total power consumption of the chip at a very low level; the detection current for detecting the power supply state and connection state of the present invention is gradually increased to the set value in an ascending slope manner when enabled, and gradually decreased to zero in a descending slope manner when turned off, which can reduce the downward ringing and / or upward ringing caused by parasitic inductance and capacitance, improve the detection accuracy and reduce the stress of power devices at the same time.

[0035] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments of equivalent changes by using the technical content disclosed above within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, and based on the technical essence of the present invention, any simple modification, equivalent replacement and improvement made to the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A power supply detection circuit, characterized in that: It includes a power control circuit, a switch SW0, a voltage clamping circuit CLAMP, and a power supply detection module Input State Detection. One end of the switch SW0 is connected to the VCOMP signal of the power control circuit, and the other end of the switch SW0 is connected to the output end of the voltage clamping circuit CLAMP. The input end of the power supply detection module Input State Detection is connected to the signal VIN. The first output end of the power supply detection module Input State Detection generates a signal STATE1, and the second output end of the power supply detection module Input State Detection generates a signal STATE2. The OR gate G2 of the power control circuit uses a three-input OR gate. The second input end of the OR gate G2 is connected to the signal STATE2, and the third input end of the OR gate G2 is connected to the signal STATE1.

2. The power supply detection circuit according to claim 1, characterized in that: The power control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier module EA, a comparator CMP1, an OR gate G2, a comparator CMP2, an RS flip-flop G1, and a drive circuit module Driver. The input end of the sample and hold module Sample&Hold is connected to the signal VCS. The output end of the sample and hold module Sample&Hold is connected to the inverting input end of the error amplifier module EA. The non-inverting input end of the error amplifier module EA is connected to a reference voltage Reference1. The output end of the error amplifier module EA is connected to one end of the switch SW0 and the inverting input end of the comparator CMP1 and generates a signal VCOMP. The output end of the ramp generation circuit RampGenerator is connected to the non-inverting input end of the comparator CMP1. The output end of the comparator CMP1 is connected to the first input end of the OR gate G2. The second input end of the OR gate G2 is connected to the signal STATE2. The third input end of the OR gate G2 is connected to the signal STATE1. The output end of the OR gate G2 is connected to the R end of the RS flip-flop G1. The non-inverting input end of the comparator CMP2 is grounded. The output end of the comparator CMP2 is connected to the S end of the RS flip-flop G1. The Q end of the RS flip-flop G1 is connected to the input end of the drive circuit module Driver. The output end of the drive circuit module Driver is connected to the inverting input end of the comparator CMP2 and generates a signal GATE.

3. The power supply detection circuit according to claim 1, wherein: The power supply detection module InputState Detection includes an input voltage divider and filter circuit Divider&Filter, a comparator CMP3, a comparator CMP4, a comparator CMP5, a clock generator OSC, a timer Counter, a sample and hold module Sample&Hold, a subtractor Subtractor1, a subtractor Subtractor2, an RS flip-flop G3, an RS flip-flop G4, a D flip-flop G5, a D flip-flop G6, an AND gate G7, a NOT gate G8, an AND gate G9, a switch SW1, a switch SW2, a current source Isource1, and a current source Isource2. The input terminal of the input voltage divider and filter circuit Divider&Filter is connected to the signal VIN. The output terminal of the input voltage divider and filter circuit Divider&Filter is connected to the positive input terminal of the comparator CMP3 and generates the signal VIN_DET. The negative input terminal of the comparator CMP3 is connected to the reference voltage Reference2. The output terminal of the comparator CMP3 is connected to the EN terminal of the timer Counter. The output terminal of the clock generator OSC is connected to the CK terminal of the timer Counter and generates the clock signal CLK. The T1 terminal of the timer Counter is connected to the S terminal of the RS flip-flop G3. The T2 terminal of the timer Counter is connected to the CK terminal of the D flip-flop G5. The T3 terminal of the timer Counter is connected to the R terminal of the RS flip-flop G3. The T4 terminal of the timer Counter is connected to the S terminal of the RS flip-flop G4. The T5 terminal of the timer Counter is connected to the CK terminal of the D flip-flop G6. The T6 terminal of the timer Counter is connected to the R terminal of the RS flip-flop G4. The Q terminal of the RS flip-flop G3 is connected to the control terminal of the switch SW1 and generates the control signal CTRL1. The Q terminal of the RS flip-flop G4 is connected to the first input terminal of the AND gate G7. The output terminal of the AND gate G7 is connected to the control terminal of the switch SW2 and generates the control signal CTRL2. One end of the switch SW1 and one end of the switch SW2 are connected to the signal VIN. The other end of the switch SW1 is connected to one end of the current source Isource1. The other end of the switch SW2 is connected to one end of the current source Isource2. The other ends of the current source Isource1 and the current source Isource2 are grounded. The input terminal of the sample and hold module Sample&Hold is connected to the signal VIN_DET. The output terminal of the sample and hold module Sample&Hold is connected to the positive input terminals of the subtractor Subtractor1 and the subtractor Subtractor2. The negative input terminal of the subtractor Subtractor1 is connected to the reference voltage Reference3. The output terminal of the subtractor Subtractor1 is connected to the negative input terminal of the comparator CMP4. The positive input terminal of the comparator CMP4 is connected to the signal VIN_DET,The output terminal of comparator CMP4 is connected to the D terminal of D flip-flop G5. The negative input terminal of subtractor Subtractor2 is connected to reference voltage Reference4. The output terminal of subtractor Subtractor2 is connected to the inverting input terminal of comparator CMP5. The non-inverting input terminal of comparator CMP5 is connected to signal VIN_DET. The output terminal of comparator CMP5 is connected to the D terminal of D flip-flop G6. The Q terminal of D flip-flop G5 is connected to the second input terminal of AND gate G7 and the input terminal of NOT gate G8. The output terminal of NOT gate G8 is connected to the first input terminal of AND gate G9 and generates signal STATE1. The Q terminal of comparator G6 is connected to the second input terminal of AND gate G9. The output terminal of AND gate G9 generates signal STATE2., 4. The power supply detection circuit according to claim 3, characterized in that: The time waited for the signals T1 to T6 generated by the T1 terminal to the T6 terminal of the timer Counter to flip from a logic low level to a logic high level becomes longer in sequence.

5. The power supply detection circuit according to claim 3, wherein: The conduction time of the switch SW1 is before the conduction time of the switch SW2.

6. The power supply detection circuit according to claim 3, wherein: Both the current source Isource1 and the current source Isource2 are turned on in a manner of gradually increasing to a set value with a rising slope, and both the current source Isource1 and the current source Isource2 are turned off in a manner of gradually decreasing to zero with a falling slope.

7. A power supply detection method for the power supply detection circuit according to claim 3, characterized in that It includes the following steps: First Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter transitions from a logic low level to a logic high level, thereby turning on the switch SW1, causing the current IVIN flowing into the VIN pin of the power supply controller U1 to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a weak voltage source, the signal VIN starts to be significantly pulled down by the current IVIN and the drop amplitude exceeds Reference3*K, where K is the voltage division ratio of the voltage divider and filter circuit Divider&Filter. At time T2, the T2 terminal of the timer Counter transitions from a logic low level to a logic high level. At this time, it is detected that the drop amplitude of the signal VIN exceeds Reference3*K, causing the signal STATE1 to transition from a logic low level to a logic high level, enabling the power control circuit and delivering a switching waveform to the GATE pin of the power supply controller U1, and turning on the switch SW0, enabling the voltage clamping of the signal VCOMP output by the error amplifier module EA, causing the power control loop to operate in a set limited state. At time T3, the T3 terminal of the timer Counter transitions from a logic level to a logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, with a fall time of tm2. Because the signal STATE1 flips to a logic high level at time T2, the detection circuit for the signal STATE2 is not enabled, thereby causing the signal STATE2 to be constantly at a logic low level. Second Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a high-capability voltage source, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from logic low level to logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at logic low level, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from logic level to logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm2. At time T4, the T4 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope to be equal to the current of the current source Isource2, and the rise time is tm3. At this time, since the state of the signal VIN connected to the input voltage source is a weak connection state and there is a large connection impedance on the connection path, the voltage of the signal VIN starts to be significantly pulled down by the current IVIN, and the drop amplitude exceeds Reference4*K. At time T5, the T5 terminal of the timer Counter changes from logic low level to logic high level. It is detected that the drop amplitude of the signal VIN exceeds Reference4*K, causing the signal STATE2 to remain at logic low level, still not enabling the power control circuit and delivering a switching waveform to the GATE pin of the power controller U1. At time T6, the T6 terminal of the timer Counter changes from logic low level to logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm4; Third Schematic Waveform: At time T0, the signal VIN powers on and stabilizes, and the timer Counter starts to work. By time T1, the T1 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW1, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource1, with a rise time of tm1. At this time, since the source connected to the power supply system is a high-capacity voltage source, the signal VIN starts to be slightly pulled down by the current IVIN, and the drop amplitude does not exceed Reference3*K. At time T2, the T2 terminal of the timer Counter changes from logic low level to logic high level. At this time, it is detected that the drop amplitude of the signal VIN does not exceed Reference3*K, causing the signal STATE1 to remain at logic low level, still not enabling the power control circuit and sending a switching waveform to the GATE pin of the power controller U1. At time T3, the T3 terminal of the timer Counter changes from logic level to logic high level, thereby turning off the switch SW1, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm2. At time T4, the T4 terminal of the timer Counter changes from logic low level to logic high level, thereby turning on the switch SW2, causing the current IVIN to gradually increase with a rising slope until it equals the current of the current source Isource2, and the rise time is tm3. At this time, since the signal VIN is in good contact with the input voltage source and there is no large impedance on the connection path, the voltage of the signal VIN starts to be slightly pulled down by IVIN, and the drop amplitude does not exceed Reference4*K. At time T5, the T5 terminal of the timer Counter changes from logic low level to logic high level. It is detected that the drop amplitude of the signal VIN does not exceed Reference4*K, causing the signal STATE2 to change from logic low level to logic high level, thereby enabling the power control circuit and sending a switching waveform to the GATE pin of the power controller U1. At the same time, since the signal STATE1 is still at logic low level, it does not enable the voltage clamping of the signal VCOMPD output by the error amplifier module EA, and the power control loop is not limited by clamping. At time T6, the T6 terminal of the timer Counter changes from logic low level to logic high level, thereby turning off the switch SW2, and the current IVIN gradually returns to zero with a falling slope, and the fall time is tm4; The input voltage divider and filter circuit Divider&Filter divides the signal VIN and filters out high-frequency disturbances through filtering, and outputs a processable signal VIN_DET; the sample and hold module Sample&Hold samples the signal VIN_DET before the switch SW1 conducts and / or before the switch SW2 conducts, and holds the sampled value VHOLD after the switch SW1 conducts and / or after the switch SW2 conducts; the held sampled value VHOLD generates a reference voltage for the detection state through the subtractor Subtractor1 and the subtractor Subtractor2 respectively, which are used as the reference voltages for the comparator CMP4 and the comparator CMP5 respectively; the time waited for the signals T1 to T6 generated by the T1 to T6 terminals of the timer Counter to flip from logic low level to logic high level increases sequentially; the conduction time of the switch SW1 is before the conduction time of the switch SW2, and the current sources Isource1 and Isource2 are enabled respectively to pull down the current to detect the power supply state and the connection state of the VIN pin of the power supply controller U1. The detection duration is set by the timer Counter. The current sources Isource1 and Isource2 are both turned on in an ascending slope gradually to the set value, and the current sources Isource1 and Isource2 are both turned off in a descending slope gradually to zero; when the signal STATE1 is at a high logic level, the conduction of the switch SW2 and the detection of the external state of the VIN pin of the power supply controller U1 by the current source Isource2 pulling down the current are not enabled.

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