A method, device and medium for simulating a static var generator

Abstract

This invention discloses a method, apparatus, and medium for simulating a static var generator (SVA). The method includes: constructing a constant voltage control model, a constant reactive power control model, a fault ride-through control model, a grid disconnection protection model, and a mode switching control model; constructing a SVA simulation model based on these models; and outputting reactive current to the grid equipment according to the specified voltage or reactive power control target and input control parameters, based on the SVA simulation model, wherein the grid equipment operates stably based on the reactive current.

Description

Technical Field

[0001] This invention relates to the field of power grid simulation technology, and more specifically, to a method, apparatus, and medium for simulating a static var generator. Background Technology

[0002] With the increasing proportion of wind power, photovoltaic, and other new energy installations in my country's total installed capacity, and the substantial construction of numerous energy bases in barren and desert areas, the issue of grid voltage stability has become prominent. Static var generators (SVAs), as third-generation reactive power compensation devices, are widely used in new energy power plants and substations, playing a crucial role in mitigating voltage fluctuations and improving grid stability.

[0003] To assess the effectiveness of equipment and ensure its safe and stable operation after grid connection, electromechanical transient simulation analysis of large power grids is essential as a crucial basis for understanding power grid characteristics, analyzing planning schemes, verifying defense measures, and specifying operating modes.

[0004] Accurate simulation models are fundamental to power grid simulation. However, existing static var generator (SVR) simulation models are primarily based on theoretical models, which differ significantly from actual systems. Furthermore, there are numerous manufacturers of SVRs, and even within the same manufacturer, various unit models exist. These different manufacturers and models exhibit substantial differences in their output characteristics under grid voltage dips. Modeling based solely on a specific model cannot reflect the grid connection characteristics of these different manufacturers and signal units, failing to meet the accuracy requirements of power system modeling and simulation. Conversely, establishing separate simulation models for each specific model would significantly increase the workload and complexity of the modeling process.

[0005] Therefore, there is an urgent need to establish a simulation model and system for the static var generator (SVM) of new energy power plants that balances accuracy and versatility. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a method, apparatus, and medium for simulating a static var generator.

[0007] According to one aspect of the present invention, a method for simulating a static var generator is provided, comprising:

[0008] Construct constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model;

[0009] A simulation model of a static var generator is constructed based on constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model.

[0010] Based on the static var generator simulation model, according to the specified voltage or reactive power control target and the input control parameters, the reactive current is output to the grid equipment, and the grid equipment operates stably based on the reactive current.

[0011] Optionally, the constant voltage control model is configured with a first measurement stage, a first dead zone stage, a first phase correction stage, a first PI control stage, a first limiting control stage, a first output stage, and a parallel distribution control stage in sequence according to the signal control transmission direction.

[0012] Optionally, the first measurement stage includes a first delay stage, a first inertial stage, and a first adder stage, wherein...

[0013] The transfer function of the first delay element is:

[0014] G delay_V (s)=e -Ts

[0015] The expression function for the first inertial element is:

[0016] dV FILTER / dt=(V DELAY -V FILTER ) / T 1V

[0017] The expression function for the first adder stage is:

[0018] V ERR =V REF -V FILTER

[0019] In the formula, V is the control node voltage, V DELAY For the output of the delay circuit, V FILTER For the output of the inertial element, T S T is the time constant of the delay element. 1V V is the time constant of the inertial element. REF For the target voltage, V ERR For voltage deviation, T S The time constant of the delay element;

[0020] The expression function for the first dead zone is:

[0021]

[0022] In the formula, V DB For voltage dead-time output, DB NV For the negative dead zone threshold, DB PV As the positive dead zone threshold, MAX V For positive dead zone limiting, MIN V For negative dead zone limiting;

[0023] The first phase correction stage includes two lead-lag stages. The expression function of the lead-lag stage consists of two parts. The first part is:

[0024]

[0025] The second part is:

[0026]

[0027] In the formula, V IN The input is for the lead-lag system, where V is the input for the first lead-lag system. DB The second lead-lag element is the output of the first lead-lag element, V. L_D V is an intermediate variable in the lead-lag process. LD For the output of the lead-lag link, T C T is the lead time constant. D V is the time lag constant. MAX For positive voltage limiting, V MIN For negative voltage limiting;

[0028] The expression function of the first PI control stage is:

[0029]

[0030] In the formula, K PV For proportional gain, T PV K is the inertial time constant. IV For integral gain, I PI_V For the output of the PI circuit, I PV For the proportional circuit output, I IV For the output of the integral stage, I CMAX For positive limiting, I LMAX Negative amplitude limiting;

[0031] The expression function for the first limiting stage is:

[0032]

[0033] In the formula, I LIMIT_V Output for the limiting stage;

[0034] The expression function for the first output stage is:

[0035]

[0036] In the formula, T SV To output the time constant of the inertial element, I Q For the device's output current;

[0037] The expression function of the parallel distribution control loop is:

[0038] I D =K D *I Q

[0039] In the formula, K D I is the allocation coefficient. D This is the feedback current.

[0040] Optionally, the constant reactive power control model is configured with a second measurement stage, a second dead zone stage, a second phase correction stage, a second PI control stage, a second limiting stage, and a second output stage in sequence according to the control transmission direction of the signal.

[0041] Optionally, the second measurement step includes:

[0042] Second delay stage transfer function:

[0043] G delay_Q (s)=e -Ts

[0044] The expression function for the second inertial element is:

[0045] dQ FILTER / dt=(Q DELAY -Q FILTER ) / T 1Q

[0046] The expression function for the second adder stage is:

[0047] Q ERR =Q REF -Q FILTER

[0048] In the formula, Q represents the reactive power of the control node, and T... S T is the time constant of the delay element. 1Q Q is the time constant of the inertial element. FILTER For the output of the inertial element, Q REF Unsuccessful in achieving the goal, Q ERR This is reactive power deviation;

[0049] The expression function for the second dead zone is:

[0050]

[0051] In the formula, Q DB For voltage dead-time output, DB NQ For the negative dead zone threshold, DB PQ As the positive dead zone threshold, MAX Q For positive dead zone limiting, MIN QFor negative dead zone limiting;

[0052] The second phase correction stage includes two lead-lag stages. The expression function of the lead-lag stage consists of two parts. The first part is:

[0053]

[0054] The second part is:

[0055]

[0056] In the formula, Q LQ The output is for the lead-lag element, where Q is the output for the first lead-lag element. DB The second lead-lag element is the output of the first lead-lag element, V. L_D V is an intermediate variable in the lead-lag process. LD For the output of the lead-lag link, T C T is the lead time constant. D Q is the time lag constant. MAX For positive voltage limiting, Q MIN For negative voltage limiting;

[0057] The expression function of the second PI control stage is:

[0058]

[0059] In the formula, K PQ For proportional gain, T PQ K is the inertial time constant. IQ For integral gain, I PQ For the proportional circuit output, I IQ For the output of the integral stage, I PI_Q For the PI stage output;

[0060] The expression function for the second limiting stage is:

[0061]

[0062] In the formula, I LIMIT_Q This is the output for the second limiting stage;

[0063] The expression function for the second output stage is:

[0064]

[0065] In the formula, T SQ To output the time constant of the inertial element, I Q This is the output current of the device.

[0066] Optionally, the fault ride-through control model includes: a reactive current calculation model during low-voltage ride-through.

[0067] I Q_LVRT =K 1_LV (V IN_LV -V T )+K 2_LV *I Q0 +K 3_LV *Q SET / V T +K 4_LV *I QSET_LV

[0068] In the formula, I Q_LVRT For low-voltage output reactive current, K 1_LV K 2_LV K 3_LV K 4_LV V is the calculation factor for low-voltage reactive current. IN_LV For calculating the reference voltage for low-through reactive current, I Q0 Q is the initial reactive current. SET No results were achieved for the target, I QSET_LV Low-pass reactive current setting value;

[0069] Reactive current calculation model during high voltage ride-through:

[0070] I Q_HVRT =K 1_HV (V IN_HV -V T )+K 2_HV *I Q0 +K 3_HV *Q SET / V T +K 4_HV *I QSET_HV

[0071] In the formula, I Q_HVRT To achieve high-voltage output reactive current, K 1_HV K 2_HV K 3_HV K 4_LV V is the calculation factor for high-voltage reactive current. IN_HV For calculating the reference voltage for high-voltage reactive current, I QSET_HV High-voltage reactive current setting value;

[0072] Reactive current tripping modes include instantaneous tripping, constant-time tripping, and constant-slope tripping:

[0073] Instantaneous action: The next simulation step action after the fault crossing action is completed;

[0074] Fixed timeout: The action is completed within the specified timeout period after the fault crossing action;

[0075] Fixed slope: After the fault crossing action, the action is completed according to the specified slope.

[0076] Optionally, the disconnection protection model is used to disconnect the device from the network based on the actual device's disconnection protection curve, when the device's access point voltage is lower than a specified voltage and the duration is greater than a specified time requirement.

[0077] Optionally, the mode switching control employs a priority algorithm to implement multiple mode switching controls. The priority of the algorithm is as follows: the grid disconnection protection model has the highest priority, followed by the fault ride-through control model, then the constant voltage control model, and the constant reactive power control model has the lowest priority.

[0078] When simulating the constant reactive power control model throughout the entire process, the positive threshold of the constant reactive power and constant voltage control model is set to the maximum value, and the negative threshold is set to negative.

[0079] When simulating the constant voltage control model throughout the entire process, the constant reactive power control model is directly disabled.

[0080] When simulating the combined voltage control of the reactive power control model and the constant voltage control model, hysteresis control is used to switch between the constant reactive power control model and the constant voltage control model.

[0081] According to another aspect of the present invention, a static var generator simulation device is provided, comprising:

[0082] The first building module is used to build constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model and mode switching control model;

[0083] The second building module is used to construct a static var generator simulation model based on the constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model.

[0084] The simulation module is used to output reactive current to the grid equipment based on the static var generator simulation model, according to the specified voltage or reactive power control target and the input control parameters. The grid equipment operates stably based on the reactive current.

[0085] According to another aspect of the present invention, a computer-readable storage medium is provided, the storage medium storing a computer program for performing the methods described in any of the above aspects of the present invention.

[0086] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the method described in any of the preceding aspects of the present invention.

[0087] Therefore, the method proposed in this invention establishes a high-precision static var generator (SVM) simulation method that balances accuracy and practicality. It can accurately describe the SVM's operating characteristics under different application scenarios and different disturbance conditions, while also taking into account the ease of use of the model and greatly simplifying the modeling process. Attached Figure Description

[0088] Exemplary embodiments of the present invention can be more fully understood by referring to the following figures:

[0089] Figure 1 This is a flowchart illustrating a static var generator simulation method provided in an exemplary embodiment of the present invention.

[0090] Figure 2 This is a schematic diagram of a static var generator model provided in an exemplary embodiment of the present invention;

[0091] Figure 3 This is a schematic diagram of a constant voltage control model provided in an exemplary embodiment of the present invention;

[0092] Figure 4 This is a schematic diagram of the first measurement step provided in an exemplary embodiment of the present invention;

[0093] Figure 5 This is a schematic diagram of the first dead zone segment provided in an exemplary embodiment of the present invention;

[0094] Figure 6 This is a schematic diagram of the first phase correction stage provided in an exemplary embodiment of the present invention;

[0095] Figure 7 This is a schematic diagram of the first PI control loop provided in an exemplary embodiment of the present invention;

[0096] Figure 8 This is a schematic diagram of the first limiting stage provided in an exemplary embodiment of the present invention;

[0097] Figure 9 This is a schematic diagram of the first output stage provided in an exemplary embodiment of the present invention;

[0098] Figure 10 This is a schematic diagram of a parallel distribution control loop provided in an exemplary embodiment of the present invention;

[0099] Figure 11This is a schematic diagram of a constant reactive power control model provided in an exemplary embodiment of the present invention;

[0100] Figure 12 This is a schematic diagram of the second measurement step provided in an exemplary embodiment of the present invention;

[0101] Figure 13 This is a schematic diagram of the second dead zone segment provided in an exemplary embodiment of the present invention;

[0102] Figure 14 This is a schematic diagram of the second phase correction stage provided in an exemplary embodiment of the present invention;

[0103] Figure 15 This is a schematic diagram of the second PI control loop provided in an exemplary embodiment of the present invention;

[0104] Figure 16 This is a schematic diagram of the second limiting stage provided in an exemplary embodiment of the present invention;

[0105] Figure 17 This is a schematic diagram of the second output stage provided in an exemplary embodiment of the present invention;

[0106] Figure 18 This is a geographical wiring diagram of a single-machine infinite bus system provided in an exemplary embodiment of the present invention;

[0107] Figure 19 This is a schematic diagram comparing constant reactive power control voltage provided by an exemplary embodiment of the present invention;

[0108] Figure 20 This is a schematic diagram of constant reactive power control reactive power comparison provided by an exemplary embodiment of the present invention;

[0109] Figure 21 This is a schematic diagram of constant voltage control voltage comparison provided by an exemplary embodiment of the present invention;

[0110] Figure 22 This is a schematic diagram of constant voltage control reactive power comparison provided by an exemplary embodiment of the present invention;

[0111] Figure 23 This is a schematic diagram comparing fault ride-through control voltages provided in an exemplary embodiment of the present invention;

[0112] Figure 24 This is a schematic diagram of reactive power comparison for fault ride-through control provided in an exemplary embodiment of the present invention;

[0113] Figure 25 This is a schematic diagram of the structure of a static var generator simulation device provided in an exemplary embodiment of the present invention;

[0114] Figure 26This is the structure of an electronic device provided in an exemplary embodiment of the present invention. Detailed Implementation

[0115] Hereinafter, exemplary embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments of the present invention. It should be understood that the present invention is not limited to the exemplary embodiments described herein.

[0116] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of the invention.

[0117] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of the present invention are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0118] It should also be understood that in the embodiments of the present invention, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0119] It should also be understood that any component, data or structure mentioned in the embodiments of the present invention can generally be understood as one or more unless explicitly defined or given contrary instructions in the context.

[0120] Furthermore, the term "and / or" in this invention is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this invention generally indicates that the preceding and following related objects have an "or" relationship.

[0121] It should also be understood that the description of the various embodiments in this invention emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0122] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0123] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the invention or its application or use.

[0124] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, they should be considered part of the specification.

[0125] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0126] The embodiments of this invention can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Well-known examples of terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0127] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0128] Exemplary methods

[0129] Figure 1 This is a flowchart illustrating a static var generator simulation method provided in an exemplary embodiment of the present invention. This embodiment can be applied to electronic devices, such as... Figure 1 As shown, the static var generator simulation method 100 includes the following steps:

[0130] Step 101: Construct constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model;

[0131] Step 102: Based on the constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model, construct a static var generator simulation model.

[0132] Step 103: Based on the static var generator simulation model, according to the specified voltage or reactive power control target and the input control parameters, output reactive current to the grid equipment, wherein the grid equipment operates stably based on the reactive current.

[0133] Specifically, a generalized simulation model and system for the static var generator (SVM) operating characteristics in new energy power plants will be established, taking into account both accuracy and versatility. This model and system can accurately simulate the operating characteristics of SVM under different application scenarios and disturbance conditions, improve the accuracy of power grid simulation, and help achieve the "dual carbon" target.

[0134] refer to Figure 2 As shown, the overall approach is as follows: The static var generator model ignores the dynamic characteristics of the device's d-axis and does not consider DC voltage control. It performs a detailed simulation of the dynamic characteristics of the q-axis and supports four different operating modes: constant voltage control, constant reactive power control, fault ride-through control, and grid disconnection protection. Different operating modes can be switched under certain conditions (see Mode Switching Control for details). Figure 2 In this context, VHmax is the high-voltage grid disconnection threshold, VHmin is the high-voltage ride-through threshold, Vd+ is the constant reactive power to constant voltage high-voltage threshold, Vd- is the constant reactive power to constant voltage low-voltage threshold, VLmax is the low-voltage ride-through threshold, and VLmin is the low-voltage grid disconnection voltage threshold.

[0135] 1) Constant voltage control model

[0136] refer to Figure 3 As shown, the constant voltage control model includes: a first measurement stage, a first dead zone stage, a first phase correction stage, a first PI control stage, a first limiting stage, a first output stage, and a parallel distribution control stage.

[0137] (1)Reference Figure 4 As shown, the first measurement stage is used to simulate the delay and smoothing characteristics in the actual equipment measurement process. It is based on a pure delay stage and a first-order inertial stage, with a typical time constant of 0.01s.

[0138] The transfer function of the first delay element is:

[0139] G delay_V (s)=e -Ts

[0140] The expression function of the first inertial element is:

[0141] dV FILTER / dt=(V DELAY -V FILTER ) / T 1V

[0142] The expression function of the first adder stage is:

[0143] V ERR =V REF -V FILTV

[0144] In the formula, V is the control node voltage, V DELAY For the output of the delay circuit, V FILTER For the output of the inertial element, T S T is the time constant of the delay element. 1V V is the time constant of the inertial element. REF For the target voltage, V ERR s represents the voltage deviation, and s is the integration factor.

[0145] (2)Reference Figure 5 As shown, the first dead zone stage is used to simulate the dead zone control of actual equipment. To ensure the versatility of this stage, a dead zone control stage can be simulated based on the positive and negative dead zones and the amplitude limiting dead zones.

[0146]

[0147] In the formula, V DB For voltage dead-time output, DB NV For the negative dead zone threshold, DB PV As the positive dead zone threshold, MAX V For positive dead zone limiting, MIN V This is a negative dead zone limiter.

[0148] (3)Reference Figure 6 As shown, in the first phase correction stage, the actual equipment phase has a correction condition of 180°. A single lead-lag stage can only correct 90°. This stage is simulated based on two lead-lag stages.

[0149] The expression function for the lead-lag element is:

[0150]

[0151]

[0152] In the formula, V IN Input for the lead-lag element (V for the first lead-lag element) DB The second lead-lag element is the output of the first lead-lag element), V L_D V is an intermediate variable in the lead-lag process. LD For the output of the lead-lag link, T C T is the lead time constant. D V is the time lag constant. MAX For positive voltage limiting, V MIN This is a negative voltage limiting measure.

[0153] (4)Reference Figure 7As shown, the first PI control element is used to simulate the control function of the actual device's regulator, and the simulation is based on proportional and integral elements. Power electronic equipment operates at high speeds, resulting in a small stability region in the simulation. Therefore, a first-order inertial element is added to the integral element based on pure proportional control to improve the numerical stability in the simulation.

[0154]

[0155] In the formula, K PV For proportional gain, T PV K is the inertial time constant. IV For integral gain, I PI_V For the output of the PI circuit, I PV For the proportional circuit output, I IV For the output of the integral stage, I CMAX For positive limiting, I LMAX This is a negative amplitude limit.

[0156] (5)Reference Figure 8 As shown, the first limiting stage is used to simulate the inner current loop limiting of actual equipment. To ensure the universality of this stage, the simulation is based on bidirectional asymmetric limiting.

[0157]

[0158] In the formula, I LIMIT_V This is the output for the amplitude limiting stage.

[0159] (6)Reference Figure 9 As shown, the first output stage is used to simulate the delay and smoothing effect generated during the modulation process of the actual device converter. The simulation is based on pure delay and first-order inertia, with a typical time constant of 0.01s.

[0160]

[0161] In the diagram, T SV To output the time constant of the inertial element, I Q This is the output current of the device.

[0162] (7)Reference Figure 10 As shown, the parallel distribution control loop is used to simulate the reactive power distribution control between static var generators connected to the same grid connection point, and the simulation is based on feedback control with a specified slope.

[0163] I D =K D *I Q

[0164] In the diagram, K D I is the allocation coefficient. D This is the feedback current.

[0165] 2) Constant reactive power control model

[0166] refer to Figure 11 As shown, the constant voltage control model includes: measurement stage, dead zone stage, phase correction stage, PI control stage, limiting stage, output stage, and parallel distribution control stage.

[0167] (1)Reference Figure 12 As shown, the second measurement stage is used to simulate the delay and smoothing characteristics in the actual equipment measurement process. It is based on a pure delay stage and a first-order inertial stage, with a typical time constant of 0.01s.

[0168] The transfer function of the delay element is:

[0169] G delay_Q (s)=e -Ts

[0170] The expression function for the inertial element is:

[0171] dQ FILTER / dt=(Q DELAY -Q FILTER ) / T 1Q

[0172] The expression function for the adder stage is:

[0173] Q ERR =Q REF -Q FILTER

[0174] In the diagram, Q represents the reactive power of the control node, and T... S T is the time constant of the delay element. 1Q Q is the time constant of the inertial element. REF Unsuccessful in achieving the goal, Q ERR This is reactive power deviation.

[0175] (2)Reference Figure 13 As shown, the second dead zone is used to simulate the dead zone control of actual equipment. To ensure the versatility of this zone, a dead zone control zone simulation is performed based on the positive and negative dead zones and the amplitude limiting dead zones, which can be set separately.

[0176]

[0177] In the formula, Q DB For voltage dead-time output, DB NQ For the negative dead zone threshold, DB PQ As the positive dead zone threshold, MAX Q For positive dead zone limiting, MIN Q This is a negative dead zone limiter.

[0178] (3)Reference Figure 14 As shown, in the second phase correction stage, the actual equipment phase has a correction condition of 180°. A single lead-lag stage can only correct 90°. This stage is simulated based on two lead-lag stages.

[0179] The expression function for the lead-lag element is:

[0180]

[0181] In the formula, Q LQ The output of the lead-lag element (Q for the first lead-lag element) is... DB The second lead-lag element is the output of the first lead-lag element), V L_D V is an intermediate variable in the lead-lag process. LD For the output of the lead-lag link, T C T is the lead time constant. D Q is the time lag constant. MAX For positive voltage limiting, Q MIN This is a negative voltage limiting measure.

[0182] (4)Reference Figure 15 As shown, the second PI control element is used to simulate the control function of the actual device's regulator, and the simulation is based on proportional and integral elements. Power electronic equipment operates at high speeds, resulting in a small stability region in the simulation. Therefore, a first-order inertial element is added to the integral element based on pure proportional control to improve the numerical stability in the simulation.

[0183]

[0184] In the diagram, K PQ For proportional gain, T PQ K is the inertial time constant. IQ For integral gain, I PQ For the proportional circuit output, I IQ For the output of the integral stage, I PI_Q This is the output of the PI stage.

[0185] (5)Reference Figure 16 As shown, the second limiting stage is used to simulate the inner current loop limiting of actual equipment. To ensure the universality of this stage, the simulation is based on bidirectional asymmetric limiting.

[0186]

[0187] In the formula, I LIMIT_Q This is the output of the second limiting stage.

[0188] (6)Reference Figure 17As shown, the second output stage is used to simulate the delay and smoothing effect generated during the modulation process of the actual device converter. The simulation is based on pure delay and first-order inertia, with a typical time constant of 0.01s.

[0189]

[0190] In the formula, T SQ This is to output the time constant of the inertial element.

[0191] 3) Fault ride-through control model

[0192] The actual device has complex control logic, but during fault ride-through, the equipment has the characteristic of responding in milliseconds and acting extremely fast.

[0193] The simulation is based on open-loop control. That is, according to the control strategy adopted by the equipment and the current simulation step size, the target current is calculated and directly output, without considering the influence of other components on the dynamic characteristics.

[0194] The control is based on the positive sequence fundamental component, ignoring the second harmonic component, and the reactive power command current can be calculated using the following mode.

[0195] (1) Calculation model for reactive current during low voltage ride-through

[0196] I Q_LVRT =K 1_LV (V IN_LV -V T )+K 2_LV *I Q0 +K 3_LV *Q SET / V T +K 4_LV *I QSET_LV

[0197] In the formula, I Q_LVRT For low-voltage output reactive current, K 1_LV K 2_LV K 3_LV K 4_LV V is the calculation factor for low-voltage reactive current. IN_LV For calculating the reference voltage for low-through reactive current, I Q0 Q is the initial reactive current. SET No results were achieved for the target, I QSET_LV Low-pass reactive current setting value.

[0198] (2) Calculation model for reactive current during high voltage ride-through

[0199] I Q_HVRT =K 1_HV (V IN_HV -V T)+K 2_HV *I Q0 +K 3_HV *Q SET / V T +K 4_HV *I QSET_HV

[0200] In the formula, I Q_HVRT To achieve high-voltage output reactive current, K 1_HV K 2_HV K 3_HV K 4_LV V is the calculation factor for high-voltage reactive current. IN_HV For calculating the reference voltage for high-voltage reactive current, I QSET_HV High-voltage reactive current setting value.

[0201] (3) Reactive current operating modes include instantaneous operation, constant-time operation, and constant-slope operation:

[0202] Instantaneous action: The next simulation step action after the fault crossing action is in place.

[0203] Fixed timeout: The action is completed within the specified timeout period after the fault crossing action.

[0204] Fixed slope: After the fault crossing action, the action is completed according to the specified slope.

[0205] 4) Off-grid protection model

[0206] According to the actual equipment's disconnection protection curve, the equipment will disconnect from the network when the voltage at the equipment's access point is lower than the specified voltage and the duration is longer than the specified time requirement.

[0207] In the simulation, the interval between different voltage values ​​can be smoothed by linear interpolation, and the equipment disconnection from the grid can be simulated by injecting grid current into the locked equipment.

[0208] 5) Mode switching control

[0209] Based on mode switching control, it should be able to simulate full-range constant reactive power control, full-range constant voltage control (the two are collectively referred to as normal control), and comprehensive reactive power and voltage control, and be compatible with fault ride-through and grid disconnection protection control logic according to the voltage range.

[0210] The compatibility between different control modes is achieved using a priority algorithm: grid disconnection protection has the highest priority, followed by fault ride-through control, then constant voltage control, and constant reactive power control has the lowest priority.

[0211] When simulating full-process constant reactive power control, set the positive threshold for constant reactive power and constant voltage control switching to a maximum value (e.g., 999.pu) and the negative threshold to a negative value (e.g., -1.pu).

[0212] When simulating constant voltage control throughout the entire process, the constant reactive power control mode is directly disabled.

[0213] When simulating integrated reactive power and voltage control, the switching between reactive power and voltage uses hysteresis control. The hysteresis control logic is as follows:

[0214] Taking high-voltage switching as an example: For high-voltage constant reactive power switching to constant voltage switching, the node voltage must be higher than (1) the high-voltage threshold of constant reactive power switching to constant voltage switching superimposed with the hysteresis width (2) and the duration must be greater than the specified time before it can switch from constant reactive power to constant voltage. If the voltage or current fails to meet the above two conditions at the same time during the period, the switching will not be performed. In actual modeling, the hysteresis width and the specified time value can be 0.

[0215] The low-voltage switching logic is similar.

[0216] Hysteresis control can also be used to switch between normal control (constant reactive power / constant voltage control) and fault ride-through control.

[0217] 6) Model matching

[0218] The established model encompasses the main operational logic of mainstream models from domestic equipment manufacturers. During modeling, based on this model and the equipment's operational curves, parameter fitting was performed, ultimately forming a block diagram with multiple sets of parameters simulating the static var generators of different manufacturers and models.

[0219] In one embodiment of the present invention, the method proposed in this invention has been implemented in the power system simulation software PSD-BPA. This paper illustrates the model effect based on a single-machine infinite bus model, wherein the SVG is installed at node Hualurui Y1, and the geographical wiring diagram is as follows. Figure 18 As shown.

[0220] Comparison of constant reactive power control:

[0221] The model uses constant reactive power control. A three-phase short-circuit fault is simulated at the Hualurui bus, causing the bus voltage to drop to 0.8 pu. The simulation results are compared with the waveforms recorded by the actual device. Figure 19 and Figure 20 As shown, the simulation results are basically consistent with the recorded waveforms.

[0222] Comparison of constant voltage control:

[0223] The model uses constant voltage control. A three-phase short-circuit fault is simulated on the Hualurui busbar, causing the busbar voltage to drop to 0.8 pu. The simulation results are compared with the waveforms recorded by the actual device. Figure 21 and Figure 22 As shown, the simulation results are basically consistent with the recorded waveforms.

[0224] Fault Trip Control Comparison

[0225] The model selects constant voltage or constant reactive power control, sets a fault on the Hualurui bus, and causes the fault point voltage to first drop to 0.2 pu and then rise to 1.3 pu. The simulation results are compared with the waveforms recorded by the actual device. Figure 23 and Figure 24 As shown, the simulation results are basically consistent with the recorded waveforms.

[0226] The results of the comparison under various working conditions show that the simulation method proposed in this patent can accurately simulate the action characteristics of equipment under different working conditions, and has high accuracy and good versatility.

[0227] Therefore, the method proposed in this invention establishes a high-precision static var generator (SVM) simulation method that balances accuracy and practicality. It can accurately describe the SVM's operating characteristics under different application scenarios and different disturbance conditions, while also taking into account the ease of use of the model and greatly simplifying the modeling process.

[0228] Exemplary device

[0229] Figure 25 This is a schematic diagram of the structure of a static var generator simulation device provided in an exemplary embodiment of the present invention. Figure 25 As shown, the device 2500 includes:

[0230] The first construction module 2510 is used to construct a constant voltage control model, a constant reactive power control model, a fault ride-through control model, a grid disconnection protection model, and a mode switching control model.

[0231] The second building module 2520 is used to build a static var generator simulation model based on the constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model and mode switching control model.

[0232] The simulation module 2530 is used to output reactive current to the grid equipment based on the static var generator simulation model, according to the specified voltage or reactive power control target and the input control parameters, wherein the grid equipment operates stably based on the reactive current.

[0233] Optionally, the constant voltage control model is configured with a first measurement stage, a first dead zone stage, a first phase correction stage, a first PI control stage, a first limiting control stage, a first output stage, and a parallel distribution control stage in sequence according to the signal control transmission direction.

[0234] Optionally, the first measurement stage includes a first delay stage, a first inertial stage, and a first adder stage, wherein...

[0235] The transfer function of the first delay element is:

[0236] G delay_V(s)=e -Ts

[0237] The expression function for the first inertial element is:

[0238] dV FILTER / dt=(V DELAY -V FILTER ) / T 1V

[0239] The expression function for the first adder stage is:

[0240] V ERR =V REF -V FILTER

[0241] In the formula, V is the control node voltage, V DELAY For the output of the delay circuit, V FILTER For the output of the inertial element, T S T is the time constant of the delay element. 1V V is the time constant of the inertial element. REF For the target voltage, V ERR For voltage deviation, T S The time constant of the delay element;

[0242] The expression function for the first dead zone is:

[0243]

[0244] In the formula, V DB For voltage dead-time output, DB NV For the negative dead zone threshold, DB PV As the positive dead zone threshold, MAX V For positive dead zone limiting, MIN V For negative dead zone limiting;

[0245] The first phase correction stage includes two lead-lag stages. The expression function of the lead-lag stage consists of two parts. The first part is:

[0246]

[0247] The second part is:

[0248]

[0249] In the formula, V IN The input is for the lead-lag system, where V is the input for the first lead-lag system. DB The second lead-lag element is the output of the first lead-lag element, V. L_D V is an intermediate variable in the lead-lag process. LDFor the output of the lead-lag link, T C T is the lead time constant. D V is the time lag constant. MAX For positive voltage limiting, V MIN For negative voltage limiting;

[0250] The expression function of the first PI control stage is:

[0251]

[0252]

[0253] In the formula, K PV For proportional gain, T PV K is the inertial time constant. IV For integral gain, I PI_V For the output of the PI circuit, I PV For the proportional circuit output, I IV For the output of the integral stage, I CMAX For positive limiting, I LMAX Negative amplitude limiting;

[0254] The expression function for the first limiting stage is:

[0255]

[0256] In the formula, I LIMIT_V Output for the limiting stage;

[0257] The expression function for the first output stage is:

[0258]

[0259] In the formula, T SV To output the time constant of the inertial element, I Q For the device's output current;

[0260] The expression function of the parallel distribution control loop is:

[0261] I D =K D *I Q

[0262] In the formula, K D I is the allocation coefficient. D This is the feedback current.

[0263] Optionally, the constant reactive power control model is configured with a second measurement stage, a second dead zone stage, a second phase correction stage, a second PI control stage, a second limiting stage, and a second output stage in sequence according to the control transmission direction of the signal.

[0264] Optionally, the second measurement step includes:

[0265] Second delay stage transfer function:

[0266] G delay_Q (s)=e -Ts

[0267] The expression function for the second inertial element is:

[0268] dQ FILTER / dt=(Q DELAY -Q FILTER ) / T 1Q

[0269] The expression function for the second adder stage is:

[0270] Q ERR =Q REF -Q FILTER

[0271] In the formula, Q represents the reactive power of the control node, and T... S T is the time constant of the delay element. 1Q Q is the time constant of the inertial element. FILTER For the output of the inertial element, Q REF Unsuccessful in achieving the goal, Q ERR This is reactive power deviation;

[0272] The expression function for the second dead zone is:

[0273]

[0274] In the formula, Q DB For voltage dead-time output, DB NQ For the negative dead zone threshold, DB PQ As the positive dead zone threshold, MAX Q For positive dead zone limiting, MIN Q For negative dead zone limiting;

[0275] The second phase correction stage includes two lead-lag stages. The expression function of the lead-lag stage consists of two parts. The first part is:

[0276]

[0277] The second part is:

[0278]

[0279] In the formula, Q LQ The output is for the lead-lag element, where Q is the output for the first lead-lag element. DBThe second lead-lag element is the output of the first lead-lag element, V. L_D V is an intermediate variable in the lead-lag process. LD For the output of the lead-lag link, T C T is the lead time constant. D Q is the time lag constant. MAX For positive voltage limiting, Q MIN For negative voltage limiting;

[0280] The expression function of the second PI control stage is:

[0281]

[0282] In the formula, K PQ For proportional gain, T PQ K is the inertial time constant. IQ For integral gain, I PQ For the proportional circuit output, I IQ For the output of the integral stage, I PI_Q For the PI stage output;

[0283] The expression function for the second limiting stage is:

[0284]

[0285] In the formula, I LIMIT_Q This is the output for the second limiting stage;

[0286] The expression function for the second output stage is:

[0287]

[0288] In the formula, T SQ To output the time constant of the inertial element, I Q This is the output current of the device.

[0289] Optionally, the fault ride-through control model includes: a reactive current calculation model during low-voltage ride-through.

[0290] I Q_LVRT =K 1_LV (V IN_LV -V T )+K 2_LV *I Q0 +K 3_LV *Q SET / V T +K 4_LV *I QSET_LV

[0291] In the formula, I Q_LVRT For low-voltage output reactive current, K 1_LVK 2_LV K 3_LV K 4_LV V is the calculation factor for low-voltage reactive current. IN_LV For calculating the reference voltage for low-through reactive current, I Q0 Q is the initial reactive current. SET No results were achieved for the target, I QSET_LV Low-pass reactive current setting value;

[0292] Reactive current calculation model during high voltage ride-through:

[0293] I Q_HVRT =K 1_HV (V IN_HV -V T )+K 2_HV *I Q0 +K 3_HV *Q SET / V T +K 4_HV *I QSET_HV

[0294] In the formula, I Q_HVRT To achieve high-voltage output reactive current, K 1_HV K 2_HV K 3_HV K 4_LV V is the calculation factor for high-voltage reactive current. IN_HV For calculating the reference voltage for high-voltage reactive current, I QSET_HV High-voltage reactive current setting value;

[0295] Reactive current tripping modes include instantaneous tripping, constant-time tripping, and constant-slope tripping:

[0296] Instantaneous action: The next simulation step action after the fault crossing action is completed;

[0297] Fixed timeout: The action is completed within the specified timeout period after the fault crossing action;

[0298] Fixed slope: After the fault crossing action, the action is completed according to the specified slope.

[0299] Optionally, the disconnection protection model is used to disconnect the device from the network based on the actual device's disconnection protection curve, when the device's access point voltage is lower than a specified voltage and the duration is greater than a specified time requirement.

[0300] Optionally, the mode switching control employs a priority algorithm to implement multiple mode switching controls. The priority of the algorithm is as follows: the grid disconnection protection model has the highest priority, followed by the fault ride-through control model, then the constant voltage control model, and the constant reactive power control model has the lowest priority.

[0301] When simulating the constant reactive power control model throughout the entire process, the positive threshold of the constant reactive power and constant voltage control model is set to the maximum value, and the negative threshold is set to negative.

[0302] When simulating the constant voltage control model throughout the entire process, the constant reactive power control model is directly disabled.

[0303] When simulating the combined voltage control of the reactive power control model and the constant voltage control model, hysteresis control is used to switch between the constant reactive power control model and the constant voltage control model.

[0304] Exemplary electronic devices

[0305] Figure 26 This is the structure of an electronic device provided in an exemplary embodiment of the present invention. For example... Figure 26 As shown, the electronic device 260 includes one or more processors 261 and memory 262.

[0306] The processor 261 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0307] Memory 262 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and processor 261 may execute the program instructions to implement the methods of the software programs of the various embodiments of the present invention described above, and / or other desired functions. In one example, the electronic device may also include an input device 263 and an output device 264, these components being interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0308] In addition, the input device 263 may also include, for example, a keyboard, a mouse, etc.

[0309] The output device 264 can output various information to the outside. The output device 264 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0310] Of course, for the sake of simplicity, Figure 26Only some of the components of this electronic device relevant to the present invention are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0311] Exemplary computer program products and computer-readable storage media

[0312] In addition to the methods and apparatus described above, embodiments of the present invention may also be computer program products, which include computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of the present invention described in the "Exemplary Methods" section above.

[0313] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of the present invention. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0314] Furthermore, embodiments of the present invention may also be computer-readable storage media storing computer program instructions thereon, which, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of the present invention described in the "Exemplary Methods" section above.

[0315] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0316] The basic principles of the present invention have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in the present invention are merely examples and not limitations, and should not be considered as essential features of each embodiment of the present invention. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the present invention to the necessity of employing the aforementioned specific details.

[0317] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0318] The block diagrams of devices, systems, devices, and systems involved in this invention are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, systems, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0319] The methods and systems of the present invention may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of the present invention are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, the present invention may also be implemented as a program recorded on a recording medium, the program comprising machine-readable instructions for implementing the methods according to the present invention. Thus, the present invention also covers recording media storing programs for performing the methods according to the present invention.

[0320] It should also be noted that in the systems, apparatus, and methods of the present invention, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered equivalents of the present invention. The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0321] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of the invention to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for simulating a static var generator, characterized in that, include: Construct constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model; Based on the constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model, a static var generator simulation model is constructed. Based on the aforementioned static var generator simulation model, and according to the specified voltage or reactive power control target, reactive current is output to the power grid equipment according to the input control parameters. The power grid equipment operates stably based on this reactive current. The mode switching control employs a priority algorithm to implement multiple mode switching controls. The priority of the algorithm is as follows: the grid disconnection protection model has the highest priority, followed by the fault ride-through control model, then the constant voltage control model, and the constant reactive power control model has the lowest priority. When simulating the constant reactive power control model throughout the entire process, the positive threshold of the constant reactive power and constant voltage control model is set to the maximum value, and the negative threshold is set to negative. When simulating the constant voltage control model throughout the entire process, the constant reactive power control model is directly disabled. When the voltage of the simulated horizontal reactive power control model and the constant voltage control model is combined for voltage control, hysteresis control is used to switch between the constant reactive power control model and the constant voltage control model.

2. The method according to claim 1, characterized in that, The constant voltage control model is configured with a first measurement stage, a first dead zone stage, a first phase correction stage, a first PI control stage, a first limiting stage, a first output stage, and a parallel distribution control stage in sequence according to the signal control transmission direction.

3. The method according to claim 2, characterized in that, The first measurement stage includes a first delay stage, a first inertial stage, and a first adder stage, wherein... The transfer function of the first delay element is: The expression function of the first inertial element is: The expression function of the first adder stage is: In the formula, V To control node voltage, V DELAY For the output of the delay stage, V FILTER For the output of the inertial element, T S The time constant of the delay element, T 1V The time constant of the inertial element, V REF For the target voltage, V ERR For voltage deviation, T S The time constant of the delay element; The expression function for the first dead zone is: In the formula, V DB For voltage dead-time output, DB NV For negative dead zone threshold, DB PV For positive dead zone threshold, MAX V For positive dead zone limiting, MIN V For negative dead zone limiting; The first phase correction stage includes two lead-lag stages, wherein the expression function of the lead-lag stage consists of two parts, the first part being: The second part is: In the formula, V IN The input for the lead-lag element is, where the first lead-lag element is... V DB The second lead-lag element is the output of the first lead-lag element. V L_D As intermediate variables in the lead-lag stage of the first measurement stage, V LD This is the output of the lead-lag stage in the first measurement stage. T C The lead time constant, T D The time lag constant is V MAX For positive voltage limiting, V MIN For negative voltage limiting; The expression function of the first PI control loop is: In the formula, K PV For proportional gain, T PV The inertial time constant, K IV For integral gain, I PI_V For the output of the PI stage, I PV For the output of the proportional circuit, I IV For the output of the integration stage, I CMAX For positive amplitude limiting, I LMAX Negative amplitude limiting; The expression function for the first limiting stage is: In the formula, I LIMIT_V Output for the limiting stage; The expression function of the first output stage is: In the formula, T SV To output the time constant of the inertial element, I Q For the device's output current; The expression function of the parallel allocation control loop is: In the formula, K D For allocation coefficients, I D This is the feedback current.

4. The method according to claim 3, characterized in that, The constant reactive power control model is configured with a second measurement stage, a second dead zone stage, a second phase correction stage, a second PI control stage, a second amplitude limiting stage, and a second output stage in sequence according to the control transmission direction of the signal.

5. The method according to claim 4, characterized in that, The second measurement step includes: Second delay stage transfer function: The expression function for the second inertial element is: The expression function for the second adder stage is: In the formula, Q To control the reactive power of the nodes, T S The time constant of the delay element, T 1Q The time constant of the inertial element, Q FILTER For the output of the inertial element, Q REF To achieve the goal without success Q ERR This is reactive power deviation; The expression function for the second dead zone is: In the formula, Q DB For voltage dead-time output, DB NQ For negative dead zone threshold, DB PQ For positive dead zone threshold, MAX Q For positive dead zone limiting, MIN Q For negative dead zone limiting; The second phase correction stage includes two lead-lag stages, wherein the expression function of the lead-lag stage consists of two parts, the first part being: The second part is: In the formula, Q LQ The output is for the lead-lag element, where the first lead-lag element is... Q DB The second lead-lag element is the output of the first lead-lag element. Q L_D As an intermediate variable in the lead-lag stage of the second measurement stage, Q LD This is the output of the lead-lag stage in the second measurement stage. T C The lead time constant, T D The time lag constant is Q MAX For positive voltage limiting, Q MIN For negative voltage limiting; The expression function of the second PI control loop is: In the formula, K PQ For proportional gain, T PQ The inertial time constant, K IQ For integral gain, I PQ For the output of the proportional circuit, I IQ For the output of the integration stage, I PI_Q For the PI stage output; The expression function for the second limiting stage is: In the formula, I LIMIT_Q This is the output for the second limiting stage; The expression function of the second output stage is: In the formula, T SQ To output the time constant of the inertial element, I Q This is the output current of the device.

6. The method according to claim 1, characterized in that, The fault ride-through control model includes: a reactive current calculation model during low-voltage ride-through. In the formula, I Q_LVRT For low-through-voltage output reactive current, K 1_LV , K 2_LV , K 3_LV , K 4_LV The calculation factor for low-voltage reactive current is given. V IN_LV The reference voltage is calculated for the low-through reactive current. I Q0 This is the initial reactive current. Q SET To achieve the goal without success I QSET_LV Low-pass reactive current setting value; Reactive current calculation model during high voltage ride-through: In the formula, I Q_HVRT For high-voltage output reactive current, K 1_HV , K 2_HV , K 3_HV , K 4_LV For calculating high-voltage reactive current, V IN_HV The reference voltage is calculated for high-voltage reactive current. I QSET_HV High-voltage reactive current setting value; Reactive current tripping modes include instantaneous tripping, constant-time tripping, and constant-slope tripping: Instantaneous action: The next simulation step action after the fault crossing action is completed; Fixed timeout: The action is completed within the specified timeout period after the fault crossing action; Fixed slope: After the fault crossing action, the action is completed according to the specified slope.

7. The method according to claim 1, characterized in that, The disconnection protection model is used to disconnect the device from the network based on the actual device's disconnection protection curve. When the voltage at the device's access point is lower than a specified voltage and the duration is greater than a specified time requirement, the device disconnects from the network.

8. A static var generator simulation device, used to implement the method described in any one of claims 1-7, characterized in that, include: The first building module is used to build constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model and mode switching control model; The second construction module is used to construct a static var generator simulation model based on the constant voltage control model, constant reactive power control model, fault ride-through control model, grid disconnection protection model, and mode switching control model. The simulation module is used to output reactive current to the grid equipment based on the static var generator simulation model, according to the specified voltage or reactive power control target and the input control parameters, wherein the grid equipment operates stably based on the reactive current.

9. A computer-readable storage medium, characterized in that, The storage medium stores a computer program for performing the method described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method described in any one of claims 1-7.

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