Clock generation circuit and signal generation method
By dynamically adjusting the clock duty cycle, the insufficient signal comparison and reconstruction time caused by the fixed duty cycle is solved, the accuracy of signal comparison and reconstruction is improved, and the circuit performance is improved.
Patent Information
- Application Number
- CN202510559722.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-30
- Publication Date
- 2025-08-12
AI Technical Summary
In the prior art, a clock signal with a fixed duty cycle leads to insufficient time for signal comparison, signal reconstruction and signal amplification, resulting in errors in comparison results and gain errors, especially when the input of a very small signal is obvious.
A clock generation circuit is designed to generate a clock signal whose duty cycle is dynamically adjusted with the amplitude of the input signal through a dynamic comparator, logic gate circuit, controlled delay unit and synchronization loop, including the output signal of the dynamic comparator and delay control of the controlled delay unit, the state of the flip-flop is reversed, and the logic gate circuit is logically combined to generate a closed-loop control clock signal.
The clock duty cycle is automatically adjusted according to the input signal size, extending the signal comparison and reconstruction time under the small signal input, shortening the response time under the large signal input, improving the accuracy of signal comparison and reconstruction, and improving circuit performance.
Smart Images
Figure CN120474552A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a clock generation circuit and a signal generation method. Background Art
[0002] Analog-to-digital converters (ADCs), which convert external analog signals into digital signals, are often used in various data acquisition systems. Typically, ADCs operate under the control of a clock with a fixed duty cycle. For example, in a successive approximation ADC, after the external analog signal is sampled, it is fed into a comparator for signal comparison. The comparator compares the input signal under the control of a low-level clock. Because the duty cycle of this clock is fixed, the time it takes for the comparator to reconstruct the signal and complete the comparison is relatively fixed. Consequently, with extremely small input signals, the fixed duty cycle may not provide sufficient time for the comparator to reconstruct the signal, which can easily lead to erroneous comparison results.
[0003] At the same time, based on the working principle of SAR ADC, an internal digital-to-analog converter is required to generate a new signal that enters the comparator next time. The process of DAC generating a new signal is often completed under the high level of the control clock. If a new signal with a large difference from the previous signal is generated, it often requires a longer setup time and stabilization time to make the new signal meet the accuracy requirements.
[0004] Therefore, when the duty cycle is fixed, the resulting signal error is relatively large. The same problem also occurs during signal amplification between pipeline ADC stages. A fixed duty cycle results in a fixed amplification time, which causes the amplified signal to fail to meet accuracy requirements, leading to gain error. This problem arises because the clock duty cycle is not adjustable, leaving insufficient time for signal comparison, reconstruction, and amplification. Summary of the Invention
[0005] In view of the deficiencies in the prior art, the present invention proposes a clock generation circuit and a signal generation method to solve the above technical problems.
[0006] In a first aspect, a clock generation circuit is provided, comprising:
[0007] Dynamic comparators, logic gates, controlled delay cells, flip-flops, and synchronization loops;
[0008] The synchronous loop generates a clock signal whose duty cycle is dynamically adjusted according to the amplitude of the input signal through the output signal of the dynamic comparator, the delay control of the controlled delay unit and the state flip-flop.
[0009] Furthermore, the input end of the dynamic comparator is connected to an analog signal, the output end of the dynamic comparator is connected to the logic gate circuit, and the comparison result of the dynamic comparator is fed back to the input end of the trigger through the synchronization loop to form a closed-loop control.
[0010] Furthermore, the logic gate circuit includes:
[0011] The two-input NAND gate, OR gate and AND gate are used to logically combine the output signal of the dynamic comparator with the output signal of the controlled delay unit to control the flip-flop timing.
[0012] Furthermore, the controlled delay unit includes:
[0013] A switch and capacitor network controlled by the input signal amplitude changes the capacitor charge and discharge time by adjusting the on and off state of the switch.
[0014] Furthermore, the trigger is a JK trigger, the input end of the trigger receives the output signal of the logic gate circuit, and the output end of the trigger is connected to the synchronization loop to control the duty cycle of the clock signal.
[0015] Furthermore, the adjustment of the duty cycle includes:
[0016] When the input signal has a small amplitude, the clock low level time is extended to increase the signal comparison time;
[0017] When the input signal has a large amplitude, shorten the clock low level time to reduce the signal setup time.
[0018] Furthermore, the control signal of the switch is determined by an amplitude threshold of the input signal;
[0019] When the input signal is lower than the preset threshold, the switch is disconnected to increase the delay time;
[0020] When the input signal is higher than the preset threshold, the switch is closed to reduce the delay time.
[0021] Furthermore, the initial state of the synchronization loop is controlled by an external reset pulse, and the external reset pulse directly pulls down the clock signal through an OR gate to trigger the initial comparison operation of the dynamic comparator.
[0022] In a second aspect, a clock signal generation method is provided, based on a clock generation circuit as described in any one of the preceding claims, comprising:
[0023] Receiving an external reset pulse triggers the initial comparison;
[0024] adjusting the delay time of the controlled delay unit according to the amplitude of the input signal;
[0025] Generate a clock signal with a dynamically adjustable duty cycle through coordinated control of the logic gate circuit and the trigger;
[0026] The clock signal is fed back to the synchronization loop to continuously adjust the duty cycle to adapt to input signal changes.
[0027] The invention adopting the above technical solution has the following advantages:
[0028] The clock duty cycle generated by this invention automatically adjusts based on the magnitude of the analog input signal. For small input signals, the signal comparison and reconstruction amplification times are automatically extended; for large input signals, the response time is shortened. This design, in which the duty cycle is dependent on the input signal amplitude, significantly improves the accuracy of signal comparison and reconstruction, thereby enhancing circuit performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] In order to more clearly illustrate the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the specific embodiments. In all the drawings, each element or part is not necessarily drawn according to the actual scale.
[0030] Figure 1 This is a principle block diagram of a clock generating circuit of the present invention;
[0031] Figure 2 This is a working timing diagram of a clock generating circuit of the present invention;
[0032] Figure 3 A circuit diagram of a controlled delay unit in a clock generation circuit of the present invention;
[0033] Figure 4 This is a simulation result diagram of a clock generating circuit of the present invention;
[0034] Figure 5 The present invention is a flowchart of a clock signal generation method. DETAILED DESCRIPTION
[0035] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.
[0036] The terms "first," "second," and the like in the specification and claims of this application and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.
[0037] References to "embodiments" in this application mean that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described in this application may be combined with other embodiments.
[0038] like Figures 1 to 5 As shown, a clock generating circuit of the present invention includes:
[0039] Dynamic comparators, logic gates, controlled delay cells, flip-flops, and synchronization loops;
[0040] The synchronous loop generates a clock signal whose duty cycle is dynamically adjusted according to the amplitude of the input signal through the output signal of the dynamic comparator, the delay control of the controlled delay unit and the state flip-flop.
[0041] Specifically, the clock duty cycle generated by the present invention automatically adjusts based on the magnitude of the analog input signal. For small input signals, the signal comparison and reconstruction amplification times are automatically extended; for large input signals, the response time is shortened. This design, in which the duty cycle is dependent on the input signal amplitude, significantly improves the accuracy of signal comparison and reconstruction, thereby enhancing circuit performance.
[0042] In this embodiment, the input of the dynamic comparator is connected to an analog signal, the output of the dynamic comparator is connected to a logic gate circuit, and the comparison result of the dynamic comparator is fed back to the input of the trigger through a synchronous loop to form a closed-loop control.
[0043] In this embodiment, the logic gate circuit includes:
[0044] The two-input NAND gate, OR gate and AND gate are used to logically combine the output signal of the dynamic comparator with the output signal of the controlled delay unit to control the flip-flop timing.
[0045] In this embodiment, the controlled delay unit includes:
[0046] The switch and capacitor network is controlled by the input signal amplitude, and the capacitor charging and discharging time is changed by adjusting the on and off state of the switch.
[0047] Specifically, by Figure 1 The pulse width of the master clock clk generated by the circuit shown depends on the comparison setup time t of the comparator to the input signal. c , if the signal is small, t c The low level of the main clock clk is automatically prolonged, thereby improving the metastable effect of the comparator caused by too short a comparison time.
[0048] At the same time, the input signal in is added to the synchronization loop p / in n The delay (t d1 ) adjustable unit. When the input signal amplitude is small, the on-resistance Ron of the controlled switch becomes larger, and the time delay t generated by the capacitor C d1 If the DAC signal is reconstructed, the high level of the master clock clk is automatically extended, thereby increasing the DAC establishment accuracy or alleviating the complexity of the switch design in the capacitor array.
[0049] Therefore, the frequency of the master clock generated by this circuit can be automatically changed according to the amplitude of the input signal.
[0050] In order to make the high level time of the main clock clk change with the input signal amplitude, Figure 1 The controlled delay unit in is specifically implemented as follows Figure 3 As shown, the specific working principle is as follows:
[0051] When clk1 is at a high level, the output node out is reset to a low level through transistor M10. At the same time, the inverted signal clk1 of clk1 charges the capacitor C through two transmission gates. When the voltage on the capacitor C exceeds the turn-on voltage of transistor M4, M4 is turned on, causing the gate end of M7 to become a low level, causing M7 to be turned on, and then the output node out is pulled to a high level through M7 and M9, thereby generating a new pulse.
[0052] In this process, the on-resistance Ron of the transmission gate (S1 and S2) is controlled by the differential input signal. p When the voltage in the positive direction changes, clk1 charges the capacitor C through the transmission gate S1. p When the signal changes in the reverse direction, clk1 charges the capacitor C through the transmission gate S2. The capacitor C is continuously charged during the entire input signal conversion cycle. Therefore, the charging time t d1 It fully reflects the amplitude of the input signal, so that the high level time of the main clock clk changes with the amplitude of the input signal.
[0053] according to Figure 2 Architecture and utilization Figure 3 Delay circuit, based on the standard CMOS process to build a simulation verification circuit in EDA software, under the input signal is a differential sine wave input, as the start excitation signal (set) changes from high to low, the period of the clock frequency clk output by the architecture changes with the amplitude of the input signal. The simulation results are as follows Figure 4 shown.
[0054] For example, when the amplitudes of the two differential input signals are close, the CLK period becomes longer and the frequency becomes lower. When the amplitude difference between the two input signals is large, the CLK period becomes shorter and the frequency becomes higher. Simulations also show that the duration of the CLK high and low levels is also related to the amplitude of the input signals. Therefore, simulations verify the feasibility of this clock circuit.
[0055] In this embodiment, the trigger is a JK trigger, an input end of the trigger receives an output signal of the logic gate circuit, and an output end of the trigger is connected to a synchronization loop to control the duty cycle of the clock signal.
[0056] In this embodiment, the duty cycle adjustment includes:
[0057] When the input signal has a small amplitude, the clock low level time is extended to increase the signal comparison time;
[0058] When the input signal has a large amplitude, shorten the clock low level time to reduce the signal setup time.
[0059] In this embodiment, the control signal of the switch is determined by the amplitude threshold of the input signal;
[0060] When the input signal is lower than the preset threshold, the switch is disconnected to increase the delay time;
[0061] When the input signal is higher than the preset threshold, the switch is closed to reduce the delay time.
[0062] In this embodiment, the initial state of the synchronous loop is controlled by an external reset pulse, which directly pulls down the clock signal through an OR gate to trigger the initial comparison operation of the dynamic comparator.
[0063] The clock generation circuit principle architecture of the present invention is as follows Figure 1 As shown, it includes a dynamic comparator, a two-input NAND gate, a controlled delay unit, an AND gate, a JK trigger and an OR gate. Figure 1 The method shown in the figure forms a synchronous loop and generates a clock with controllable duty cycle. Figure 2 shown.
[0064] Specific working principle:
[0065] In the initial state, the comparator is reset to a high level by an external pulse (set), and the main clock (clk) maintains a high level. When the external pulse falls, the main clock is pulled through the OR gate, thereby controlling the comparator to respond to the two differential input voltage signals (in p / in n ) for comparison. Then the comparator outputs the result out p and out n is sent to a NAND gate. Since the two outputs of the comparator will not be '1' at the same time during normal comparison, a Figure 2 The clk1 clock shown in the figure has a pulse width (t c ) is input by the comparator signal (in p / in n ) is determined by the amplitude.
[0066] After that, clk1 and its own inverted and delayed clock clk are respectively 1_td Send to JK trigger, because clk 1_td The falling edge of clk1 always lags behind the rising edge of clk1, so 1_td When the falling edge arrives, the output of the JK flip-flop realizes the transition from low level to high level, which in turn causes clk to realize the transition from low to high level. During the period when clk is high level, the comparator is reset, making clk1 maintain low level. 1_td Lagging behind clk1, after t d1 After the delay, clk 1_td When the rising edge of clk1 arrives, at this moment, since clk1 is at a low level, the output of the JK trigger realizes a transition from a high level to a low level, thereby controlling the comparator to compare the next input signal, and then generating subsequent working clocks according to the above working principle.
[0067] According to the above working principle, the period of the main clock (t clk ) by t c and t d1 The sum of the two is determined, that is, t clk =t c +t d1.
[0068] In some other embodiments, a clock signal generation method is provided, based on a clock generation circuit according to any one of the foregoing items, comprising:
[0069] Step S01, receiving an external reset pulse to trigger initial comparison;
[0070] Step S02: adjusting the delay time of the controlled delay unit according to the input signal amplitude;
[0071] Step S03: Generate a clock signal with a dynamically adjustable duty cycle through coordinated control of logic gate circuits and triggers;
[0072] Step S04: Feedback the clock signal to the synchronization loop, and continuously adjust the duty cycle to adapt to changes in the input signal.
[0073] It should be noted that for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that this application is not limited by the order of the actions described, because according to this application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by this application.
[0074] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0075] In the several embodiments provided in this application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.
[0076] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.
[0077] In addition, the functional units in the various embodiments of the application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software program modules.
[0078] If the integrated unit is implemented in the form of a software program module and sold or used as an independent product, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a memory, including a number of instructions for enabling a computer device (which can be a personal computer, a server or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned memory includes: various media that can store program codes, such as a U disk, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.
[0079] Those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable memory, which may include: a flash drive, a read-only memory, a random access memory, a magnetic disk or an optical disk, etc.
[0080] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of the present application. At the same time, for those skilled in the art, according to the idea of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A clock generating circuit, characterized in that: include: Dynamic comparators, logic gates, controlled delay cells, flip-flops, and synchronization loops; The synchronous loop generates a clock signal whose duty cycle is dynamically adjusted according to the amplitude of the input signal through the output signal of the dynamic comparator, the delay control of the controlled delay unit and the state flip-flop.
2. A clock generating circuit according to claim 1, characterized in that: The input end of the dynamic comparator is connected to an analog signal, the output end of the dynamic comparator is connected to the logic gate circuit, and the comparison result of the dynamic comparator is fed back to the input end of the trigger through the synchronization loop to form a closed-loop control.
3. The clock generating circuit according to claim 1, wherein: The logic gate circuit comprises: The two-input NAND gate, OR gate and AND gate are used to logically combine the output signal of the dynamic comparator with the output signal of the controlled delay unit to control the flip-flop timing.
4. The clock generating circuit according to claim 1, wherein: The controlled delay unit comprises: A switch and capacitor network controlled by the input signal amplitude changes the capacitor charge and discharge time by adjusting the on and off state of the switch.
5. A clock generating circuit according to claim 4, characterized in that: The trigger is a JK trigger, an input end of the trigger receives an output signal of the logic gate circuit, and an output end of the trigger is connected to the synchronization loop to control the duty cycle of the clock signal.
6. A clock generating circuit according to claim 5, characterized in that: The adjustment of the duty cycle includes: When the input signal has a small amplitude, the clock low level time is extended to increase the signal comparison time; When the input signal has a large amplitude, shorten the clock low level time to reduce the signal setup time.
7. A clock generating circuit according to claim 6, characterized in that: The control signal of the switch is determined by the amplitude threshold of the input signal; When the input signal is lower than the preset threshold, the switch is disconnected to increase the delay time; When the input signal is higher than the preset threshold, the switch is closed to reduce the delay time.
8. The clock generating circuit according to claim 1, wherein: The initial state of the synchronous loop is controlled by an external reset pulse, and the external reset pulse directly pulls down the clock signal through an OR gate to trigger the initial comparison operation of the dynamic comparator.
9. A clock signal generation method, characterized in that: A clock generating circuit according to any one of claims 1 to 8, comprising: Receiving an external reset pulse triggers the initial comparison; adjusting the delay time of the controlled delay unit according to the amplitude of the input signal; Generate a clock signal with a dynamically adjustable duty cycle through coordinated control of the logic gate circuit and the trigger; The clock signal is fed back to the synchronization loop to continuously adjust the duty cycle to adapt to input signal changes.