Comparator, analog-to-digital conversion circuit, chip and electronic equipment

Abstract

The invention relates to the technical field of chips, and provides a comparator, an analog-to-digital conversion circuit, a chip and electronic equipment. A comparator comprises a voltage reduction unit, a pre-amplification unit and a comparison unit. The comparator is suitable for the first voltage domain and is used for receiving the analog voltage provided by the analog signal source, the analog signal source is suitable for the second voltage domain, and the first voltage domain is smaller than the second voltage domain, so that each unit in the comparator and the analog signal source can be prevented from being in the same voltage domain. Therefore, under the condition that normal work of the comparator is ensured, the unit in the comparator and the analog signal source are in different voltage domains, and the first voltage domain corresponding to the comparator is smaller than the second voltage domain corresponding to the analog signal, so that the leakage of the transistor in the comparator is relatively small, and the requirement of low leakage can be better met; therefore, a comparator scheme with a wider application range is provided.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and in particular relates to a comparator, an analog-to-digital conversion circuit, a chip, and an electronic device. Background Art

[0002] As a relatively important module in the analog-to-digital conversion circuit, the comparator's main function is to compare the voltage in the digital-to-analog conversion unit with the reference voltage, and then output a binary signal to the control unit, thereby controlling the on and off of the switch in the digital-to-analog conversion unit to realize cyclic comparison, and finally obtain the code value corresponding to the input voltage.

[0003] However, to adapt to the DAC, the comparator and DAC usually operate in the same voltage domain. This results in significant transistor leakage interference in the comparator, meaning that the signal amplified by the transistor exhibits significant noise, failing to meet the low leakage requirements of the comparator. Summary of the Invention

[0004] The purpose of this application is to provide a comparator, an analog-to-digital conversion circuit, a chip, and an electronic device, aiming to provide a comparator solution that can meet the requirements of low leakage and has a wider range of applications.

[0005] A first aspect of an embodiment of the present application provides a comparator, the comparator being applicable to a first voltage domain and configured to receive an analog voltage provided by an analog signal source, wherein the analog signal source is applicable to a second voltage domain, the first voltage domain being smaller than the second voltage domain, the comparator comprising:

[0006] a step-down unit, configured to step down the analog voltage so that the stepped-down analog voltage is adapted to the first voltage domain;

[0007] A pre-amplifier unit is used to amplify the stepped-down analog voltage and output the amplified analog voltage;

[0008] The comparison unit is used to compare the amplified analog voltage with a preset given voltage and output a comparison result corresponding to the analog voltage.

[0009] A comparator provided in an embodiment of the present application includes a step-down unit, a pre-amplifier unit, and a comparison unit. Since the comparator is applicable to a first voltage domain and is used to receive an analog voltage provided by an analog signal source, the analog signal source is applicable to a second voltage domain, and the first voltage domain is smaller than the second voltage domain, it is possible to avoid that each unit in the comparator and the analog signal source are in the same voltage domain. At the same time, the analog voltage is stepped down by the step-down unit, so that the stepped-down analog voltage can be adapted to the first voltage domain. The stepped-down analog voltage is amplified by the pre-amplifier unit and the amplified analog voltage is output. The amplified analog voltage is compared with a preset given voltage by the comparison unit, and a comparison result corresponding to the analog voltage is output. In this way, while ensuring the normal operation of the comparator, since each unit in the comparator and the analog signal source are in different voltage domains, and the first voltage domain corresponding to the comparator is smaller than the second voltage domain corresponding to the analog signal, the transistor leakage in the comparator is smaller, which is more able to meet the low leakage requirement, thereby providing a comparator solution with a wider range of applications.

[0010] In addition, since the individual units in the comparator are in different voltage domains from the analog signal source, and the first voltage domain corresponding to the comparator is smaller than the second voltage domain corresponding to the analog signal, the comparator provided in this embodiment has a smaller area than a conventional comparator, which not only meets the small area requirement for the comparator, but also saves costs.

[0011] A second aspect of the embodiments of the present application provides an analog-to-digital conversion circuit for sampling a signal source and outputting a corresponding digital signal. The analog-to-digital conversion circuit includes:

[0012] A digital-to-analog conversion unit suitable for the second voltage domain, used to sample the signal source and output a corresponding analog voltage; and the comparator provided by the first aspect above.

[0013] A third aspect of the embodiments of the present application provides a chip, which includes the comparator provided by the first aspect; or

[0014] The chip is used to execute the analog-to-digital conversion circuit provided by the second aspect.

[0015] A fourth aspect of the embodiments of the present application provides an electronic device, comprising the comparator provided by the first aspect above; and / or

[0016] The electronic device includes the analog-to-digital conversion circuit provided by the second aspect above; or

[0017] The electronic device includes the chip provided by the third aspect above.

[0018] It can be understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a comparator provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the specific structure of a comparator provided in an embodiment of the present application Figure 1 ;

[0021] Figure 3 A specific implementation circuit diagram of the step-down circuit in the embodiment of the present application;

[0022] Figure 4 A schematic diagram of the specific structure of a comparator provided in an embodiment of the present application Figure 2 ;

[0023] Figure 5 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application Figure 1 ;

[0024] Figure 6 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application Figure 2 ;

[0025] Figure 7 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application Figure 3 ;

[0026] Figure 8 A specific circuit diagram of the amplifier circuit in the embodiment of the present application;

[0027] Figure 9 A schematic diagram of the overall circuit of a comparator provided in an embodiment of the present application;

[0028] Figure 10 A schematic diagram of the specific structure of a comparison unit in a comparator provided in an embodiment of the present application;

[0029] Figure 11 The specific circuit of the comparison unit in the comparator provided in the embodiment of the present application Figure 1 ;

[0030] Figure 12 The specific circuit of the comparison unit in the comparator provided in the embodiment of the present application Figure 2 ;

[0031] Figure 13 Schematic diagram of the structure of the analog-to-digital conversion circuit provided in the embodiment of the present application Figure 1 ;

[0032] Figure 14 Schematic diagram of the structure of the analog-to-digital conversion circuit provided in the embodiment of the present application Figure 2 . DETAILED DESCRIPTION

[0033] The embodiments of the present application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and are not to be construed as limiting the present application.

[0034] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0035] In the embodiments of the present application, it should be noted that, in this document, relational terms such as first and second, etc., are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0036] Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not preclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0037] In the description of the embodiments of this application, words such as "example" or "for example" are used to indicate an example, illustration, or description. Any embodiment or design described as "for example" or "for example" in the embodiments of this application is not to be construed as being preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to clearly present relative concepts.

[0038] In addition, in the embodiments of the present application, "plurality" refers to two or more. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two, or more. For example, "including at least one" means including one, two, or more, and does not limit which ones are included. For example, "including at least one of A, B, and C" means including A, B, C, A and B, A and C, B and C, or A, B, and C.

[0039] It should be noted that in the embodiments of the present application, "and / or" describes the association relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects are in an "or" relationship.

[0040] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0041] The first electrode / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second electrode / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain can be structurally indistinguishable, that is, the first electrode / first end and the second electrode / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode / first end of the transistor is the source, and the second electrode / second end is the drain.

[0042] As a key module in analog-to-digital conversion circuits, the comparator compares the voltage in the DAC with a reference voltage, outputting a binary signal to the control unit, which in turn controls the on / off switches in the DAC to implement a cyclic comparison, ultimately obtaining a code value corresponding to the input voltage. To ensure compatibility with the DAC, the comparator typically operates in the same voltage domain as the DAC.

[0043] For example, the StrongARM dynamic comparator, a dual-tail dynamic comparator, uses a pre-amplifier circuit with a latch circuit (i.e., a comparator circuit). Because the pre-amplifier circuit, latch circuit, and digital-to-analog conversion unit are in the same voltage domain, the leakage current of the transistors in the comparator is very high, which is not conducive to the requirements of small area and low leakage.

[0044] To address the above technical issues, an embodiment of the present application provides a comparator comprising a step-down unit, a pre-amplifier unit, and a comparison unit. Since the comparator is adapted to a first voltage domain and is configured to receive an analog voltage provided by an analog signal source, the analog signal source being adapted to a second voltage domain, where the first voltage domain is smaller than the second voltage domain, it is possible to prevent the individual units in the comparator from being in the same voltage domain as the analog signal source. Furthermore, the step-down unit is used to step down the analog voltage, allowing the stepped-down analog voltage to adapt to the first voltage domain. The pre-amplifier unit amplifies the stepped-down analog voltage and outputs the amplified analog voltage. The comparison unit compares the amplified analog voltage with a preset given voltage and outputs a comparison result corresponding to the analog voltage. Thus, while ensuring the normal operation of the comparator, since the individual units in the comparator are in different voltage domains from the analog signal source, and the first voltage domain corresponding to the comparator is smaller than the second voltage domain corresponding to the analog signal, the transistors in the comparator have lower leakage current, better meeting low leakage requirements, thereby providing a comparator solution with a wider range of applications.

[0045] In addition, since the step-down unit, pre-amplifier unit and comparison unit in the comparator are in different voltage domains from the analog signal source, and the first voltage domain corresponding to the comparator is smaller than the second voltage domain corresponding to the analog signal, the comparator provided in this embodiment has a smaller area than the conventional comparator, which not only meets the small area requirement for the comparator, but also saves costs.

[0046] See Figure 1 , Figure 1 FIG. 1 shows a schematic diagram of the structure of a comparator provided in an embodiment of the present application. Figure 1 As shown, the comparator 100 includes a step-down unit 10 , a pre-amplification unit 20 and a comparison unit 30 .

[0047] Specifically:

[0048] The comparator 100 is applicable to a first voltage domain and is used to receive an analog voltage provided by an analog signal source 110 . The analog signal source 110 is applicable to a second voltage domain, and the first voltage domain is smaller than the second voltage domain.

[0049] The step-down unit 10 is configured to step down the analog voltage so that the stepped-down analog voltage is compatible with the first voltage domain. The pre-amplifier unit 20 is configured to amplify the stepped-down analog voltage and output the amplified analog voltage. The comparison unit 30 is configured to compare the amplified analog voltage with a preset given voltage and output a comparison result corresponding to the analog voltage.

[0050] In this embodiment, both the first voltage domain and the second voltage domain can be understood as operating voltage ranges. Accordingly, the comparator 100 being adapted for the first voltage domain can be understood as meaning that the operating voltage of the comparator 100 is within the first voltage range. Similarly, the analog signal source 110 being adapted for the second voltage domain can be understood as meaning that the operating voltage of the analog signal source 110 is within the second voltage range. The first voltage domain is smaller than the second voltage domain, i.e., the first voltage range is smaller than the second voltage range. Therefore, the maximum value of the first voltage range is smaller than the minimum value of the second voltage range.

[0051] For example, the first voltage range corresponding to the comparator 100 is U1, and U1∈[3.3V, 4V], that is, the operating voltage of the comparator 100 is in the range of 3.3V to 4V. The second voltage range corresponding to the analog signal source 110 is U2, and U2∈[5.5V, 6V], that is, the operating voltage of the analog signal source 110 is in the range of 5.5V to 6V.

[0052] It should be pointed out that since the comparator 100 is applicable to the first voltage domain, in order for the comparator 100 to compare the analog voltage provided by the analog signal source with the preset given voltage, it is necessary to step down the analog voltage provided by the analog signal source so that the stepped-down analog voltage is adapted to the first voltage domain. Since the comparator 100 is applicable to the first voltage domain, the analog signal source 110 is applicable to the second voltage domain, and the second voltage domain is greater than the first voltage domain, the comparator 100 cannot directly use the analog voltage provided by the analog signal source 110 as an input signal. Based on this, by using the step-down unit 10 to step down the analog voltage, the stepped-down analog voltage can be adapted to the first voltage domain. Here, making the stepped-down analog voltage adapted to the first voltage domain means that the stepped-down analog voltage can be amplified by the pre-amplification unit 20.

[0053] In all embodiments of the present application, the analog voltage provided by the analog signal source 110 generally refers to an analog voltage pair / analog voltage difference, that is, the analog voltage can specifically be a pair of differential voltages. Using the step-down unit 10 to step down the analog voltage can be understood as stepping down the analog voltage pair / analog voltage difference adapted to the first voltage domain, so that the analog voltage pair / analog voltage difference can be adapted to the first voltage domain after stepping down. In a specific implementation, the analog signal source 110 can be a digital-to-analog conversion unit DAC, which performs digital-to-analog conversion on the collected data and then outputs an analog voltage. Of course, in actual implementation, the analog signal source 110 can also include a reference signal generating unit (not shown) for providing a preset given voltage VCM.

[0054] Exemplarily, when the comparator 100 is adapted to the first voltage domain, the pre-amplification unit 20 can amplify the analog voltage with a voltage amplitude of V1~V2 in the first voltage domain. Since the voltage amplitude of the analog voltage provided by the analog signal source 110 is V3~V4, and V3~V4>V1~V2, based on this, it is necessary to step down the analog voltage provided by the analog signal source 110 so that the voltage of the stepped-down analog voltage can be adapted to the first voltage domain, that is, the voltage amplitude of the stepped-down analog voltage can be within the range of V1~V2.

[0055] In all embodiments of the present application, the analog voltage is stepped down by the step-down unit 10 so that the stepped-down analog voltage can be applied to the comparator 100 of the first voltage domain, that is, the stepped-down analog voltage pair / analog voltage difference can be applied to the pre-amplifier unit 20 in the comparator 100 .

[0056] In a specific implementation, the pre-amplifier unit 20 may include an amplifier circuit including a pre-amplifier. By changing the area of the pre-amplifier, the operating voltage domain of the pre-amplifier unit 20 can be adjusted. Here, the operating voltage of the pre-amplifier is positively correlated or proportional to its area. That is, the area of the pre-amplifier unit 20 is also positively correlated or proportional to the size of the voltage domain / voltage range in which it operates. Based on this, in actual implementation, the pre-amplifier unit 20 can be adapted to the first voltage domain by reducing the area of the pre-amplifier in the pre-amplifier unit 20.

[0057] For example, let the area of the first type of preamplifier applicable to the first voltage domain be X, and the area of the second type of preamplifier applicable to the second voltage domain be X+ΔY, where both X and Y are positive numbers. In a specific implementation, the preamplifier unit 20 can be implemented using an amplifier circuit composed of the first type of preamplifier.

[0058] It is easy to understand that amplifying the stepped-down analog voltage by the pre-amplifier unit 20 actually increases the voltage amplitude of the stepped-down analog voltage according to the voltage gain (i.e., the amplification factor). For example, a weak millivolt-level analog voltage can be amplified to the volt level, making it easier for subsequent circuits such as the comparison unit 30 to process or transmit it.

[0059] For example, in a specific implementation, the pre-amplifier unit 20 may be configured with a multi-stage pre-amplifier circuit, so that the gain of the pre-amplifier unit 20 is a fixed value, such as 10 times, 20 times, 30 times, etc. Of course, the pre-amplifier unit 20 may also be configured with multiple pre-amplifier branches corresponding to multiple gains. In actual use, different pre-amplifier branches in the pre-amplifier unit 20 can be selected according to different amplification requirements to achieve the selection of different gains.

[0060] It is easy to understand that in all embodiments of the present application, the analog voltage is stepped down by the step-down unit 10 so that the voltage of the stepped-down analog voltage can be adapted to the first voltage domain. It can be understood that the analog voltage adapted to the second voltage domain is mapped to the stepped-down analog voltage adapted to the first voltage domain. That is, the analog voltage pair / analog voltage difference is processed to reduce or shift down the voltage range without changing the information represented by the analog voltage. Based on this, the comparison unit 30 is used to compare the amplified analog voltage with the preset given voltage, and the comparison result output corresponds to the analog voltage. In a specific implementation, the comparison unit 30 may include a latch circuit.

[0061] In some embodiments, the kickback noise of the latch circuit itself affects the input voltage, which in turn has a certain impact on the amplified analog voltage. For example, when the latch circuit is operating in the comparison stage, the jump of the clock signal (i.e., the CLK signal) will cause a voltage mutation at the internal node of the latch circuit (such as the output end of the cross-coupled inverter). This mutation is coupled to the sensitive node at the input end through the parasitic capacitance of the transistor in the latch circuit (such as the gate-drain capacitance of the MOS tube), interfering with the original input signal, which in turn has a certain impact on the amplified analog voltage. Based on this, the kickback noise of the latch circuit itself can be eliminated by increasing the area of the input pair tube in the latch circuit, or increasing the size of the symmetrical tube at the feedback end of the latch circuit.

[0062] As an embodiment, the comparator 100 may further include a noise elimination unit (not shown in the figure). Specifically, the noise elimination unit is connected to the comparison unit 30 and is used to eliminate the kickback noise of the comparison unit 30.

[0063] In a specific implementation, the noise elimination unit can be connected to the transistor at the input end of the Latch circuit. By suppressing the response of the parasitic capacitance of the transistor in the Latch circuit to the sudden signal, the voltage mutation of the internal node of the Latch circuit can be suppressed or eliminated, thereby preventing the mutation from being coupled to the sensitive node at the input end through the parasitic capacitance of the transistor in the Latch circuit, thereby eliminating the kickback noise.

[0064] Figure 2 The specific structure of a comparator provided in the embodiment of the present application is shown in FIG. Figure 1 .like Figure 2 As shown, the step-down unit 10 includes: a step-down circuit 11. Specifically:

[0065] A first input terminal of the step-down circuit 11 is connected to a first output terminal of the analog signal source 110, and a second input terminal of the step-down circuit 11 is connected to a second output terminal of the analog signal source 110. A first output terminal of the step-down circuit 11 is connected to a first input terminal of the pre-amplifier unit 20, and a second output terminal of the step-down circuit 11 is connected to a second input terminal of the pre-amplifier unit 20.

[0066] In this embodiment, the comparator 100 is connected to the analog signal source 110 via the step-down circuit 11. Upon receiving the analog voltage transmitted by the analog signal source 110, the comparator 100 can step down the analog voltage to obtain a stepped-down analog voltage, and transmit the stepped-down analog voltage to the pre-amplifier unit 20. In a specific implementation, the step-down circuit 11 can include a voltage divider circuit composed of resistors, or can be implemented using an existing DC-DC step-down circuit.

[0067] As an implementation manner, the voltage-reducing circuit 11 may include at least two identical resistor voltage-dividing circuits. Figure 3 FIG. 1 shows a specific implementation circuit diagram of the step-down circuit in the embodiment of the present application. Figure 3 As shown, the resistance voltage divider circuit can be a pure resistance circuit consisting of a first resistor R1 and a second resistor R2 connected in series. Figure 2 and Figure 3 The first end of the first resistor R1 serves as the first input end of the step-down circuit 11, or as the second input end of the step-down circuit 11, for connecting to the analog signal source 110. The second end of the first resistor R1 is connected to the first end of the second resistor R2, and the node formed serves as the first output end or the second output end of the step-down circuit 11, for connecting to the pre-amplifier unit 20. The second end of the second resistor R2 is grounded. Figure 3 In the voltage divider circuit, the first resistor R1 and the second resistor R2 divide the analog voltage to lower the analog voltage, so that the stepped-down analog voltage is adapted to the first voltage domain.

[0068] As another implementation method, the voltage-reducing circuit 11 may include at least two identical capacitor voltage-dividing circuits. Figure 3 Similar to the embodiment shown, the capacitor voltage divider circuit can be composed of a first voltage divider capacitor and a second voltage divider capacitor connected in series, wherein the first voltage divider capacitor and Figure 3 The first resistor R1 corresponds to the second voltage divider capacitor Figure 3 Corresponding to the second resistor R2 in. Based on this, the first end of the first voltage-dividing capacitor serves as the first input end of the step-down circuit, or as the second input end of the step-down circuit, for connecting the analog signal source. The second end of the first voltage-dividing capacitor is connected to the first end of the second voltage-dividing capacitor, and the node formed serves as the first output end or the second output end of the step-down circuit, for connecting the pre-amplification unit. The second end of the second voltage-dividing capacitor is grounded. The first voltage-dividing capacitor and the second voltage-dividing capacitor in the voltage-dividing circuit can pull down the analog voltage by dividing the analog voltage, so that the stepped-down analog voltage is adapted to the first voltage domain.

[0069] In some embodiments, the step-down circuit 11 may further include multiple pairs of resistor divider circuits. For example, the comparator 100 is provided with multiple groups of pre-amplifier units 20, each group of pre-amplifier units 20 corresponding to a different voltage domain. In actual use, the analog voltage can be stepped down by selecting a corresponding pair of resistor divider circuits. In this way, the analog voltage is stepped down by different amplitudes through different pairs of resistor divider circuits, so that the stepped-down analog voltage can adapt to different voltage domains, providing a basis for further broadening the scope of application of the comparator 100.

[0070] like Figure 2 As shown in FIG. 1 , as an embodiment, the pre-amplification unit 20 includes at least a first-stage amplification unit 21 and a second-stage amplification unit 22. Figure 2 In the embodiment, the first input end of the first-stage amplifying unit 21 serves as the first input end of the pre-amplifying unit 20, and the second input end of the first-stage amplifying unit 21 serves as the second input end of the pre-amplifying unit 20. The first input end of the second-stage amplifying unit 22 is connected to the first output end of the first-stage amplifying unit 21, and the second input end of the second-stage amplifying unit 22 is connected to the second output end of the first-stage amplifying unit 21. The first output end and the second output end of the second-stage amplifying unit 22 are both connected to the comparison unit 30.

[0071] In this embodiment, the first-stage amplifier unit 21 is configured to perform a primary amplification on the stepped-down analog voltage and then output the amplified voltage to the second-stage amplifier unit 22. The second-stage amplifier unit 22 then performs a secondary amplification on the stepped-down analog voltage and then outputs the amplified analog voltage. Here, since the first-stage amplifier unit 21 performs a primary amplification on the stepped-down analog voltage and the second-stage amplifier unit 22 further amplifies the amplified analog voltage, the output amplified analog voltage is amplified N times compared to the stepped-down analog voltage, where N is the product of the amplification factor of the first-stage amplifier unit 21 and the amplification factor of the second-stage amplifier unit 22.

[0072] For example, assuming that the amplification factors of the first-stage amplifying unit 21 and the second-stage amplifying unit 22 are both 10 times, after the first-stage amplifying unit 21 amplifies the stepped-down analog voltage, the voltage value of the amplified analog voltage is 10 times the voltage value of the stepped-down analog voltage. The second-stage amplifying unit 22 further amplifies the amplified analog voltage by 10 times, and the output amplified analog voltage is amplified by 10×10=100 times compared to the stepped-down analog voltage.

[0073] For another example, assuming the amplification factor of the first-stage amplifier unit 21 is 20 times, and the amplification factors of the second-stage amplifier unit 22 are both 10 times, after the first-stage amplifier unit 21 amplifies the stepped-down analog voltage, the voltage value of the amplified analog voltage is 20 times the voltage value of the stepped-down analog voltage. The second-stage amplifier unit 22 further amplifies the amplified analog voltage by 10 times, and the output amplified analog voltage is amplified by 20×10=200 times compared to the stepped-down analog voltage.

[0074] In specific implementation, amplifier circuits with the same or different amplification factors / gains can be selected as the first-stage amplification unit 21 and the second-stage amplification unit 22 according to usage requirements. The first-stage amplification unit 21 and the second-stage amplification unit 22 can gradually amplify the stepped-down analog voltage to obtain the amplified analog voltage.

[0075] Figure 4 The specific structure of a comparator provided in the embodiment of the present application is shown in FIG. Figure 2 .like Figure 4 As shown, as an embodiment, the pre-amplification unit further includes a three-stage amplification unit 23. Specifically:

[0076] The first input end of the three-stage amplifying unit 23 is connected to the first output end of the two-stage amplifying unit 22, the second input end of the three-stage amplifying unit 23 is connected to the second output end of the two-stage amplifying unit 22, and the first output end of the three-stage amplifying unit 23 and the second output end of the three-stage amplifying unit 23 are both used to connect to the comparison unit 30.

[0077] In this embodiment, the third-stage amplifying unit 23 is connected between the second-stage amplifying unit 22 and the comparing unit 30, and is configured to further amplify the analog voltage amplified by the second-stage amplifying unit 22. In a specific implementation, the third-stage amplifying unit 23 can be implemented using the same amplifying circuit as the first-stage amplifying unit 21 and / or the second-stage amplifying unit 22, and thus will not be described in detail here.

[0078] It is understood that when the comparator 100 is adapted to the first voltage domain, the voltage domain can be adjusted by changing the area of each transistor in the pre-amplifier unit 20. Specifically, the area of each transistor in the first-stage amplification unit 21 and the second-stage amplification unit 22 can be reduced so that the cascaded first-stage amplification unit 21 and the second-stage amplification unit 22 in the pre-amplifier unit 20 operate in the first voltage domain. Similarly, the area of each transistor in the third-stage amplification unit 23 can be reduced so that the third-stage amplification unit 23 in the pre-amplifier unit 20 operates in the first voltage domain. In this way, since the first voltage domain is smaller than the second voltage domain, by reducing the area of each transistor in the pre-amplifier unit 20, not only can the leakage of each device in the pre-amplifier unit 20 be reduced, but the overall area of the pre-amplifier unit 20 can also be greatly reduced, thereby optimizing overall performance and saving costs.

[0079] Figure 5 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application is shown. Figure 1 .like Figure 5 As shown, as an embodiment, the step-down unit 10 includes:

[0080] The first voltage dividing branch 101 is used to divide the first analog voltage input from the first input terminal of the pre-amplifier unit 20 so that the divided first analog voltage is adapted to the first voltage domain. The second voltage dividing branch 102 is used to divide the second analog voltage input from the second input terminal of the pre-amplifier unit 20 so that the divided second analog voltage is adapted to the first voltage domain. Figure 5As shown, in this embodiment, the pre-amplifier unit 20 is connected to the analog signal source 110. It can be understood that since the analog voltage provided by the analog signal source 110 generally refers to an analog voltage pair / analog voltage difference, that is, the analog voltage can specifically be a pair of differential voltages, in this embodiment, the analog signal source 110 can transmit the analog voltage to the pre-amplifier unit 20 through two paths. In order to achieve a step-down operation on the analog voltage, the first voltage dividing branch 101 in the step-down unit 10 is connected to the first intermediate node of the pre-amplifier unit 20 to form a first voltage dividing node P1, and the second voltage dividing branch 102 in the step-down unit 10 is connected to the second intermediate node of the pre-amplifier unit 20 to form a second voltage dividing node P2, so that the first voltage dividing branch 101 and the second voltage dividing branch 102 can simultaneously perform a step-down operation on the differential voltage pair, thereby achieving a step-down operation on the analog voltage.

[0081] In a specific implementation, the first voltage dividing branch 101 and the second voltage dividing branch 102 can be voltage dividing branches implemented by resistors or capacitors, and the first intermediate node and the second intermediate node of the pre-amplifier unit 20 are connected to form a first voltage dividing node P1 and a second voltage dividing node P2, thereby realizing the voltage division of the analog voltage flowing through the first voltage dividing node P1 and the second voltage dividing node P2.

[0082] exist Figure 5 In the example shown, the first voltage-dividing branch 101 is used to divide the first analog voltage input from the first input terminal of the pre-amplifier unit 20, and the second voltage-dividing branch 102 is used to divide the second analog voltage input from the second input terminal of the pre-amplifier unit 20. Both of them are used to synchronously step down the first analog voltage and the second analog voltage by discharging discharge energy through voltage division. This can not only effectively achieve voltage clamping for the analog voltage at the first input terminal and the analog voltage at the second input terminal of the pre-amplifier unit 20, but also avoid introducing other device characteristics or other interference signals, and can further improve the stability of the comparator.

[0083] Figure 6 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application is shown. Figure 2 .like Figure 6As shown, as an embodiment, the pre-amplification unit 20 includes at least a first-stage amplification unit 21 and a second-stage amplification unit 22. Specifically, the first input terminal of the first-stage amplification unit 21 is connected to the first output terminal of the analog signal source 110, the second input terminal of the first-stage amplification unit 21 is connected to the second output terminal of the analog signal source 110, the first intermediate node of the first-stage amplification unit 21 is connected to the first voltage divider branch 101, and the second intermediate node of the first-stage amplification unit 21 is connected to the second voltage divider branch 102. The first input terminal of the second-stage amplification unit 22 is connected to the first output terminal of the first-stage amplification unit 21, and the second input terminal of the second-stage amplification unit 22 is connected to the second output terminal of the first-stage amplification unit 21. The first output terminal and the second output terminal of the second-stage amplification unit 22 are both used to connect to the comparison unit 30.

[0084] In this embodiment, the first midpoint of the first-stage amplifying unit 21 serves as the first intermediate node P1 for connecting to the first voltage dividing branch 101 , and the second midpoint of the first-stage amplifying unit 21 serves as the second intermediate node P2 for connecting to the second voltage dividing branch 102 .

[0085] and Figure 4 The difference between the embodiments is that the first-stage amplification unit 21 in this embodiment is provided with a first midpoint and a second midpoint, and the first voltage divider branch 101 is connected through the first midpoint, and the second midpoint is connected to the second voltage divider branch 102. The analog voltage can be stepped down before being amplified, and the stepped-down analog voltage is adapted to the first voltage domain, so that the first-stage amplification unit 21 and the second-stage amplification unit 22 can amplify it once.

[0086] Figure 7 A schematic diagram of the specific structure of a comparator provided in another embodiment of the present application is shown. Figure 3 .like Figure 7 As shown, as an embodiment, the pre-amplification unit 20 further includes a three-stage amplification unit 23. A first input end of the three-stage amplification unit 23 is connected to a first output end of the two-stage amplification unit 22, a second input end of the three-stage amplification unit 23 is connected to a second output end of the two-stage amplification unit 22, and a first output end and a second output end of the three-stage amplification unit 23 are both connected to the comparison unit 30.

[0087] exist Figure 7 In the embodiment shown, the three-stage amplification unit 23 and Figure 4 It is easy to understand that in Figure 4 The embodiment shown and Figure 7 In the illustrated embodiment, the specific circuits of the first-stage amplifying unit 21 , the second-stage amplifying unit 22 , and the third-stage amplifying unit 23 may be implemented using the same amplifier circuit.

[0088] It is easy to understand that in a specific implementation, the comparison unit 30 includes a latch circuit. Since the kick-back noise of the latch circuit itself affects the input voltage, that is, it has a certain impact on the amplified analog voltage. Therefore, in order to suppress / eliminate the kick-back noise of the latch circuit itself, the specific circuits of the first-stage amplification unit 21, the second-stage amplification unit 22 and the third-stage amplification unit 23 can adopt a static pre-amplifier, which can amplify the stepped-down analog voltage through high gain, thereby reducing the sensitivity of the subsequent latch circuit to noise.

[0089] As an implementation method, the specific implementation circuits of the first-stage amplification unit 21, the second-stage amplification unit 22, and the third-stage amplification unit 23 can also be designed based on offset storage technology. Specifically, by combining input offset storage technology with cascade amplification, the offset storage technology can be used to periodically sample and compensate for the input stage offset voltage (for example, via a switched capacitor or dynamic correction circuit) to dynamically correct the offset of the preceding stage, significantly reducing the overall offset. Since the offset of the preceding stage in the cascade structure is corrected, the error amplification effect of the subsequent stage is suppressed, thereby improving the overall output accuracy.

[0090] As an example, input offset storage can be used to add a storage capacitor to the preamplifier input terminal. This allows the input offset voltage to be captured and stored during the reset phase, and the coupling effect of the kickback noise to be offset during the comparison phase. For example, the specific implementation circuits of the first-stage amplification unit 21, the second-stage amplification unit 22, and the third-stage amplification unit 23 can all adopt an input offset storage structure, with capacitors connected in series between the two input terminals of the preamplifier. This allows the input offset voltage to be captured and stored during the reset phase, and the coupling effect of the kickback noise to be offset during the comparison phase.

[0091] In conjunction with the above example, as another example, the input offset storage technology can be combined with output offset storage, that is, the offset voltage can be stored in a capacitor at the output of the preamplifier. For example, the specific implementation circuits of the first-stage amplification unit 21 and the second-stage amplification unit 22 can both adopt an input offset storage structure, with capacitors connected in series between the two input terminals of the preamplifier. The specific implementation circuit of the third-stage amplification unit 23 can adopt an output offset storage structure, with capacitors connected in series between the two output terminals of the preamplifier, thereby storing the offset voltage in the capacitor at the output of the preamplifier.

[0092] As an embodiment, the first-stage amplifying unit 21, the second-stage amplifying unit 22, and the third-stage amplifying unit 23 include the same amplifying circuit. The first input terminal of the amplifying circuit serves as the first input terminal of the pre-amplifying unit 20, the second input terminal of the amplifying circuit serves as the second input terminal of the pre-amplifying unit 20, the first output terminal of the amplifying circuit serves as the first output terminal of the pre-amplifying unit 20, and the second output terminal of the amplifying circuit serves as the second output terminal of the pre-amplifying unit 20.

[0093] Figure 8 FIG. 1 shows a specific circuit diagram of the amplifier circuit in the embodiment of the present application. Figure 8 As shown, as an embodiment, the amplifier circuit includes: a first input capacitor C1, a second input capacitor C2, a first switch S1, a second switch S2, and a pre-amplifier D. The first end of the first input capacitor C1 serves as the first input end of the amplifier circuit, the second end of the first input capacitor C1 is commonly connected to the first end of the first switch S1 and the first input end of the pre-amplifier D, the second end of the first switch S1 is connected to the negative output end of the pre-amplifier D, the first end of the second input capacitor C2 serves as the second input end of the amplifier circuit, the second end of the second input capacitor C2 is commonly connected to the first end of the second switch S2 and the second input end of the pre-amplifier D, and the second end of the second switch S2 is connected to the positive output end of the pre-amplifier.

[0094] In this embodiment, the amplifier circuit adopts an input offset storage technology amplifier circuit. In the specific implementation, the two groups can be Figure 8 The amplifier circuits shown are cascaded to construct the cascaded first-stage amplifier unit 21 and the second-stage amplifier unit 22. Similarly, the three groups can be Figure 8 The amplifier circuits shown are cascaded to form a cascaded first-stage amplifier unit 21 , a second-stage amplifier unit 22 , and a third-stage amplifier unit 23 .

[0095] Figure 9 FIG. 1 shows a schematic diagram of the overall circuit of the comparator provided in the embodiment of the present application. Figure 9 As shown, the first-stage amplification unit 21, the second-stage amplification unit 22, and the third-stage amplification unit 23 are all amplifier circuits based on input offset storage technology. In the first-stage amplification unit 21, the node formed by the connection between the input capacitor C1 and the first input terminal of the preamplifier D1 serves as the first midpoint. This first midpoint is used to connect to the first voltage divider branch 101, and in this case, the first midpoint also serves as the first voltage divider node P1. Similarly, the node formed by the connection between the input capacitor C2 and the second input terminal of the preamplifier D1 serves as the second midpoint. This second midpoint is used to connect to the second voltage divider branch 102, and in this case, the second midpoint also serves as the second voltage divider node P2.

[0096] exist Figure 9 In the figure, the first voltage divider branch 101 includes a voltage divider capacitor C3, and the second voltage divider branch 102 includes a voltage divider capacitor C4. Let the analog voltage be Vin, and the voltage is divided by the input capacitor C1 and the voltage divider C3 to obtain Vx. At this time, the value of Vx can be expressed as: Vx = C1*Vin / (C1+C3). Among them, C1 is the capacitance value of the input capacitor C1, and C3 is the capacitance value of the voltage divider capacitor C3. For example, taking the first voltage domain as 3.3V as an example, by setting the capacitance ratio between the input capacitor C1 and the voltage divider capacitor C3, the Vx voltage can be adapted to the first voltage domain 3.3V.

[0097] The following combination Figure 9 The circuit diagram shown in FIG. 1 illustrates the principle of offset voltage calibration.

[0098] 1) During the offset calibration phase, all switches in each amplifier stage are closed. That is, switch pair S0, switch pair S1, and switch pair S2 are all high, and all switch pairs are closed. The offset voltage of each amplifier stage is stored in the corresponding output capacitor, and the output of the latch is 0. Here, the output capacitors of preamplifier D1 are capacitors C5 and C6, and the output capacitors of preamplifier D2 are capacitors C7 and C8.

[0099] 2) During the pre-amplification phase, switch pairs S0, S1, and S2 are not disconnected simultaneously, but are disconnected in a specific sequence. For example, switch pairs S0 and S1 are disconnected in sequence, with switch pair S2 being disconnected last.

[0100] In the sampling and amplification stage of each amplifier unit:

[0101] First, Vin of the first-stage amplifier unit 21 can be shorted to a preset voltage, VCM. Because the switches are closed during the reset phase, the outputs of the three amplifier stages are clamped to their respective common-mode voltages. Let the voltage difference across input capacitor C1 be VC1, the voltage difference across input capacitor C5 be VC5, and the voltage difference across input capacitor C7 be VC7.

[0102] For the first-stage amplification unit 21:

[0103] In the sampling stage: (VX-Vos1)(-A1)=VX, which can be transformed into VX=Vos1×A1 / (1+A1); where: VC1=VCM-VX, VCM is a preset given voltage, Vos1 is the offset voltage of the pre-amplifier D1 in the first-stage amplification unit 21, and A1 is the gain of the pre-amplifier D1 in the first-stage amplification unit 21.

[0104] In the amplification stage: (Vin-VC1-Vos1)(-A1)=Vout1, wherein Vout1 is the output voltage of the pre-amplifier D1 in the first-stage amplification unit 21.

[0105] By simplifying, we can obtain: (Vin-VCM-1 / (1+A1)×Vos1)(-A1)=Vout1. Based on this, it can be seen that the offset voltage Vos1 of the preamplifier D1 in the first-stage amplification unit 21 is multiplied by 1 / (1+A1), which is equivalent to reducing the offset voltage Vos1 of the preamplifier D1 by (1+A1) times.

[0106] For the secondary amplification unit 22:

[0107] In the sampling phase: (VY-Vos2)(-A2)=VY, which can be transformed to VY=Vos2×A2 / (1+A2); where VC5=VCM1-VX, VCM1 is the common-mode voltage of the pre-amplifier D1 in the first-stage amplification unit 21 in the sampling phase, and A2 is the gain of the pre-amplifier D2 in the second-stage amplification unit 22.

[0108] In the amplification stage: (Vout1−VC5−Vos2)(−A2)=Vout2, where Vout2 is the output voltage of the pre-amplifier D2 in the secondary amplification unit 22.

[0109] By simplification, we can obtain: (Vout1-VCM1-1 / (1+A2)×Vos2)(-A2)=Vout2. Similarly, it can be seen that compared with the circuit without offset storage, the offset voltage is attenuated by (1+A2). Similarly, for the three-stage amplification unit 23, the offset voltage is attenuated by (1+A3).

[0110] for Figure 9 For the circuit shown in FIG. 1 , the input offset voltage of the entire comparator 100 can be expressed as:

[0111] ΔV OS =ΔQ / (A1*A2*C)+Vos3 / (A1*A2)+VOSL / (A1*A2*A3); where Vos3 is

[0112] VOSL is the offset voltage of the preamplifier D3 in the three-stage amplification unit 23; VOSL is the offset voltage of the latch. It is easy to understand that when the stepped-down analog voltage is amplified by the first-stage amplification unit 21, the second-stage amplification unit 22, and the third-stage amplification unit 23, the offset voltage injected by the input capacitor is relatively small after the gain of each stage of the amplification unit. Therefore, in the above formula, ΔQ / C can represent the offset voltage generated by the charge injected into the input capacitor corresponding to each stage of the amplification unit 21, the second-stage amplification unit 22, and the third-stage amplification unit 23, and can also represent the sum of the offset voltages generated by the charge injected into all input capacitors.

[0113] Figure 10 FIG. 1 shows a schematic diagram of the specific structure of the comparison unit in the comparator provided in the embodiment of the present application. Figure 10 As shown, the comparison unit 30 includes:

[0114] The comparison circuit 31 includes a first voltage input terminal 311, a second voltage input terminal 312, a first connection node PA, and a second connection node PB. The first noise cancellation branch 32 is connected between the first voltage input terminal 311 and the second connection node PB of the comparison circuit 31. The second noise cancellation branch 33 is connected between the second voltage input terminal 312 of the comparison circuit 31 and the first connection node PA.

[0115] In this embodiment, the comparison circuit 31 can be implemented using a latch circuit. Since the kickback noise of the latch circuit itself affects the input voltage, it also has a certain impact on the amplified analog voltage. For example, when the latch circuit operates in the comparison stage, the jump of the clock signal (i.e., the CLK signal) will cause a voltage mutation at the internal node of the latch circuit (such as the output end of the cross-coupled inverter). This mutation is coupled to the sensitive node of the input end through the parasitic capacitance of the transistor in the latch circuit (such as the gate-drain capacitance of the MOS tube), interfering with the original input signal, that is, it has a certain impact on the amplified analog voltage. Here, the sensitive nodes of the input end are the first connection node PA and the second connection node PB. By connecting the first noise cancellation branch 32 between the first voltage input terminal 311 of the comparison circuit 31 and the second connection node PB, and connecting the second noise cancellation branch 33 between the second voltage input terminal 312 of the comparison circuit 31 and the first connection node PA, the response of the parasitic capacitance of the transistors corresponding to the first voltage input terminal 311 and the second voltage input terminal 312 in the latch circuit to the sudden change signal can be suppressed, thereby suppressing or eliminating the voltage sudden change of the internal node of the latch circuit, and further preventing the sudden change from being coupled to the sensitive node of the input terminal through the parasitic capacitance of the transistor in the latch circuit, thereby eliminating the kick-back noise.

[0116] Figure 11 The specific circuit diagram of the comparison unit in the comparator provided in the embodiment of the present application is shown. Figure 1 . Combined Figure 10 and Figure 11 As an embodiment, the comparison circuit 31 includes: a first transistor MP1, a second transistor MP2, a third transistor MP3, a fourth transistor MP4, a fifth transistor MP5, a sixth transistor MN6, a seventh transistor MN7, an eighth transistor MP8, a ninth transistor MN9, a tenth transistor MN10, an eleventh transistor MN11, a first inverter U1, and a second inverter U2.

[0117] The control terminal of the first transistor MP1 is used to input the clock signal CLK. The first terminal of the first transistor MP1 and the first terminal of the second transistor MP2 are commonly connected to the power supply terminal AVD3. The second terminal of the first transistor MP1 and the second terminal of the second transistor MP2 are commonly connected to the first terminal of the first inverter U1. The second terminal of the first inverter U1 serves as the negative output terminal VOUTN of the comparison circuit 31. The control terminal of the second transistor MP2 is connected to the first terminal of the second inverter U2. The second terminal of the second inverter U2 serves as the positive output terminal VOUTP of the comparison circuit 31.

[0118] A first end of the third transistor MP3 and a first end of the fourth transistor MP4 are commonly connected to the power supply terminal AVD3. A control end of the fourth transistor MP4 is used to input a clock signal CLK. The control end of the third transistor MP3 is connected to a first end of the first inverter U1. A second end of the third transistor MP3 and a second end of the fourth transistor MP4 are commonly connected to a first end of the second inverter U2.

[0119] The control terminal of the fifth transistor MP5 is used to input the clock signal CLK. The first terminal of the fifth transistor MP5 is connected to the power supply terminal AVD3. The second terminal of the fifth transistor MP5 and the first terminal of the sixth transistor MN6 are connected to form a node serving as a first connection node PA. The second terminal of the sixth transistor MN6 and the control terminal of the seventh transistor MN7 are commonly connected to the first terminal of the first inverter U1. The control terminal of the sixth transistor MN6 is connected to the first terminal of the second inverter U2.

[0120] A control terminal of the eighth transistor MP8 is used to input a clock signal CLK. A first terminal of the eighth transistor MP8 is connected to the power supply terminal AVD3. A node formed by connecting the second terminal of the eighth transistor MP8 and the first terminal of the seventh transistor MN7 serves as a second connecting node PB. A second terminal of the seventh transistor MN7 is connected to a first terminal of the second inverter U2. A control terminal of the seventh transistor MN7 is connected to a first terminal of the first inverter U1.

[0121] The control terminal of the ninth transistor MN9 serves as the first voltage input terminal VIN of the comparison circuit 31 , the first terminal of the ninth transistor MN9 is connected to the first terminal of the tenth transistor MN10 , and the second terminal of the ninth transistor MN9 is connected to the first connection node PA.

[0122] The control terminal of the tenth transistor MN10 serves as the second voltage input terminal VIP of the comparison circuit 31. The second terminal of the tenth transistor MN10 is connected to the second connection node PB. The control terminal of the eleventh transistor MN11 is used to input the clock signal CLK. The first terminal of the eleventh transistor MN11 is grounded, and the second terminal of the eleventh transistor MN11 is commonly connected to the first terminal of the ninth transistor MN9 and the first terminal of the tenth transistor MN10.

[0123] Combine Figure 10 and Figure 11 The input voltage of the comparison circuit 31 is the amplified analog voltage. When the comparison circuit 31 is operating, the input voltage determines the current at the control terminal of the ninth transistor MN9 and the current at the control terminal of the tenth transistor MN10. That is, the voltage at the drain terminal of the ninth transistor MN9 and the tenth transistor MN10 will also experience a large jump. Among them, the gate-drain parasitic capacitance of the ninth transistor MN9 and the tenth transistor MN10 is both Cgd. When receiving the amplified analog voltage, the first connection node PA and the second connection node PB will show a phenomenon of increase and decrease depending on the magnitude of the amplified analog voltage. When the amplified analog voltage is a pair of small voltage differences, the voltages of the first connection node PA and the second connection node PB may be coupled to the first voltage input terminal VIN and the second voltage input terminal VIP through the parasitic capacitances Cgd1 and Cgd2, causing the voltages of the first voltage input terminal VIN and the second voltage input terminal VIP to change, thereby causing a comparison error.

[0124] Combine Figure 10 and Figure 11 In order to eliminate the above noise influence, Figure 11 In the illustrated embodiment, the first noise cancellation branch 32 includes a first capacitor Cn1. The second noise cancellation branch 33 includes a second capacitor Cn2. A first end of the first capacitor Cn1 is connected to the first voltage input terminal VIN of the comparison circuit 31, and a second end of the first capacitor Cn1 is connected to the second connection node PB. A first end of the second capacitor Cn2 is connected to the second voltage input terminal VIP of the comparison circuit 31, and a second end of the second capacitor Cn2 is connected to the first connection node PA.

[0125] exist Figure 11 In the circuit, since the voltages at the first connection node PA and the second connection node PB increase and decrease, the first capacitor Cn1 and the second capacitor Cn2 are provided so that Cn1 = Cgd1 and Cn2 = Cgd2. When the voltage at the first connection node PA changes, the parasitic capacitor Cgd1 and the first capacitor Cn1 produce the same charge change at the first voltage input terminal VIN. Similarly, when the voltage at the second connection node PB changes, the parasitic capacitor Cgd2 and the second capacitor Cn2 produce the same charge change at the second voltage input terminal VIP. This significantly reduces the noise generated by parasitic capacitance, suppresses non-ideal characteristics of the circuit, improves the robustness of the circuit, and enhances the accuracy of the comparison circuit.

[0126] Figure 12 The specific circuit diagram of the comparison unit in the comparator provided in the embodiment of the present application is shown. Figure 2 . Combined Figure 10 and Figure 12The first noise cancellation branch 32 includes a twelfth transistor MN12. The second noise cancellation branch 33 includes a thirteenth transistor MN13.

[0127] The first and second terminals of the twelfth transistor MN12 are connected to the first voltage input terminal VIN, and the control terminal of the twelfth transistor MN12 is connected to the second connection node PB. The first and second terminals of the thirteenth transistor MN13 are connected to the second voltage input terminal VIP, and the control terminal of the thirteenth transistor MN13 is connected to the first connection node PA.

[0128] As an embodiment, the area of the twelfth transistor MN12 is less than or equal to 1 / 2 of the area of the ninth transistor MN9 . Similarly, the area of the thirteenth transistor MN13 is less than or equal to 1 / 2 of the area of the tenth transistor MN10 .

[0129] exist Figure 12 In the example shown, the twelfth transistor MN12 corresponds to the ninth transistor MN9, and the thirteenth transistor MN13 corresponds to the tenth transistor MN10. That is, in a specific implementation, the twelfth transistor MN12 can be a transistor of the same model as the ninth transistor MN9 and smaller in size than the ninth transistor MN9. Similarly, the thirteenth transistor MN13 can be a transistor of the same model as the tenth transistor MN10 and smaller in size than the ninth transistor MN9. In this way, the relationship between the twelfth transistor MN12 and the parasitic capacitance Cgd1 can be strengthened. Similarly, the relationship between the thirteenth transistor MN13 and the parasitic capacitance Cgd2 can be strengthened, so that the parasitic capacitance effect deviation is reduced due to the action of the twelfth transistor MN12 and the thirteenth transistor MN13.

[0130] Figure 13 The schematic diagram of the structure of the analog-to-digital conversion circuit provided in the embodiment of the present application is shown Figure 1 .like Figure 13 As shown, the embodiment of the present application further provides an analog-to-digital conversion circuit 200, as shown in FIG. Figure 13 As shown, the analog-to-digital conversion circuit 200 includes:

[0131] An analog signal source 110 suitable for the second voltage domain, used for sampling the signal source and outputting a corresponding analog voltage; and the comparator 100 provided in the above embodiment.

[0132] Figure 14 The schematic diagram of the structure of the analog-to-digital conversion circuit provided in the embodiment of the present application is shown Figure 2 .like Figure 14As shown, as an embodiment, the analog-to-digital conversion circuit 200 further includes a signal source selection unit 120. The signal source selection unit 120 includes N sampling channels, each of which includes sampling resistors (R1 to Rn) and path switches (SW1 to SWn). Where N is a positive integer greater than 1.

[0133] The first ends of the sampling resistors (R1-Rn) are connected to the signal sources (vin1-vinn), and the second ends of the sampling resistors (R1-Rn) are connected to the path switches (SW1-SWn). The path switches (SW1-SWn) are used to open or close the path between the sampling resistors (R1-Rn) and the analog signal source 110.

[0134] It is understandable that the analog-to-digital conversion circuit 200 provided in this embodiment, the improvements and specific implementations related to this application are all in Figures 1 to 13 The embodiments shown are described in detail, so no further details will be given here.

[0135] The present application also provides a chip including the above-mentioned analog-to-digital conversion circuit. An integrated circuit (IC) is also referred to as a chip, and the chip may be, but is not limited to, a SOC (System on Chip) chip or a SIP (System in Package) chip. Since the chip of the present application has the comparator 100 provided in the above-mentioned embodiment, or has the analog-to-digital conversion circuit 200 provided in the above-mentioned embodiment, it has all the beneficial effects of the analog-to-digital conversion circuit in the above-mentioned embodiment, which will not be described in detail here.

[0136] An embodiment of the present application also provides an electronic device, which includes a device body and at least one or any one of the comparator 100, analog-to-digital conversion circuit 200, and chips as described above, which are arranged in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a fast charger, a car charger, an adapter, a display, a USB (Universal Serial Bus) docking station, a stylus, a true wireless headset, a car central control panel, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminals). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0137] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A comparator, characterized in that: The comparator is adapted for a first voltage domain and is configured to receive an analog voltage provided by an analog signal source, wherein the analog signal source is adapted for a second voltage domain, the first voltage domain being smaller than the second voltage domain, and the comparator comprises: a step-down unit, configured to step down the analog voltage so that the stepped-down analog voltage is adapted to the first voltage domain; a pre-amplifier unit, configured to amplify the stepped-down analog voltage and output the amplified analog voltage; The comparison unit is used to compare the amplified analog voltage with a preset given voltage and output a comparison result corresponding to the analog voltage.

2. The comparator according to claim 1, wherein: The step-down unit comprises: A step-down circuit, wherein a first input end of the step-down circuit is connected to a first output end of the analog signal source, a second input end of the step-down circuit is connected to a second output end of the analog signal source, a first output end of the step-down circuit is connected to a first input end of the pre-amplifier unit, and a second output end of the step-down circuit is connected to a second input end of the pre-amplifier unit.

3. The comparator according to claim 2, wherein: The pre-amplification unit includes at least a first-stage amplification unit and a second-stage amplification unit; The first input end of the first-stage amplifying unit serves as the first input end of the pre-amplifying unit, and the second input end of the first-stage amplifying unit serves as the second input end of the pre-amplifying unit; The first input end of the secondary amplifying unit is connected to the first output end of the primary amplifying unit, the second input end of the secondary amplifying unit is connected to the second output end of the primary amplifying unit, and the first output end of the secondary amplifying unit and the second output end of the secondary amplifying unit are both used to connect to the comparison unit.

4. The comparator according to claim 1, wherein: The step-down unit comprises: a first voltage dividing branch, configured to divide the first analog voltage input from the first input terminal of the pre-amplifier unit so that the divided first analog voltage is adapted to the first voltage domain; The second voltage dividing branch is used to divide the second analog voltage input from the second input terminal of the pre-amplifier unit, so that the divided second analog voltage is adapted to the first voltage domain.

5. The comparator according to claim 4, wherein: The pre-amplification unit includes at least a first-stage amplification unit and a second-stage amplification unit; a first input end of the first-stage amplification unit is connected to a first output end of the analog signal source, a second input end of the first-stage amplification unit is connected to a second output end of the analog signal source, a first midpoint of the first-stage amplification unit is connected to the first voltage divider branch, and a second midpoint of the first-stage amplification unit is connected to the second voltage divider branch; The first input end of the secondary amplifying unit is connected to the first output end of the primary amplifying unit, the second input end of the secondary amplifying unit is connected to the second output end of the primary amplifying unit, and the first output end of the secondary amplifying unit and the second output end of the secondary amplifying unit are both used to connect to the comparison unit.

6. The comparator according to claim 3 or 5, wherein: The pre-amplification unit also includes a three-stage amplification unit; The first input end of the three-stage amplifying unit is connected to the first output end of the two-stage amplifying unit, the second input end of the three-stage amplifying unit is connected to the second output end of the two-stage amplifying unit, and the first output end of the three-stage amplifying unit and the second output end of the three-stage amplifying unit are both used to connect to the comparison unit.

7. The comparator according to claim 6, wherein: The first-stage amplifying unit, the second-stage amplifying unit and the third-stage amplifying unit include the same amplifying circuit; Among them, the first input end of the amplifier circuit serves as the first input end of the pre-amplifier unit, the second input end of the amplifier circuit serves as the second input end of the pre-amplifier unit, the first output end of the amplifier circuit serves as the first output end of the pre-amplifier unit, and the second output end of the amplifier circuit serves as the second output end of the pre-amplifier unit.

8. The comparator according to claim 7, wherein: The amplifier circuit includes: a first input capacitor, a second input capacitor, a first switch, a second switch and a pre-amplifier; The first end of the first input capacitor serves as the first input end of the amplifier circuit, the second end of the first input capacitor is commonly connected to the first end of the first switch and the first input end of the pre-amplifier, the second end of the first switch is connected to the negative output end of the pre-amplifier, the first end of the second input capacitor serves as the second input end of the amplifier circuit, the second end of the second input capacitor is commonly connected to the first end of the second switch and the second input end of the pre-amplifier, and the second end of the second switch is connected to the positive output end of the pre-amplifier.

9. The comparator according to claim 1, wherein: The comparison unit includes: A comparison circuit comprising a first voltage input terminal, a second voltage input terminal, a first connection node, and a second connection node; a first noise cancellation branch connected between the first voltage input terminal of the comparison circuit and the second connection node; The second noise cancellation branch is connected between the second voltage input terminal of the comparison circuit and the first connection node.

10. The comparator according to claim 9, wherein: The comparison circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, a first inverter, and a second inverter; The control terminal of the first transistor is used to input a clock signal, the first terminal of the first transistor and the first terminal of the second transistor are commonly connected to a power supply terminal, the second terminal of the first transistor and the second terminal of the second transistor are commonly connected to the first terminal of the first inverter, the second terminal of the first inverter serves as the negative output terminal of the comparison circuit, the control terminal of the second transistor is connected to the first terminal of the second inverter, and the second terminal of the second inverter serves as the positive output terminal of the comparison circuit; The first end of the third transistor and the first end of the fourth transistor are commonly connected to a power supply end, the control end of the fourth transistor is used to input a clock signal, the control end of the third transistor is connected to the first end of the first inverter, and the second end of the third transistor and the second end of the fourth transistor are commonly connected to the first end of the second inverter; The control terminal of the fifth transistor is used to input a clock signal, the first terminal of the fifth transistor is connected to the power supply terminal, the second terminal of the fifth transistor and the first terminal of the sixth transistor are connected to form a node serving as a first connection node, the second terminal of the sixth transistor and the control terminal of the seventh transistor are commonly connected to the first terminal of the first inverter, and the control terminal of the sixth transistor is connected to the first terminal of the second inverter; The control terminal of the eighth transistor is used to input a clock signal, the first terminal of the eighth transistor is connected to the power supply terminal, the second terminal of the eighth transistor and the first terminal of the seventh transistor are connected to form a node serving as the second connection node, the second terminal of the seventh transistor is connected to the first terminal of the second inverter, and the control terminal of the seventh transistor is connected to the first terminal of the first inverter; The control terminal of the ninth transistor serves as the first voltage input terminal of the comparison circuit, the first terminal of the ninth transistor is connected to the first terminal of the tenth transistor, and the second terminal of the ninth transistor is connected to the first connection node; The control terminal of the tenth transistor serves as the second voltage input terminal of the comparison circuit, and the second terminal of the tenth transistor is connected to the second connection node; The control terminal of the eleventh transistor is used to input a clock signal, the first terminal of the eleventh transistor is grounded, and the second terminal of the eleventh transistor is commonly connected to the first terminal of the ninth transistor and the first terminal of the tenth transistor.

11. The comparator according to claim 10, wherein: The first noise cancellation branch includes a first capacitor; the second noise cancellation branch includes a second capacitor; A first terminal of the first capacitor is connected to the first voltage input terminal of the comparison circuit, and a second terminal of the first capacitor is connected to the second connection node; A first end of the second capacitor is connected to the second voltage input end of the comparison circuit, and a second end of the second capacitor is connected to the first connection node.

12. The comparator according to claim 10, wherein: The first noise cancellation branch includes a twelfth transistor; the second noise cancellation branch includes a thirteenth transistor; The first terminal and the second terminal of the twelfth transistor are commonly connected to the first voltage input terminal, and the control terminal of the twelfth transistor is connected to the second connection node; The first terminal and the second terminal of the thirteenth transistor are commonly connected to the second voltage input terminal, and the control terminal of the thirteenth transistor is connected to the first connection node.

13. An analog-to-digital conversion circuit, characterized in that: The analog-to-digital conversion circuit comprises: An analog signal source suitable for a second voltage domain, configured to sample a signal from the signal source and output a corresponding analog voltage; and a comparator according to any one of claims 1 to 12.

14. A chip, characterized in that: The chip comprises the comparator according to any one of claims 1 to 12; and / or The chip includes the analog-to-digital conversion circuit according to claim 13.

15. An electronic device, characterized in that: The electronic device comprises the comparator according to any one of claims 1 to 12; and / or The electronic device comprises the analog-to-digital conversion circuit according to claim 13; and / or The electronic device comprises the chip according to claim 14.

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