Circuit having latch with multiple set inverters

Abstract

The invention relates to a circuit having a latch with multiple sets of inverters. A latch includes two outputs and two inputs, wherein the outputs latch complementary values indicative of a voltage at the latch inputs. The latch includes two sets of one or more inverters. For each set of inverters, the signal input of the first series inverter is connected to the latch input and the output of the last series inverter is connected to the latch output. The first series inverter of each set of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by another latch input. During a reset phase, the latch outputs are configured to be set to the same output value state. During the latching phase, the latch output is configured to latch a complementary output value state. In some embodiments, the latch is used in a comparison circuit.

Description

Technical Field

[0001] The present invention relates to a circuit having a latch with an inverter. Background Art

[0002] Latches are used in circuits to at least temporarily store data states for further use. For example, latches can be used in circuits such as comparison circuits to temporarily store a final comparison result. Summary of the Invention

[0003] In one embodiment, a circuit includes a latch. The latch includes a first input, a second input, a first output, a second output, and a first group of one or more inverters coupled in a signal series path. The signal input of the first series inverter of the first group is connected to the first input, and the signal output of the last series inverter of the first group is connected to the first output. The first series inverter of the first group includes a first power supply input configured to be biased by the second input. The latch includes a second group of one or more inverters coupled in the signal series path. The signal input of the first series inverter of the second group is connected to the second input, and the signal output of the last series inverter of the second group is connected to the second output. The first series inverter of the second group includes a first power supply input configured to be biased by the first input. During a reset phase, the first output and the second output are configured to be set to the same output value state. During a latch phase, the first output and the second output are configured to latch in complementary output value states that depend on the voltages of the first and second inputs.

[0004] Illustratively, during the reset phase, the first input and the second input are configured to be equalized in voltage.

[0005] Illustratively, during the reset phase, the first input and the second input are configured to equalize to a common mode voltage of a voltage of the first input and the second input before equalization.

[0006] Illustratively, the first group of one or more inverters includes two or more inverters, and the second group of one or more inverters includes two or more inverters.

[0007] Example:

[0008] The first series inverters of the first group and the first series inverters of the second group each include a P-type transistor coupled in series with an N-type transistor;

[0009] For the first series inverter of the first group, a first current terminal of one of the P-type transistor or the N-type transistor is configured to be biased by the second input, and a first current terminal of the other of the P-type transistor or the N-type transistor is configured to be biased by a voltage supply terminal;

[0010] For the first series inverter of the second group, the first current terminal of one of the P-type transistor or the N-type transistor is configured to be biased by the first input, and the first current terminal of the other of the P-type transistor or the N-type transistor is configured to be biased by the voltage supply terminal.

[0011] Example:

[0012] During a reset phase, the first input and the second input are configured to be equalized in voltage;

[0013] For the first series inverters of the first group, when the first input and the second input are equal in voltage, the other of the P-type transistor or the N-type transistor is turned on;

[0014] For the first series inverters of the second group, when the first input and the second input are balanced in voltage, the other of the P-type transistor or the N-type transistor is turned on.

[0015] Example:

[0016] For the first series inverters of the first group and the first series inverters of the second group, the P-type transistors are PFETs and the N-type transistors are NFETs;

[0017] For the first series inverter of the first group, the source terminal of the NFET is connected to the second input, and the source terminal of the PFET is configured to be biased by a high voltage supply terminal;

[0018] For the first series inverter of the second group, the source terminal of the NFET is connected to the first input, and the source terminal of the PFET is configured to be biased by the high voltage supply terminal.

[0019] Example:

[0020] For the first series inverters of the first group and the first series inverters of the second group, the P-type transistors are PFETs and the N-type transistors are NFETs;

[0021] For the first series inverter of the first group, the source terminal of the PFET is connected to the second input, and the source terminal of the NFET is configured to be biased by a low voltage supply terminal;

[0022] For the first series inverter of the second group, the source terminal of the PFET is connected to the first input, and the source terminal of the NFET is configured to be biased by the low voltage supply terminal.

[0023] Illustratively, the circuit further comprises:

[0024] A comparison circuit, the comparison circuit comprising the latch and a preamplifier circuit, the preamplifier circuit comprising:

[0025] First input;

[0026] Second input;

[0027] a first output coupled to the first input of the latch;

[0028] a second output coupled to the second input of the latch;

[0029] Wherein the first output of the latch and the second output of the latch are latched in complementary output value states, the complementary output value states indicating a comparison of the voltages of the first input of the preamplifier and the second input of the preamplifier.

[0030] For example, the preamplifier includes:

[0031] a first self-biased inverter comprising a signal input connected to the first output of the preamplifier and a signal output;

[0032] a second self-biased inverter comprising a signal input connected to the second output of the preamplifier and a signal output;

[0033] wherein during the pre-amplification phase of the comparison circuit, the high-side power supply input of the first self-biased inverter is configured to be biased by a high power supply voltage terminal, and the low-side power supply input of the first self-biased inverter is configured to be biased by a low power supply voltage terminal;

[0034] wherein during the pre-amplification stage, the high-side power supply input of the second self-biased inverter is configured to be biased by the high power supply voltage terminal, and the low-side power supply input of the second self-biased inverter is configured to be biased by the low power supply voltage terminal;

[0035] During a reset phase of the comparison circuit, the high-side power supply inputs of the first self-biased inverter and the second self-biased inverter are not configured to be biased by the high power supply voltage terminal, and the low-side power supply inputs of the first self-biased inverter and the second self-biased inverter are not configured to be biased by the low power supply voltage terminal.

[0036] Example:

[0037] The first output of the preamplifier is coupled to the first input of the latch via a first switch, and the second output of the preamplifier is coupled to the second input of the latch via a second switch;

[0038] wherein during the reset phase, the first switch and the second switch are configured to be open, and during the pre-amplification phase, the first switch and the second switch are configured to be closed;

[0039] During the reset phase, the first output of the preamplifier and the second output of the preamplifier are configured to be balanced, and during the preamplification phase, the first output of the preamplifier and the second output of the preamplifier are not balanced.

[0040] For example, during the preamplification stage, the preamplifier is configured to be biased by a high supply voltage terminal and by a low supply voltage terminal for providing power to the circuit system of the preamplifier, wherein during the reset mode, the preamplifier is configured not to be biased by the high supply voltage terminal and the low supply voltage terminal.

[0041] Illustratively, the comparison circuit further includes a second latch, wherein the second latch includes:

[0042] a first latching inverter and a second latching inverter configured in a cross-coupled configuration; wherein a signal input of the first latching inverter is coupled to the second output of the preamplifier, to a signal output of the second latching inverter and to the second input of the latch;

[0043] Wherein a signal input of the second latch inverter is coupled to the first output of the preamplifier, coupled to the signal output of the first latch inverter and coupled to the first input of the latch.

[0044] Example:

[0045] The signal input of the first latch inverter is coupled to the second output of the preamplifier via a first switch;

[0046] The signal input of the second latch inverter is coupled to the first output of the preamplifier via a second switch;

[0047] During the reset phase, the first switch and the second switch are opened; and during the pre-amplification phase, the first switch and the second switch are closed.

[0048] Example:

[0049] During the latching phase, the high-side power supply input of the first latching inverter is configured to be biased by the high power supply voltage terminal, and the low-side power supply input of the first latching inverter is configured to be biased by the low power supply voltage terminal to power the first latching inverter;

[0050] During the latching phase, the high-side power supply input of the second latching inverter is configured to be biased by the high power supply voltage terminal, and the low-side power supply input of the second latching inverter is configured to be biased by the low power supply voltage terminal, so as to power the second latching inverter;

[0051] wherein during the reset phase and the preamplification phase, the high-side supply input of the first latching inverter and the low-side supply input of the first latching inverter are configured to be unbiased;

[0052] During the reset phase and the pre-amplification phase, the high-side supply input of the second latching inverter and the low-side supply input of the second latching inverter are configured to be unbiased.

[0053] Another embodiment includes a method for comparing a voltage at a first input of a preamplifier with a voltage at a second input of the preamplifier. The method includes controlling a first switch to be in a conductive state during a reset phase to equalize the first and second outputs of the preamplifier, and controlling a second switch to be in a non-conductive state. The second switch is coupled at one end to the first output of the preamplifier and at a second end to a first signal input of a set of cross-coupled inverters. During the reset phase, a third switch is controlled to be in a non-conductive state. The third switch is coupled at one end to the second output of the preamplifier and at a second end to a second signal input of the set of cross-coupled inverters. During the reset phase, a fourth switch is controlled to be in a conductive state. The fourth switch is coupled at one end to a first input of a latch and to a second input of the latch. The latch includes a first output and a second output. The latch includes a first set of one or more inverters coupled in a series signal path, wherein the signal input of a first series inverter of the first set is connected to a first input of the latch, and the signal output of a last series inverter of the first set is connected to a first output of the latch, wherein the first series inverter of the first set includes a first supply input coupled to a second input of the latch to be biased by the second input of the latch. The latch includes a second set of one or more inverters coupled in the series signal path, wherein the signal input of a first series inverter of the second set is connected to the second input of the latch, and the signal output of a last series inverter of the second set is connected to the second output of the latch, wherein the first series inverter of the second set includes a first supply input coupled to the first input of the latch to be biased by the first input of the latch. During a reset phase, the first output of the latch and the second output of the latch are each in a first voltage state. During a preamplification phase, the first switch is controlled to be in a non-conducting state, the second switch and the third switch are controlled to be in a conducting state, and the fourth switch is controlled to be in a non-conducting state. During the latching phase, the second switch and the third switch are controlled to be in a non-conducting state. During the latching phase, the first output and the second output of the latch circuit are each in a complementary state to each other to indicate a comparison result of the voltage of the first input of the preamplifier and the voltage of the second input of the preamplifier.

[0054] Example:

[0055] During the reset phase:

[0056] controlling the bias of the high supply voltage node of the preamplifier to be in an unbiased condition;

[0057] controlling the bias of the low supply voltage node of the preamplifier to be in an unbiased condition;

[0058] During the pre-amplification stage:

[0059] biasing the high supply voltage node of the preamplifier at a high supply voltage;

[0060] The low supply voltage node of the preamplifier is biased at a low supply voltage.

[0061] Example:

[0062] During the reset phase and during the preamplification phase:

[0063] controlling the bias of the high supply voltage nodes of the set of cross-coupled inverters to be in an unbiased condition;

[0064] controlling the bias of the low supply voltage nodes of the set of cross-coupled inverters to be in an unbiased condition;

[0065] During the latch phase:

[0066] biasing the high supply voltage node of the set of cross-coupled inverters at a high supply voltage;

[0067] The low supply voltage node of the set of cross-coupled inverters is biased at a low supply voltage.

[0068] In another embodiment, a comparison circuit includes a preamplifier including a first input, a second input, a first output, a second output, and a first switch coupled between the first output and the second output, wherein when the first switch is on, a voltage of the first output and a voltage of the second output are equalized. The comparison circuit includes a set of cross-coupled inverters including a first signal input coupled to the first output of the preamplifier via a second switch, a second signal input coupled to the second output of the preamplifier via a third switch, a first signal output, and a second signal output. The comparison circuit includes a latch including a first input coupled to the first signal output of the set of cross-coupled inverters, a second input coupled to the second signal output of the set of cross-coupled inverters, and a fourth switch coupled between the first input and the second input of the latch, wherein when the fourth switch is on, a voltage of the first input of the latch and a voltage of the second input of the latch are equalized. The latch comprises a first latch output, a second latch output, and a first set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the first set is connected to a first input of the latch, and a signal output of a last series inverter of the first set is connected to the first latch output, wherein the first series inverter of the first set comprises a first supply input, the first supply input being coupled to a second input of the latch to be biased by the second input of the latch. The latch comprises a second set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the second set is connected to a second input of the latch, and a signal output of a last series inverter of the second set is connected to a second latch output, wherein the first series inverter of the second set comprises a first supply input, the first supply input being coupled to a first input of the latch to be biased by the first input of the latch. During a latching phase, the first latch output and the second latch output are latched in complementary output value states, the complementary output value states indicating a comparison of the voltages of the first input of the preamplifier and the second input of the preamplifier.

[0069] For example, when the comparison circuit is in the reset phase:

[0070] The first switch and the fourth switch are configured to be turned on;

[0071] The second switch and the third switch are configured to be non-conductive;

[0072] The high supply voltage node and the low supply voltage node of the set of cross-coupled inverters are configured to be unbiased;

[0073] A high supply voltage node and a low supply voltage node of the preamplifier are configured to be unbiased. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] By referencing the accompanying drawings, the present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art.

[0075] Figure 1 is a circuit diagram of a comparison circuit including a latch according to an embodiment of the present invention.

[0076] Figure 2 According to one embodiment of the present invention Figure 1 Timing diagram of the circuit.

[0077] Figure 3 is a circuit diagram of a latch according to one embodiment of the present invention.

[0078] Unless otherwise indicated, the same reference numerals are used in different figures to indicate the same items.The figures are not necessarily drawn to scale. DETAILED DESCRIPTION

[0079] The following is a detailed description of a mode for carrying out the invention. This description is intended to be illustrative of the invention and should not be considered limiting.

[0080] Disclosed herein is a latch comprising two outputs and two inputs, wherein the output latch indicates a complementary value of the voltage at the latch input. The latch comprises two groups of one or more inverters each coupled in a signal series path. For each group of inverters, the signal input of the first series inverter is connected to the latch input, and the output of the last series inverter is connected to the latch output. The first series inverter of each group of one or more inverters has a signal input connected to one latch input and a supply voltage input configured to be biased by another latch input. During the reset phase, the latch output is configured to be set to the same output value state. During the latch phase, the latch output is configured to latch in a complementary output value state depending on the voltage of the first input and the second input. In some embodiments, the latch is used in a comparison circuit, wherein the output indicates a comparison result of the two inputs of the comparison circuit.

[0081] One advantage of providing a latch in which a first series inverter has a signal input connected to one of the latch inputs and a supply input coupled to the other latch input is that, in some embodiments, the latch changes state of an output value based on a voltage differential between the two latch inputs transmitting a particular threshold voltage, thereby allowing for faster transmission across the latch. Furthermore, setting the latch output to the same output value during a reset phase can advantageously provide synchronization for output data and avoid intersymbol interference from previous circuitry generating the latch input signal.

[0082] Figure 1 1 is a circuit diagram of a comparator circuit according to one embodiment of the present invention. Comparator circuit 101 includes a preamplifier 103, a latch 104, and a latch 105. The outputs (VOUT+, VOUT-) of latch 105 provide a latched differential indication of the voltage difference between the inputs (VIN+, VIN-) of preamplifier 103. In the illustrated embodiment, comparator circuit 101 operates in three phases: a reset phase, a preamplification phase, and a latch phase.

[0083] Preamplifier 103 includes two inputs (VIN+, VIN-). VIN+ is connected to the signal input of inverter 107, which includes P-type field-effect transistor (PFET) 113 and N-type field-effect transistor (NFET) 111. The signal output of inverter 107 is connected to preamplifier output VI+. VIN- is connected to the signal input of inverter 109, which includes PFET 117 and NFET 115. The signal output of inverter 109 is connected to preamplifier output VI-. Outputs VI+ and VI- are each connected to a terminal of a switch 119 controlled by a signal PHR. Switch 119 is closed during the reset phase to equalize the voltages of VI+ and VI-. Signal PHR is provided by controller 106.

[0084] Preamplifier 103 includes two self-biased inverters 125 and 127. Inverter 125 includes a PFET 131 and an NFET 129. The signal input and signal output of inverter 125 are connected to preamplifier output VI-. Inverter 127 includes a PFET 135 and an NFET 133. The signal input and signal output of inverter 127 are connected to preamplifier output VI+.

[0085] Preamplifier 103 includes a latch of two cross-coupled inverters 137 and 139. Inverter 137 includes a PFET 143 and an NFET 141. The signal input of inverter 137 is connected to VI+ and to the signal output of inverter 139. Inverter 139 includes a PFET 147 and an NFET 145. The signal input of inverter 139 is connected to VI- and to the signal output of inverter 137.

[0086] The high supply inputs of inverters 107, 109, 125, 127, 137, and 139 (the sources of the inverter's PFETs) are coupled to a high supply voltage terminal VDD via a switch 123 controlled by a PHPA signal from controller 106. The low supply inputs of inverters 107, 109, 125, 127, 137, and 139 (the sources of the inverter's NFETs) are coupled to a low supply voltage terminal VSS via a switch 121 controlled by a PHPA signal. In one embodiment, switch 123 is implemented by a PFET, and switch 121 is implemented by an NFET. However, in other embodiments, these switches may be implemented by other types of switches (e.g., pass gates, transmission gates, or other types of transistors).

[0087] During the preamplification phase, switches 123 and 121 are closed to provide power to the circuitry of preamplifier 103 to bias the upper supply node (e.g., the upper supply input of inverters 107, 109, 125, 127, 137, and 139) and the lower supply node (e.g., the lower supply input of inverters 107, 109, 125, 127, 137, and 139) at VDD and VSS, respectively. During other phases of comparator circuit 101 (e.g., reset phase, latch phase), switches 123 and 121 are open. See below. Figure 2 Discussion.

[0088] Comparison circuit 101 includes latch 104, which includes cross-coupled inverters 155 and 157. In one embodiment, inverters 155 and 157 each include a PFET and an NFET (not shown, but similar to the latch circuits of inverters 137 and 139). The signal input of inverter 155 is connected to a terminal of switch 153, to the output of inverter 157, and to the VL- input of latch 105. The input of inverter 157 is connected to a terminal of switch 151, to the output of inverter 155, and to the VL+ input of latch 105. The other terminal of switch 153 is connected to the VI+ output of preamplifier 103, and the other terminal of switch 151 is connected to the VI- output of preamplifier 103. In one embodiment, switches 153 and 151 are implemented using NFETs, but may be implemented using other types of switches (pass gates, transmission gates, or other types of transistors, such as PFETs).

[0089] The high supply input of inverter 155 is coupled to a high supply voltage terminal VDD via switch 165, and the low supply terminal of inverter 155 is coupled to a low supply voltage terminal VSS via switch 163. The high supply input of inverter 157 is coupled to a high supply voltage terminal VDD via switch 161, and the low supply terminal of inverter 157 is coupled to a low supply voltage terminal VSS via switch 159. Switches 165, 163, 161, and 159 are controlled by signal PHL from controller 106 and are conductive during the latch phase and non-conductive during the preamplification phase and the reset phase. In one embodiment, switches 165 and 161 are implemented using PFETs, and switches 163 and 159 are implemented using NFETs, but in other embodiments, these switches may be implemented using other types of switches (pass gates or other types of transistors). In some embodiments, the high supply inputs of inverters 155 and 157 can both be coupled to VDD via a single switch, and the low supply inputs of inverters 155 and 157 can both be coupled to VSS via a single switch.

[0090] Comparator circuit 101 includes latch 105. Latch 105 includes inputs VL+ and VL- connected to the outputs of inverter 155 and inverter 157, respectively. Latch 105 includes switch 167, which is connected to input VL+ at one end and to input VL- at the other end. Switch 167 is controlled by the PHR signal from controller 106 and is turned on (closed) during the reset phase to equalize the voltages of inputs VL+ and VL- during the reset phase. Switch 167 is turned off (non-conductive) during the preamplification phase and the latching phase.

[0091] Latch 105 includes two sets of inverters, each coupled in a series signal path between a latch input and a latch output. One set includes inverters 183 and 185, wherein the signal input of the first series inverter 183 is connected to the latch input VL+, and the signal output of the last series inverter 185 is connected to the latch output VOUT+. The signal output of inverter 183 is connected to the signal input of inverter 185. Inverter 183 includes a PFET 189 having a source (high supply input of inverter 183) connected to the high supply voltage terminal VDD and a drain connected to the drain of NFET 187 and the signal output of inverter 183. Inverter 183 includes an NFET 187 having a gate connected to the gate of PFET 189 and connected to the latch input VL+ at the signal input of inverter 183. The source of NFET 187 (the low supply input of inverter 183) is connected to the latch input VL- so that the low supply input of inverter 183 is biased by the latch input VL-.

[0092] Inverter 185 includes a PFET 193 and an NFET 191. The gates of PFET 193 and NFET 191 are connected to the signal output of inverter 183 at the signal input of inverter 185. The high supply input of inverter 185 (the source of PFET 193) is connected to the high supply voltage terminal VDD, and the low supply input of inverter 185 (the source of NFET 191) is connected to the low supply voltage terminal VSS. The drains of PFET 193 and NFET 191 are connected to the latch output VOUT+ at the signal output of inverter 185.

[0093] The signal output of inverter 171 is connected to the signal input of inverter 173. Inverter 171 includes a PFET 177 whose source (high supply input of inverter 171) is connected to the high supply voltage terminal VDD and whose drain is connected to the drain of NFET 175 and the signal output of inverter 171. Inverter 171 includes an NFET 175 whose gate is connected to the gate of PFET 177 and is connected to the latch input VL- at the signal input of inverter 171. The source of NFET 175 (low supply input of inverter 171) is connected to the latch input VL+, so that the low supply input of inverter 171 is biased by the latch input VL+.

[0094] Inverter 173 includes a PFET 181 and an NFET 179. The gates of PFET 181 and NFET 179 are connected to the signal output of inverter 171 at the signal input of inverter 173. The high supply input of inverter 173 (the source of PFET 181) is connected to the high supply voltage terminal VDD, and the low supply input of inverter 173 (the source of NFET 179) is connected to the low supply voltage terminal VSS. The drains of PFET 181 and NFET 179 are connected to the latch output VOUT- at the signal output of inverter 173.

[0095] In one embodiment, the VDD high supply voltage terminal is biased at 0.8 V and the VSS low supply voltage terminal is biased at ground voltage. However, these supply voltage terminals may be biased at other supply voltages including a negative voltage of VSS.

[0096] In other embodiments, the comparison circuit may have other configurations, include other circuit systems, and / or operate in other modes. For example, some embodiments (e.g., embodiments with high input voltages) do not include latch 104. Although Figure 1 The inverter is shown as being implemented with a P-type transistor (eg, PFET) in series with an N-type transistor (eg, and NFET), but in other embodiments, Figure 1At least some of the inverters in the circuit 101 may be implemented using other inverter configurations. Additionally, in other embodiments, the preamplifier 103 may have other configurations. In other embodiments (e.g., bipolar), the circuit 101 may be implemented using other types of transistors.

[0097] Figure 2 is a timing diagram illustrating the voltages of comparison circuit 101 during operation according to one embodiment of the present invention. In the illustrated embodiment, comparison circuit 101 operates in three phases: a reset phase (PHR), a preamplification ("preamp") phase (PHPA), and a latch phase (PHL). These sequential phases are repeatedly executed to provide a differential indication of the comparison of the voltage at VIN+ to the voltage at VIN+ at VOUT+ and VOUT-. Controller 106 controls the timing of each phase.

[0098] During the reset phase, the PHR signal is asserted to close switch 119 to equalize the voltages of VI+ and VI- to the common-mode voltage of VI+ and VI- during the previous latch phase. The assertion of the PHR signal also closes switch 167 to equalize the voltages of VL+ and VL- to the common-mode voltage (VCM) of VL+ and VL- during the previous latch phase. Because VL+ and VL- are equalized during the reset phase, the gate-source voltage (VGS) of NFETs 187 and 175 is at 0V.

[0099] During the reset phase, the PHPA signal is not asserted, causing switches 151 and 153 to be open, isolating VI+ and VI- from latch 104. The PHPA signal being in a non-conductive state during the reset phase also causes switches 123 and 121 to be open, so that the inverter of preamplifier 103 is not biased by the high supply voltage terminal VDD and the low supply voltage terminal VSS at its supply voltage input. Consequently, the transistors of the inverter of preamplifier 103 are unable to pull the voltage of output VI+ or VI- away from the common-mode voltage.

[0100] During the reset phase, the PHL signal is not asserted, so that switches 159, 161, 163, and 165 are not conducting, and inverters 157 and 155 are not biased by the supply voltages VDD and VSS. Therefore, inverters 157 and 155 cannot pull the voltage of the latch inputs VL+ and VL- away from the common mode voltage.

[0101] During the reset phase, the voltage of the latch outputs VOUT+ and VOUT- is pulled to a low voltage state of VSS. In some embodiments, the threshold voltage of PFETs 189 and 177 is less than the voltage difference between VDD and the common-mode voltage of VL+ and VL-, causing PFETs 189 and 177 to be conductive during the reset phase. With PFETs 189 and 177 conductive, NFETs 191 and 179 conduct to pull the voltage of VOUT+ and VOUT-, respectively, to VSS. In one embodiment where VDD is 0.8V, VSS is ground, and the common-mode voltage is 0.4V, PFETs 189 and 177 have a threshold voltage of 0.3V, causing both PFETs 189 and 177 to be conductive during the reset phase. In some embodiments, NFETs 175 and 187 also have a threshold voltage of 0.3V, but in other embodiments, these threshold voltages can be other values.

[0102] During the preamplification phase (PHPA), switches 121 and 123 are closed to bias the low supply voltage node of preamplifier 103 at VSS and the high supply voltage node of preamplifier 103 at VDD. Switch 119 is open so that VI+ and VI- are no longer balanced. Switches 151 and 153 are closed, and switch 167 is open. As a result of these switch positions, the voltage difference at VIN+ and VIN- begins to create a voltage difference between VI+ and VI-, and between VL+ and VL-, pulling those voltages in opposite directions. Figure 2 In the embodiment of FIG. 5 , VIN+ is at a higher voltage than VIN−, which causes VL+ to increase and VL− to decrease during the pre-amplification phase.

[0103] During the preamplification stage, inverters 125 and 127 are used to pull VI- and VI+ to the threshold voltages of inverters 125 and 127, respectively, which are designed to approximate the common-mode voltage of VIN+ and VIN-. Self-biasing inverters 125 and 127 is used to reduce the common-mode sensitivity of preamplifier 103, but self-biasing inverters 125 and 127 also reduces the gain of preamplifier 103.

[0104] For a given amount of transistor current, cross-coupled inverters 137 and 139 serve to increase the rate of increase of the voltage difference between VI- and VI+ (and between VL+ and VL-) (i.e., to increase the gain of preamplifier 103). The transistors of inverters 137 and 139 are stronger than those of inverters 125 and 127 to overcome the effects of self-biasing inverters 125 and 127. In some embodiments, the size of the transistors of inverters 125, 127, 137, and 139 can be adjusted to tailor the gain and common-mode sensitivity of preamplifier 103. Additionally, because preamplifier 103 includes only one set of internal signal nodes (VI-, VI+), the speed of preamplifier 103 is greater than that of preamplifiers with multiple sets of nodes.

[0105] During the latch phase, switches 151 and 153 are opened to isolate VI+ and VI- from VL- and VL+, respectively. Additionally, switches 123 and 121 are opened, leaving the supply nodes of the inverters of preamplifier 103 unbiased.

[0106] During the latch phase, switches 159, 161, 163, and 165 are closed, causing the high supply inputs of inverters 155 and 157 to be biased at VDD, and the low supply inputs of inverters 155 and 157 to be biased at VSS. Because cross-coupled inverters 155 and 157 are powered during the latch phase, the voltage difference between VL+ and VL- increases at a higher rate. Figure 2 As shown in , during the latch phase, the voltage of VL+ rises at a faster rate, and the voltage of VL- falls at a faster rate.

[0107] Because the signal inputs of inverters 183 and 171 are connected to one latch input (VL+, VL-), and the low supply inputs of inverters 183 and 171 are connected to the other latch input (VL-, VL+), the latch output (VOUT+, VOUT-) will change state when the voltage difference between the latch inputs exceeds the threshold voltage of one of NFETs 187 and 175, depending on which latch input has the higher voltage.

[0108] Figure 2 The gate-source voltage of NFET 187 (VGS NFET 187) is shown, which is the voltage of VL+ minus the voltage of VL-. Figure 2 Also shown is the gate-source voltage of NFET 175 (VGS NFET 175), which is the voltage of VL- minus the voltage of VL+. Figure 2 As shown in FIG, the VGS voltage of NFETs 187 and 175 is at 0V during the reset phase because VL+ and VL- are equalized at the same voltage.

[0109] During the preamplification phase, as preamplifier 103 amplifies the difference between VI- and VI+, the gate-source voltages (VGS) of NFETs 187 and 175 begin to diverge in opposite directions. During the latch phase, the VGS voltages diverge at an even faster rate due to the power supplied by cross-coupled inverters 155 and 157. When NFET 187 or NFET 175 has a positive VGS exceeding its threshold, the NFET becomes conductive, causing the PFET (193 or 181) of the subsequent inverter (185 or 173) to turn on, pulling VOUT+ or VOUT- to a high voltage state. The NFET (189 or 177) with a negative VGS remains non-conductive, with its corresponding latch output (VOUT+, VOUT-) unchanged.

[0110] exist Figure 2 In the embodiment of FIG1 , as VL+ rises and VL- falls, NFET 187 becomes conductive when its gate-source voltage (VGS) rises above its threshold voltage (e.g., 0.3V in some embodiments). This occurs when VL+ minus VL- is greater than the threshold voltage of NFET 187. NFET 187 becomes conductive, pulling PFET 193 to its corresponding latch output, VOUT+, to a high voltage state of VDD, while VOUT- remains at its low voltage state of VSS.

[0111] exist Figure 2 After VOUT+ changes state to VDD, VL+ continues to rise and VL- continues to fall until VL+ reaches VDD and VL- reaches VSS. Because VGS NFET 187 represents the voltage of VL+ minus the voltage of VL-, VGS NFET 187 rises to VDD at twice the rate at which VL+ rises to VDD. Because VGS NFET 175 represents the voltage of VL- minus the voltage of VL+, VGS NFET 175 falls to -VDD at twice the rate at which VL- falls to VSS.

[0112] Because the sources of NFETs 187 and 175 are biased by another latch input that is not applied to its signal input, the gate-source voltages of NFETs 187 and 175 will change at twice the rate of the latch input voltage applied to its signal input due to the diverging directions of the voltages at the latch inputs (VL+, VL-). Consequently, the NFETs will turn on faster than if the source of each NFET were biased at VSS, thereby providing a faster latch and a faster comparison circuit.

[0113] At the beginning of the second reset phase, switches 159, 161, 163, and 165 are open, leaving inverters 157 and 155 unbiased. Switch 119 is closed to equalize the voltages on VI+ and VI- to the common mode voltage of VI+ and VI-. Switch 167 is closed to equalize the voltages on VL+ and VL- to the common mode voltage (VCM) of VL+ and VL-. Due to the equalization of the voltages on VL+ and VL-, the gate-source voltages of NFETs 187 and 175 return to 0 volts. Figure 2 As shown in , when the gate-source voltage of NFET 187 drops beyond its threshold voltage, VOUT+ returns to its low voltage state.

[0114] Thus, the comparison circuit 101 includes two outputs (VOUT+ and VOUT-) that are in the same low voltage state during the reset phase and in complementary voltage states during the latch phase, depending on whether VIN+ or VIN- is at a higher voltage relative to each other. With such an embodiment, only one latch output is required to change state to indicate the voltage comparison result during the latch phase. In other embodiments, the comparison circuit may have a different number of phases.

[0115] Figure 3 FIG. 3 is a circuit diagram of another latch 305 according to an embodiment of the present invention. The latch 305 is similar to Figure 1 Latch 105 is similar to latch 105, except that the high supply inputs (sources of PFETs 389 and 377) of the first series inverters (383 and 371) are connected to opposite latch inputs (VL- and VL+, respectively), and the low supply inputs (sources of NFETs 387 and 375) of the first series inverters (383 and 371) are connected to VSS.

[0116] The signal input of inverter 383 is connected to the latch input VL+, and the signal input of inverter 371 is connected to the latch input VL-. Latch 305 includes switch 367 for balancing the latch inputs VL+ and VL- during the reset phase. The signal output of inverter 383 is connected to the signal input of inverter 385, which includes PFET 393 and NFET 391. The signal output of inverter 371 is connected to the signal input of inverter 373, which includes PFETs 381 and 379.

[0117] NFETs 387 and 375 have threshold voltages less than the common-mode voltage of VL+ and VL-. Therefore, when VL+ and VL- are at common-mode voltage, NFETs 387 and 375 conduct, causing both VOUT+ and VOUT- to be in a high voltage state. As the voltages of VL+ and VL- diverge during the latch phase, when the gate-source voltage of PFET 389 or PFET 377 drops below its threshold voltage (or its source-gate threshold rises above its threshold voltage), PFET 389 or PFET 377 will become conductive. Under this condition, the latch output (VOUT+, VOUT-) corresponding to the conductive PFET is pulled to its low voltage state (VSS), with VOUT+ and VOUT- in complementary states to indicate which input has the higher voltage. In some embodiments, each set of inverters can have more than two inverters in the signal path, so that the reset voltage state of VOUT+ and VOUT- can be at VSS.

[0118] Comparison circuit 101 can be used to provide a comparison between two input voltages in various systems, such as memories, serial interfaces, data converters, computing hardware, and ADCs. In some embodiments, comparison circuit 101 can be used in a successive approximation register (SAR) analog-to-digital converter (ADC), where the relatively high speed and large differential gain of comparison circuit 101 can facilitate high clock speeds and high resolution. Therefore, such a comparison circuit can be advantageous for high-frequency applications (e.g., 5 GHz or higher), such as those used in conjunction with 5G / 6G implementations and other wireless systems or in conjunction with autonomous radar systems, as well as in serializer and deserializer-to-parallel converter (SerDes) applications.

[0119] In some embodiments with large input voltages, the gain of preamplifier 103 can be large enough that latch 104 is not required. In addition, for lower frequencies, the size of input inverters 107 and 109 can be relatively small, thereby providing small input capacitance and lower noise. In some embodiments, the comparison circuit can be optimized for a wide range of frequencies by adjusting the length of the preamplification stage without modifying the design.

[0120] In some embodiments, each group of one or more inverters may have only one inverter in the signal path, or may have more than two inverters in the signal path. One advantage of having a group of two or more inverters in the signal path is that the latch outputs (VOUT+ and VOUT-) can transition to well-defined complementary digital output states more quickly based on relatively small differential latch input voltages near common mode.

[0121] Features described herein with respect to one embodiment may be implemented in other embodiments described herein. The source or drain is the current terminal of a FET (field effect transistor). The gate is the control terminal of a FET. Two devices may be "coupled" to each other through other devices or by being connected to each other. For example, referring to Figure 1 , latch inputs VL+ and VL- are coupled through switch 167. Latch input VL+ is also coupled to the gate of PFET 189 by being connected to the gate of PFET 189.

[0122] While particular embodiments of the present invention have been shown and described, those skilled in the art will recognize that, based on the teachings herein, further changes and modifications may be made without departing from this invention and its broader aspects, and, therefore, it is intended that the appended claims cover within their scope all such changes and modifications that come within the true spirit and scope of this invention.

Claims

1. A circuit, characterized in that: include: A latch, the latch comprising: First input; Second input; First output; Second output; a first set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the first set is connected to the first input and a signal output of a last series inverter of the first set is connected to the first output, wherein the first series inverter of the first set includes a first supply input configured to be biased by the second input; a second set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the second set is connected to the second input and a signal output of a last series inverter of the second set is connected to the second output, wherein the first series inverter of the second set includes a first supply input configured to be biased by the first input; wherein during a reset phase, the first output and the second output are configured to be set to a same output value state, wherein during a latch phase, the first output and the second output are configured to be latched in complementary output value states dependent on the voltages of the first input and the second input.

2. The circuit according to claim 1, wherein: Also includes: A comparison circuit, the comparison circuit comprising the latch and a preamplifier circuit, the preamplifier circuit comprising: First input; Second input; a first output coupled to the first input of the latch; a second output coupled to the second input of the latch; wherein the first output of the latch and the second input of the latch The latch-out state exists at a complementary output value state indicating a comparison of the voltages of the first input of the preamplifier and the second input of the preamplifier.

3. The circuit according to claim 2, characterized in that The preamplifier comprises: a first self-biased inverter comprising a signal input connected to the first output of the preamplifier and a signal output; a second self-biased inverter comprising a signal input connected to the second output of the preamplifier and a signal output; wherein during the pre-amplification phase of the comparison circuit, the high-side power supply input of the first self-biased inverter is configured to be biased by a high power supply voltage terminal, and the low-side power supply input of the first self-biased inverter is configured to be biased by a low power supply voltage terminal; wherein during the pre-amplification stage, the high-side power supply input of the second self-biased inverter is configured to be biased by the high power supply voltage terminal, and the low-side power supply input of the second self-biased inverter is configured to be biased by the low power supply voltage terminal; During a reset phase of the comparison circuit, the high-side power supply inputs of the first self-biased inverter and the second self-biased inverter are not configured to be biased by the high power supply voltage terminal, and the low-side power supply inputs of the first self-biased inverter and the second self-biased inverter are not configured to be biased by the low power supply voltage terminal.

4. The circuit according to claim 2, wherein: The first output of the preamplifier is coupled to the first input of the latch via a first switch, and the second output of the preamplifier is coupled to the second input of the latch via a second switch; wherein during the reset phase, the first switch and the second switch are configured to be open, and during the pre-amplification phase, the first switch and the second switch are configured to be closed; During the reset phase, the first output of the preamplifier and the second output of the preamplifier are configured to be balanced, and during the preamplification phase, the first output of the preamplifier and the second output of the preamplifier are not balanced.

5. The circuit according to claim 2, characterized in that The comparison circuit further comprises a second latch comprising: a first latched inverter and a second latched inverter configured in a cross-coupled configuration; wherein a signal input of the first latch inverter is coupled to the second output of the preamplifier, to a signal output of the second latch inverter and to the second input of the latch; Wherein a signal input of the second latch inverter is coupled to the first output of the preamplifier, coupled to the signal output of the first latch inverter and coupled to the first input of the latch.

6. A method for comparing a voltage at a first input of a preamplifier with a voltage at a second input of the preamplifier, characterized in that The method comprises: During the reset phase: controlling the first switch to be in an on state to balance the first output of the preamplifier and the second output of the preamplifier; controlling a second switch to be in a non-conducting state, the second switch coupled at one end to the first output of the preamplifier and at a second end to a first signal input of a set of cross-coupled inverters; controlling a third switch to be in a non-conducting state, the third switch coupled at one end to the second output of the preamplifier and at a second end to a second signal input of a set of cross-coupled inverters; controlling a fourth switch to be in a conducting state, the fourth switch being coupled at one end to the first input of the latch and to the second input of the latch, wherein the latch additionally comprises: First output; Second output; a first set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the first set is connected to the first input of the latch and a signal output of a last series inverter of the first set is connected to the first output of the latch, wherein the first series inverter of the first set includes a first supply input coupled to the second input of the latch to be biased by the second input of the latch; a second set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the second set is connected to the second input of the latch and a signal output of a last series inverter of the second set is connected to the second output of the latch, wherein the first series inverter of the second set includes a first supply input coupled to the first input of the latch to be biased by the first input of the latch; wherein during the reset phase, the first output of the latch and the second output of the latch are each in a first voltage state; During the pre-amplification stage: controlling the first switch to be in a non-conducting state; controlling the second switch and the third switch to be in an on state; controlling the fourth switch to be in a non-conducting state; During the latch phase: The second switch and the third switch are controlled to be in the non-conducting state; the first output and the second output of the latch circuit are each in a complementary state to each other to indicate a comparison result of the voltage of the first input of the preamplifier and the voltage of the second input of the preamplifier.

7. The method according to claim 6, characterized in that: During the reset phase: controlling the bias of the high supply voltage node of the preamplifier to be in an unbiased condition; controlling the bias of the low supply voltage node of the preamplifier to be in an unbiased condition; During the pre-amplification stage: The high supply voltage node of the preamplifier is biased at a high supply voltage; and the low supply voltage node of the preamplifier is biased at a low supply voltage.

8. The method according to claim 6, wherein: During the reset phase and during the preamplification phase: controlling the bias of the high supply voltage nodes of the set of cross-coupled inverters to be in an unbiased condition; controlling the bias of the low supply voltage nodes of the set of cross-coupled inverters to be in an unbiased condition; During the latch phase: biasing the high supply voltage node of the set of cross-coupled inverters at a high supply voltage; The low supply voltage node of the set of cross-coupled inverters is biased at a low supply voltage.

9. A comparison circuit, characterized in that: include: A preamplifier comprising: First input; Second input; First output; Second output; a first switch coupled between the first output and the second output, wherein when the first switch is turned on, a voltage of the first output and a voltage of the second output are equalized; A set of cross-coupled inverters comprising: a first signal input coupled to the first output of the preamplifier via a second switch; a second signal input coupled to the second output of the preamplifier via a third switch; a first signal output and a second signal output; A latch comprising: a first input coupled to the first signal output of the set of cross-coupled inverters; a second input coupled to the second signal output of the set of cross-coupled inverters; a fourth switch coupled between the first input of the latch and the second input of the latch, wherein when the fourth switch is turned on, a voltage of the first input of the latch and a voltage of the second input of the latch are equalized; First latch output; Second latch output; a first set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the first set is connected to the first input of the latch and a signal output of a last series inverter of the first set is connected to the first latch output, wherein the first series inverter of the first set includes a first supply input coupled to the second input of the latch to be biased by the second input of the latch; a second set of one or more inverters coupled in a signal series path, wherein a signal input of a first series inverter of the second set is connected to the second input of the latch and a signal output of a last series inverter of the second set is connected to the second latch output, wherein the first series inverter of the second set includes a first supply input coupled to the first input of the latch to be biased by the first input of the latch; Wherein during a latching phase, the first latch output and the second latch output are latched in complementary output value states, the complementary output value states indicating a comparison of the voltages of the first input of the preamplifier and the second input of the preamplifier.

10. The comparison circuit according to claim 9, wherein: When the comparison circuit is in the reset phase: The first switch and the fourth switch are configured to be turned on; The second switch and the third switch are configured to be non-conductive; The high supply voltage node and the low supply voltage node of the set of cross-coupled inverters are configured to be unbiased; A high supply voltage node and a low supply voltage node of the preamplifier are configured to be unbiased.

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