Chip-on-wafer layout method, layout device and preparation method of silicon capacitor

Abstract

The disclosure provides a wafer-on-chip layout method, a layout device and a preparation method of a silicon capacitor. In the layout method, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin, and an exposure area is arranged in each of the four wafer regions of the coordinate system. For each exposure area, each chip is arranged in the order of center, four corners, edge line and remaining empty position on the exposure area according to the size from large to small, and each chip is arranged symmetrically with the center of the exposure area. The application optimizes the exposure area division and the chip arrangement rule, not only realizes the optimized utilization of the center region of the wafer, but also enhances the structural strength of the center and the four corners of the exposure area, significantly improves the structural strength of the wafer, and effectively reduces the risk of wafer warping in subsequent processes.

Description

Methods for chip placement on wafers, placement apparatus, and fabrication methods for silicon capacitors. Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for laying out chips on a wafer, a layout apparatus, and a method for fabricating silicon capacitors. Background Technology

[0002] In the field of semiconductor manufacturing technology, various circuit structures are typically fabricated on wafers. For ease of fabrication, wafers are divided into several exposure units (Shots), which are usually used as the basic unit in production and are arranged periodically on the wafer. Each exposure unit contains one or more dies. After all the silicon capacitors on the wafer are fabricated, the wafer is diced into several dies, each containing an independent circuit structure capable of performing a predetermined function.

[0003] However, in order to maximize efficiency, designers will arrange dense chips on a wafer, which will lead to reliability problems such as excessive warpage during the manufacturing process. Summary of the Invention

[0004] The purpose of this disclosure is to solve the technical problem in the field of semiconductor manufacturing technology where densely packed chips on a wafer cause warping during the manufacturing process.

[0005] To address the aforementioned problems, this application provides a chip-on-wafer layout method, comprising the following steps:

[0006] S1. Obtain layout planning information, the layout planning information including wafer specification data and chip specification data, the chip specification data including the dimensions of multiple chips;

[0007] S2. Based on the wafer specification data, establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin; set exposure areas in the four wafer regions of the coordinate system respectively;

[0008] S3. For each exposure area, arrange the chips according to the chip layout rules to complete the chip layout on the wafer;

[0009] The chip layout rules refer to:

[0010] The chips are arranged in descending order of size, and their positions on the exposure area are arranged in the following order: center, four corners, edge, and remaining empty space.

[0011] Furthermore, each chip is arranged symmetrically around the center of the exposure area.

[0012] In an optional implementation, the layout planning information further includes lithography machine exposure field parameters; S2 includes:

[0013] Based on the wafer specification data, a two-dimensional rectangular coordinate system of XY is established with the center of the wafer as the origin;

[0014] Exposure areas are set in the four wafer regions of the coordinate system according to the regional layout rules;

[0015] The regional layout rule refers to the fact that each exposure region is within the exposure field of view corresponding to the exposure field of view parameters of the lithography machine, and adjacent exposure regions are axially symmetrical.

[0016] As a further improvement of this application, the closest distance between each of the exposure areas and the X-axis and Y-axis is 1mm to 5mm.

[0017] As a further improvement to this application, the spacing between adjacent chips within the same exposure area is no more than 0.5 mm.

[0018] As a further improvement of this application, a blank area of ​​at least 1 mm is reserved at the edge region of the wafer.

[0019] As a further improvement of this application, at least one alignment mark is provided in each of the exposure areas for alignment in the photolithography process.

[0020] To achieve the above objectives, this application provides a wafer-on-a-chip layout apparatus, comprising:

[0021] A layout plan acquisition module is used to acquire layout plan information, which includes wafer specification data and chip specification data, and the chip specification data includes the dimensions of multiple chips.

[0022] The exposure area acquisition module is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data; and to set the exposure area in each of the four wafer regions of the coordinate system.

[0023] The chip layout module is used to arrange the chips according to the chip layout rules for each exposure area, thus completing the chip layout on the wafer.

[0024] The chip layout rules refer to:

[0025] The chips are arranged in descending order of size, and their positions on the exposure area are arranged in the following order: center, four corners, edge, and remaining empty space.

[0026] Furthermore, each chip is arranged symmetrically around the center of the exposure area.

[0027] As a further improvement to this application, the layout planning information also includes lithography machine exposure field parameters; the exposure field parameter acquisition module includes:

[0028] The coordinate system establishment unit is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data;

[0029] The exposure area setting unit is used to set the exposure area in each of the four wafer regions of the coordinate system according to the area layout rules;

[0030] The regional layout rules include: each exposure region is within the exposure field of view corresponding to the exposure field of view parameters of the lithography machine, and adjacent exposure regions are axially symmetrical.

[0031] As a further improvement of this application, the closest distance between each of the exposure areas and the X-axis and Y-axis is 1mm to 5mm.

[0032] As a further improvement to this application, the spacing between adjacent chips within the same exposure area is no more than 0.5 mm.

[0033] As a further improvement of this application, a blank area of ​​at least 1 mm is reserved at the edge region of the wafer.

[0034] As a further improvement of this application, at least one alignment mark is provided in each of the exposure areas for alignment in the photolithography process.

[0035] To achieve the above objectives, this application also provides a method for fabricating a silicon capacitor, comprising the following steps:

[0036] A1. Obtain the chip layout design according to the chip-on-wafer layout method described above;

[0037] A2. The wafer to be processed is sequentially cleaned, an oxide layer is grown, a photoresist is coated, and exposure and development are performed according to the layout design.

[0038] A3. Temporarily bond the back sides of the two wafers after the treatment in step A2 together;

[0039] A4. According to the layout design, deep trenches are etched on the upper surfaces of the two wafers to isolate the chips;

[0040] A5. Polysilicon is deposited on the upper surfaces of two wafers respectively, and multiple electrode structures are formed by photolithography and etching. An insulating medium is deposited between the multiple electrode structures, and then annealed.

[0041] A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers respectively, and then alloyed.

[0042] A7. Debond the two wafers after step A6;

[0043] A8. Finally, the circuitry is laid out on the wafer surface, passivation is completed, and electrical signals are extracted.

[0044] The beneficial effects of this application are as follows: This application provides a chip layout method on a wafer. In this method, a two-dimensional Cartesian coordinate system (XY) is established with the center of the wafer as the origin. Exposure areas are set in four wafer regions within this coordinate system. For each exposure area, the chips are arranged in descending order of size, and their positions on the exposure area are arranged in the order of center, four corners, edge, and remaining empty space. Furthermore, the chips are arranged symmetrically around the center of the exposure area. By optimizing the exposure area division and chip layout rules, this application not only optimizes the utilization of the wafer's central region but also enhances the structural strength of the center and four corners of the exposure area, significantly improving the wafer's structural strength and effectively reducing the risk of wafer warpage in subsequent processes. Attached Figure Description

[0045] Figure 1 is a flowchart of a wafer-on-chip layout method according to an embodiment of this application;

[0046] Figure 2 is a flowchart of a method for fabricating a silicon capacitor according to an embodiment of this application;

[0047] Figure 3 is a schematic diagram of the layout of the exposure area on the wafer according to an embodiment of this application;

[0048] Figure 4 is a schematic diagram of the chip layout in each exposure area of ​​an embodiment of this application;

[0049] Figure 5 is a schematic diagram of the structure after step A3 in the fabrication process of the silicon capacitor according to an embodiment of this application;

[0050] Figure 6 is a schematic diagram of the structure after step A4 in the fabrication process of the silicon capacitor according to an embodiment of this application;

[0051] Figure 7 is a schematic diagram of the structure after step A5 in the fabrication process of the silicon capacitor according to an embodiment of this application;

[0052] Figure 8 is a schematic diagram of the structure after step A6 in the fabrication process of the silicon capacitor according to an embodiment of this application;

[0053] Figure 9 is a schematic diagram of the structure after step A7 in the fabrication process of the silicon capacitor according to an embodiment of this application;

[0054] Figure 10 is a schematic diagram of the structure after passivation is completed in step A8 during the fabrication process of the silicon capacitor according to an embodiment of this application.

[0055] Figure 11 is a schematic diagram of the structure after the electrical signal is drawn out in step A8 of the silicon capacitor manufacturing process according to an embodiment of this application. Detailed Implementation

[0056] As is known from the background art, in the field of semiconductor manufacturing technology, densely arranged chips on a wafer can easily lead to warping problems during the manufacturing process. According to some embodiments of this disclosure, one embodiment of this disclosure provides a chip layout method on a wafer, which can at least solve the warping problem in subsequent processes.

[0057] The technical solutions of this disclosure will be clearly and completely described below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0058] To make the above-mentioned objectives, features and advantages of this disclosure more apparent and understandable, the disclosure will be further described in detail below with reference to specific embodiments.

[0059] In the description of this disclosure, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0060] In the description of this disclosure, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0061] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0062] Figure 1 is a flowchart of a wafer-on-chip layout method according to an embodiment of the present application; Figure 2 is a flowchart of a silicon capacitor fabrication method according to an embodiment of the present application; Figure 3 is a schematic diagram of the layout of the exposure areas on the wafer according to an embodiment of the present application; Figure 4 is a schematic diagram of the chip layout in each exposure area according to an embodiment of the present application.

[0063] Based on Figures 1-4, this disclosure provides a method for placing chips on a wafer, including the following steps:

[0064] S1. Obtain layout planning information, the layout planning information including wafer specification data and chip specification data, the chip specification data including the dimensions of multiple chips;

[0065] Specifically, wafer specifications include wafer size, wafer shape, wafer material, wafer surface characteristics, and wafer process-related data. Among these:

[0066] Wafer dimensions include diameter and thickness. Common wafer diameters include 200mm and 300mm, while wafer thickness typically ranges from several hundred micrometers to several millimeters, such as 750μm and 800μm. Wafers are generally circular in shape. Common wafer materials include monocrystalline silicon and polycrystalline silicon. Wafer surface characteristics include surface roughness, surface defect density, and oxide layer thickness. Wafer process-related data include lithography resolution, etching depth, and thin film thickness.

[0067] Specifically, chip specifications include chip size, chip function, and chip layout. Among these:

[0068] Chip dimensions include chip area, chip shape, and chip size range. Chip area is typically expressed in square millimeters (mm²). 2 This indicates, for example, that a typical chip area can be 1 mm². 2 5mm 2 10mm 2 The chip shape is usually square or rectangular, but it can also be other shapes (such as round or irregular shapes). The chip size range refers to the length and width of the chip. For example, the chip size range can be 2mm×2mm, 5mm×3mm, etc.

[0069] Chip functions include function types, function modules, and performance indicators. Function types include CPU, GPU, memory, sensors, RF chips, and capacitors. Function modules include logic circuits, analog circuits, and storage units. Performance indicators include clock frequency, power consumption, storage capacity, and processing speed.

[0070] Chip layout includes chip arrangement, chip spacing, and chip orientation. Chip arrangement includes array arrangement, centrosymmetric arrangement, etc. Chip spacing refers to the distance between adjacent chips, usually expressed in millimeters (mm). For example, chip spacing can be 0.5mm, 1mm, etc. Chip orientation refers to the direction of chip pins or the direction of main functional surfaces, usually aligned with the coordinate system of the wafer.

[0071] S2. Based on the wafer specification data, establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin; set exposure areas in the four wafer regions of the coordinate system respectively; in this step, the wafer specification data mainly includes wafer size and wafer shape, preferably, the wafer shape is circular.

[0072] S3. For each exposure area, arrange the chips according to the chip layout rules to complete the chip layout on the wafer; wherein, the chip layout rules refer to:

[0073] The chips are arranged in descending order of size, and their positions on the exposure area are arranged in the order of center, four corners, edge, and remaining empty space. The chips are arranged symmetrically with respect to the center of the exposure area. In this step, the chips are arranged in descending order of chip area size. The shape of the chips is mainly square or rectangular, and the area of ​​the chips is calculated by multiplying the length and width of the chips.

[0074] Based on the above technical solution, this application provides a method for chip layout on a wafer, which significantly improves the overall structural strength and manufacturing efficiency of the wafer by optimizing the exposure area and chip arrangement rules. Specifically,

[0075] First, layout planning information is obtained, which includes wafer specification data and chip specification data. The chip specification data details the dimensions of multiple chips. This information provides a foundation for subsequent layout design, ensuring that the layout scheme accurately matches the actual characteristics of the wafer and chips.

[0076] Secondly, based on the wafer specifications, a two-dimensional Cartesian coordinate system (XY) is established with the wafer's center as the origin, and exposure areas are set within the four wafer regions of this coordinate system. This design cleverly divides the entire wafer into four independent exposure areas, providing a clear framework for subsequent chip placement. By dividing the exposure area into four regions and offsetting them, a central wafer region is effectively reserved. This innovative approach significantly improves the wafer's structural strength and substantially reduces the possibility of wafer warpage. The reserved space in the wafer's central region not only facilitates subsequent process operations but also enhances the overall stability of the wafer, reducing structural deformation caused by stress concentration.

[0077] Furthermore, for each exposure area, chips are arranged according to chip layout rules to complete the overall chip layout on the wafer. These chip layout rules explicitly state that chips are arranged in descending order of size, positioned in the exposure area in the order of center, four corners, edge, and remaining empty space, with each chip arranged symmetrically around the center of the exposure area. This arrangement not only fully utilizes the space of the exposure area but also balances the warpage of individual exposure areas by rationally distributing chips of different sizes. Specifically, prioritizing the placement of larger chips in the center of the exposure area effectively increases the structural strength of the central region; while placing smaller chips at the four corners and edge positions further optimizes the weight distribution of the entire exposure area, thereby reducing the risk of warpage across the entire wafer. In addition, the symmetrical arrangement not only ensures the aesthetics and consistency of the chip layout but also further enhances the overall structural stability of the wafer, ensuring that the wafer maintains good flatness and mechanical properties during subsequent manufacturing and use.

[0078] In summary, this application achieves optimized utilization of the wafer's central region through innovative exposure area division and chip layout rules, significantly improving the wafer's structural strength and effectively reducing the risk of wafer warpage. Simultaneously, this layout method balances the warpage of individual exposure areas, enhancing the structural strength of the center and corners of the exposure area, further reducing the overall wafer warpage. These technical effects not only improve the overall quality and reliability of the wafer but also provide strong support for high-precision processing in semiconductor manufacturing, demonstrating significant industrial application value and broad market prospects.

[0079] In an optional implementation, the layout planning information further includes lithography machine exposure field parameters; S2 includes:

[0080] Based on the wafer specification data, a two-dimensional rectangular coordinate system of XY is established with the center of the wafer as the origin;

[0081] Exposure areas are set in the four wafer regions of the coordinate system according to the regional layout rules;

[0082] The regional layout rule refers to the fact that each exposure region is within the exposure field of view corresponding to the exposure field of view parameters of the lithography machine, and adjacent exposure regions are axially symmetrical.

[0083] The aforementioned scheme further optimizes the chip layout method on the wafer. By introducing the exposure field of view parameters of the lithography machine, it ensures that each exposure area is located within the exposure field of view of the lithography machine, while adjacent exposure areas are axially symmetrical. This improvement not only enhances the precision and consistency of the lithography process but also further optimizes the space utilization of the wafer. The axially symmetrical design makes the wafer more uniformly stressed during processing, effectively reducing the risk of stress concentration and warpage caused by asymmetrical layout, thereby significantly improving the overall structural stability and manufacturing quality of the wafer.

[0084] In an optional implementation, in step S2, a two-dimensional Cartesian coordinate system is established with the center of the wafer as the origin, dividing the wafer into four quadrants, each corresponding to an exposure area. The shape of each exposure area is typically a fan or rectangle, and its size and shape are determined based on the wafer size and the exposure field of view parameters of the lithography machine.

[0085] Determine the boundary coordinates of each exposure region. For example, for a 300mm diameter wafer, if each exposure region is rectangular, its boundary coordinates in the XY coordinate system can be represented as: upper left exposure region (-d,d) to (-m,n), upper right exposure region (d,d) to (m,n), lower right exposure region (m,-n) to (d,-d), lower left exposure region (-d,-d) to (-m,-n), where d is less than the wafer radius (150mm), and d is greater than m and greater than n, m>0, n>0.

[0086] In an optional implementation, step S3 further includes chip classification and sorting: First, all chips to be arranged are classified and sorted according to their size. The chip area (length × width) is used as the primary classification criterion, and the chips are arranged in descending order of area. For example, if there are three types of chips with sizes of 30mm × 30mm, 30mm × 7.5mm, and 10mm × 10mm, their areas are first calculated to be 1600mm². 2 400mm 2 400mm 2 Then, after sorting by area size, the sorting order is 30mm×30mm, 30mm×7.5mm, and 10mm×10mm.

[0087] When chip areas are the same, the shape of the chip should be further considered. For example, for chips with the same area but different aspect ratios, chips with aspect ratios closer to a square should be prioritized, as this shape makes better use of space during arrangement.

[0088] In an optional implementation, step S3 also provides a chip location determination algorithm, as follows:

[0089] 1) Determining the center location

[0090] For each exposure area, the largest chip is first placed at its geometric center. The center coordinates of the exposure area are calculated. Taking the upper left exposure area as an example, if d = 100, m = 1, and n = 1, its center coordinates are ((-100mm + (-1mm)) / 2, (100mm + 1mm) / 2) = (-50.5mm, 50.5mm). The center of the largest chip (e.g., 30mm × 30mm) is then aligned with the center of the exposure area to determine the coordinates of the four corner points of that chip. The center of the chip is at (-50.5mm, 50.5mm), and its half-length and half-width are both 15mm. Therefore, the coordinates of its four corner points are (-50.5mm+15mm, 50.5mm+15mm), (-50.5mm-15mm, 50.5mm+15mm), (-50.5mm-15mm, 50.5mm-15mm), and (-50.5mm+15mm, 50.5mm-15mm).

[0091] Check if the coordinates of the four corner points of the chip are within the exposure area, specifically if they meet the boundary coordinates of the upper left exposure area (-100mm, 100mm) to (-1mm, 1mm), meaning the x-coordinate is between (-100mm, -1mm) and the y-coordinate is between (1mm, 100mm). If they are, determine this position as the chip's placement. If not, adjust the chip's position according to the boundary coordinates of the exposure area, ensuring all four corner points are within the exposure area. This could involve appropriately reducing the offset between the chip and the center coordinates until the condition is met.

[0092] 2) Determine the positions of the four corners of the edge

[0093] Determine the positions of the four corners of the exposure area. For the upper left exposure area, the coordinates of its four corners are (-d, d), (-m, d), (-m, n), and (-d, n). For example, according to the previous parameters, the coordinates of the four corners of the upper left exposure area are (-100mm, 100mm), (-1mm, 100mm), (-1mm, 1mm), and (-100mm, 1mm).

[0094] Arrange the second-largest chips sequentially at the four corners of the edge. Taking a 30mm x 30mm chip arranged at position (-d, d) in the upper left exposure area as an example, choose any side to place along either the negative x-axis or the positive y-axis (the specific direction can be determined based on layout optimization requirements). Assuming one side of the chip is placed along the negative x-axis, (-d+15mm, d-15mm) = (-100mm+15mm, 100mm-15mm) = (-85mm, 85mm). The coordinates of the four corner points of the chip are (-85mm+15mm, 85mm+15mm), (-85mm-15mm, 85mm+15mm), (-85mm-15mm, 85mm-15mm), and (-85mm+15mm, 85mm-15mm). Check if these four corner point coordinates are within the exposure area, i.e., the x-coordinate is between (-100mm, -1mm) and the y-coordinate is between (1mm, 100mm). If it is present, then that position is determined as the chip's placement position; if it is not present, then the chip's position is adjusted according to the boundary coordinates of the exposure area so that all four corners are within the exposure area.

[0095] 3) Determining the position of the sideline

[0096] Determine the edge position of the exposure area. Taking the upper left exposure area as an example, there are two edge lines along the x-axis. Taking the lower edge line as an example, first determine the blank area where the chip can be arranged. Since the chip has already been arranged in the center and four corners of the exposure area, based on the center position and the four corner positions determined above, calculate the coordinates of the four points of this blank area as (-31mm, 1mm), (-70mm, 1mm), (-31mm, 35.5mm), and (-70mm, 35.5mm). Arrange a 30mm × 7.5mm chip along the edge of the lower edge line of the upper left exposure area, which is parallel to the x-axis. Set the long side of the chip to be parallel to the x-axis and the chip spacing to be greater than 0.5mm. Taking a chip spacing of 1mm as an example, calculate the coordinates of the four corner points of the chip as (-32mm, 1mm), (-62mm, 1mm), (-32mm, 8.5mm), and (-62mm, 8.5mm). Check if the coordinates of these four corner points are within the exposure area, i.e., the x-coordinate is between (-100mm, -1mm) and the y-coordinate is between (1mm, 100mm). Also check if these four corner point coordinates overlap with the coordinates of the chip located at the center and the four corners. The check shows that the four corner point coordinates of the chip are within the exposure area and do not overlap with the coordinates of the chip located at the center and the four corners. Therefore, this position is determined to be the chip's placement position. If the corner point coordinates of the chip exceed the boundary of the exposure area, or overlap with the coordinates of the chip located at the center and the four corners, the position or orientation of the chip needs to be adjusted so that its corner point coordinates meet the boundary conditions.

[0097] 4) Fill remaining empty spaces

[0098] After arranging the chips at the center, four corners, and edges, the remaining spaces in the exposure area are filled. Appropriate chips are selected based on the size and shape of the remaining space. For irregularly shaped remaining spaces, a greedy algorithm can be used to prioritize chips that can fill the space to the greatest extent possible.

[0099] Calculate the boundary coordinates of the remaining space to determine the chip's position within it. For example, if the remaining space is an irregularly shaped area, its boundary coordinates can be approximated by a series of points. Determine that the chip's center coordinates are within this remaining space, calculate the coordinates of its four corner points, and check if they are within the remaining space (i.e., within the boundary coordinates of the exposure area and outside the area where chips have already been arranged). If they are, then this position is determined as the chip's placement position; otherwise, adjust the chip's position or select chips of a different size for arrangement.

[0100] In an optional implementation, the closest distance between each exposure area and the X and Y axes is 1mm to 5mm. By dividing the exposure area into four regions and offsetting them, with each region's closest distance to the X and Y axes set to 1mm to 5mm, this design not only effectively reserves space in the wafer's central area, further enhancing the wafer's structural strength, but also optimizes the overall wafer layout through reasonable space allocation. This layout significantly reduces the possibility of wafer warpage while improving the precision and consistency of the lithography process, ensuring high quality and high reliability in chip manufacturing.

[0101] In an optional implementation, the spacing between adjacent chips within the same exposure area is no more than 0.5 mm. This compact chip spacing maximizes wafer utilization while ensuring that chips do not interfere with each other, thus improving overall integration.

[0102] In an optional implementation, a blank area of ​​at least 1 mm is reserved at the edge of the wafer. This reserved edge area facilitates wafer dicing and subsequent packaging, reduces the risk of edge chip damage, and improves yield.

[0103] In an optional implementation, at least one alignment mark is provided in each of the exposure areas for alignment during the photolithography process. The alignment marks ensure high-precision alignment during photolithography, improving chip manufacturing yield and consistency.

[0104] Another embodiment of this disclosure also provides a wafer-on-chip layout apparatus, including:

[0105] A layout plan acquisition module is used to acquire layout plan information, which includes wafer specification data and chip specification data, and the chip specification data includes the dimensions of multiple chips.

[0106] The exposure area acquisition module is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data; and to set the exposure area in each of the four wafer regions of the coordinate system.

[0107] The chip layout module is used to arrange the chips according to the chip layout rules for each exposure area, thus completing the chip layout on the wafer.

[0108] The chip layout rules refer to:

[0109] The chips are arranged in descending order of size, and their positions on the exposure area are arranged in the following order: center, four corners, edge, and remaining empty space.

[0110] Furthermore, each chip is arranged symmetrically around the center of the exposure area.

[0111] The wafer-on-chip placement apparatus provided in this embodiment achieves the same beneficial effects as some embodiments of the wafer-on-chip placement method described above, and some details will not be repeated here.

[0112] In an optional implementation, the layout planning information further includes lithography machine exposure field-of-view parameters; the exposure field-of-view parameter acquisition module includes:

[0113] The coordinate system establishment unit is used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data;

[0114] The exposure area setting unit is used to set the exposure area in each of the four wafer regions of the coordinate system according to the area layout rules;

[0115] The regional layout rules include: each exposure region is within the exposure field of view corresponding to the exposure field of view parameters of the lithography machine, and adjacent exposure regions are axially symmetrical.

[0116] In an optional implementation, the layout plan acquisition module is used to obtain layout plan information from multiple sources to ensure that the chip arrangement accurately meets the operational requirements of the lithography machine. The specific acquisition methods of the layout plan acquisition module are as follows:

[0117] Manual Input: This module features a user interface, allowing operators to manually input relevant information, including wafer and chip specifications, into the system. For example, by inputting wafer specifications such as diameter, thickness, and material, as well as chip specifications such as size and function, basic information is provided for subsequent chip layout. Manual input is suitable for small-scale production or customized needs. When production scale is small, or when there are special requirements for wafer and chip layout that necessitate flexible adjustments based on specific circumstances, manual input allows for convenient input of personalized layout plans.

[0118] Automatic File Reading: The module can automatically read layout plan files in preset formats, which contain key information such as wafer and chip specifications. For example, it can read specific format files generated by lithography machines or design software, extract wafer and chip dimensions, and convert them into the format required for chip layout. Automatic file reading is suitable for integration with existing design software or lithography systems. In highly automated production environments, this method enables seamless integration with design software or lithography machines, improving the efficiency and accuracy of layout plan information acquisition and reducing errors that may result from manual input.

[0119] Retrieving from databases or servers: The layout plan acquisition module can communicate with external databases or servers to retrieve stored layout plan information. For example, it can retrieve existing wafer and chip specification data from an enterprise's production database, or download the latest design files from a cloud server to obtain information such as chip dimensions and functions. Retrieving from databases or servers is suitable for large-scale production and enterprise-level applications. For large semiconductor manufacturing companies, production data is often stored in databases or servers. By retrieving layout plan information from these databases or servers, centralized management and sharing of production data can be achieved, facilitating unified monitoring and optimization of the production process.

[0120] The implementation principle of the layout plan acquisition module is as follows: When acquiring layout plan information, the layout plan acquisition module needs to transmit data from different sources and convert it into a unified format for use by the chip layout module. For example, data read from files or databases is parsed to extract key fields of wafer specification data and chip specification data, and then converted into a format that the chip layout module can recognize. To achieve data transmission and interaction, the layout plan acquisition module needs to communicate with external devices or systems, which involves the design of interfaces and protocols. For example, the communication interface with the lithography machine follows specific industry protocols to ensure the stability and reliability of data transmission; the interface with the database needs to support standard database query languages ​​(such as SQL) to retrieve the required data from the database.

[0121] The core structure of a silicon capacitor typically consists of two parallel silicon wafers as electrodes, sandwiched with an insulating dielectric layer. This structure is similar to that of a traditional capacitor, but semiconductor technology enables miniaturization and high performance. Due to the high compatibility of silicon capacitors with semiconductor manufacturing processes, they can be integrated with integrated circuit chips, significantly reducing circuit size and power consumption, and improving system reliability. In modern electronic devices, silicon capacitors are widely used in power management circuits, signal processing circuits, and radio frequency circuits, providing crucial support for the efficient operation of semiconductor devices. In the field of semiconductor manufacturing technology, silicon capacitors are also fabricated on wafers. During the wafer fabrication process, for ease of fabrication, the wafer is divided into several exposure units (Shots), which are typically used as the basic unit in production and are arranged periodically on the wafer. Each exposure unit contains one or more dies. After all the silicon capacitors on the wafer are fabricated, the wafer is diced into several dies, each containing an independent silicon capacitor capable of performing a predetermined function.

[0122] However, in order to maximize efficiency, designers may also arrange dense chips on a wafer during the fabrication of silicon capacitors, which can lead to reliability issues such as excessive warpage during the manufacturing process.

[0123] Figure 5 is a schematic diagram of the structure after step A3 in the silicon capacitor fabrication process of this application embodiment; Figure 6 is a schematic diagram of the structure after step A4 in the silicon capacitor fabrication process of this application embodiment; Figure 7 is a schematic diagram of the structure after step A5 in the silicon capacitor fabrication process of this application embodiment; Figure 8 is a schematic diagram of the structure after step A6 in the silicon capacitor fabrication process of this application embodiment; Figure 9 is a schematic diagram of the structure after step A7 in the silicon capacitor fabrication process of this application embodiment; Figure 10 is a schematic diagram of the structure after passivation is completed in step A8 in the silicon capacitor fabrication process of this application embodiment; Figure 11 is a schematic diagram of the structure after the electrical signal is led out in step A8 in the silicon capacitor fabrication process of this application embodiment.

[0124] According to Figures 5-11, another embodiment of this disclosure provides a method for fabricating a silicon capacitor, including the following steps:

[0125] A1. Obtain the chip layout design according to the chip-on-wafer layout method disclosed in the above embodiments;

[0126] A2. The wafer to be processed is sequentially cleaned, an oxide layer is grown, a photoresist is coated, and exposure and development are performed according to the layout design.

[0127] A3. Temporarily bond the back sides of the two wafers after the treatment in step A2 together;

[0128] A4. According to the layout design, deep trenches are etched on the upper surfaces of the two wafers to isolate the chips;

[0129] A5. Polysilicon is deposited on the upper surfaces of two wafers respectively, and multiple electrode structures are formed by photolithography and etching. An insulating medium is deposited between the multiple electrode structures, and then annealed.

[0130] A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers respectively, and then alloyed.

[0131] A7. Debond the two wafers after step A6;

[0132] A8. Finally, the circuitry is laid out on the wafer surface, passivation is completed, and electrical signals are extracted.

[0133] Based on the disclosed embodiments above, this embodiment mainly applies the wafer-on-chip layout method described above to the fabrication of silicon capacitors. Some embodiments and the technical effects achieved are the same as those in the aforementioned embodiments, and will not be repeated here.

[0134] In a more specific embodiment, taking a wafer diameter of 300mm as an example, the following steps are taken: First, layout planning information is obtained. This information includes wafer specification data and chip specification data. The chip specification data includes the dimensions of multiple chips. In this embodiment, the dimensions of the selected chips are divided into three types according to length × width: 30mm × 30mm, 30mm × 7.5mm, and 10mm × 10mm. Second, based on the wafer specification data, an XY two-dimensional rectangular coordinate system is established with the center of the wafer as the origin. Exposure areas are set in the four wafer regions of the coordinate system, as shown in Figure 3. Finally, for each... In the exposure area, chips are arranged according to chip layout rules to complete the chip layout on the wafer. The chip layout rules refer to the following: each chip is arranged in descending order of size, and its position on the exposure area is arranged in the order of center, four corners of the edge, edge line, and remaining empty space. Moreover, each chip is arranged symmetrically with respect to the center of the exposure area, as shown in Figure 4. In Figure 4, 30mm×30mm chips are arranged in the center and four corners of the exposure area, 30mm×7.5mm chips are arranged at the edge line, and 10mm×10mm chips are arranged in the remaining empty space. At the same time, the spacing between adjacent chips does not exceed 0.5mm.

[0135] The detailed descriptions listed above are merely specific descriptions of feasible implementations of this disclosure and are not intended to limit the scope of protection of this disclosure. All equivalent implementations or modifications made without departing from the spirit of the art of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for manufacturing a silicon capacitor, characterized in that, The process includes the following steps: A1. Obtain the chip layout design based on the chip layout method on the wafer; A2. Clean the wafer to be processed, grow an oxide layer, coat photoresist, expose and develop according to the layout design in sequence; A3. Temporarily bond the back sides of the two wafers after the processing in step A2 together; A4. Etch deep trenches on the upper surfaces of the two wafers according to the layout design to facilitate chip isolation; A5. Polysilicon is deposited on the upper surfaces of two wafers respectively, and multiple electrode structures are formed by photolithography and etching. An insulating medium is deposited between the multiple electrode structures, and then annealed. A6. Based on step A5, a passivation layer and a seed layer are deposited on the upper surfaces of the two wafers respectively, and then alloyed. A7. Debond the two wafers after step A6; A8. Finally, arrange the circuitry on the wafer surface, complete passivation, and extract electrical signals; The chip layout method on the wafer includes the following steps: S1. Obtain layout plan information, which includes wafer specification data and chip specification data, the chip specification data including the dimensions of multiple chips; S2. Based on the wafer specification data, establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin; set exposure areas in the four wafer regions of the coordinate system respectively; S3. For each exposure area, arrange the chips according to the chip layout rules to complete the chip layout on the wafer; wherein, the chip layout rules refer to: each chip is arranged in descending order of size, and its position on the exposure area is arranged in the order of center, four corners of the edge, edge line, and remaining empty space; and each chip is arranged symmetrically with respect to the center of the exposure area.

2. The method for preparing a silicon capacitor according to claim 1, characterized in that, The layout plan information also includes the lithography machine exposure field parameters; S2 includes: establishing an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data; setting exposure areas in the four wafer areas of the coordinate system according to the area layout rules; the area layout rules refer to: each exposure area is within the exposure field of view corresponding to the lithography machine exposure field parameters, and adjacent exposure areas are axially symmetrical.

3. The method for preparing a silicon capacitor according to claim 1, characterized in that, The closest distance between each of the exposure areas and the X and Y axes is 1 mm to 5 mm.

4. The method for preparing a silicon capacitor according to claim 1, characterized in that, Within the same exposure area, the spacing between adjacent chips shall not exceed 0.5 mm.

5. The method for preparing a silicon capacitor according to claim 1, characterized in that, The edge area of ​​the wafer is reserved with a blank area of ​​at least 1 mm.

6. The method for preparing a silicon capacitor according to claim 1, characterized in that, At least one alignment mark is provided in each of the exposure areas for alignment during the photolithography process.

7. A wafer-on-a-chip layout apparatus, characterized in that, A wafer-on-chip layout method for the fabrication method of a silicon capacitor according to any one of claims 1-6, the apparatus comprising: a layout plan acquisition module for acquiring layout plan information, the layout plan information including wafer specification data and chip specification data, the chip specification data including the dimensions of multiple chips; an exposure area acquisition module for establishing an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data; and setting exposure areas in four wafer areas of the coordinate system; and a chip layout module for arranging chips according to chip layout rules for each exposure area to complete the chip layout on the wafer; wherein the chip layout rules refer to: each chip being arranged in descending order of size, and its position on the exposure area being arranged in the order of center, four corners of the edge, edge line, and remaining empty space; and each chip being arranged symmetrically with respect to the center of the exposure area.

8. The layout device according to claim 7, characterized in that, The layout plan information also includes lithography machine exposure field of view parameters; the exposure field of view parameter acquisition module includes: a coordinate system establishment unit, used to establish an XY two-dimensional rectangular coordinate system with the center of the wafer as the origin based on the wafer specification data; an exposure area setting unit, used to set exposure areas in the four wafer areas of the coordinate system according to the area layout rules; the area layout rules include: each exposure area is within the exposure field of view corresponding to the lithography machine exposure field of view parameters, and adjacent exposure areas are axially symmetrical.

9. The layout device according to claim 7, characterized in that, The closest distance between each of the exposure areas and the X and Y axes is 1 mm to 5 mm.

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