A heat dissipation chip packaging structure, a heat dissipation packaging device and an electronic equipment

Abstract

The application relates to the technical field of chip packaging, in particular to a heat dissipation chip packaging structure, a heat dissipation packaging device and electronic equipment. The heat dissipation chip packaging structure comprises a heat dissipation part, a chip, a packaging substrate and a heat conductive material layer. The heat dissipation part is an integrated structure. The lower surface of the heat dissipation part is provided with a containing groove for fixing the chip. The first surface of the containing groove is connected with the heat conductive material layer. The second surface of the containing groove is abutted with the packaging substrate and forms a containing space. The chip is welded and fixed on the packaging substrate. In the application, the integrated heat dissipation part is used as the chip packaging structure and the heat dissipation structure. The thermal resistance of heat propagation between the packaging structure and the heat dissipation structure is reduced. Therefore, the heat can be quickly dissipated to the outside, and the heat dissipation function and working efficiency of the chip packaging structure are improved.

Description

Technical Field

[0001] This invention relates to the field of chip packaging technology, and in particular to a heat dissipation chip packaging structure, heat dissipation packaging device, and electronic device. Background Technology

[0002] As chip development progresses, the heat generated by its computing power continues to increase, leading to continuous advancements in chip packaging technology. Chip packaging technology isolates semiconductor chips from the external environment, providing electrical connections, mechanical protection, and heat dissipation functions, playing a crucial role in improving chip performance and reliability.

[0003] In existing packaging processes, chips are fixed to a substrate using methods such as soldering and wire bonding. Then, a molding compound is used to cover both the chip and the substrate to protect the chip from external environmental influences. A heat sink is then fixed to the packaged chip casing. However, in actual packaging, the thermal conductivity of the adhesive used to fix the heat sink is much lower than that of the heat sink and the chip casing. Due to the additional contact thermal resistance between the different materials, the overall thermal resistance of the chip package structure hinders heat conduction between the materials, making it difficult for heat to dissipate outwards and affecting the heat dissipation function of the chip package structure.

[0004] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0005] In view of the shortcomings of the prior art, the purpose of this invention is to provide a heat dissipation chip packaging structure, heat dissipation packaging device and electronic device, thereby solving the problems of high thermal resistance and low heat dissipation efficiency in the heat dissipation part of the existing chip packaging structure, which affect the chip working efficiency.

[0006] The technical solution of the present invention is as follows:

[0007] In a first aspect, the present invention provides a heat dissipation chip packaging structure, comprising: a heat dissipation section, a chip, a packaging substrate, and a thermally conductive material layer, wherein...

[0008] The heat dissipation unit is an integrally molded structure. The lower surface of the heat dissipation unit is provided with a receiving groove for fixing the chip. The first surface of the receiving groove is connected to the thermally conductive material layer, and the second surface of the receiving groove abuts against the packaging substrate and forms a receiving space with the packaging substrate. The heat dissipation unit includes upper heat dissipation fins, a heat dissipation substrate, and lower heat dissipation fins. A plurality of upper heat dissipation fins are vertically arranged on the upper surface of the heat dissipation substrate, and a plurality of lower heat dissipation fins are vertically arranged on the lower surface of the heat dissipation substrate.

[0009] The chip is soldered and fixed to the upper surface of the packaging substrate and disposed in the accommodating space;

[0010] The thermally conductive material layer is disposed on the upper surface of the chip. The thermally conductive material layer is used to make thermal contact with the chip and the heat dissipation part respectively, and to conduct the heat generated inside the chip to the heat dissipation part.

[0011] In a further embodiment of the present invention, the heat dissipation portion further includes supporting fins; wherein,

[0012] The receiving groove is formed in the middle of the lower surface of the heat dissipation substrate; the support fin is disposed at the edge of the receiving groove and is fixedly connected to the upper surface of the packaging substrate; the lower heat dissipation fin is located outside the receiving groove; the length of the upper heat dissipation fin is greater than that of the lower heat dissipation fin.

[0013] In a further embodiment of the present invention, at least one clearance space is provided on the lower heat dissipation fin, and multiple clearance fins are vertically arranged in the clearance space, or no fin structure is provided; when multiple clearance fins are vertically arranged in the clearance space, the clearance fins are arranged on the lower surface of the heat dissipation substrate, and the length of the clearance fins is less than the length of the lower heat dissipation fin.

[0014] In a further embodiment of the present invention, the upper heat dissipation fin is a plate-wing type fin or a needle-shaped fin, and the lower heat dissipation fin is a plate-wing type fin or a needle-shaped fin.

[0015] In a further embodiment of the present invention, the thermally conductive material layer is one of a thermally conductive silicone grease layer, a thermally conductive silicone rubber layer, a heat dissipation pad layer, a phase change material layer, a phase change metal layer, or a thermally conductive adhesive layer.

[0016] In a further embodiment of the present invention, a plurality of conductive bumps are provided between the lower surface of the chip and the upper surface of the packaging substrate, the conductive bumps being located on the upper surface of the packaging substrate; the conductive bumps are respectively used to electrically connect with the chip and the packaging substrate, and to conduct the heat generated inside the chip to the packaging substrate.

[0017] In a further embodiment of the present invention, a plurality of ball grid structures are provided on the lower surface of the packaging substrate. The ball grid structures are mounted in an array on the lower surface of the packaging substrate to conduct heat from the packaging substrate to the printed circuit board.

[0018] In a further embodiment of the present invention, the material of the heat dissipation part is selected from one of aluminum, copper, aluminum alloy, iron, and graphite.

[0019] Secondly, the present invention also provides a heat dissipation packaging device, which includes the heat dissipation chip packaging structure and the printed circuit board described above. The heat dissipation chip packaging structure is disposed on the printed circuit board, and the on-board circuit of the printed circuit board is electrically connected to the packaging substrate of the heat dissipation chip packaging structure.

[0020] Thirdly, the present invention also provides an electronic device comprising the chip heat dissipation packaging device described above.

[0021] This invention provides a heat dissipation chip packaging structure, a heat dissipation packaging device, and an electronic device. The heat dissipation chip packaging structure includes: a heat dissipation part, a chip, a packaging substrate, and a thermally conductive material layer. The heat dissipation part is an integrally formed structure. A receiving groove for fixing the chip is provided on the lower surface of the heat dissipation part. A first surface of the receiving groove is connected to the thermally conductive material layer, and a second surface of the receiving groove abuts against the packaging substrate, forming a receiving space with the packaging substrate. The chip is soldered and fixed to the upper surface of the packaging substrate and disposed in the receiving space. The thermally conductive material layer is disposed on the upper surface of the chip, and is used for thermally conductive contact with both the chip and the heat dissipation part, conducting heat generated inside the chip to the heat dissipation part. In this invention, the integrally formed heat dissipation part serves as both a chip packaging structure and a heat dissipation component, reducing the overall thermal resistance of the heat conduction channel to two layers, significantly reducing the overall thermal resistance of the chip packaging structure, thereby rapidly dissipating heat to the outside and improving the heat dissipation function and working efficiency of the chip packaging structure. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0023] Figure 1 This is an implementation of a chip packaging structure in the prior art.

[0024] Figure 2 This is another implementation of a chip packaging structure in the prior art.

[0025] Figure 3 This is a schematic diagram of the chip packaging structure in this invention.

[0026] Figure 4 This is a schematic diagram of the chip packaging structure in a preferred embodiment of the present invention.

[0027] Figure 5 This is a schematic diagram of the heat dissipation unit in a preferred embodiment of the present invention.

[0028] Figure 6 This is a schematic diagram showing the relative positions between the heat dissipation unit and the chip in a preferred embodiment of the present invention.

[0029] Figure 7 This is a schematic diagram of the chip packaging structure in another preferred embodiment of the present invention.

[0030] The following are the markings in the attached figures: 11, solder ball; 12, heat sink cover; 13, thermally conductive adhesive; 14, chip; 15, solder ball; 16, adhesive layer; 17, substrate; 18, heat dissipation package device; 100, heat dissipation section; 110, upper heat dissipation fin; 110a, upper plate-fin type fin; 110b, upper needle-shaped fin; 120, heat dissipation substrate; 121, receiving groove; 1211, first surface; 1212, second surface; 130, lower heat dissipation fin; 130a, lower plate-fin type fin; 130b, lower needle-shaped fin; 140, support fin; 150, clearance space; 200, chip; 300, package substrate; 400, thermally conductive material layer; 500, conductive bump; 600, ball grid structure. Detailed Implementation

[0031] This invention provides a heat dissipation chip packaging structure, a heat dissipation packaging device, and an electronic device. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0032] In the implementation methods and claims, unless otherwise specified in the text, the terms "a," "an," "the," and "the" may also include plural forms. If the embodiments of the present invention involve descriptions of "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0033] It should be further understood that the term "comprising" as used in this specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may be intermediate elements. Furthermore, "connected" or "coupled" as used herein can include wireless connections or wireless coupling. The term "and / or" as used herein includes all or any unit and all combinations of one or more associated listed items.

[0034] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0035] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0036] The inventors discovered that semiconductor packaging technology is a crucial process for protecting, connecting, and supporting manufactured integrated circuit chips. Specifically, it involves encapsulating the exposed chip within a protective casing. The chip is electrically connected to external circuits through conductive materials on the chip package structure, and heat generated during operation is conducted from the chip package structure to the external environment. Therefore, chip packaging provides essential support for the electrical connection and heat dissipation of the chip, playing a vital role in the performance and stability of electronic products. In existing packaging processes, chips are fixed to a substrate using methods such as soldering and wire bonding, and then a molding compound is used to cover both the chip and the substrate to protect the chip from external environmental influences. During normal chip operation, the integrated circuits inside the chip undertake computational tasks. The energy required for this operation is input from the chip's power pins, but not all energy is converted into work; some is converted into heat. Without proper heat dissipation, the chip may overheat, leading to decreased chip performance, shortened lifespan, and even component damage.

[0037] Commonly used chip packaging structures in existing technologies include Figure 1As shown, the wafer 14 is flip-chip mounted and electrically connected to the substrate 17 via solder balls 15. The central portion of the heat sink 12 protrudes upwards to form a raised portion, which is connected to the upper surface of the wafer 14 via thermally conductive adhesive 13. The periphery of the heat sink 12 is fixedly connected to the substrate 17 via an adhesive layer 16, ensuring that a sealed space for accommodating the wafer 14 is formed below the raised portion. Solder balls 11 are located on the lower surface of the substrate 17, and the substrate 17 is electrically connected to external circuitry via the solder balls 11. At this time, the wafer 14 has two heat conduction channels: one from the upper surface of the heat sink 12 to the air, and the other from the wafer 14 downwards to the substrate 17 via the solder balls 15. Subsequently, some of the heat is transferred from the substrate 17 to the solder balls 11, and further conducted to external materials by the solder balls 11; the other portion of the heat is conducted from the substrate 17 to the air. When the chip package structure transfers heat through natural convection, only a small portion of the heat is conducted upwards. Most of the heat is transferred downwards to the substrate 17 via the solder balls 15, resulting in limited heat dissipation of the chip package structure. Due to the inherent limitations of the heat dissipation efficiency of the existing chip package structure, it is necessary to improve heat dissipation by adding external heat dissipation packaging devices.

[0038] To improve the heat dissipation of chip packaging structures, another existing chip packaging structure further incorporates a heat dissipation unit on top of the heat sink solution to enhance heat dissipation performance. A schematic diagram of this structure is shown below. Figure 2As shown. Based on the existing chip packaging structure described above, a layer of thermally conductive adhesive 13 is applied to the upper surface of the heat sink 12, and the heat dissipation packaging device 18 is pressed and fixed to the upper surface of the heat sink 12 using the thermally conductive adhesive 13. The heat dissipation packaging device 18 serves to conduct heat and can be any fin structure or other heat dissipation structure that increases the heat exchange area with the air. When the chip package with the heat dissipation packaging device 18 is in operation, a portion of the generated heat is conducted from the upper surface of the wafer 14 to the heat sink 12 through the first layer of thermally conductive adhesive 13, and then conducted to the heat dissipation packaging device 18 through the second layer of thermally conductive adhesive 13 on the upper surface of the heat sink 12. Since the heat sink 12 and the heat dissipation packaging device 18 are two separate devices in the conventional solution, an additional layer of thermally conductive adhesive 13 is required for their connection and fixation during processing. The thermally conductive adhesive 13 is generally made of glue, and its thermal conductivity is much lower than that of the copper or aluminum metal materials used in the heat sink 12 and the heat dissipation packaging device 18. Furthermore, the thermally conductive adhesive 13 is disposed on the upper surface of the heat sink 12, and the heat dissipation packaging device 18 is fixedly connected above the thermally conductive adhesive 13. This means that heat propagation at the interfaces between the heat sink 12 and the thermally conductive adhesive 13, and between the thermally conductive adhesive 13 and the heat dissipation packaging device 18, requires crossing materials with different thermal conductivity, volume, density, and structure. This results in additional, non-negligible contact thermal resistance across multiple layers during heat propagation between the materials. Specifically, using conventional solutions would add an extra layer of thermally conductive adhesive, thereby introducing two additional layers of contact thermal resistance. This contact thermal resistance inevitably leads to a reduction in the rate and efficiency of heat transfer within the chip packaging structure.

[0039] To solve the above-mentioned technical problems, in a first aspect, the present invention provides a heat dissipation chip packaging structure, such as... Figure 3As shown, it includes: a heat dissipation section 100, a chip 200, a packaging substrate 300, and a thermally conductive material layer 400. The heat dissipation section 100 is an integrally formed structure. A receiving groove 121 for fixing the chip 200 is provided on the lower surface of the heat dissipation section 100. The first surface 1211 of the receiving groove 121 is connected to the thermally conductive material layer 400; the second surface 1212 of the receiving groove 121 abuts against the packaging substrate 300 and forms a receiving space with the packaging substrate 300. The heat dissipation section 100 includes upper heat dissipation fins 110, a heat dissipation substrate 120, and a lower heat dissipation fin. Fins 130, a plurality of upper heat dissipation fins 110 are vertically disposed on the upper surface of the heat dissipation substrate 120, and a plurality of lower heat dissipation fins 130 are vertically disposed on the lower surface of the heat dissipation substrate 120; the chip 200 is soldered and fixed to the upper surface of the packaging substrate 300 and disposed in the accommodating space; the thermally conductive material layer 400 is disposed on the upper surface of the chip 200, and the thermally conductive material layer 400 is used to make thermally conductive contact with the chip 200 and the heat dissipation part 100 respectively, and to conduct the heat generated inside the chip 200 to the heat dissipation part 100.

[0040] Specifically, the heat dissipation part 100 is made of one of aluminum, copper, aluminum alloy, iron, or graphite, or other materials with good thermal conductivity, and is processed by cutting, extrusion, stamping, die casting, or other methods to obtain an integrally formed structure. In this invention, the integrally formed heat dissipation part 100 can serve as a heat dissipation structure to conduct heat. The receiving groove 121 includes a first surface 1211 formed inwardly and a second surface 1212 formed around it. Specifically, the heat dissipation part 100 is upside down on the packaging substrate 300. When the second surface 1212 of the receiving groove 121 abuts against the packaging substrate 300, a sealed receiving space for accommodating the chip 200 is formed between the first surface 1211 of the receiving groove 121 and the upper surface of the packaging substrate 300, thereby realizing the integration of heat dissipation and packaging of the heat dissipation part 100. While achieving heat dissipation, it is reused as a chip packaging structure and plays a role in placing, fixing, sealing, and protecting the chip 200. When the chip 200 is operating, some of the heat generated inside it is conducted upwards through the thermally conductive material layer 400 to the heat dissipation section 100. This process can be equivalent to having two layers of contact thermal resistance. Since the heat dissipation section 100 is made of a high thermal conductivity material, the heat in the heat dissipation section 100 is rapidly conducted horizontally to the end of the heat dissipation section 100 closest to the air, achieving rapid heat transfer. Simultaneously, another portion of the heat generated inside the chip 200 is conducted downwards from the second surface 1212 of the receiving groove 121 to the packaging substrate 300, and then dissipated to the outside via the packaging substrate 300. Furthermore, since the heat dissipation section 100 is connected to the packaging substrate 300, the packaging substrate 300 can also conduct some heat to the heat dissipation section 100.

[0041] A thermally conductive material layer 400 made of a thermally conductive interface material can also be provided on the contact surface between the heat dissipation part 100 and the packaging substrate 300 to fill the gaps at the contact position and further reduce the overall thermal resistance. The chip 200 is a semiconductor chip wafer, which can be made of silicon wafer or other non-silicon-based materials that can be used as wafers. The packaging substrate 300 is typically made of ceramic, BT resin, glass laminate, or polyimide, but can also be made of other organic materials or flexible materials. The packaging substrate 300 serves as an electrical interconnect and mechanical support. Accordingly, the heat dissipation part 100 can be used to provide natural convection or forced convection. When the heat dissipation part 100 dissipates heat through natural convection, it can maximize the heat dissipation surface area and conduct heat without adding active components. If the heat dissipation part 100 uses forced convection for heat dissipation, a fan device corresponding to the heat dissipation part 100 can be added externally. The fan device is an active device used to provide airflow through the heat dissipation part 100. The fan assembly forces cooler air through the heat sink 100, generating turbulence within the structure of the heat sink 100 and improving its cooling performance. The upper heat sink fin 110 is a plate-fin type fin or a needle-shaped fin, and the lower heat sink fin 130 is a plate-fin type fin or a needle-shaped fin.

[0042] In a further embodiment of the present invention, the heat dissipation unit 100 further includes a support fin 140; wherein, the receiving groove 121 is formed in the middle of the lower surface of the heat dissipation substrate 120, and the support fin 140 is provided at the edge of the receiving groove 121, and the support fin 140 is fixedly connected to the upper surface of the packaging substrate 300; at this time, the second surface 1212 of the receiving groove 121 is located on the lower surface of the support fin 140, that is, the support fin 140 is formed by extending downward from the second surface 1212 of the receiving groove 121, thereby the support fin 140 is reused so that it can be used for both heat dissipation and connection and fixation with the packaging substrate 300. The lower heat dissipation fin 130 is located outside the receiving groove 121; the length of the upper heat dissipation fin 110 is greater than that of the lower heat dissipation fin 130.

[0043] It should be noted that, in order to facilitate a clear and intuitive demonstration and explanation of the internal structure of the chip package, the... Figures 4 to 7This is a schematic diagram of the structure after vertically cutting both ends of the heat dissipation chip packaging structure. In actual use, the chip 200 is located in a sealed space. Specifically, the receiving groove 121 is located on the vertical center line of the heat dissipation substrate 120, and the support fins 140 in the four directions form a vertical structure that is perpendicular to each other. When the support fins 140 are fixedly connected to the packaging substrate 300, a sealed receiving space for accommodating the chip 200 is formed inside its receiving groove 121. Thus, the chip packaging structure can simultaneously provide mechanical protection, electrical connection, and integrated heat dissipation for the chip.

[0044] In some preferred embodiments of the present invention, the upper heat dissipation fin 110 and the lower heat dissipation fin 130 are plate-fin type fins, such as... Figures 4 to 6 As shown, the upper heat dissipation fin 110 is an upper plate-fin type fin 110a, and the lower heat dissipation fin 130 is a lower plate-fin type fin 130a. The upper plate-fin type fins 110a are arranged vertically in an array on the upper surface of the heat dissipation substrate 120, and the lower plate-fin type fins 130a are arranged vertically in an array on the lower surface of the heat dissipation substrate 120. In another preferred embodiment of the present invention, the upper heat dissipation fin 110 is an upper needle-shaped fin 110b, and the lower heat dissipation fin 130 is a lower needle-shaped fin 130b. Similarly, the upper needle-shaped fins 110b are arranged vertically in an array on the upper surface of the heat dissipation substrate 120, and the lower needle-shaped fins 130b are arranged vertically in an array on the lower surface of the heat dissipation substrate 120. Figure 7 As shown. The needle-shaped fins can be at least one of rectangular fins, circular fins, and elliptical fins, which have the advantages of being lightweight and small in size, while also having high volumetric efficiency and isodirectionality. The isodirectionality means that the needle-shaped fins have the same characteristics when facing airflow in all directions, which is beneficial to the forced convection process.

[0045] It should be noted that, in some other preferred embodiments, the upper heat dissipation fin 110 of the heat dissipation unit 100 can be a plate-fin type fin, and the lower heat dissipation fin 130 can be a needle-shaped fin; or the upper heat dissipation fin 110 of the heat dissipation unit 100 can be a needle-shaped fin, and the lower heat dissipation fin 130 can be a plate-fin type fin. The specific structure of the upper heat dissipation fin 110 and the lower heat dissipation fin 130 can be set according to the heat dissipation requirements, convection method and chip model, and will not be described in detail here.

[0046] Specifically, the heat dissipation section 100 contacts the upper surface of the chip 200, which serves as a heat source, through a thermally conductive material layer 400, and diffuses the heat from the chip 200 from the hot spot to the plane of the upper heat dissipation fin 110, the lower heat dissipation fin 130, and the support fin 140. The upper heat dissipation fin 110, the lower heat dissipation fin 130, and the support fin 140 can be cut or forged into any number and any geometric shape of heat dissipation structures, which are typically perpendicular to the base to disperse heat. Preferably, the upper heat dissipation fin 110, the lower heat dissipation fin 130, and the support fin 140 in this invention can be rectangular fins, thereby increasing the overall surface area of ​​the heat dissipation section 100 to improve the total heat transfer and dissipation, and optimize the heat dissipation effect.

[0047] Furthermore, the lower heat sink 130 is also provided with at least one clearance space 150, in which multiple clearance fins are vertically arranged, or no fin structure is provided; when multiple clearance fins are vertically arranged in the clearance space 150, the clearance fins are arranged on the lower surface of the heat sink substrate, and the length of the clearance fins is less than the length of the lower heat sink 130. Specifically, when there are other electrical components such as inductors and capacitors on the external circuit that needs to be assembled in the chip package structure, they need to occupy a certain space, making it impossible to completely cover the lower heat sink 130 in an array pattern at all positions of the heat sink substrate 120. Therefore, the present invention can refer to the relative position of the corresponding electronic components in space and set the clearance space 150 accordingly at the occupied position. Furthermore, according to the height of the corresponding electronic component, clearance fins of appropriate length can be set at corresponding positions in the clearance space 150. The minimum distance between the clearance fins and the plane where the electronic component is located is greater than the maximum height of the electronic component. This achieves a certain heat dissipation effect while leaving clearance space 150 for the electronic component in the chip packaging structure. Alternatively, the clearance space 150 on the heat dissipation substrate 120 may not have additional clearance fins, further reducing the impact of heat conducted by the chip packaging structure on the operating efficiency of the electronic component.

[0048] Furthermore, the thermally conductive material layer 400 is one of the following: a thermally conductive silicone grease layer, a thermally conductive silicone rubber layer, a heat dissipation pad layer, a phase change material layer, a phase change metal layer, or a thermally conductive adhesive layer. The thermally conductive material layer 400 can be any organic or inorganic material with high thermal conductivity and high flexibility, capable of fully filling the pores of the contact surface and ensuring low contact thermal resistance between the thermal interface material and the contact surface.

[0049] In a further embodiment of a preferred embodiment of the present invention, a first conductive structure layer is further included between the lower surface of the chip 200 and the upper surface of the packaging substrate 300. The first conductive structure layer is electrically connected to the chip 200 and the packaging substrate 300, respectively, and is used to conduct heat generated inside the chip 200 to the packaging substrate 300. The first conductive structure layer includes a plurality of conductive bumps 500, which are located on the upper surface of the packaging substrate 300. The conductive bumps 500 are electrically connected to the chip 200 and the packaging substrate 300, respectively, and are used to conduct heat generated inside the chip 200 to the packaging substrate 300. In flip-chip bonding, the active side of the chip 200 is facing down, and it is directly connected to the substrate through conductive bumps on the surface of the chip 200. This eliminates the need for long metal bonding wires and further shortens the signal transmission path. The conductive bumps 500 serve as a connection bridge between the chip 200 and the printed circuit board (PCB). They are preferably made of tin, but other metals with excellent thermal conductivity can also be used.

[0050] Furthermore, a second conductive structure is also provided on the lower surface of the packaging substrate 300. The second conductive structure is electrically connected to the packaging substrate 300 and is used to conduct the heat of the packaging substrate 300 to the outside. The second conductive structure layer includes a plurality of ball grid structures 600, which are mounted in an array on the lower surface of the packaging substrate 300 to conduct the heat of the packaging substrate 300 to the printed circuit board.

[0051] The plurality of ball grid structures 600 constitute a ball grid array (BGA). BGA packaging technology, or BGA packaging, is a surface mount technology used on integrated circuits, often used to permanently mount devices such as microprocessors. Compared to other packaging methods such as dual in-line packages (DIP) or quad flat packages (QFP), BGA packaging can accommodate more pins, enabling more complex computing tasks. Furthermore, compared to surrounding limited package types, the ball grids on the bottom surface of the chip 200 using a ball grid array can all be used as pins, resulting in shorter average conductor lengths and better high-speed performance. The ball grid structures 600 use conductive and thermally conductive materials such as tin, lead, or metal alloys to form an electrical connection with the packaging substrate 300. Simultaneously, the ball grid structures 600 also provide heat dissipation paths for the BGA package, which helps improve the chip's power density. Specifically, the connection points between the ball grid structure 600 of the BGA package and the package substrate 300 are distributed in two dimensions, with a wider connection surface. This can be equivalent to increasing the heat transfer area, reducing the junction thermal resistance of the chip 200, and providing good heat dissipation conditions for the chip 200.

[0052] Specifically, it will be as follows Figure 2 The chip packaging structure used in the prior art shown is similar to that in this invention. Figure 4 The heat dissipation effect of the heat dissipation chip package structure shown was tested, and the test results are shown in Table 1.

[0053] Table 1

[0054]

[0055] Where Tj represents the chip junction temperature, Rj_hs represents the thermal resistance from chip 200 to heat sink 100, and Rja represents the thermal resistance from chip 200 to the environment. When chip 200 is operating, the main source of heat for the microcircuit on chip 200 is the temperature of the semiconductor junction, i.e., the chip junction temperature. The chip junction temperature is the highest temperature in the chip package structure, typically higher than the case temperature and device surface temperature. The chip junction temperature measures the time required for heat dissipation from the semiconductor wafer to the package device casing and the overall thermal resistance. The environment refers to the air environment surrounding the chip package structure; that is, the thermal resistance from chip 200 to the environment is the overall thermal resistance of heat conduction from chip 200 to the air in the heat conduction channel. According to Table 1, the chip junction temperature in this invention is 96.529℃, the thermal resistance from chip 200 to heat sink 100 is 4.61℃ / W, and the thermal resistance from chip 200 to the environment is 15.31℃ / W. In the prior art, the junction temperature of the chip packaging structure is 99.39℃, the thermal resistance from chip 200 to heat sink 100 is 5.95℃ / W, and the thermal resistance from chip 200 to the environment is 15.88℃ / W. According to Table 1, the chip junction temperature in the chip packaging structure of the present invention is reduced by 3% compared to the conventional solution, the thermal resistance from chip 200 to heat sink 100 is reduced by 29%, and the thermal resistance from chip 200 to the environment is reduced by 4%. Therefore, the chip packaging structure of the present invention has lower overall thermal resistance and lower chip junction temperature during operation compared to the conventional solution, resulting in better heat dissipation. Furthermore, according to the Arrhenius equation, the chip packaging structure of the present invention can significantly improve the lifespan of chip 200.

[0056] Secondly, the present invention also provides a heat dissipation packaging device, which includes the heat dissipation chip packaging structure and a printed circuit board described above. The heat dissipation chip packaging structure is disposed on the printed circuit board, and the on-board circuit of the printed circuit board is electrically connected to the packaging substrate of the heat dissipation chip packaging structure. Specific details are as described in the specific embodiments of the heat dissipation chip packaging structure, and will not be repeated here.

[0057] Thirdly, the present invention also provides an electronic device, which includes the chip heat dissipation packaging device described above, specifically as described in the specific embodiments of the heat dissipation chip packaging structure, which will not be repeated here.

[0058] This invention provides a heat dissipation chip packaging structure, a heat dissipation packaging device, and an electronic device. The heat dissipation chip packaging structure includes: a heat dissipation part, a chip, a packaging substrate, and a thermally conductive material layer. The heat dissipation part is an integrally formed structure. A receiving groove for fixing the chip is provided on the lower surface of the heat dissipation part. A first surface of the receiving groove is connected to the thermally conductive material layer, and a second surface of the receiving groove abuts against the packaging substrate, forming a receiving space with the packaging substrate. The chip is soldered and fixed to the upper surface of the packaging substrate and disposed in the receiving space. The thermally conductive material layer is disposed on the upper surface of the chip. The thermally conductive material layer is used for thermally conductive contact with both the chip and the heat dissipation part, and conducts the heat generated inside the chip to the heat dissipation part. This provides the following beneficial effects:

[0059] By integrating the heat sink and packaging substrate into a single integrated chip package structure, the internal chip is protected while heat conduction and dissipation are achieved, eliminating the need for thermally conductive materials between the package and the heat sink structure. This reduces the thermal resistance of heat propagation between the package and the heat sink structure, decreases the overall thermal resistance of the heat conduction channel, and significantly reduces the overall thermal resistance of the chip package structure. Consequently, heat is rapidly dissipated to the outside, improving the heat dissipation effect and operating efficiency of the chip package structure.

[0060] The heat in the chip can be conducted vertically upwards to the heat dissipation unit or downwards to the packaging substrate, achieving heat dissipation through dual heat conduction channels. At the same time, the heat is further conducted outwards in both horizontal and vertical directions through the heat dissipation unit and the packaging substrate, achieving three-dimensional heat conduction. The heat is then rapidly dissipated to the outside through the heat dissipation channels, thereby significantly improving the heat dissipation effect of the chip packaging structure.

[0061] The heat dissipation of the heat sink is mainly achieved through convection heat transfer. The effect of convection heat transfer is positively correlated with the heat dissipation area. Based on the same on-chip area, this invention increases the heat dissipation area, thereby improving the thermal conductivity and heat dissipation efficiency.

[0062] By adopting a packaging structure with lower heat dissipation fins, the heat dissipation part of the chip packaging structure can be equipped with an array of lower heat dissipation fins, which effectively utilizes the space below the chip packaging structure and increases the heat exchange area on the basis of the same chip area. This significantly improves the heat dissipation effect of the chip packaging structure under limited chip space conditions and realizes integrated heat dissipation and packaging.

[0063] It should be understood that the application of the present invention is not limited to the examples above. Those skilled in the art can make improvements or modifications based on the above description, and all such improvements and modifications should fall within the protection scope of the appended claims.

Claims

1. A heat dissipating chip package structure, characterized by, The application relates to a heat dissipation device for electronic components. The heat dissipation device comprises a heat dissipation part, a chip, a packaging substrate and a heat conductive material layer. The heat dissipation part is integrally formed, and a lower surface of the heat dissipation part is provided with a receiving groove for fixing the chip. The first surface of the receiving groove is connected with the heat conductive material layer, and the second surface of the receiving groove is in abutment with the packaging substrate and forms a receiving space with the packaging substrate. The heat dissipation part comprises upper heat dissipation fins, a heat dissipation substrate and lower heat dissipation fins. A plurality of upper heat dissipation fins are vertically arranged on the upper surface of the heat dissipation substrate, and a plurality of lower heat dissipation fins are vertically arranged on the lower surface of the heat dissipation substrate. The chip is welded and fixed on the upper surface of the packaging substrate and arranged in the receiving space. The heat conductive material layer is arranged at the upper surface of the chip. The heat conductive material layer is used for being in heat conductive contact with the chip and the heat dissipation part respectively and conducting the heat generated in the chip to the heat dissipation part.

2. The heat dissipation chip package structure according to claim 1, wherein, The heat conductive material layer is used for filling the gap at the contact position of the chip and the heat dissipation part.

3. The heat dissipation chip package structure of claim 1, wherein, The heat dissipation part further comprises support fins.

4. The heat dissipation chip package structure of claim 1, wherein, The receiving groove is located on the vertical center line of the heat dissipation substrate, and the support fins form a vertical facade structure.

5. The heat dissipation chip package structure of claim 1, wherein, When the support fins are fixedly connected with the packaging substrate, a sealed receiving space for receiving the chip is formed in the receiving groove.

6. The heat dissipation chip package structure of claim 1, wherein, The lower plate fin type fins are vertically arranged in an array structure on the lower surface of the heat dissipation substrate. The receiving groove is arranged in the middle part of the lower surface of the heat dissipation substrate. The support fins are arranged at the edge of the receiving groove and are fixedly connected with the upper surface of the packaging substrate. The length of the upper heat dissipation fin is greater than that of the lower heat dissipation fin. At least one avoiding space is arranged on the lower heat dissipation fin. A plurality of avoiding fins are vertically arranged in the avoiding space. The avoiding fins are arranged on the lower surface of the heat dissipation substrate, and the length of the avoiding fin is smaller than that of the lower heat dissipation fin. The avoiding space is arranged according to the position of the corresponding electronic component in space. The minimum distance between the avoiding fin and the plane where the electronic component is located is greater than the maximum height of the electronic component. The upper heat dissipation fin is a plate fin type fin or a needle type fin. The lower heat dissipation fin is a plate fin type fin or a needle type fin. The heat conductive material layer adopts one of a heat conductive silicone grease layer, a heat conductive silicone rubber layer, a heat dissipation gasket layer, a phase change material layer, a phase change metal layer and a heat conductive glue layer. A plurality of conductive bumps are arranged between the lower surface of the chip and the upper surface of the packaging substrate. The conductive bumps are arranged on the upper surface of the packaging substrate. The conductive bumps are used for electrically connecting the chip and the packaging substrate and conducting the heat generated in the chip to the packaging substrate. A plurality of ball grid structures are arranged on the lower surface of the packaging substrate. The ball grid structures are arranged in an array form on the lower surface of the packaging substrate and are used for conducting the heat of the packaging substrate to a printed circuit board. The material of the heat dissipation part is selected from one of aluminum, copper, iron and graphite.

7. A heat dissipating packaged device, characterized by, A printed circuit board comprising the heat dissipation chip package structure as claimed in any one of claims 1-6, wherein the heat dissipation chip package structure is arranged on the printed circuit board, and the on-board circuit of the printed circuit board is electrically connected with the package substrate of the heat dissipation chip package structure.

8. An electronic device, comprising: A heat dissipation package device comprising the heat dissipation chip package structure as claimed in claim 7.

Images