Semiconductor photonic device and forming method thereof

Abstract

The invention provides a semiconductor photonic device and a method of forming the same, a dielectric waveguide structure of the semiconductor photonic device is formed on a separate substrate and then bonded to the semiconductor photonic device after forming a semiconductor photonic component of the semiconductor photonic device. A dielectric waveguide structure may be formed in a dielectric layer on a carrier substrate, and the dielectric layer may be used to bond the dielectric waveguide structure to a dielectric layer on a semiconductor photonic device. Since the dielectric waveguide structures are separately formed, the dielectric waveguide structures may be formed using high temperature process techniques without concern of potential damage and / or performance degradation to the semiconductor photonic component if the dielectric waveguide is formed over the semiconductor photonic component.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor photonic device and a method of forming the same. BACKGROUND

[0002] Photonics integrated circuits (PICs) can include multiple types of waveguide structures configured to perform different functions. Semiconductor waveguide structures (e.g., silicon (Si) waveguide structures) are often used in optical modulator structures because the refractive index in the semiconductor waveguide structures can be modulated by applying an electric field to the semiconductor material of the semiconductor waveguide structures. Dielectric waveguide structures are often used for signal propagation and / or edge coupling because the dielectric waveguide structures have lower optical loss and higher thermal stability compared to the semiconductor material of the semiconductor waveguide structures. SUMMARY

[0003] Some embodiments described herein provide a method of forming a semiconductor photonic device. The method includes forming one or more semiconductor photonic components in a semiconductor layer of the semiconductor photonic device. The method includes bonding a dielectric layer to the semiconductor photonic device after forming the one or more semiconductor photonic components, wherein a dielectric waveguide structure is included in the dielectric layer.

[0004] Some embodiments described herein provide a method of forming a semiconductor photonic device. The method includes forming a first portion of a first dielectric layer on a carrier substrate. The method includes forming a dielectric waveguide structure on the first portion of the first dielectric layer. The method includes forming a second portion of the first dielectric layer on the dielectric waveguide structure such that the dielectric waveguide structure is encapsulated in the first dielectric layer. The method includes bonding the first dielectric layer to a second dielectric layer of the semiconductor photonic device such that the dielectric waveguide structure is positioned above one or more semiconductor photonic components in the second dielectric layer.

[0005] Some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a semiconductor layer. The semiconductor photonic device includes a first dielectric region above the semiconductor layer. The semiconductor photonic device includes a semiconductor waveguide structure in the first dielectric region. The semiconductor photonic device includes a second dielectric region vertically adjacent to the first dielectric region. The semiconductor photonic device includes a dielectric waveguide structure in the second dielectric region, wherein the first dielectric region has a first etch rate to an etchant, wherein the second dielectric region has a second etch rate to the etchant, and wherein the first etch rate is greater than the second etch rate. BRIEF DESCRIPTION OF DRAWINGS

[0006] The various aspects of the disclosure can be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that the various features are not drawn to scale. In fact, the dimensions can be arbitrarily increased or decreased for clarity. It is also noted that like-referenced numerals and characters herein reflect like features, components, and / or structures.

[0007] FIG. 1A and FIG. 1B is an example diagram of a semiconductor photonic device described herein.

[0008] FIG. 2A to FIG. 2F is an example diagram of a semiconductor photonic device described herein.

[0009] FIG. 3A to FIG. 3H is an example diagram of a semiconductor photonic device described herein.

[0010] FIG. 4 is an example diagram of a semiconductor photonic device described herein.

[0011] FIG. 5A to FIG. 5K is an example diagram of a semiconductor photonic device described herein.

[0012] FIG. 6 is an example diagram of a semiconductor photonic device described herein.

[0013] FIG. 7A to FIG. 7G is an example diagram of a semiconductor photonic device described herein.

[0014] FIG. 8 is a flow diagram of an example process related to forming a semiconductor photonic device described herein.

[0015] FIG. 9 is a flow diagram of an example process related to forming a semiconductor photonic device described herein. DETAILED DESCRIPTION

[0016] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to provide a thorough understanding of the

[0017] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0018] Semiconductor waveguides and other semiconductor photonic components of a semiconductor photonic device can be formed in a top silicon layer of a silicon on insulator (SOI) substrate of the semiconductor photonic device. Layers and structures formed after the semiconductor photonic components can be limited in the process technology and / or process parameter types that can be used to form the layers and structures. For example, semiconductor photonic components formed in the top silicon layer can have limitations on the temperatures to which they can be exposed, which limits the semiconductor process technology and / or process parameter types that can be used to form dielectric edge coupler waveguides above the top silicon layer. Exposing semiconductor photonic components formed in the top silicon layer to excessive temperatures can damage and / or degrade the performance of these semiconductor photonic components. For example, active components such as optical modulator structures and / or photodetectors can be formed in the top silicon layer, and metal silicide layers for contacts of the active components can be susceptible to material migration and / or increased contact resistance from high temperature processes. As another example, active components such as photodetectors can have epitaxially grown regions of semiconductor material (e.g., germanium (Ge)), and these epitaxially grown regions can be susceptible to increased dark current (which can result in reduced sensitivity and / or decreased low spin performance) from high temperature processes. Thus, the formation of dielectric edge coupler waveguides can be limited to low temperature processes to avoid damage to the active components.

[0019] The dielectric material of the dielectric edge coupler waveguide can be more susceptible to absorption and retention of hydrogen (H) at lower process temperatures, resulting in increased hydrogen concentration in the dielectric edge coupler waveguide. For example, the dielectric edge coupler waveguide can be formed from silicon nitride (Si x N y) formation, which can have high concentrations of silicon (Si) and nitrogen (N) dangling bonds that are prone to absorbing hydrogen by forming silicon-hydrogen (Si-H) and nitrogen-hydrogen (N-H) bonds. The absorbed hydrogen in the dielectric edge coupler waveguide can cause optical absorption in the dielectric edge coupler waveguide, and thus an increase in hydrogen concentration in the dielectric edge coupler waveguide can result in an increase in optical loss in the dielectric edge coupler waveguide. As a result, low temperature process techniques can result in a lower performance (e.g., lower efficiency and reduced optical communication bandwidth) of the dielectric edge coupler waveguide than when high temperature process techniques are used.

[0020] In some embodiments described herein, a dielectric waveguide structure (e.g., a dielectric edge coupler waveguide) of a semiconductor photonic device is formed (e.g., pre-formed) on a separate substrate (e.g., on a carrier substrate) and then bonded to the semiconductor photonic device after forming semiconductor photonic components (e.g., semiconductor waveguide structures, optical modulator structures, photodetectors) of the semiconductor photonic device. The dielectric waveguide structure can be formed in a dielectric layer on the carrier substrate, and the dielectric layer can be used to bond the dielectric waveguide structure to a dielectric layer on the semiconductor photonic device. This enables the dielectric waveguide structure to be bonded to the semiconductor photonic device using bonding techniques such as wafer-on-wafer (WoW) bonding.

[0021] Since the dielectric waveguide structure is formed separately, high temperature process techniques (e.g., high temperature deposition techniques, annealing techniques) can be used to form the dielectric waveguide structure without the concern of potential damage and / or performance degradation to the semiconductor photonic components if the dielectric waveguide structure were formed on top of the semiconductor photonic components. Using high temperature process techniques can enable the dielectric waveguide structure to achieve low optical loss, as the high temperature process techniques can be used to achieve low hydrogen concentration (e.g., low concentrations of silicon-hydrogen and nitrogen-hydrogen bonds) in the dielectric waveguide structure while having minimal or no impact on the optical coupling performance between the dielectric waveguide structure and the semiconductor photonic components. The low hydrogen concentration in the dielectric waveguide structure enables the dielectric waveguide structure to achieve higher performance, including higher operational efficiency and increased communication bandwidth. In addition, the high temperature process techniques can enable the dielectric waveguide structure to be formed with greater surface uniformity and smoothness than when low temperature process techniques are used, resulting in a higher quality interface between the dielectric waveguide structure and surrounding dielectric layers, which enables increased optical confinement (and reduced optical loss) in the dielectric waveguide structure.

[0022] FIG. 1A and FIG. 1BThis is an example diagram of the semiconductor photonic device 100 described herein. The semiconductor photonic device 100 may include a photonic integrated circuit comprising multiple optical components, such as a dielectric waveguide structure and a semiconductor waveguide structure. The dielectric waveguide structure and the semiconductor waveguide structure are optically coupled to facilitate optical signal transmission between them. Furthermore, the dielectric waveguide structure and the semiconductor waveguide structure are formed using the process techniques described herein, such that the dielectric waveguide structure is located beneath the semiconductor waveguide structure. This allows the dielectric waveguide structure to be formed prior to the semiconductor waveguide structure and other semiconductor photonic components of the photonic integrated circuit, providing greater process flexibility in forming the dielectric waveguide structure and enabling the use of high-temperature process techniques to form the dielectric waveguide structure.

[0023] FIG. 1A A perspective view of a semiconductor photonic device 100 is shown. (As shown) FIG. 1A As shown, the semiconductor photonic device 100 may include a substrate layer 102 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate) and a dielectric layer 104 on and / or on the substrate layer 102. The dielectric layer 104 may include a buried oxide or bottom oxide (BOX) layer, a silicon oxide layer (SiO2), or a silicon oxide layer. x Such as SiO2), undoped silicate glass (USG) layers, and / or another type of oxide dielectric layer.

[0024] Semiconductor waveguide structure 106 may be contained within dielectric layer 104. Semiconductor waveguide structure 106 may include one or more semiconductor materials, such as silicon (Si), silicon doped with one or more types of dopants (e.g., p-type dopants, n-type dopants), germanium (Ge), silicon-germanium (SiGe), group III-V semiconductor materials (e.g., semiconductor materials comprising one or more group III elements and one or more group V elements in the periodic table), and / or other suitable semiconductor materials. Semiconductor waveguide structure 106 may include an elongated structure extending in the x-direction within semiconductor photonic device 100. Optical signals may propagate primarily in the x-direction through semiconductor waveguide structure 106. Semiconductor waveguide structure 106 may be formed from semiconductor layers etched to define semiconductor waveguide structure 106. FIG. 1A In the example shown, the semiconductor waveguide structure 106 has a strip waveguide structure shape. However, the semiconductor waveguide structure 106 may conform to other structural shapes, such as rib waveguide structure shapes and / or tapered waveguide structure shapes, etc.

[0025] Another dielectric layer 108 is included above the dielectric layer 104, and a dielectric waveguide structure 110 is included in the dielectric layer 108. The dielectric layer 108 can comprise a silicon oxide layer (SiO x , e.g., SiO2), an undoped silicate glass layer, and / or another type of oxide dielectric layer. In some embodiments, the dielectric waveguide structure 110 is an edge coupler waveguide configured to receive and / or provide optical signals from and / or to an optical fiber, an optical fiber cable, and / or another type of external optical connection. Additionally and / or alternatively, the dielectric waveguide structure 110 can be configured as another type of dielectric waveguide structure. The dielectric waveguide structure 110 can be located above the semiconductor waveguide structure 106 (e.g., at a higher z-direction location in the semiconductor photonic device 100 than the semiconductor waveguide structure 106), and can be at least partially laterally offset from the semiconductor waveguide structure 106 in the x-direction. The dielectric waveguide structure 110 can be physically separated from the semiconductor waveguide structure 106 by the dielectric layers 104 and 108, which provides optical isolation while still allowing coupling of optical signals 112 between the semiconductor waveguide structure 106 and the dielectric waveguide structure 110 at ends of the semiconductor waveguide structure 106 facing ends of the dielectric waveguide structure 110.

[0026] The dielectric waveguide structure 110 can comprise a nitride dielectric layer comprising a nitride dielectric material having a higher refractive index than silicon dioxide, such as silicon nitride (Si x N y , e.g., Si3N4). Additionally and / or alternatively, the dielectric waveguide structure 110 can comprise another type of dielectric material, such as an aluminum oxide material (Al x O y , e.g., Al2O3), an aluminum nitride material (AIN), a hafnium oxide material (HfO x , e.g., HfO2), a titanium oxide material (TiO x , e.g., TiO2), a zinc oxide material (ZnO), and / or a germanium oxide material (GeO x , e.g., GeO2), lithium niobate (LiNbO3), and / or other examples.

[0027] The dielectric waveguide structure 110 can comprise an elongated structure extending in the x-direction in the semiconductor photonic device 100. Optical signals can primarily propagate through the dielectric waveguide structure 110 in the x-direction. The shape of the dielectric waveguide structure 110 can comprise a strip waveguide structure, a rib waveguide structure, a deep-rib waveguide structure, and / or another type of waveguide structure.

[0028] The dielectric layer 108 surrounding the dielectric waveguide structure 110 can act as a cladding for the dielectric waveguide structure 110. Thus, the dielectric waveguide structure 110 and the dielectric layer 108 surrounding the dielectric waveguide structure 110 can correspond to a slab waveguide, where the dielectric waveguide structure 110 includes a high-k material core sandwiched between low-k material cladding layers relative to the dielectric layer 108. The difference in dielectric constant between the high-k material of the dielectric waveguide structure 110 and the low-k material of the dielectric layer 108 can enable loose coupling of optical signal modes in the dielectric waveguide structure 110 while providing a relatively low critical angle to enable total internal reflections in the dielectric waveguide structure 110. This enables the dielectric waveguide structure 110 to be used for high-speed and / or high-bandwidth applications of high-frequency optical signals, such as data center communications, millimeter-wave telecommunications (e.g., fifth generation (5G) telecommunications, sixth generation (6G) telecommunications, or a newer generation of telecommunications), autonomous driving, Internet of Things (IoT), and / or artificial intelligence, among other examples.

[0029] As described herein, for example, in connection with FIG. 2A to FIG. 2F and / or 3A to FIG. 3H The dielectric layer 108 is used to bond the dielectric waveguide structure 110 to the semiconductor photonic device 100. The dielectric waveguide structure 110 can be pre-formed in the dielectric layer 108, and then the dielectric layer 108 can be dielectric-to-dielectric bonded to the dielectric layer 104. Pre-forming the dielectric waveguide structure 110 and then bonding the dielectric waveguide structure 110 to the semiconductor photonic device 100 enables the dielectric waveguide structure 110 to be formed using high-temperature semiconductor processing techniques without damaging the semiconductor waveguide structure 106 and / or other layers and / or components formed in and / or from the semiconductor layer in which the semiconductor waveguide structure 106 is formed. This enables low hydrogen concentration (e.g., low concentration of silicon-hydrogen bonds, low concentration of nitrogen-hydrogen bonds) to be achieved in the dielectric material (e.g., silicon nitride (SixNy, such as Si3N4)) of the dielectric waveguide structure 110. For example, the hydrogen concentration in the dielectric waveguide structure 110 can be less than about 5% of the weight of the dielectric waveguide structure 110 material, can be less than about 5% of the volume of the dielectric waveguide structure 110 material, less than about 5% of the atomic composition of the dielectric waveguide structure 110 material, and / or can be another hydrogen concentration. The hydrogen concentration in the dielectric waveguide structure 110 can be detected by Fourier transform infrared spectroscopy (FTIR) and / or other types of spectroscopy.

[0030] In some embodiments, the dielectric layer 104 and the dielectric layer 108 are formed of the same material, such as silicon dioxide (Si02). In some embodiments, a bonding interface between the dielectric layer 104 and the dielectric layer 108 is visible in a cross-sectional view of the semiconductor photonic device 100. In other words, the dielectric layer 104 and the dielectric layer 108 can be visibly distinct layers in the semiconductor photonic device.

[0031] Alternatively, the dielectric layer 104 and the dielectric layer 108 can merge due to bonding, such that the dielectric layer 104 is a first dielectric region of a continuous dielectric layer, and the dielectric layer 108 is a second dielectric region of the continuous dielectric layer above the first dielectric region. However, the silicon dioxide material of the dielectric layer 108 (e.g., the second dielectric region) can have one or more properties that are different from the properties of the silicon dioxide material of the dielectric layer 104 (e.g., the first dielectric region) because the dielectric layer 108 experienced high-temperature process operations during formation of the dielectric waveguide structure 110, while the dielectric layer 104 was only exposed to low-temperature process operations due to the semiconductor waveguide structure 106 and / or other layers and / or components in and / or formed from the semiconductor layer in which the semiconductor waveguide structure 106 was formed. For example, the dielectric layer 108 can have a higher density than the dielectric layer 104.

[0032] As another example, the dielectric layer 104 has a first etch rate for an etchant (e.g., for a silicon dioxide etchant such as hydrofluoric acid (HF) or diluted hydrofluoric acid (DHF)), while the dielectric layer 108 has a second etch rate for the etchant that is different from the first etch rate. The first etch rate of the dielectric layer 104 can be greater than the second etch rate of the dielectric layer 108 because the dielectric layer 108 experienced high-temperature process operations during formation of the dielectric waveguide structure 110. In some embodiments, the difference between the first etch rate of the dielectric layer 104 and the second etch rate of the dielectric layer 108 can be used to detect the bonding interface between the dielectric layer 104 and the dielectric layer 108. For example, etchant staining (e.g., HF staining or DHF staining) can be detected in a scanning electron microscope (SEM) image of a cross-section of the semiconductor photonic device 100, and the etchant staining (e.g., size, color) of the dielectric layer 104 and the dielectric layer 108 can be different, thereby indicating the interface between the dielectric layer 104 and the dielectric layer 108.

[0033] As FIG. 1AAs further shown, another dielectric layer 114 (e.g., a third dielectric region) may be located above dielectric layer 108. Dielectric layer 114 may be referred to as a back-end dielectric layer (or back-end process (BEOL) dielectric layer) because a back-end metallization layer of the semiconductor photonic device 100 may be formed in dielectric layer 114. Dielectric layer 114 may include a silicon oxide layer (SiO2). x For example, SiO2), undoped silicate glass layers, silicon oxynitride (SiON) layers and / or other types of dielectric layers.

[0034] FIG. 1B Drawing along FIG. 1A A cross-sectional view of the semiconductor photonic device 100 along the AA line in the x-direction. Therefore, FIG. 1B The cross-sectional view of the semiconductor photonic device 100 is located along the dielectric waveguide structure 110 and along the semiconductor waveguide structure 106. For example... FIG. 1B As shown, one end of the semiconductor waveguide structure 106 may face one end of the dielectric waveguide structure 110. The end of the dielectric waveguide structure 110 facing the semiconductor waveguide structure 106 may be located on a portion of the semiconductor waveguide structure 106 and may overlap with it. The overlapping region between the dielectric waveguide structure 110 and the semiconductor waveguide structure 106 may be a transition region between the dielectric waveguide structure 110 and the semiconductor waveguide structure 106.

[0035] like FIG. 1B As further shown, the semiconductor waveguide structure 106 and the dielectric waveguide structure 110 may be perpendicularly spaced by a certain distance in the z-direction (in FIG. 1B (The dimension is indicated as D1). In some embodiments, the vertical (z-direction) distance between the semiconductor waveguide structure 106 and the dielectric waveguide structure 110 is in the range of about 50 nanometers to about 400 nanometers. However, other values ​​and ranges of the vertical (z-direction) distance between the semiconductor waveguide structure 106 and the dielectric waveguide structure 110 are also within the scope of this disclosure.

[0036] like FIG. 1B As further shown, the dielectric waveguide structure 110 may have a dimension D2 corresponding to the z-direction thickness of the dielectric waveguide structure 110. In some embodiments, the z-direction thickness of the dielectric waveguide structure 110 is contained in the range of about 300 nanometers to about 600 nanometers to achieve sufficient confinement and low loss of optical signals in the dielectric waveguide structure 110, depending on the wavelength of the optical signal and / or other parameters of the dielectric waveguide structure 110, such as material and refractive index. However, other values ​​and ranges of the z-direction thickness of the dielectric waveguide structure 110 are also within the scope of this disclosure.

[0037] As mentioned above, providing FIG. 1A and 1BAs an example. Other examples can differ FIG. 1A and 1B as described with respect to

[0038] FIG. 2A to FIG. 2F FIG. 1 1 1 is a diagram of an example embodiment 200 to form a dielectric waveguide structure 1 10 described herein. In the example embodiment 200, the dielectric waveguide structure 1 10 is pre-formed on a carrier substrate, such that the dielectric waveguide structure 1 10 can be subsequently bonded to a semiconductor photonic device 100 after formation.

[0039] As shown in FIG. 1 12, a carrier substrate 202 can be provided. The carrier substrate 202 can be provided in the form of a semiconductor wafer (e.g., a silicon (Si) wafer) and / or another type of semiconductor workpiece. FIG. 2A As shown in FIG. 1 13, a first portion of the dielectric layer 108 can be formed on the carrier substrate 202. The first portion of the dielectric layer 108 can be deposited using a deposition tool via a physical vapor deposition (PVD) technique, an atomic layer deposition (ALD) technique, a chemical vapor deposition (CVD) technique, an oxidation technique, and / or another suitable deposition technique. The first portion of the dielectric layer 108 can be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., a chemical mechanical planarization (CMP) operation) after the first portion of the dielectric layer 108 is deposited to planarize the first portion of the dielectric layer 108.

[0040] FIG. 2B As shown in FIG. 1 14, a dielectric layer 204 can be formed on the first portion of the dielectric layer 108. The dielectric layer 204 can be the dielectric layer that forms the dielectric waveguide structure 1 10. Accordingly, the dielectric layer 204 can include one or more high dielectric materials, such as silicon nitride (Si x N y , for example, Si3N4). Additionally and / or alternatively, the dielectric layer 204 can include another type of dielectric material, such as an aluminum oxide material (Al x O y , for example, Al2O3), an aluminum nitride material (AIN), a hafnium oxide material (HfO x , for example, HfO2), a titanium oxide material (TiO x , for example, TiO2), a zinc oxide material (ZnO), and / or a germanium oxide material (GeO x , for example, GeO2), lithium niobate (LiNbO3), and / or other examples. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., a chemical mechanical planarization operation) after the first portion of the dielectric layer 204 is deposited to planarize the first portion of the dielectric layer 204.

[0041] As shown in FIG. 1 15, a second portion of the dielectric layer 108 can be formed on the dielectric layer 204. The second portion of the dielectric layer 108 can be deposited using a deposition tool via a physical vapor deposition (PVD) technique, an atomic layer deposition (ALD) technique, a chemical vapor deposition (CVD) technique, an oxidation technique, and / or another suitable deposition technique. The second portion of the dielectric layer 108 can be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., a chemical mechanical planarization (CMP) operation) after the second portion of the dielectric layer 108 is deposited to planarize the second portion of the dielectric layer 108. FIG. 2C As shown in FIG. 1 16, a third portion of the dielectric layer 108 can be formed on the second portion of the dielectric layer 108. The third portion of the dielectric layer 108 can be deposited using a deposition tool via a physical vapor deposition (PVD) technique, an atomic layer deposition (ALD) technique, a chemical vapor deposition (CVD) technique, an oxidation technique, and / or another suitable deposition technique. The third portion of the dielectric layer 108 can be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., a chemical mechanical planarization (CMP) operation) after the third portion of the dielectric layer 108 is deposited to planarize the third portion of the dielectric layer 108.

[0042] ​The dielectric layer 204 can be formed using high temperature process techniques to ensure that the dielectric layer 204 formed contains little to no hydrogen. In some embodiments, the dielectric layer 204 can be deposited using a deposition tool via a high temperature deposition technique, such as low pressure chemical vapor deposition (LPCVD) with or without a post-deposition anneal operation, such that the material of the dielectric layer 204 is deposited at a temperature range of about 700 degrees Celsius to about 900 degrees Celsius. In some embodiments, the material of the dielectric layer 204 is deposited at a temperature greater than about 900 degrees Celsius. Depositing the material of the dielectric layer 204 at high temperatures can drive out hydrogen in the dielectric layer 204 and prevent or inhibit the formation of silicon-hydrogen bonds and / or nitrogen-hydrogen bonds in the dielectric layer 204. If the material of the dielectric layer 204 is deposited at too low of a temperature (e.g., less than about 900 degrees Celsius, less than about 700 degrees Celsius), the hydrogen concentration in the dielectric layer 204 can be high, resulting in reduced optical performance of the dielectric waveguide structure 110. However, other deposition temperature values for the material of the dielectric layer 204 are included within the scope of the present disclosure.

[0043] In some embodiments, the dielectric layer 204 can be deposited using a deposition tool via a plasma enhanced chemical vapor deposition (PECVD) technique, and an anneal operation can be performed on the dielectric layer 204 after (or during) deposition of the dielectric layer 204 using an anneal tool. In some embodiments, a high temperature deposition technique, such as low pressure chemical vapor deposition, is used in combination with an anneal operation.

[0044] The anneal operation can include a nitrogen (N2) anneal or nitrogen treatment operation to reduce the hydrogen concentration in the dielectric layer 204. The anneal operation can break the silicon-hydrogen (Si-H) bonds and / or nitrogen-hydrogen (N-H) bonds in the dielectric layer 204, thereby reducing the hydrogen content and concentration in the dielectric layer 204. The anneal operation can include a rapid thermal annealing (RTA) operation, a furnace annealing operation, and / or other types of anneal operations. In some embodiments, the anneal operation is performed at a temperature greater than or equal to about 900 degrees Celsius. In some embodiments, the anneal operation is performed at a temperature greater than or equal to about 1150 degrees Celsius. If the anneal operation is performed at a temperature less than about 900 degrees Celsius, the hydrogen concentration in the dielectric layer 204 can be high, resulting in reduced optical performance of the dielectric waveguide structure 110. However, other temperature values for the anneal operation are included within the scope of the present disclosure.

[0045] In some embodiments, the anneal operation is performed for at least one hour. In some embodiments, the anneal operation is performed for a time duration in a range of about 60 minutes to about 180 minutes. The longer the time duration, the more hydrogen can be driven out of the dielectric layer 204. However, other time duration values for the anneal operation are included within the scope of the present disclosure.

[0046] In some embodiments, the annealing operation is performed before the dielectric layer 204 is etched to define the dielectric waveguide structure 110. Alternatively, the dielectric layer 204 may be deposited and etched first (e.g., FIG. 2D The dielectric waveguide structure 110 is formed by etching the dielectric layer 204 to define the dielectric waveguide structure 110, and then an annealing operation is performed on the dielectric waveguide structure 110.

[0047] like FIG. 2D As shown, an etchable dielectric layer 204 defines a dielectric waveguide structure 110. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 204 to define the dielectric waveguide structure 110. In these embodiments, a photoresist layer can be formed on the dielectric layer 204 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the dielectric layer 204 based on the pattern to form the dielectric waveguide structure 110. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard photomask layer is used as an alternative to the pattern-based etching dielectric layer 204.

[0048] like FIG. 2E As shown, a second portion of a dielectric layer 108 can be formed on the dielectric waveguide structure 110, such that the dielectric waveguide structure 110 is encapsulated within the dielectric layer 108. The second portion of the dielectric layer 108 can be formed after or before annealing the dielectric waveguide structure 110. The second portion of the dielectric layer 108 can be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The second portion of the dielectric layer 108 can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) can be performed on the second portion of the dielectric layer 108 after deposition using a planarization tool to planarize the second portion of the dielectric layer 108.

[0049] like FIG. 2FAs shown, an alignment mark 206 can be formed in the dielectric layer 108. The alignment mark 206 can include a patterned structure to facilitate aligning the dielectric layer 108 to the dielectric layer 104 of the semiconductor photonic device 100 for bonding. In some embodiments, the alignment mark 206 includes a plurality of wires. In some embodiments, the alignment mark 206 includes a plurality of concentric rings. In some embodiments, the alignment mark 206 includes other arrangements of structures. The alignment mark 206 can include one or more dielectric materials, one or more metallic materials, and / or combinations thereof, among other examples.

[0050] In some embodiments, the alignment mark 206 is formed by forming one or more recesses in the dielectric layer 108 and depositing a material of the alignment mark 206 in the one or more recesses. In some embodiments, one or more portions of the dielectric layer 108 can be doped with one or more types of dopants to form the alignment mark 206. In some embodiments, other semiconductor processing techniques can be used to form the alignment mark 206.

[0051] As described above, FIG. 2A to FIG. 2F are provided by way of example only. Other examples can differ from those described. FIG. 2A to FIG. 2F without departing from the spirit of the disclosure.

[0052] FIG. 3A to FIG. 3H is a schematic diagram of an example embodiment 300 of forming the semiconductor photonic device 100 described herein. In particular, the example embodiment 300 includes an example of bonding the dielectric waveguide structure 110 to the semiconductor photonic device 100 after forming the dielectric waveguide structure 110 (e.g., by performing the process flow in FIG. 2A to FIG. 2F This limits exposure of the semiconductor photonic components of the semiconductor photonic device 100 to high temperatures that can damage and / or degrade performance of the semiconductor photonic components.

[0053] As FIG. 3AAs shown, a substrate 302 may be provided for a semiconductor photonic device 100. The substrate 302 may include a silicon-on-insulator (SOI) substrate comprising a substrate layer 102 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a portion of a dielectric layer 104 (e.g., a buried oxide (BOX) layer and / or another type of insulating layer) over the substrate layer 102, and a semiconductor layer 304 (e.g., a silicon (Si) layer and / or another type of semiconductor layer) over the portion of the dielectric layer 104. Alternatively, the substrate layer 102 may be provided as a semiconductor wafer, and a portion of the dielectric layer 104 may be formed over the substrate layer 102 using deposition tools, and the semiconductor layer 304 may be formed over the portion of the dielectric layer 104. The portion of the dielectric layer 104 may be deposited using chemical vapor deposition, physical vapor deposition, oxidation techniques (e.g., thermal oxidation), and / or another type of deposition technique. Semiconductor layer 304 can be formed using deposition tools via epitaxial technology and / or another type of deposition technology.

[0054] like FIG. 3B As shown, a semiconductor waveguide structure 106 can be formed from the semiconductor layer 304 over the dielectric layer 104. In some embodiments, in addition to the semiconductor waveguide structure 106, other semiconductor photonic components are formed from the semiconductor layer 304. In some embodiments, a hard photomask layer can be formed over the semiconductor layer 304, and a pattern in the hard photomask layer can be used to etch the semiconductor layer 304 to form the semiconductor waveguide structure 106. The hard photomask layer can be deposited on the semiconductor layer 304 using deposition tools (e.g., using chemical vapor deposition, physical vapor deposition, and / or another type of deposition technique) and a photoresist layer can be deposited on the hard photomask layer (e.g., using spin coating and / or another type of deposition technique). The hard photomask layer may include silicon nitride (Si). x N y Materials such as Si3N4 or another hard photomask material. The photoresist layer may include a photosensitive material that can be patterned using exposure tools such as deep ultraviolet (DUV) lithography tools and / or extreme ultraviolet (EUV) lithography tools.

[0055] The photoresist layer can be exposed to a radiation source using an exposure tool to form a pattern in the photoresist layer. Portions of the photoresist layer can be developed and removed using a development tool to expose the pattern. The hard photomask layer can be etched using an etching tool to transfer the pattern from the photoresist layer to the hard photomask layer. The semiconductor layer 304 can then be etched based on the pattern in the hard photomask layer using the etching tool to remove material from the semiconductor layer 304 to form the semiconductor waveguide structure 106. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool removes remaining portions of the photoresist layer (e.g., using a chemical stripper, a plasma ashing, and / or another technique).

[0056] As shown in FIG. 3C additional material of the dielectric layer 104 can be deposited around and / or over the semiconductor waveguide structure 106 such that the semiconductor waveguide structure 106 is encapsulated in the dielectric layer 104. The additional material of the dielectric layer 104 can be deposited using a deposition tool using a chemical vapor deposition technique, a physical vapor deposition technique, an oxidation technique, and / or another type of deposition technique. In some embodiments, after the additional material of the dielectric layer 104 is deposited, a planarization operation (e.g., a chemical mechanical planarization operation) is performed using a planarization tool to planarize the dielectric layer 104.

[0057] As shown in FIG. 3D An alignment mark 306 can be formed in the dielectric layer 104. The alignment mark 306 can include a patterned structure that facilitates aligning the dielectric layer 108 of the semiconductor photonic device 100 to the dielectric layer 104 for bonding. In some embodiments, the alignment mark 306 includes a plurality of wires. In some embodiments, the alignment mark 306 includes a plurality of concentric rings. In some embodiments, the alignment mark 306 includes other arrangements of structures. The alignment mark 306 can include one or more dielectric materials, one or more metallic materials, and / or combinations thereof, among others.

[0058] In some embodiments, the alignment mark 306 is formed by forming one or more recesses in the dielectric layer 104 and depositing a material of the alignment mark 306 in the one or more recesses. In some embodiments, one or more portions of the dielectric layer 104 can be doped with one or more types of dopants to form the alignment mark 206. In some embodiments, the alignment mark 306 can be formed using other semiconductor process techniques.

[0059] As shown in FIG. 3E and 3FAs shown, after forming the semiconductor waveguide structure 106, a dielectric waveguide structure 110 (e.g., a pre-formed dielectric waveguide structure 110) can be bonded to the semiconductor photonic device 100. A bonding tool can be used to directly dielectric-to-dielectric bond the dielectric layer 108 to the dielectric layer 104 to bond the dielectric waveguide structure 110 to the semiconductor photonic device 100. The dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 at least partially overlaps with the semiconductor waveguide structure 106. Alternatively, the dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 and the semiconductor waveguide structure 106 do not overlap in the semiconductor photonic device 100.

[0060] To bond dielectric layers 104 and 108, alignment marks 206 in dielectric layer 108 and alignment marks 306 in dielectric layer 104 can be used to align dielectric layers 104 and 108 for bonding. This allows for achieving a particular overlay (OVL) tolerance to align dielectric waveguide structure 110 and semiconductor waveguide structure 106. After aligning dielectric layers 104 and 108 using alignment marks 206 and 306, dielectric layers 104 and 108 can be bonded.

[0061] like FIG. 3G As shown, after the dielectric layers 104 and 108 are bonded together, the carrier substrate 202 can be removed from the semiconductor photonic device 100. In some embodiments, the material to be removed from the carrier substrate 202 is etched by performing one or more etching operations. In some embodiments, a wafer grinding tool can be used to perform a wafer grinding operation to remove the carrier substrate 202. In some embodiments, a planarization tool can be used to perform a CMP operation to remove the carrier substrate 202.

[0062] like FIG. 3H As shown, after removing the carrier substrate 202, a dielectric layer 114 may be formed over and / or on the dielectric layer 108. The dielectric layer 114 may be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The dielectric layer 114 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) may be performed after the deposition of the dielectric layer 114 using planarization tools to planarize the dielectric layer 114.

[0063] As mentioned above, providing FIG. 3A to FIG. 3H As an example. Other examples may be related to... FIG. 3A to FIG. 3H The descriptions are different.

[0064] FIG. 4 is an example diagram of a semiconductor photonic device 400 described herein. The semiconductor photonic device 400 can include a photonic integrated circuit that includes a similar arrangement of structures and layers as the semiconductor photonic device 100, such as the semiconductor waveguide structure 106 and the dielectric waveguide structure 110 positioned above the semiconductor waveguide structure 106. As FIG. 4 Further shown, the semiconductor photonic device 400 includes one or more additional semiconductor photonic components, such as an optical modulator structure 402. The optical modulator structure 402 can be formed from the same semiconductor layers as the semiconductor waveguide structure 106.

[0065] The optical modulator structure 402 can be positioned next to the semiconductor waveguide structure 106 in the y-direction in the semiconductor photonic device 400. The optical modulator structure 402 can include a micro-ring modulator (MRM), a Mach-Zender modulator (MZM), and / or other types of optical modulators that include a semiconductor waveguide structure electrically coupled to a set of electrical contacts. The optical modulator structure 402 can be configured to encode data onto an input optical signal 404 for optical communication.

[0066] The input optical signal 404 can be transmitted from the dielectric waveguide structure 110 to the semiconductor waveguide structure 106 and from the semiconductor waveguide structure 106 to the optical modulator structure 402. The dielectric waveguide structure 110 can receive the input optical signal 404 from an input optical fiber 406 or other type of external optical connection. The input optical fiber 406 can be positioned on a side of the semiconductor photonic device 100 (e.g., as shown in the example of FIG. 4 ), can be positioned on top of the semiconductor photonic device 400, and / or can be positioned in other locations.

[0067] The optical modulator structure 402 can modulate the input optical signal 404 based on an input electrical signal 408 to produce a modulated optical signal 410. The optical modulator structure 402 can modulate an amplitude of the input optical signal 404, a phase of the input optical signal 404, a frequency of the input optical signal 404, and / or other characteristics of the input optical signal 404 based on the input electrical signal 408. The optical modulator structure 402 can include a P-N junction formed from different doped regions of a semiconductor material. The semiconductor material can include silicon (Si), germanium (Ge), silicon germanium (SiGe), and / or other semiconductor materials. The semiconductor material can be doped with p-type dopants to form one or more p-type regions and can be doped with n-type dopants to form one or more n-type regions, thereby forming the P-N junction. The p-type dopants can include p-type ions of p-type materials (e.g., boron (B) or germanium (Ge), among others). The n-type dopants can include n-type ions of n-type materials (e.g., phosphorus (P) or arsenic (As), among others).

[0068] The input electrical signal 408 can be applied to the optical modulator structure 402 through contacts 412 and / or 414 of the optical modulator structure 402. The contacts 412 and / or 414 can include one or more types of doped semiconductor material. The contacts 412 and 414 can each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other conductive materials.

[0069] When the input electrical signal 408 is applied to the P-N junction of the optical modulator structure 402, the junction depletion width of the P-N junction changes. This results in a change in electron and hole concentration within the optical modulator structure 402. The change in electron and hole concentration can result in a change in the effective refractive index of the optical modulator structure 402, which can modulate the input optical signal 404 (e.g., the phase and / or other characteristics of the input optical signal 404) to produce the modulated optical signal 410.

[0070] Alternatively, the optical modulator structure 402 can include a thermo-optic modulator that modulates the input optical signal 404 based on a change in temperature in the semiconductor waveguide structure of the optical modulator structure 402. In these embodiments, the contacts 412 and 414 of the optical modulator structure 402 can be coupled to a heater structure that generates heat and is provided to the semiconductor waveguide structure of the optical modulator structure 402.

[0071] A contact etch stop layer (CESL) 416 can be included in the dielectric layer 104. The contact etch stop layer 416 can be located above the optical modulator structure 402, as well as above the contacts 412 and 414 of the optical modulator structure 402. The contact etch stop layer 416 is included to facilitate the precise formation of recesses for the contacts 412 and 414. In particular, the contact etch stop layer 416 can include one or more dielectric materials to provide etch selectivity with respect to the dielectric layers 104 and 108, such that the dielectric layers 104 and 108 can be etched and the contact etch stop layer 416 can be stopped upon during the formation of the recesses (which can prevent etching into the optical modulator structure 402). The contact etch stop layer 416 can include silicon nitride (Si x N y such as Si3N4), silicon oxynitride (SiON), aluminum oxide (AI x O y such as AI2O3), and / or other suitable materials.

[0072] Metal silicide layers 418 and 420 can be included between the optical modulator structure 402 and the contacts 412 and 414, respectively. The metal silicide layers 418 and 420 can each include titanium silicide (TiSi), ruthenium silicide (RuSi), and / or other types of metal silicide materials. The metal silicide layers 418 and 420 provide a transition between the semiconductor material of the optical modulator structure 402 and the contacts 412 and 414, enabling low contact resistance between the optical modulator structure 402 and the contacts 412 and 414.

[0073] As described herein, forming (e.g., pre-forming) the dielectric waveguide structure 110 in the dielectric layer 108 and incorporating the dielectric waveguide structure 110 after forming the semiconductor photonic component (e.g., the optical modulator structure 402) can prevent, minimize, and / or reduce the likelihood of causing damage and / or degradation to the semiconductor photonic component (e.g., the optical modulator structure 402). If the dielectric waveguide structure 110 is formed directly on the semiconductor photonic device 400 after the metal silicide layers 418 and 420 of the optical modulator structure 402 are formed, and if high temperature process techniques (e.g., low pressure chemical vapor deposition and / or annealing) are used to form the dielectric waveguide structure 110, these high temperature process techniques can cause damage to the metal silicide layers 418 and 420. For example, the high temperature process techniques used to form the dielectric waveguide structure 110 can cause the metal atoms of the metal layer to further (unwanted) diffuse into the semiconductor structure of the optical modulator structure 402, thereby negatively altering the electrical properties of the optical modulator structure 402 and / or increasing the contact resistance of the optical modulator structure 402. Pre-forming the dielectric waveguide structure 110 in the dielectric layer 108 before incorporating the dielectric waveguide structure 110 to the semiconductor photonic device 400 enables the use of high temperature process techniques to form the dielectric waveguide structure 110, as the dielectric waveguide structure 110 is formed on a substrate that is separate from the metal silicide layers 418 420 and other temperature sensitive structures.

[0074] The interconnect layer 422 can be included above the dielectric layer 108. The interconnect layer 422 can include a back end region or a back end of line (BEOL) region of the semiconductor photonic device 400. The interconnect layer 422 can include one or more dielectric layers 114 and one or more metallization layers 424 in the one or more dielectric layers 114. The contacts 412 and 414 can be electrically and / or physically coupled with one or more metallization layers 424 in the one or more dielectric layers 114 of the interconnect layer 422. The input electrical signal 408 can be provided to the optical modulator structure 402 through the metallization layers 424. The metallization layers 424 correspond to circuitry that enables signals and / or power to be provided to and / or received from the optical modulator structure 402 and / or other devices in the semiconductor photonic device 400. The metallization layers 424 can each include one or more electrically conductive materials such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), among other examples of electrically conductive materials. The metallization layers 424 can each include vias, trenches, contact plugs, electrically conductive pads, electrically conductive pillars, and / or other types of metallization layers.

[0075] As described above, FIG. 4 are provided by way of example. Other examples can differ FIG. 4 from the examples described.

[0076] FIG. 5A to FIG. 5K is a schematic diagram of an example embodiment 500 of forming the semiconductor photonic device 400 described herein. In particular, the example embodiment 500 includes an example of bonding the dielectric waveguide structure 110 to the semiconductor photonic device 400 after the dielectric waveguide structure 110 and the optical modulator structure 402 are formed. This limits exposure of the semiconductor photonic assembly (and associated metal silicide layers 418 and 420) of the semiconductor photonic device 400 to high temperatures that can damage and / or degrade performance of the semiconductor photonic assembly.

[0077] As FIG. 5A shown, a substrate 502 of the semiconductor photonic device 400 can be provided. The substrate 502 can include a silicon-on-insulator (SOI) substrate including a substrate layer 102 (e.g., a silicon (Si) substrate and / or other type of semiconductor substrate), a partial dielectric layer 104 (e.g., a buried oxide (BOX) layer and / or other type of insulating layer) above and / or on the substrate layer 102, and a semiconductor layer 504 (e.g., a silicon (Si) layer and / or other type of semiconductor layer) above and / or on the partial dielectric layer 104.

[0078] As FIG. 5BAs shown, a semiconductor waveguide structure 106 and an optical modulator structure 402 can be formed from a semiconductor layer 504 above a dielectric layer 104. In some embodiments, a hard mask layer can be formed on and / or on the semiconductor layer 504, and a pattern in the hard mask layer can be used to etch the semiconductor layer 504 to form the semiconductor waveguide structure 106 and the optical modulator structure 402. A hard mask layer can be deposited on the semiconductor layer 504 using deposition tools (e.g., using chemical vapor deposition, physical vapor deposition, and / or other types of deposition techniques) and a photoresist layer can be deposited on the hard mask layer (e.g., using spin coating and / or other types of deposition techniques). The hard mask layer may comprise silicon nitride (Si). x N y Materials such as Si3N4 or other hard mask materials. The photoresist layer may contain photosensitive materials that can be patterned using exposure tools (such as deep ultraviolet lithography tools and / or extreme ultraviolet lithography tools).

[0079] An exposure tool can be used to expose a photoresist layer to a radiation source to form a pattern in the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch a hard mask layer to transfer the pattern from the photoresist layer to the hard mask layer. The semiconductor layer 504 can then be etched based on the pattern in the hard mask layer using an etching tool to remove material from the semiconductor layer 504 to form the semiconductor waveguide structure 106 and the optical modulator structure 402. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool removes the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0080] like FIG. 5C As shown, additional material can be deposited around and / or over the semiconductor waveguide structure 106 and the optical modulator structure 402, such that the semiconductor waveguide structure 106 and the optical modulator structure 402 are encapsulated within the dielectric layer 104. The additional material of the dielectric layer 104 can be deposited using chemical vapor deposition, physical vapor deposition, oxidation techniques, and / or other types of deposition techniques using deposition tools. In some embodiments, after depositing the additional material of the dielectric layer 104, a planarization operation (e.g., a chemical mechanical planarization operation) is performed using a planarization tool to planarize the dielectric layer 104.

[0081] like FIG. 5DAs shown, recesses 506 and 508 may be formed over portions of the light modulator structure 402, such that portions of the light modulator structure 402 are exposed through recesses 506 and 508. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 104 to form recesses 506 and 508. In these embodiments, a photoresist layer may be formed on the dielectric layer 104 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer 104 based on the pattern to form recesses 506 and 508. In some embodiments, the etching operations include dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer may be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based recesses 506 and 508.

[0082] like FIG. 5E As shown, metal silicide layers 418 and 420 are formed on the exposed portions of the light modulator structure 402 in recesses 506 and 508, respectively. Metal layers can be formed on the exposed portions of the light modulator structure 402 in recesses 506 and 508 using a deposition tool. An annealing operation can be performed using a deposition tool or an annealing tool to achieve self-aligned silicideing of the metal layers and the semiconductor material of the light modulator structure 402, thereby forming metal silicide layers 418 and 420. Self-aligned silicideing may include diffusion of the metal layer into the surface of the exposed portion of the light modulator structure 402.

[0083] like FIG. 5F As shown, a contact etch stop layer 416 is formed on the dielectric layer 104 and in the recesses 506 and 508. Therefore, the contact etch stop layer 416 is formed on the metal silicide layers 418 and 420. The contact etch stop layer 416 protects the metal silicide layers 418 and 420 from oxidation and contamination during subsequent process operations. The contact etch stop layer 416 can be deposited using chemical vapor deposition, physical vapor deposition, oxidation techniques, and / or other types of deposition techniques.

[0084] like FIG. 5GAs shown, additional material for the dielectric layer 104 may be deposited on the contact etch stop layer 416 and in the recesses 506 and 508. The additional material for the dielectric layer 104 may be deposited using chemical vapor deposition, physical vapor deposition, oxidation techniques, and / or other types of deposition techniques using deposition tools. In some embodiments, after depositing the additional material for the dielectric layer 104, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize the dielectric layer 104.

[0085] like FIG. 5H As shown, after forming the semiconductor waveguide structure 106 and the optical modulator structure 402, the dielectric waveguide structure 110 (e.g., a pre-formed dielectric waveguide structure 110) can be bonded to the semiconductor photonic device 100. The dielectric layer 108 can be directly bonded to the dielectric layer 104 using a bonding tool to bond the dielectric waveguide structure 110 to the semiconductor photonic device 100. The dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 at least partially overlaps with the semiconductor waveguide structure 106. Alternatively, the dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 and the semiconductor waveguide structure 106 do not overlap in the semiconductor photonic device 100.

[0086] In some embodiments, alignment marks 206 in dielectric layer 108 and alignment marks 306 in dielectric layer 104 can be used to align dielectric layers 104 and 108 for bonding. In some embodiments, after dielectric layers 104 and 108 are bonded together, the carrier substrate 202 is removed from the semiconductor photonic device 400.

[0087] Since the contact etch stop layer 416 is formed on the semiconductor photonic device 400 after the formation of the semiconductor waveguide structure 106, the optical modulator structure 402, and the metal silicide layers 418 and 420, the formation of the contact etch stop layer 416 may be limited to low-temperature (or lower-temperature) process techniques, such as plasma-enhanced chemical vapor deposition. Therefore, the contact etch stop layer 416 may have a higher hydrogen concentration than the dielectric waveguide structure 110 because the pre-formation of the dielectric waveguide structure 110 on a separate substrate allows the use of high-temperature process techniques, such as low-pressure chemical vapor deposition and annealing, to achieve a low hydrogen concentration in the dielectric waveguide structure 110.

[0088] like FIG. 5I As shown, recesses 510 and 512 can be formed on metal silicide layers 418 and 420 on the optical modulator structure 402, respectively. Recesses 510 and 512 can be formed through dielectric layer 108 and extend into dielectric layer 104. Recesses 510 and 512 can also be formed through contact etch stop layer 416.

[0089] In some embodiments, patterns in the photoresist layer are used to etch dielectric layers 104 and 108 and contact etch stop layer 416 to form recesses 510 and 512. In these embodiments, a photoresist layer can be formed on dielectric layer 108 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch dielectric layers 104, 108, and contact etch stop layer 416 based on the pattern to form recesses 510 and 512. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique to pattern-forming recesses 510 and 512.

[0090] As mentioned above FIG. 1A and 1B The dielectric layer 104 may have a first etching rate for the etchant used to etch the dielectric layers 104 and 108 to form the recesses 510 and 512 (e.g., for silicon dioxide etchants such as hydrofluoric acid (HF) or diluted hydrofluoric acid (DHF)), while the dielectric layer 108 may have a second etching rate for that etchant. The first etching rate of the dielectric layer 104 may be greater than the second etching rate of the dielectric layer 108 because the dielectric layer 108 undergoes high-temperature processing operations during the formation of the dielectric waveguide structure 110.

[0091] like FIG. 5J As shown, contact 412 may be formed in recess 510, and contact 414 may be formed in recess 512. Contacts 412 and 414 may pass through dielectric layer 108, through contact etch stop layer 416, and extend into dielectric layer 104. Contact 412 may be formed on metal silicide layer 418, and contact 414 may be formed on metal silicide layer 420.

[0092] Contacts 412 and 414 can be deposited using deposition tools via chemical vapor deposition, physical vapor deposition, atomic layer deposition, electroplating, and / or other suitable deposition techniques. Contacts 412 and 414 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and then contacts 412 and 414 are deposited on the seed layer. In some embodiments, a planarization operation (e.g., chemical mechanical planarization) is performed on contacts 412 and 414 after deposition using a planarization tool to planarize contacts 412 and 414.

[0093] like FIG. 5K As shown, the dielectric layer 114 and metallization layer 424 of interconnect layer 422 may be formed on and / or on the dielectric layer 108 (e.g., after the formation of contacts 412 and 414). The dielectric layer 114 may be deposited using deposition tools via physical vapor deposition, atomic layer deposition, chemical vapor deposition, oxidation techniques, and / or other suitable deposition techniques. The metallization layer 424 may be deposited using physical vapor deposition, atomic layer deposition, chemical vapor deposition, electroplating techniques, and / or other suitable deposition techniques.

[0094] In some embodiments, the dielectric layer 114 and the metallization layer 424 of the interconnect layer 422 are formed sequentially. For example, a first dielectric layer 114 may be formed, a recess may be formed in the first dielectric layer 114, and a first metallization layer 424 may be formed in the recess of the first dielectric layer 114. A second dielectric layer 114 may be formed on the first dielectric layer 114, a recess may be formed in the second dielectric layer 114, and a second metallization layer 424 may be formed in the recess of the second dielectric layer 114. Additional dielectric layers 114 and metallization layers 424 may be formed in a similar manner.

[0095] As mentioned above, FIG. 5A to FIG. 5K This is provided as an example. Other examples may be related to... FIG. 5A to FIG. 5K The descriptions are different.

[0096] FIG. 6 This is an example diagram of the semiconductor photonic device 600 described herein. The semiconductor photonic device 600 may include a photonic integrated circuit having a structure and layer arrangement similar to that of the semiconductor photonic device 400, such as a semiconductor waveguide structure 106 and a dielectric waveguide structure 110 situated above the semiconductor waveguide structure 106. However, the semiconductor photonic device 600 includes a photodetector structure 602, instead of (or except for) the optical modulator structure 402. A portion of the photodetector structure 602 may be formed from the same semiconductor layers as the semiconductor waveguide structure 106.

[0097] The photodetector structure 602 includes a semiconductor photonic component configured to generate an electrical current, voltage, and / or other type of output electrical signal based on photons absorbed from an input optical signal. The photodetector structure 602 can include an absorption region 604 that converts photons to electrons, and contact pads 606 and 608 that correspond to collection regions of the electrons generated by the absorption region 604.

[0098] The absorption region 604 can include an epitaxially grown region of semiconductor material that includes germanium (Ge), germanium tin (GeSn), silicon germanium (SiGe), indium gallium arsenide (InGaAs), and / or gallium arsenide (GaAs), among others. The absorption region 604 can be configured to absorb photons of an input optical signal 610. The input optical signal 610 can be received from the input optical fiber 406 and can be passed through the dielectric waveguide structure 110 and the semiconductor waveguide structure 106 to the absorption region 604 of the photodetector structure 602. The photons interact with electron-hole pairs in the absorption region 604. This interaction causes the electrons and holes to separate and migrate to opposing contact pads 606 and 608 (e.g., opposing collection regions), resulting in an electric field (e.g., a built-in electric field) that is provided to the contacts 412 and 414 as an output electrical signal 612. In some embodiments, the photodetector structure 602 includes a semiconductor waveguide structure coupled to the absorption region 604 to direct the input optical signal 610 toward the absorption region 604.

[0099] A metal silicide layer 418 can be included between the contact pad 412 and the contact pad 606 of the photodetector structure 602. A metal silicide layer 420 can be included between the contact pad 414 and the contact pad 608 of the photodetector structure 602. As described herein, forming (e.g., pre-forming) the dielectric waveguide structure 110 in the dielectric layer 108 and incorporating the dielectric waveguide structure 110 after forming a semiconductor photonic component such as the photodetector structure 602 can prevent, minimize, and / or reduce the likelihood of damage and / or degradation of the metal silicide layers 418 and 420. Further, forming (e.g., pre-forming) the dielectric waveguide structure 110 in the dielectric layer 108 and incorporating the dielectric waveguide structure 110 after forming a semiconductor photonic component such as the photodetector structure 602 can prevent, minimize, and / or reduce the likelihood of an increase in dark current in the absorption region 604 of the photodetector structure 602.

[0100] As shown above, FIG. 6 are provided as examples. Other examples can differ from what is described with respect to at least one of the following. FIG. 6

[0101] FIG. 7A to FIG. 7G ​This is a diagram of an exemplary embodiment 700 of the semiconductor photonic device 600 described herein. Specifically, exemplary embodiment 700 includes an example of incorporating the dielectric waveguide structure 110 into the semiconductor photonic device 600 after the formation of the dielectric waveguide structure 110 and the photodetector structure 602. This limits the exposure of the semiconductor photonic components of the semiconductor photonic device 600 (and the associated metal silicide layers 418 and 420) to high-temperature environments that could damage and / or degrade the performance of the semiconductor photonic components.

[0102] like FIG. 7A As shown, a portion of the semiconductor waveguide structure 106 and the photodetector structure 602 may be formed from a semiconductor layer (e.g., semiconductor layer 504 of substrate 502) above the dielectric layer 104. In some embodiments, a hard mask layer may be formed above and / or on the semiconductor layer, and a pattern in the hard mask layer may be used to etch the semiconductor layer to form portions of the semiconductor waveguide structure 106 and the photodetector structure 602. The hard mask layer may be deposited on the semiconductor layer using deposition tools (e.g., using chemical vapor deposition, physical vapor deposition, and / or other types of deposition techniques), and a photoresist layer may be deposited on the hard mask layer (e.g., using spin coating and / or other types of deposition techniques). The hard mask layer may include silicon nitride (Si). x N y Materials such as Si3N4 or other hard mask materials. The photoresist layer may include photosensitive materials that can be patterned using exposure tools such as deep ultraviolet lithography tools and / or extreme ultraviolet lithography tools.

[0103] An exposure tool can be used to expose a photoresist layer to a radiation source to form a pattern in the photoresist layer. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch a hard mask layer to transfer the pattern from the photoresist layer to the hard mask layer. The semiconductor layer can then be etched using the etching tool based on the pattern in the hard mask layer to remove material from the semiconductor layer to form portions of the semiconductor waveguide structure 106 and the photodetector structure 602. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or other types of etching operations. In some embodiments, a photoresist removal tool removes the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or other techniques).

[0104] like FIG. 7BAs shown, additional material can be deposited around and / or over portions of the semiconductor waveguide structure 106 and the photodetector structure 602, such that portions of the semiconductor waveguide structure 106 and the photodetector structure 602 are encapsulated within the dielectric layer 104. The additional material of the dielectric layer 104 can be deposited using deposition tools via chemical vapor deposition, physical vapor deposition, oxidation techniques, and / or other types of deposition techniques. In some embodiments, after depositing the additional material of the dielectric layer 104, a planarization operation (e.g., chemical mechanical planarization) is performed using a planarization tool to planarize the dielectric layer 104.

[0105] like FIG. 7C As shown, an absorption region 604 is formed in the photodetector structure 602. To form the absorption region 604, a portion of the photodetector structure 602 can be etched to form a recess, and the absorption region 604 can be formed in the recess. The absorption region 604 may define the terminals 606 and 608 of the photodetector structure 602.

[0106] In some embodiments, a pattern in the photoresist layer is used to etch portions of the photodetector structure 602 to form a recess. In these embodiments, a photoresist layer can be formed on the dielectric layer 104 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch portions of the dielectric layer 104 and the photodetector structure 602 based on the pattern to form a recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for forming recesses in portions of the photodetector structure 602 based on the pattern.

[0107] The absorption region 604 can be epitaxially grown in the depression using a deposition tool. Alternatively, another deposition technique can be used to form the absorption region 604.

[0108] like FIG. 7D As shown, metal silicide layers 418 and 420 are formed on terminals 606 and 608 of the photodetector structure 602, respectively. Furthermore, a contact etch stop layer 416 may be formed above the metal silicide layers 418 and 420 and above the photodetector structure 602. The metal silicide layers 418 and 420 and the contact etch stop layer 416 can be similar to... FIG. 5D to FIG. 5F It is formed in the manner described in [the document / document].

[0109] As FIG. 7D further shown, additional material of the dielectric layer 104 can be deposited on the contact etch stop layer 416 in a manner similar to that described in FIG. 5G

[0110] As FIG. 7E shown, after the semiconductor waveguide structure 106 and the photodetector structure 602 are formed, the dielectric waveguide structure 110 (e.g., a pre-formed dielectric waveguide structure 110) can be bonded to the semiconductor photonic device 100. The dielectric layer 108 can be directly dielectric-to-dielectric bonded to the dielectric layer 104 using a bonding tool to bond the dielectric waveguide structure 110 to the semiconductor photonic device 100. The dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 at least partially overlaps the semiconductor waveguide structure 106. Alternatively, the dielectric waveguide structure 110 can be bonded to the semiconductor photonic device 100 such that the dielectric waveguide structure 110 and the semiconductor waveguide structure 106 do not overlap in the semiconductor photonic device 100.

[0111] In some embodiments, the dielectric layer 104 and 108 can be aligned for bonding using the alignment marks 206 in the dielectric layer 108 and the alignment marks 306 in the dielectric layer 104. In some embodiments, after the dielectric layer 104 and 108 are bonded together, the carrier substrate 202 is removed from the semiconductor photonic device 400.

[0112] As FIG. 7F shown, contacts 412 can be formed on the metal silicide layer 418 and contacts 414 can be formed on the metal silicide layer 420. The contacts 412 and 414 can be formed in a manner similar to that described in FIG. 5I and 5J above.

[0113] As FIG. 7G shown, the dielectric layer 114 and the metallization layer 424 of the interconnect layer 422 can be formed over and / or on the dielectric layer 108 (e.g., after the contacts 412 and 414 are formed). The dielectric layer 114 and the metallization layer 424 of the interconnect layer 422 can be formed in a manner similar to that described in FIG. 5K above.

[0114] As described above, FIG. 7A to FIG. 7G the examples are provided as examples. Other examples can differ from what is described. FIG. 7A to FIG. 7G above.

[0115] FIG. 8 is a flowchart of an example process 800 related to forming a semiconductor photonic device described herein. In some embodiments, FIG. 8 ​One or more process blocks are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, bonding tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0116] like FIG. 8 As shown, process 800 may include forming one or more semiconductor photonic components in the semiconductor layer of a semiconductor photonic device (block 810). For example, one or more semiconductor photonic components (e.g., semiconductor waveguide structure 106, optical modulator structure 402, photodetector structure 602) may be formed in the semiconductor layer (e.g., semiconductor layer 304, semiconductor layer 504) of a semiconductor photonic device (e.g., semiconductor photonic device 100, semiconductor photonic device 400, semiconductor photonic device 600) using one or more semiconductor process tools, as described herein.

[0117] like FIG. 8 As further shown, process 800 may include bonding a dielectric layer to a semiconductor photonic device after forming one or more semiconductor photonic components (block 820). For example, a dielectric layer (e.g., dielectric layer 108) may be bonded to a semiconductor photonic device after forming one or more semiconductor photonic components using one or more semiconductor process tools, as described herein. In some embodiments, a dielectric waveguide structure (e.g., dielectric waveguide structure 110) is included in the dielectric layer.

[0118] Process 800 may include additional embodiments, such as any single embodiment or any combination of multiple embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0119] In a first embodiment, process 800 includes forming a dielectric waveguide structure in the dielectric layer using a low-pressure chemical vapor deposition technique prior to bonding the dielectric layer to a semiconductor photonic device.

[0120] In the second embodiment, separate from or in conjunction with the first embodiment, process 800 includes performing a nitrogen-based annealing operation on the dielectric waveguide structure before bonding the dielectric layer to the semiconductor photonic device.

[0121] In a third embodiment, separate from or in combination with one or more of the first and second embodiments, process 800 includes depositing a dielectric waveguide structure in a dielectric layer using plasma-enhanced chemical vapor deposition and performing an annealing operation on the dielectric waveguide structure prior to bonding the dielectric layer to a semiconductor photonic device.

[0122] In a fourth embodiment, separately or in combination with one or more of the first through third embodiments, the dielectric layer is a first dielectric layer, and the process 800 includes forming a second dielectric layer (e.g., the dielectric layer 104) over the one or more semiconductor photonic components, where bonding the dielectric layer to the semiconductor photonic device includes bonding the first dielectric layer to the second dielectric layer.

[0123] In a fifth embodiment, separately or in combination with one or more of the first through fourth embodiments, forming the one or more semiconductor photonic components includes forming an optical modulator structure (e.g., the optical modulator structure 402), and the process 800 includes forming a recess (e.g., the recess 510, the recess 512) through the first dielectric layer and the second dielectric layer to the optical modulator structure, where the first etch rate of the first dielectric layer and the second etch rate of the second dielectric layer are different etch rates, and forming a contact (e.g., the contact 418, the contact 420) of the optical modulator structure in the recess.

[0124] In a sixth embodiment, separately or in combination with one or more of the first through fifth embodiments, forming the one or more semiconductor photonic components includes forming a photodetector structure (e.g., the photodetector structure 602) prior to bonding the dielectric layer to the semiconductor photonic device, and the process 800 includes forming a contact (e.g., the contact 418, the contact 420) of the photodetector structure after bonding the dielectric layer to the semiconductor photonic device.

[0125] Although FIG. 8 An example block of the process 800 is shown, but in some embodiments, the process 800 includes additional blocks, fewer blocks, different blocks, or a different arrangement of blocks than those depicted in FIG. 8 Additionally or alternatively, two or more blocks of the process 800 can be performed in parallel.

[0126] FIG. 9 is a flow diagram of an example process 900 related to forming a semiconductor photonic device as described herein. In some embodiments, one or more process blocks of the process 900 are performed using one or more semiconductor process tools, such as a deposition tool, an exposure tool, a development tool, an etch tool, a planarization tool, an ion implantation tool, an anneal tool, a wafer / die transport tool, and / or other types of semiconductor process tools. FIG. 9

[0127] As shown, the process 900 can include forming a first portion of a first dielectric layer on a carrier substrate (block 910). For example, a first portion of a first dielectric layer (e.g., the dielectric layer 108) can be formed on a carrier substrate (e.g., the carrier substrate 202) using one or more semiconductor process tools, as described herein. FIG. 9 ​​

[0128] As FIG. 9 Further as shown in the

[0129] As FIG. 9 Further as shown in the

[0130] As FIG. 9 Further as shown in the

[0131] Process 900 can include additional embodiments, such as any single embodiment or combination of any embodiments described below and / or one or more other processes as described elsewhere herein.

[0132] In a first embodiment, forming the dielectric waveguide structure includes forming a third dielectric layer (e.g., dielectric layer 204) on the first portion of the first dielectric layer, planarizing the third dielectric layer, and etching the third dielectric layer to form the dielectric waveguide structure.

[0133] In a second embodiment, separately or in combination with the first embodiment, forming the dielectric waveguide structure includes forming the third dielectric layer using a low pressure chemical vapor deposition technique prior to bonding the dielectric layer to the semiconductor photonic device.

[0134] In a third embodiment, separately or in combination with one or more of the first and second embodiments, forming the dielectric waveguide structure includes performing a nitrogen-based anneal operation on the dielectric waveguide structure after etching the third dielectric layer.

[0135] In a fourth embodiment, separately or in combination with one or more of the first through third embodiments, the process 900 includes forming a first alignment mark (e.g., the alignment mark 206) in a first dielectric layer and forming a second alignment mark (e.g., the alignment mark 306) in a second dielectric layer, where bonding the first dielectric layer to the second dielectric layer includes using the first alignment mark and the second alignment mark to align the first dielectric layer and the second dielectric layer, and bonding the first dielectric layer to the second dielectric layer after aligning the first dielectric layer and the second dielectric layer using the first alignment mark and the second alignment mark.

[0136] In a fifth embodiment, separately or in combination with one or more of the first through fourth embodiments, forming the first alignment mark includes forming the first alignment mark after forming the dielectric waveguide structure.

[0137] In a sixth embodiment, separately or in combination with one or more of the first through fifth embodiments, the process 900 includes removing the carrier substrate after bonding the first dielectric layer to the second dielectric layer.

[0138] Although FIG. 9 While the example blocks of the process 900 are illustrated, in some embodiments, the process 900 includes more blocks, fewer blocks, different blocks, or differently arranged blocks than those shown in FIG. 8. Additionally or alternatively, two or more of the blocks of the process 900 can be performed in parallel. FIG. 9

[0139] As such, the dielectric waveguide structure of the semiconductor photonic device is formed on a separate substrate and then bonded to the semiconductor photonic device after forming the semiconductor photonic component of the semiconductor photonic device. The dielectric waveguide structure can be formed in a dielectric layer on a carrier substrate, and the dielectric layer can be used to bond the dielectric waveguide structure to a dielectric layer on the semiconductor photonic device. Because the dielectric waveguide structure is formed separately, high temperature process techniques can be used to form the dielectric waveguide structure without worrying about potential damage and / or performance degradation to the semiconductor photonic component that can occur if the dielectric waveguide structure is formed on top of the semiconductor photonic component.

[0140] As detailed above, some embodiments described herein provide a method of forming a semiconductor photonic device. The method includes forming one or more semiconductor photonic components in a semiconductor layer of the semiconductor photonic device. The method includes bonding a dielectric layer to the semiconductor photonic device after forming the one or more semiconductor photonic components, where a dielectric waveguide structure is included in the dielectric layer.

[0141] ​As detailed above, some embodiments described herein provide a method of forming a semiconductor photonic device. The method includes forming a first portion of a first dielectric layer on a carrier substrate. The method includes forming a dielectric waveguide structure on the first portion of the first dielectric layer. The method includes forming a second portion of the first dielectric layer on the dielectric waveguide structure such that the dielectric waveguide structure is encapsulated in the first dielectric layer. The method includes bonding the first dielectric layer to a second dielectric layer of the semiconductor photonic device such that the dielectric waveguide structure is positioned above one or more semiconductor photonic components in the second dielectric layer.

[0142] As detailed above, some embodiments described herein provide a semiconductor photonic device. The semiconductor photonic device includes a semiconductor layer. The semiconductor photonic device includes a first dielectric region above the semiconductor layer. The semiconductor photonic device includes a semiconductor waveguide structure in the first dielectric region. The semiconductor photonic device includes a second dielectric region vertically adjacent to the first dielectric region. The semiconductor photonic device includes a dielectric waveguide structure in the second dielectric region, wherein the first dielectric region has a first etch rate for an etchant, wherein the second dielectric region has a second etch rate for the etchant, and wherein the first etch rate is greater than the second etch rate.

[0143] The terms "approximately" and "substantially" can mean that a numerical value of a given quantity varies within a range of 5% of the numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the numerical value). These numerical values are merely examples and are not limiting. The terms "approximately" and "substantially" can refer to a percentage of a numerical value that is interpreted by one of ordinary skill in the art in light of the teachings herein.

[0144] The features of the above-described embodiments can be beneficial to one of ordinary skill in the art. One of ordinary skill in the art will understand that other processes and methods can be derived from the teachings herein without departing from the scope of the present disclosure. One of ordinary skill in the art will also understand that the equivalent substitutions and modifications can be made without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor photonic device, characterized in that, include: One or more semiconductor photonic components are formed in the semiconductor layer of a semiconductor photonic device; as well as After forming the one or more semiconductor photonic components, a dielectric layer is bonded to the semiconductor photonic device. The dielectric waveguide structure is contained within the dielectric layer.

2. The method according to claim 1, characterized in that, Further includes: Before incorporating the dielectric layer into the semiconductor photonic device, the dielectric waveguide structure is formed in the dielectric layer using low-pressure chemical vapor deposition.

3. The method as described in claim 2, characterized in that, Further includes: Before the dielectric layer is bonded to the semiconductor photonic device, the dielectric waveguide structure is subjected to a nitrogen-based annealing operation.

4. The method according to claim 1, characterized in that, Further includes: The dielectric waveguide structure is deposited in the dielectric layer using plasma-enhanced chemical vapor deposition. as well as Before the dielectric layer is bonded to the semiconductor photonic device, the dielectric waveguide structure is annealed.

5. The method according to claim 1, characterized in that, The dielectric layer thereunder is a first dielectric layer; The method further includes: Forming a second dielectric layer over the one or more semiconductor photonic components; and wherein bonding the dielectric layer to the semiconductor photonic device includes: The first dielectric layer is bonded to the second dielectric layer.

6. A method for forming a semiconductor photonic device, characterized in that, include: A first portion of a first dielectric layer is formed on a carrier substrate; A dielectric waveguide structure is formed on the first portion of the first dielectric layer; A second portion of the first dielectric layer is formed on the dielectric waveguide structure, such that the dielectric waveguide structure is encapsulated in the first dielectric layer. as well as The first dielectric layer is bonded to the second dielectric layer of the semiconductor photonic device, such that the dielectric waveguide structure is positioned on one or more semiconductor photonic components in the second dielectric layer.

7. The method according to claim 6, characterized in that, The dielectric waveguide structure includes: A third dielectric layer is formed on the first portion of the first dielectric layer; Planarize the third dielectric layer; and The third dielectric layer is etched to form the dielectric waveguide structure.

8. The method as described in claim 6, characterized in that, Further includes: A first alignment mark is formed in the first dielectric layer; as well as A second alignment mark is formed in the second dielectric layer. Wherein, bonding the first dielectric layer to the second dielectric layer includes: The first alignment mark and the second alignment mark are used to align the first dielectric layer and the second dielectric layer; and After aligning the first dielectric layer and the second dielectric layer using the first alignment mark and the second alignment mark, the first dielectric layer is bonded to the second dielectric layer.

9. A semiconductor photonic device, characterized in that, include: Semiconductor layer; A first dielectric region above the semiconductor layer; Semiconductor waveguide structure in the first dielectric region; A second dielectric region that is perpendicularly adjacent to the first dielectric region; as well as The dielectric waveguide structure in the second dielectric region, The first dielectric region has a first etching rate to the etchant. Wherein, the second dielectric region has a second etching rate for the etchant, and Wherein, the first etching rate is greater than the second etching rate.

10. The semiconductor photonic device according to claim 9, characterized in that, The dielectric waveguide structure includes: Silicon nitride (Si) x N y Waveguide; and The semiconductor photonic device further includes: The optical modulator structure in the first dielectric region; and In the first dielectric region, a silicon nitride contact etch stop layer is located above the optical modulator structure. The first hydrogen concentration in the silicon nitride contact etch stop layer is greater than the second hydrogen concentration in the silicon nitride waveguide.

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