Short circuit protection circuit and battery protection chip

Abstract

This invention provides a short-circuit protection circuit and a battery protection chip, belonging to the field of battery protection. It includes a battery, a control circuit, a first NMOS transistor, a drive circuit, and a short-circuit protection module. The power supply terminal of the control circuit is connected to a first power supply terminal. The power supply terminal of the drive circuit is also the power supply terminal of the control circuit. The first input terminal of the short-circuit protection module is connected to the output terminal of the drive circuit. The gate of the first NMOS transistor is connected to the output terminal of the short-circuit protection module, and the drain of the first NMOS transistor is connected to a second power supply terminal. The short-circuit protection module outputs a drive signal with a fixed slope to control the discharge current and voltage of the first NMOS transistor within a safe range. The positive terminal of the battery is connected to the first power supply terminal, and the source of the first NMOS transistor is connected to the negative terminal of the battery. The first and second power supply terminals are used to connect to a charger or load. The purpose is to solve the problem of insufficient safety performance of short-circuit protection circuits. The achieved technical effect is: effectively ensuring battery safety performance.

Description

Technical Field

[0001] This invention relates to the field of battery protection technology, and more particularly to a short-circuit protection circuit and a battery protection chip. Background Technology

[0002] Currently, chemical batteries have become the mainstream power solution for most mobile devices due to their advantages in energy density and portability. However, the material properties of chemical batteries mean they cannot withstand abnormal operating conditions such as overcharging, over-discharging, overcurrent, and short circuits during use. Among these, the hazards of short circuits are particularly prominent: when a short circuit occurs, the current in the circuit surges dramatically, causing a surge in instantaneous heat generation in the battery. This not only rapidly damages the battery structure and significantly shortens its lifespan, but can also trigger a chain reaction of failures such as wire overheating and melting, equipment burnout, and even directly induce fires, posing a serious threat to user property and personal safety. Therefore, configuring reliable short-circuit protection control circuits for chemical battery systems has become a critical aspect of ensuring the safe operation of mobile devices.

[0003] However, existing chemical batteries typically integrate battery protection chips for safety control, and their structure is as follows: Figure 7 As shown, the battery protection chip monitors the battery voltage and discharge current in real time, and outputs control signals based on the detection results to regulate the conduction or cutoff of the power transistors NM0 (discharge transistor) and NM1 (charge transistor), thereby ensuring that the battery operates within a safe range.

[0004] However, in practical applications, different application scenarios have different requirements for the internal resistance of the NMOS discharge tube, requiring the selection of different models of NMOS tubes. Not only do different models of NMOS tubes have different internal resistances, but also significantly different parasitic capacitances, which directly leads to large fluctuations in the switching speed and switching waveform of the NMOS discharge tube. Under short-circuit conditions, the circuit will experience a superposition of large current and high drain-source voltage. This fluctuation will further aggravate the electrical stress on the NMOS tube, i.e., the NMOS discharge tube, and have a significant impact on its safety performance. Summary of the Invention

[0005] This invention provides a short-circuit protection circuit and a battery protection chip to address the shortcomings of existing short-circuit protection circuits in ensuring safety performance, and to achieve a short-circuit protection circuit structure that effectively guarantees safety performance.

[0006] The first aspect of the present invention provides a short-circuit protection circuit, including a battery, a control circuit, a first NMOS transistor, a driving circuit, and a short-circuit protection module;

[0007] The power supply terminal of the control circuit is connected to the first power supply terminal;

[0008] The power supply terminal of the drive circuit is the same as the power supply terminal of the control circuit.

[0009] The first input terminal of the short-circuit protection module is connected to the output terminal of the drive circuit, the gate of the first NMOS transistor is connected to the output terminal of the short-circuit protection module, and the drain of the first NMOS transistor is connected to the second power supply terminal. The short-circuit protection module is used to output a drive signal with a fixed slope to control the discharge current and voltage of the first NMOS transistor to be within a safe range.

[0010] The positive terminal of the battery is connected to the first power supply terminal, and the source of the first NMOS transistor is connected to the negative terminal of the battery.

[0011] The first power terminal and the second power terminal are used to connect to the charger or the load.

[0012] In addition, the short-circuit protection circuit according to the present invention may also have the following additional technical features:

[0013] In some embodiments of the present invention, the short-circuit protection module includes a first linear ramp signal generating circuit and a follower. The first input terminal of the first linear ramp signal generating circuit is connected to the output terminal of the driving circuit, the first output terminal of the first linear ramp signal generating circuit is connected to the non-inverting input terminal of the follower, and the output terminal of the follower is connected to the gate of the first NMOS transistor.

[0014] The second input terminal of the first linear ramp signal generation circuit is connected to the positive terminal of the battery, and the second output terminal of the first linear ramp signal generation circuit is grounded.

[0015] The first linear ramp signal generation circuit is used to output a control signal that keeps the discharge current and voltage of the first NMOS transistor within a safe range.

[0016] In some embodiments of the present invention, the first linear ramp signal generation circuit includes a first current source, a second current source, a first logic switch circuit, and a capacitor;

[0017] The first input terminal of the first logic switch circuit is connected to the output terminal of the drive circuit, and the first output terminal of the first logic switch circuit is connected to the non-inverting input terminal of the follower.

[0018] The input terminal of the first current source is connected to the positive terminal of the battery, and the output terminal of the first current source is connected to the second input terminal of the first logic switch circuit.

[0019] The input terminal of the second current source is connected to the second output terminal of the first logic switch circuit, and the output terminal of the second current source is grounded.

[0020] The first end of the capacitor is connected between the first output terminal of the first logic switch circuit and the non-inverting input terminal of the follower, and the second end of the capacitor is grounded.

[0021] In some embodiments of the present invention, the first logic switch circuit includes a first PMOS transistor and a third NMOS transistor, wherein the source of the first PMOS transistor is connected to the output terminal of the first current source, and the source of the third NMOS transistor is connected to the input terminal of the second current source.

[0022] The gate of the first PMOS transistor is connected to the gate of the third NMOS transistor and then connected to the output terminal of the drive circuit.

[0023] The drain of the first PMOS transistor is connected to the drain of the third NMOS transistor and then connected to the non-inverting input of the follower.

[0024] The first end of the capacitor is connected between the non-inverting input of the follower and the node formed by connecting the drain of the first PMOS transistor and the drain of the third NMOS transistor.

[0025] In some embodiments of the present invention, the short-circuit protection module includes a second logic switch circuit and a monitoring and adjustment circuit;

[0026] The first input terminal of the second logic switch circuit is connected to the output terminal of the drive circuit, and the first output terminal of the second logic switch circuit is connected to the first terminal of the monitoring and adjustment circuit.

[0027] The second terminal of the monitoring and adjustment circuit is connected to the positive terminal of the battery, and the third terminal of the monitoring and adjustment circuit is connected to the gate of the first NMOS transistor. The monitoring and adjustment circuit is used to monitor the level of the parasitic capacitance of the first NMOS transistor. The monitoring and adjustment circuit is also used to select an appropriate resistance value according to the level of the parasitic capacitance of the first NMOS transistor so that the gate voltage and discharge current of the first NMOS transistor are within a safe range.

[0028] The second input terminal of the second logic switch circuit is connected to the power supply terminal of the control circuit, and the second output terminal of the second logic switch circuit is grounded.

[0029] In some embodiments of the present invention, the monitoring and regulation circuit includes a selection circuit and a third current source;

[0030] The input terminal of the selection circuit is connected to the first output terminal of the second logic switch circuit, and the output terminal of the selection circuit is connected to the gate of the first NMOS transistor.

[0031] The input terminal of the third current source is connected to the positive terminal of the battery, and the output terminal of the third current source is connected to the gate of the first NMOS transistor.

[0032] The selection circuit is used to monitor the level of parasitic capacitance of the first NMOS transistor;

[0033] The selection circuit is also used to select an appropriate resistor value based on the level of the parasitic capacitance of the first NMOS transistor so that the gate voltage and discharge current of the first NMOS transistor are within a safe range.

[0034] In some embodiments of the present invention, the selection circuit includes a first comparator, a first timer, and a plurality of switching resistors. The plurality of switching resistors are connected in series between the first output terminal of the second logic switching circuit and the gate of the first NMOS transistor. The non-inverting input terminal of the first comparator is connected to the gate of the first NMOS transistor, and the output terminal of the first comparator is connected to the input terminal of the first timer. The first timer is used to control the opening and closing of the plurality of switching resistors.

[0035] In some embodiments of the present invention, each switching resistor includes an adjusting resistor and a first adjusting switch, the two ends of the first adjusting switch being connected to the two ends of the adjusting resistor, and a first timer being used to control the opening and closing of the first adjusting switch.

[0036] In some embodiments of the present invention, the second logic switch circuit includes a second PMOS transistor and a fourth NMOS transistor, wherein the source of the second PMOS transistor is connected to the power supply terminal of the control circuit, and the source of the fourth NMOS transistor is grounded.

[0037] The gate of the second PMOS transistor is connected to the gate of the fourth NMOS transistor and then connected to the output terminal of the drive circuit.

[0038] The drain of the second PMOS transistor is connected to the drain of the fourth NMOS transistor, and then connected to the first terminal of the monitoring and adjustment circuit.

[0039] In some embodiments of the present invention, the short-circuit protection module includes a third logic switch circuit, a drive current selection circuit, a fourth current source, a first current selection module, and a second current selection module.

[0040] The first input terminal of the third logic switch circuit is connected to the output terminal of the drive circuit, and the first output terminal of the third logic switch circuit is connected to the input terminal of the drive current selection circuit; the first output terminal of the drive current selection circuit is connected to the gate of the first NMOS transistor.

[0041] The input terminal of the fourth current source is connected to the positive terminal of the battery, and the output terminal of the fourth current source is connected to the gate of the first NMOS transistor.

[0042] The first input terminal of the first current selection module is connected to the positive terminal of the battery, the second input terminal of the first current selection module is connected to the second output terminal of the drive current selection circuit, and the output terminal of the first current selection module is connected to the second input terminal of the third logic switch circuit.

[0043] The first input terminal of the second current selection module is connected to the second output terminal of the third logic switch circuit, the second input terminal of the second current selection module is connected to the third output terminal of the drive current selection circuit, and the output terminal of the third logic switch circuit is grounded.

[0044] The drive current selection circuit is used to monitor the level of the parasitic capacitance of the first NMOS transistor;

[0045] The drive current selection circuit is also used to select an appropriate current value based on the level of the parasitic capacitance of the first NMOS transistor so that the gate voltage and discharge current of the first NMOS transistor are within a safe range.

[0046] In some embodiments of the present invention, the third logic switching circuit includes a fifth NMOS transistor and a third PMOS transistor.

[0047] The source of the third PMOS transistor is connected to the output terminal of the first current selection module, and the source of the fifth NMOS transistor is connected to the first input terminal of the second current selection module.

[0048] The gate of the third PMOS transistor is connected to the gate of the fifth NMOS transistor and then connected to the output terminal of the drive circuit.

[0049] The drain of the third PMOS transistor is connected to the drain of the fifth NMOS transistor, and then connected to the input terminal of the drive current selection circuit.

[0050] In some embodiments of the present invention, the drive current selection circuit includes a second comparator and a second timer, and the first current selection module includes a plurality of first current switches, all of which are connected in series between the first output terminal of the third logic switch circuit and the gate of the first NMOS transistor.

[0051] The second current selection module includes multiple second current switches, which are connected in series between the first output terminal of the third logic switch circuit and the gate of the first NMOS transistor.

[0052] The non-inverting input of the second comparator is connected to the gate of the first NMOS transistor, and the output of the second comparator is connected to the input of the second timer. The second timer is used to control the opening and closing of multiple first current switches and multiple second current switches.

[0053] A second aspect of the present invention provides a battery protection chip, which includes all the technical features of the short-circuit protection circuit of the first aspect of the present invention.

[0054] In summary, this application includes the following beneficial technical effects: by setting the short-circuit protection module, the discharge current and voltage of the first NMOS transistor are always within the safe range, thereby ensuring that the battery operates within the safe range. This achieves that even under short-circuit conditions, the discharge current and voltage of the first NMOS transistor are always within the safe range, reducing current and voltage fluctuations and ensuring safety performance. Attached Figure Description

[0055] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0056] Figure 1 A schematic diagram of a short-circuit protection circuit according to some embodiments of the present invention is shown.

[0057] Figure 2 A schematic diagram of a first type of circuit diagram showing the connection between the drive circuit and the short-circuit protection module of a short-circuit protection circuit according to some embodiments of the present invention is shown.

[0058] Figure 3 A second circuit diagram illustrating the connection between the drive circuit and the short-circuit protection module of a short-circuit protection circuit according to some embodiments of the present invention is shown.

[0059] Figure 4 A schematic diagram of a monitoring and adjustment circuit for a short-circuit protection circuit according to some embodiments of the present invention is shown.

[0060] Figure 5 A schematic diagram of a third circuit is shown illustrating the connection between the drive circuit and the short-circuit protection module of a short-circuit protection circuit according to some embodiments of the present invention.

[0061] Figure 6 A schematic diagram of a drive current selection circuit for a short-circuit protection circuit according to some embodiments of the present invention is shown.

[0062] Figure 7 The diagram illustrates a circuit diagram of an existing chemical battery discharge process with a battery protection chip.

[0063] Figure 8 The diagram schematically illustrates the ideal drive signal of the first NMOS transistor in a conventional chemical battery protection chip.

[0064] Figure 9 The schematic diagram illustrates the actual operation of the drive signal of the first NMOS transistor in a conventional chemical battery protection chip.

[0065] Figure label:

[0066] 1. Battery; 2. Control circuit; 3. Load; 4. Second NMOS transistor; 5. Drive circuit; 6. Short-circuit protection module; 61. First linear ramp signal generation circuit; 611. Capacitor; 612. First current source; 613. Second current source; 614. First logic switch circuit; 6141. First PMOS transistor; 6142. Third NMOS transistor; 62. Follower; 63. Second logic switch circuit; 631. Second PMOS transistor; 632. Fourth NMOS transistor; 64. Monitoring and adjustment circuit; 641. Selection circuit; 6411. First comparator; 6412. First timer; 6413. Switching resistor; 64 131. Adjusting resistor; 64132. First adjusting switch; 6414. Second filter resistor; 642. Third current source; 65. Third logic switch circuit; 651. Fifth NMOS transistor; 652. Third PMOS transistor; 66. Drive current selection circuit; 661. Second comparator; 662. Second timer; 663. First current selection module; 6631. Fifth current source; 6632. Second adjusting switch; 664. Second current selection module; 6641. Sixth current source; 6642. Third adjusting switch; 67. Fourth current source; 7. First NMOS transistor; 8. First filter resistor; 9. Battery protection chip. Detailed Implementation

[0067] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0068] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “” used herein may also indicate the inclusion of the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated, unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0069] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0070] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may also be rotated 90 degrees or in other orientations, and the spatial relative descriptors used in the text will be interpreted accordingly.

[0071] The existing battery protection chip 9's drive circuit outputs a series of logic signals to control the off or on state of NM0, such as... Figure 8 As shown. However, due to the parasitic inductance in the wire, the actual driving signal is closer to... Figure 9 There will be some jitter. When the output drive signal rises at a fast rate, it will cause a large ringing signal, exceeding the maximum voltage that the NM0 discharge transistor (i.e., the first NMOS transistor 7) can withstand, causing the NM0 discharge transistor (i.e., the first NMOS transistor 7) to burn out. When the output drive signal rises at a slow rate, when a large current flows, the NM0 discharge transistor (i.e., the first NMOS transistor 7) will withstand the large current for a longer time before it is fully turned on, causing the NM0 discharge transistor (i.e., the first NMOS transistor 7) to be outside the safe range.

[0072] like Figures 1 to 6 As shown, according to an embodiment of the first aspect of the present invention, a short-circuit protection circuit is proposed, including a battery 1, a control circuit 2, a first NMOS transistor 7, a drive circuit 5, and a short-circuit protection module 6;

[0073] The power supply terminal of control circuit 2 is connected to the first power supply terminal;

[0074] The power supply terminal of the drive circuit 5 is the power supply terminal of the control circuit 2;

[0075] The first input terminal of the short-circuit protection module 6 is connected to the output terminal of the drive circuit 5, the gate of the first NMOS transistor 7 is connected to the output terminal of the short-circuit protection module 6, and the drain of the first NMOS transistor 7 is connected to the second power supply terminal. The short-circuit protection module 6 is used to output a drive signal with a fixed slope to control the discharge current and voltage of the first NMOS transistor 7 to be within a safe range.

[0076] The positive terminal of battery 1 is connected to the first power supply terminal, and the source of the first NMOS transistor 7 is connected to the negative terminal of battery 1.

[0077] The first power supply terminal and the second power supply terminal are used to connect to the charger or load 3.

[0078] In the above embodiments, it should be noted that the first power supply terminal is P+, the second power supply terminal is P-, the VDD voltage is the voltage of the first power supply terminal, and the voltage of the power supply terminal of the control circuit is the VDD1 voltage.

[0079] It also includes a second NMOS transistor 4, the gate of which is connected to the output terminal of the control circuit 2, the drain of which is connected to the second power supply terminal, and the source of which is connected to the drain of the first NMOS transistor 7.

[0080] It also includes a first filter resistor 8, which is connected in series between the power supply terminal of the control circuit 2 and the first power supply terminal.

[0081] The technical effect achieved by the above embodiment is as follows: by setting the short circuit protection module 6, the discharge current and voltage of the first NMOS transistor 7 are always within the safe range, thereby ensuring that the battery 1 operates within the safe range. This achieves that even under short circuit conditions, the discharge current and voltage of the first NMOS transistor 7 are always within the safe range, reducing current and voltage fluctuations and ensuring safety performance.

[0082] Optional, such as Figure 1 and Figure 2 As shown, the short-circuit protection module 6 includes a first linear ramp signal generation circuit 61 and a follower 62. The first input terminal of the first linear ramp signal generation circuit 61 is connected to the output terminal of the drive circuit 5, the first output terminal of the first linear ramp signal generation circuit 61 is connected to the non-inverting input terminal of the follower 62, and the output terminal of the follower 62 is connected to the gate of the first NMOS transistor 7.

[0083] The second input terminal of the first linear ramp signal generation circuit 61 is connected to the positive terminal of the battery 1, and the second output terminal of the first linear ramp signal generation circuit 61 is grounded.

[0084] The first linear ramp signal generation circuit 61 is used to output a control signal that keeps the discharge current and voltage of the first NMOS transistor 7 within a safe range.

[0085] Optional, such as Figure 1 and Figure 2 As shown, the first linear ramp signal generation circuit 61 includes a first current source 612, a second current source 613, a first logic switch circuit 614, and a capacitor 611.

[0086] The first input terminal of the first logic switch circuit 614 is connected to the output terminal of the drive circuit 5, and the first output terminal of the first logic switch circuit 614 is connected to the non-inverting input terminal of the follower 62.

[0087] The input terminal of the first current source 612 is connected to the positive terminal of the battery 1, and the output terminal of the first current source 612 is connected to the second input terminal of the first logic switch circuit 614.

[0088] The input terminal of the second current source 613 is connected to the second output terminal of the first logic switch circuit 614, and the output terminal of the second current source 613 is grounded.

[0089] The first end of capacitor 611 is connected between the first output terminal of the first logic switch circuit 614 and the non-inverting input terminal of the follower 62, and the second end of capacitor 611 is grounded.

[0090] Optional, such as Figure 2 As shown, the first logic switch circuit 614 includes a first PMOS transistor 6141 and a third NMOS transistor 6142. The source of the first PMOS transistor 6141 is connected to the output terminal of the first current source 612, and the source of the third NMOS transistor 6142 is connected to the input terminal of the second current source 613.

[0091] The gate of the first PMOS transistor 6141 is connected to the gate of the third NMOS transistor 6142 and then connected to the output terminal of the drive circuit 5.

[0092] The drain of the first PMOS transistor 6141 is connected to the drain of the third NMOS transistor 6142, and then connected to the non-inverting input terminal of the follower 62.

[0093] The first end of capacitor 611 is connected between the non-inverting input of follower 62 and the node where the drain of the first PMOS transistor 6141 and the drain of the third NMOS transistor 6142 are connected.

[0094] In the above optional embodiments, it should be noted that the working principle of this short-circuit protection module 6 is as follows:

[0095] When the output of the driving circuit 5 is low, the first PMOS transistor 6141 (PM1) is turned on, and the third NMOS transistor 6142 (NM1) is turned off.

[0096] At this time, the first current source 612, i.e., I0, provides charging current to capacitor 611, i.e., C0, causing the voltage across capacitor 611, i.e., C0 to rise.

[0097] The constant current characteristic of the first current source 612, i.e., I0, ensures that the capacitor C0 is charged at a relatively stable rate.

[0098] When the drive circuit 5 outputs a high level, the first PMOS transistor 6141 (PM1) is turned off, and the third NMOS transistor 6142 (NM1) is turned on.

[0099] At this time, capacitor 611 (C0) discharges through the conducting third NMOS transistor 6142 (NM1) to the second current source 613 (I1), causing the voltage across capacitor 611 (C0) to drop. The constant discharge current provided by the second current source 613 (I1) ensures that capacitor C0 discharges at a stable rate.

[0100] The first current source 612, i.e. I0, and the second current source 613, i.e. I1, work together to generate relatively stable rising and falling edge characteristics at the circuit output.

[0101] The first current source 612 and the second current source 613 both use existing current source modules, and the driving circuit 5 uses existing driving circuits. Alternatively, the driving circuit 5 can be directly integrated into the control circuit 2.

[0102] During short-circuit protection, the second NMOS transistor 4 and NM1 are always in the on state. The capacitor C0 is charged or discharged by the first current source 612 (I0) and the second current source 613 (I1) in combination with the high and low level settings of the drive circuit 5, so as to obtain a drive signal with a fixed slew rate. This control signal keeps the discharge current and voltage of the first NMOS transistor 7 in the safe range. Then, the first NMOS transistor 7 (NM0) is turned on and off by the follower 62 to ensure that the first NMOS transistor 7 (NM0) is not easily damaged.

[0103] The beneficial effects of the above optional embodiments are as follows: by setting the first current source 612 (i.e., I0), the second current source 613 (i.e., I1), and the capacitor C0 in combination with the follower 62, it is ensured that the first NMOS transistor 7 (i.e., NM0) will not be easily damaged even in the event of a short circuit.

[0104] Optional, such as Figure 3 and Figure 4 As shown, the short-circuit protection module 6 includes a second logic switch circuit 63 and a monitoring and adjustment circuit 64;

[0105] The first input terminal of the second logic switch circuit 63 is connected to the output terminal of the drive circuit 5, and the first output terminal of the second logic switch circuit 63 is connected to the first terminal of the monitoring and adjustment circuit 64.

[0106] The second terminal of the monitoring and adjustment circuit 64 is connected to the positive terminal of the battery 1, and the third terminal of the monitoring and adjustment circuit 64 is connected to the gate of the first NMOS transistor 7. The monitoring and adjustment circuit 64 is used to monitor the level of the parasitic capacitance 611 of the first NMOS transistor 7. The monitoring and adjustment circuit 64 is also used to select an appropriate resistance value according to the level of the parasitic capacitance 611 of the first NMOS transistor 7 so that the gate voltage and discharge current of the first NMOS transistor 7 are within a safe range.

[0107] The second input terminal of the second logic switch circuit 63 is connected to the power supply terminal of the control circuit 2, and the second output terminal of the second logic switch circuit 63 is grounded.

[0108] Optional, such as Figure 3 and Figure 4 As shown, the monitoring and regulation circuit 64 includes a selection circuit 641 and a third current source 642;

[0109] The input terminal of the selection circuit 641 is connected to the first output terminal of the second logic switch circuit 63, and the output terminal of the selection circuit 641 is connected to the gate of the first NMOS transistor 7.

[0110] The input terminal of the third current source 642 is connected to the positive terminal of the battery 1, and the output terminal of the third current source 642 is connected to the gate of the first NMOS transistor 7.

[0111] The selection circuit 641 is used to monitor the level of the parasitic capacitance 611 of the first NMOS transistor 7;

[0112] The selection circuit 641 is also used to select an appropriate resistance value based on the level of the parasitic capacitance 611 of the first NMOS transistor 7 so that the gate voltage and discharge current of the first NMOS transistor 7 are within a safe range.

[0113] Optional, such as Figure 2 and Figure 3 As shown, the selection circuit 641 includes a first comparator 6411, a first timer 6412, and multiple switching resistors 6413. The multiple switching resistors 6413 are connected in series between the first output terminal of the second logic switch circuit 63 and the gate of the first NMOS transistor 7. The non-inverting input terminal of the first comparator 6411 is connected to the gate of the first NMOS transistor 7, and the output terminal of the first comparator 6411 is connected to the input terminal of the first timer 6412. The first timer 6412 is used to control the opening and closing of the multiple switching resistors 6413.

[0114] In the above optional embodiments, it should be noted that the first timer 6142 adopts an existing first timer that can generate an output signal based on time parameters, and also includes a second filter resistor 6414. The second filter resistor is connected between the switching resistor 6413 located at the first end and the first output terminal of the second logic switch circuit 63.

[0115] Optional, such as Figure 3 and Figure 4 As shown, each switching resistor 6413 includes an adjusting resistor 64131 and a first adjusting switch 64132. The two ends of the first adjusting switch 64132 are connected to the two ends of the adjusting resistor 64131. The first timer 6412 is used to control the opening and closing of the first adjusting switch 64132.

[0116] The working principle of the selection circuit 641 is as follows: a reference voltage ref is set, the gate voltage of the first NMOS transistor 7 is input to the non-inverting input of the first comparator 6411, and the reference voltage ref is input to the inverting input of the first comparator 6411. When the gate voltage of the first NMOS transistor 7 is greater than the reference voltage, the first comparator 6411 flips. The time T0 from the start of comparison to the flip of the first comparator 6411 is converted into a series of digital signals by the first timer 6412 to control the selection of an appropriate resistance value of the adjusting resistor 64131. This achieves a slew rate of the gate voltage of the first NMOS transistor 7 that is close to S0V / us, which is suitable for the first NMOS transistor 7 in different applications. This ensures that the discharge current and voltage of the first NMOS transistor 7 are always within a safe range, thus ensuring safety performance.

[0117] Each of the 6413 switching resistors can be replaced by existing MOSFETs, as long as the corresponding function can be achieved. The specific structure will not be discussed in detail here.

[0118] Optional, such as Figure 3 and Figure 4 As shown, the second logic switch circuit 63 includes a second PMOS transistor 631 and a fourth NMOS transistor 632. The source of the second PMOS transistor 631 is connected to the power supply terminal of the control circuit 2, and the source of the fourth NMOS transistor 632 is grounded.

[0119] The gate of the second PMOS transistor 631 is connected to the gate of the fourth NMOS transistor 632 and then connected to the output terminal of the drive circuit 5.

[0120] The drain of the second PMOS transistor 631 is connected to the drain of the fourth NMOS transistor 632 and then connected to the first terminal of the monitoring and adjustment circuit 64.

[0121] In the above optional embodiments, it should be noted that the working principle of the second logic switch circuit 63 is as follows: the pulse signal output by the driving circuit 5 is connected to the gate of the second PMOS transistor 631 and the gate of the fourth NMOS transistor 632. When the driving circuit 5 outputs a low level, the second PMOS transistor 631 is turned on because the gate voltage is lower than the source voltage, and the fourth NMOS transistor 632 is turned off because the gate voltage is lower than the source voltage. The power supply is pulled up to the output terminal of the second PMOS transistor 631 to a high level. When the driving circuit outputs a high level, the second PMOS transistor 631 is turned off because the gate voltage is equal to the source voltage, and the fourth NMOS transistor 632 is turned on because the gate voltage is higher than the source voltage. The output terminal is pulled down to a low level by the fourth NMOS transistor 632. Thus, the input pulse signal is converted into an output level with an amplitude close to that of the power supply and ground, thereby realizing signal driving and driving the selection circuit 641 to work.

[0122] The advantages of the above optional embodiments are that the configuration of the second logic switch circuit 63 can effectively drive the selection circuit 641 to work.

[0123] Optional, such as Figure 5 and Figure 6 As shown, the short-circuit protection module 6 includes a third logic switch circuit 65, a drive current selection circuit 66, a fourth current source 67, a first current selection module 663, and a second current selection module 664.

[0124] The first input terminal of the third logic switch circuit 65 is connected to the output terminal of the drive circuit, and the first output terminal of the third logic switch circuit 65 is connected to the input terminal of the drive current selection circuit 66; the first output terminal of the drive current selection circuit 66 is connected to the gate of the first NMOS transistor 7.

[0125] The input terminal of the fourth current source 67 is connected to the positive terminal of the battery 1, and the output terminal of the fourth current source 67 is connected to the gate of the first NMOS transistor 7.

[0126] The first input terminal of the first current selection module 663 is connected to the positive terminal of the battery 1, the second input terminal of the first current selection module 663 is connected to the second output terminal of the drive current selection circuit 66, and the output terminal of the first current selection module 663 is connected to the second input terminal of the third logic switch circuit 65614.

[0127] The first input terminal of the second current selection module 664 is connected to the second output terminal of the third logic switch circuit 65, the second input terminal of the second current selection module 664 is connected to the third output terminal of the drive current selection circuit 66, and the output terminal of the third logic switch circuit 65 is grounded.

[0128] The drive current selection circuit 66 is used to monitor the level of the parasitic capacitance of the first NMOS transistor 7;

[0129] The drive current selection circuit 66 is also used to select an appropriate current value based on the level of the parasitic capacitance of the first NMOS transistor 7 so that the gate voltage and discharge current of the first NMOS transistor 7 are within a safe range.

[0130] Optional, such as Figure 5 and Figure 6 As shown, the third logic switch circuit 65 includes a fifth NMOS transistor 651 and a third PMOS transistor 652.

[0131] The source of the third PMOS transistor 652 is connected to the output terminal of the first current selection module 663, and the source of the fifth NMOS transistor 651 is connected to the first input terminal of the second current selection module 664.

[0132] The gate of the third PMOS transistor 652 is connected to the gate of the fifth NMOS transistor 651 and then connected to the output terminal of the drive circuit 5.

[0133] The drain of the third PMOS transistor 652 is connected to the drain of the fifth NMOS transistor 651, and then connected to the input terminal of the drive current selection circuit 66.

[0134] Optional, such as Figure 5 and Figure 6 As shown, the drive current selection circuit 66 includes a second comparator 661 and a second timer 662, and the first current selection module 663 includes a plurality of first current switches, all of which are connected in series between the first output terminal of the third logic switch circuit 65 and the gate of the first NMOS transistor 7.

[0135] The second current selection module 664 includes a plurality of second current switches, which are connected in series between the first output terminal of the third logic switch circuit 65 and the gate of the first NMOS transistor 7.

[0136] The non-inverting input of the second comparator 661 is connected to the gate of the first NMOS transistor 7, and the output of the second comparator 661 is connected to the input of the second timer 662. The second timer 662 is used to control the opening and closing of multiple first current switches and multiple second current switches.

[0137] In the above optional embodiments, it should be noted that each first current switch includes a fifth current source 6631 and a second regulating switch 6632. The two ends of the second regulating switch 6632 are connected to the two ends of the fifth current source 6631. The second timer 662 is used to control the opening and closing of the second regulating switch 6632.

[0138] Each second current switch includes a sixth current source 6641 and a third regulating switch 6642. The two ends of the third regulating switch 6642 are connected to the two ends of the sixth current source 6641. The second timer 662 is used to control the opening and closing of the second regulating switch 6642.

[0139] The working principle of the drive current selection circuit 66 is as follows: a reference voltage ref is set, the gate voltage of the first NMOS transistor 7 is input to the non-inverting input of the second comparator 661, and the reference voltage ref is input to the inverting input of the second comparator 661. When the gate voltage of the first NMOS transistor 7 is greater than the reference voltage, the second comparator 661 flips. The time T0 from the start of comparison to the flip of the second comparator 661 is converted into a series of digital signals by the second timer 662 to control the selection of a suitable fifth current source 6631 and / or a suitable sixth current source 6641, thereby achieving a slew rate of the gate voltage of the first NMOS transistor 7 close to S0V / us, which is suitable for the first NMOS transistor 7 in different applications, thereby ensuring that the discharge current and voltage of the first NMOS transistor 7 are always within a safe range and ensuring safety performance.

[0140] According to an embodiment of the first aspect of the present invention, a battery protection chip is provided, which includes all the technical features of the short-circuit protection circuit of the first aspect of the present invention.

[0141] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A short-circuit protection circuit, characterized in that, It includes a battery (1), a control circuit (2), a first NMOS transistor (7), a drive circuit (5), and a short-circuit protection module (6); The power supply terminal of the control circuit (2) is connected to the first power supply terminal; The power supply terminal of the driving circuit (5) is the power supply terminal of the control circuit (2); The first input terminal of the short-circuit protection module (6) is connected to the output terminal of the driving circuit (5), the gate of the first NMOS transistor (7) is connected to the output terminal of the short-circuit protection module (6), and the drain of the first NMOS transistor (7) is connected to the second power supply terminal. The short-circuit protection module (6) is used to output a driving signal with a fixed slope to control the discharge current and voltage of the first NMOS transistor (7) to be within a safe range. The positive terminal of the battery (1) is connected to the first power supply terminal, and the source of the first NMOS transistor (7) is connected to the negative terminal of the battery (1). The first power supply terminal and the second power supply terminal are used to connect to a charger or load (3).

2. The short-circuit protection circuit according to claim 1, characterized in that, The short-circuit protection module (6) includes a first linear ramp signal generation circuit (61) and a follower (62). The first input terminal of the first linear ramp signal generation circuit (61) is connected to the output terminal of the driving circuit (5). The first output terminal of the first linear ramp signal generation circuit (61) is connected to the non-inverting input terminal of the follower (62). The output terminal of the follower (62) is connected to the gate of the first NMOS transistor (7). The second input terminal of the first linear ramp signal generating circuit (61) is connected to the positive terminal of the battery (1), and the second output terminal of the first linear ramp signal generating circuit (61) is grounded. The first linear ramp signal generating circuit (61) is used to output a control signal that keeps the discharge current and voltage of the first NMOS transistor (7) within a safe range.

3. The short-circuit protection circuit according to claim 2, characterized in that, The first linear ramp signal generating circuit (61) includes a first current source (612), a second current source (613), a first logic switch circuit (614), and a capacitor (611). The first input terminal of the first logic switch circuit (614) is connected to the output terminal of the driving circuit (5), and the first output terminal of the first logic switch circuit (614) is connected to the non-inverting input terminal of the follower (62). The input terminal of the first current source (612) is connected to the positive terminal of the battery (1), and the output terminal of the first current source (612) is connected to the second input terminal of the first logic switch circuit (614). The input terminal of the second current source (613) is connected to the second output terminal of the first logic switch circuit (614), and the output terminal of the second current source (613) is grounded; The first end of the capacitor (611) is connected between the first output terminal of the first logic switch circuit (614) and the non-inverting input terminal of the follower (62), and the second end of the capacitor (611) is grounded.

4. The short-circuit protection circuit according to claim 3, characterized in that, The first logic switch circuit (614) includes a first PMOS transistor (6141) and a third NMOS transistor (6142). The source of the first PMOS transistor (6141) is connected to the output terminal of the first current source (612), and the source of the third NMOS transistor (6142) is connected to the input terminal of the second current source (613). The gate of the first PMOS transistor (6141) is connected to the gate of the third NMOS transistor (6142) and then connected to the output terminal of the driving circuit (5). The drain of the first PMOS transistor (6141) is connected to the drain of the third NMOS transistor (6142) and then connected to the non-inverting input terminal of the follower (62); The first end of the capacitor (611) is connected between the non-inverting input of the follower (62) and the node where the drain of the first PMOS transistor (6141) and the drain of the third NMOS transistor (6142) are connected.

5. The short-circuit protection circuit according to claim 1, characterized in that, The short-circuit protection module (6) includes a second logic switch circuit (63) and a monitoring and adjustment circuit (64). The first input terminal of the second logic switch circuit (63) is connected to the output terminal of the drive circuit (5), and the first output terminal of the second logic switch circuit (63) is connected to the first terminal of the monitoring and adjustment circuit (64). The second terminal of the monitoring and adjustment circuit (64) is connected to the positive terminal of the battery (1), and the third terminal of the monitoring and adjustment circuit (64) is connected to the gate of the first NMOS transistor (7). The monitoring and adjustment circuit (64) is used to monitor the level of the parasitic capacitance of the first NMOS transistor (7). The monitoring and adjustment circuit (64) is also used to select a resistance value according to the level of the parasitic capacitance of the first NMOS transistor (7) so that the gate voltage and discharge current of the first NMOS transistor (7) are within a safe range. The second input terminal of the second logic switch circuit (63) is connected to the power supply terminal of the control circuit (2), and the second output terminal of the second logic switch circuit (63) is grounded.

6. The short-circuit protection circuit according to claim 5, characterized in that, The monitoring and regulation circuit (64) includes a selection circuit (641) and a third current source (642). The input terminal of the selection circuit (641) is connected to the first output terminal of the second logic switch circuit (63), and the output terminal of the selection circuit (641) is connected to the gate of the first NMOS transistor (7). The input terminal of the third current source (642) is connected to the positive terminal of the battery (1), and the output terminal of the third current source (642) is connected to the gate of the first NMOS transistor (7). The selection circuit (641) is used to monitor the level of the parasitic capacitance of the first NMOS transistor (7); The selection circuit (641) is also used to select a resistance value according to the level of the parasitic capacitance of the first NMOS transistor (7) so that the gate voltage and discharge current of the first NMOS transistor (7) are in a safe range. The selection circuit (641) includes a first comparator (6411), a first timer (6412), and a plurality of switching resistors (6413). The plurality of switching resistors (6413) are connected in series between the first output terminal of the second logic switch circuit (63) and the gate of the first NMOS transistor (7). The non-inverting input terminal of the first comparator (6411) is connected to the gate of the first NMOS transistor (7). The output terminal of the first comparator (6411) is connected to the input terminal of the first timer (6412). The first timer (6412) is used to control the opening and closing of the plurality of switching resistors (6413).

7. The short-circuit protection circuit according to claim 5, characterized in that, The second logic switch circuit (63) includes a second PMOS transistor (631) and a fourth NMOS transistor (632). The source of the second PMOS transistor (631) is connected to the power supply terminal of the control circuit (2), and the source of the fourth NMOS transistor (632) is grounded. The gate of the second PMOS transistor (631) is connected to the gate of the fourth NMOS transistor (632) and then connected to the output terminal of the driving circuit (5); The drain of the second PMOS transistor (631) is connected to the drain of the fourth NMOS transistor (632) and then connected to the first terminal of the monitoring and adjustment circuit (64).

8. The short-circuit protection circuit according to claim 1, characterized in that, The short-circuit protection module (6) includes a third logic switch circuit (65), a drive current selection circuit (66), a fourth current source (67), a first current selection module (663), and a second current selection module (664). The first input terminal of the third logic switch circuit (65) is connected to the output terminal of the driving circuit, and the first output terminal of the third logic switch circuit (65) is connected to the input terminal of the driving current selection circuit (66); the first output terminal of the driving current selection circuit (66) is connected to the gate of the first NMOS transistor (7). The input terminal of the fourth current source (67) is connected to the positive terminal of the battery (1), and the output terminal of the fourth current source (67) is connected to the gate of the first NMOS transistor (7). The first input terminal of the first current selection module (663) is connected to the positive terminal of the battery (1), the second input terminal of the first current selection module (663) is connected to the second output terminal of the drive current selection circuit (66), and the output terminal of the first current selection module (663) is connected to the second input terminal of the third logic switch circuit (65) (614). The first input terminal of the second current selection module (664) is connected to the second output terminal of the third logic switch circuit (65), the second input terminal of the second current selection module (664) is connected to the third output terminal of the drive current selection circuit (66), and the output terminal of the third logic switch circuit (65) is grounded. The drive current selection circuit (66) is used to monitor the level of the parasitic capacitance of the first NMOS transistor (7); The drive current selection circuit (66) is also used to select a current value according to the level of the parasitic capacitance of the first NMOS transistor (7) so that the gate voltage and discharge current of the first NMOS transistor (7) are in a safe range.

9. The short-circuit protection circuit according to claim 8, characterized in that, The third logic switch circuit (65) includes a fifth NMOS transistor (651) and a third PMOS transistor (652). The source of the third PMOS transistor (652) is connected to the output terminal of the first current selection module (663), and the source of the fifth NMOS transistor (651) is connected to the first input terminal of the second current selection module (664). The gate of the third PMOS transistor (652) is connected to the gate of the fifth NMOS transistor (651) and then connected to the output terminal of the driving circuit (5). The drain of the third PMOS transistor (652) is connected to the drain of the fifth NMOS transistor (651) and then connected to the input terminal of the drive current selection circuit (66). The drive current selection circuit (66) includes a second comparator (661) and a second timer (662). The first current selection module (663) includes a plurality of first current switches. The plurality of first current switches are connected in series between the first output terminal of the third logic switch circuit (65) and the gate of the first NMOS transistor (7). The second current selection module (664) includes a plurality of second current switches, which are connected in series between the first output terminal of the third logic switch circuit (65) and the gate of the first NMOS transistor (7). The non-inverting input of the second comparator (661) is connected to the gate of the first NMOS transistor (7), and the output of the second comparator (661) is connected to the input of the second timer (662). The second timer (662) is used to control the opening and closing of the multiple first current switches and the multiple second current switches.

10. A battery protection chip, characterized in that, Includes the short-circuit protection circuit as described in any one of claims 1 to 9.

Images